IXDF504 / IXDI504 / IXDN504 4 Ampere Dual Low-Side Ultrafast MOSFET Drivers Features General Description • Built using the advantages and compatibility of CMOS and IXYS HDMOSTM processes • Latch-Up Protected up to 4 Amps • High Peak Output Current: 4A Peak • Wide Operating Range: 4.5V to 30V • -55°C to +125°C Extended Operating Temperature • High Capacitive Load Drive Capability: 1800pF in <15ns • Matched Rise And Fall Times • Low Propagation Delay Time • Low Output Impedance • Low Supply Current • Two Drivers in Single Chip The IXDF504, IXDI504 and IXDN504 each consist of two 4Amp CMOS high speed MOSFET Gate Drivers for driving the latest IXYS MOSFETs & IGBTs. Each of the outputs can source and sink 4 Amps of Peak Current while producing voltage rise and fall times of less than 15ns. The input of each driver is TTL or CMOS compatible and is virtually immune to latch up. Patented* design innovations eliminate cross conduction and current "shoot-through". Improved speed and drive capabilities are further enhanced by very fast, matched rise and fall times. Applications • • • • • • • • • • Driving MOSFETs and IGBTs Motor Controls Line Drivers Pulse Generators Local Power ON/OFF Switch Switch Mode Power Supplies (SMPS) DC to DC Converters Pulse Transformer Driver Class D Switching Amplifiers Power Charge Pumps The IXDF504 is configured with one Gate Driver Inverting + one Gate Driver Non-Inverting. The IXDI504 is configured as a Dual Inverting Gate Driver, and the IXDN504 is configured as a Dual Non-Inverting Gate Driver. The IXDF504, IXDI504 and IXDN504 are each available in the 8-Pin P-DIP (PI) package, the 8-Pin SOIC (SIA) package, and the 6-Lead DFN (D1) package, (which occupies less than 65% of the board area of the 8-Pin SOIC). *United States Patent 6,917,227 Ordering Information Part Number IXDF504PI IXDF504SIA IXDF504SIAT/R IXDF504D1 IXDF504D1T/R IXDI504PI IXDI504SIA IXDI504SIAT/R IXDI504D1 IXDI504D1T/R IXDN504PI IXDN504SIA IXDN504SIAT/R IXDN504D1 IXDN504D1T/R Description 4A Low Side Gate Driver I.C. 4A Low Side Gate Driver I.C. 4A Low Side Gate Driver I.C. 4A Low Side Gate Driver I.C. 4A Low Side Gate Driver I.C. 4A Low Side Gate Driver I.C. 4A Low Side Gate Driver I.C. 4A Low Side Gate Driver I.C. 4A Low Side Gate Driver I.C. 4A Low Side Gate Driver I.C. 4A Low Side Gate Driver I.C. 4A Low Side Gate Driver I.C. 4A Low Side Gate Driver I.C. 4A Low Side Gate Driver I.C. 4A Low Side Gate Driver I.C. Package Type 8-Pin PDIP 8-Pin SOIC 8-Pin SOIC 6-Lead DFN 6-Lead DFN 8-Pin PDIP 8-Pin SOIC 8-Pin SOIC 6-Lead DFN 6-Lead DFN 8-Pin PDIP 8-Pin SOIC 8-Pin SOIC 6-Lead DFN 6-Lead DFN Packing Style Tube Tube 13” Tape and Reel 2” x 2” Waffle Pack 13” Tape and Reel Tube Tube 13” Tape and Reel 2” x 2” Waffle Pack 13” Tape and Reel Tube Tube 13” Tape and Reel 2” x 2” Waffle Pack 13” Tape and Reel Pack Qty 50 94 2500 56 2500 50 94 2500 56 2500 50 94 2500 56 2500 Configuration Dual Drivers, one Inverting and one NonInverting Dual Inverting Drivers Dual NonInverting Drivers NOTE: All parts are lead-free and RoHS Compliant DS99567A(10/07) Copyright © 2007 IXYS CORPORATION All rights reserved First Release IXDF504 / IXDI504 / IXDN504 Figure 1 - IXDF504 Inverting + Non-Inverting 4A Gate Driver Functional Block Diagram Vcc P ANTI-CROSS CONDUCTION CIRCUIT * IN A OUT A * N P ANTI-CROSS CONDUCTION CIRCUIT * IN B OUT B * N GND Figure 2 - IXDI504 Dual Inverting 4A Gate Driver Functional Block Diagram Vcc P ANTI-CROSS CONDUCTION CIRCUIT * IN A OUT A * N P ANTI-CROSS CONDUCTION CIRCUIT * IN B OUT B * N GND Figure 3 - IXDN504 Dual 4A Non-Inverting Gate Driver Functional Block Diagram Vcc P ANTI-CROSS CONDUCTION CIRCUIT * IN A * OUT A N P ANTI-CROSS CONDUCTION CIRCUIT * IN B * GND * United States Patent 6,917,227 Copyright © 2007 IXYS CORPORATION All rights reserved 2 OUT B N IXDF504 / IXDI504 / IXDN504 Absolute Maximum Ratings (1) Operating Ratings (2) Parameter Supply Voltage All Other Pins (Unless specified otherwise) Junction Temperature Storage Temperature Lead Temperature (10 Sec) Parameter Value Operating Supply Voltage 4.5V to 30V Operating Temperature Range -55 °C to 125 °C Package Thermal Resistance * θJ-A (typ) 125 °C/W 8-PinPDIP (PI) 8-Pin SOIC (SIA) θJ-A(typ) 200 °C/W 6-Lead DFN (D1) θJ-A(typ) 125-200 °C/W θJ-C(max) 2.1 °C/W 6-Lead DFN (D1) 6-Lead DFN (D1) θJ-S(typ) 6.4 °C/W Value 35 V -0.3 V to VCC + 0.3V 150 °C -65 °C to 150 °C 300 °C Electrical Characteristics @ TA = 25 oC (3) Unless otherwise noted, 4.5V ≤ VCC ≤ 30V . All voltage measurements with respect to GND. IXD_504 configured as described in Test Conditions. All specifications are for one channel. (4) Symbol Parameter Test Conditions Min VIH High input voltage 4.5V ≤ VIN ≤ 18V 3 VIL Low input voltage 4.5V ≤ VIN ≤ 18V VIN Input voltage range IIN Input current VOH High output voltage VOL Low output voltage ROH High state output resistance ROL Low state output resistance IPEAK Peak output current IDC Continuous output current tR Rise time tF Fall time tONDLY On-time propagation delay tOFFDLY Off-time propagation delay VCC Power supply voltage ICC Power supply current 0V ≤ VIN ≤ VCC Typ Max V 0.8 V -5 VCC + 0.3 V -10 10 µA VCC - 0.025 VCC = 18V IOUT = 10mA VCC = 18V IOUT = 10mA VCC = 15V V 0.025 V 1.5 2.5 Ω 1.2 2 Ω 1 A A 9 16 ns 8 14 ns 19 40 ns 18 35 ns 18 0.25 30 10 3 10 V 4 Limited by package dissipation CLOAD =1000pF VCC =18V CLOAD =1000pF VCC =18V CLOAD =1000pF VCC =18V CLOAD =1000pF VCC =18V 4.5 VCC = 18V, VIN = 0V VIN = 3.5V VIN = VCC IXYS reserves the right to change limits, test conditions, and dimensions. 3 Units µA mA mA IXDF504 / IXDI504 / IXDN504 Electrical Characteristics @ temperatures over -55 oC to 125 oC (3) Unless otherwise noted, 4.5V ≤ VCC ≤ 30V , Tj < 150oC All voltage measurements with respect to GND. IXD_504 configured as described in Test Conditions. All specifications are for one channel. Symbol Parameter Test Conditions Min VIH High input voltage 4.5V ≤ VCC ≤ 18V 3 VIL Low input voltage 4.5V ≤ VCC ≤ 18V VIN Input voltage range IIN Input current VOH High output voltage VOL Low output voltage ROH IDC High state output resistance Low state output resistance Continuous output current tR Rise time tF Fall time 0V ≤ VIN ≤ VCC Typ Max Units V 0.8 V -5 VCC + 0.3 V -10 10 µA VCC - 0.025 V 0.025 V VCC = 18V, IOUT = 10mA 3 Ω VCC = 18V, IOUT = 10mA 2.5 Ω 1 A CLOAD =1000pF VCC =18V 20 ns CLOAD =1000pF VCC =18V 15 ns tONDLY On-time propagation delay CLOAD =1000pF VCC =18V 60 ns tOFFDLY Off-time propagation delay CLOAD =1000pF VCC =18V 50 ns VCC Power supply voltage 30 V ICC Power supply current 150 3 150 µA mA mA ROL 4.5 VCC = 18V, VIN = 0V VIN = 3.5V VIN = VCC 18 Notes: 1. Operating the device beyond the parameters listed as “Absolute Maximum Ratings” may cause permanent damage to the device. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. 2. The device is not intended to be operated outside of the Operating Ratings. 3. Electrical Characteristics provided are associated with the stated Test Conditions. 4. Typical values are presented in order to communicate how the device is expected to perform, but not necessarily to highlight any specific performance limits within which the device is guaranteed to function. * The following notes are meant to define the conditions for the θJ-A, θJ-C and θJ-S values: 1) The θJ-A (typ) is defined as junction to ambient. The θJ-A of the standard single die 8-Lead PDIP and 8-Lead SOIC are dominated by the resistance of the package, and the IXD_5XX are typical. The values for these packages are natural convection values with vertical boards and the values would be lower with forced convection. For the 6-Lead DFN package, the θJ-A value supposes the DFN package is soldered on a PCB. The θJ-A (typ) is 200 °C/W with no special provisions on the PCB, but because the center pad provides a low thermal resistance to the die, it is easy to reduce the θJ-A by adding connected copper pads or traces on the PCB. These can reduce the θJ-A (typ) to 125 °C/W easily, and potentially even lower. The θJ-A for DFN on PCB without heatsink or thermal management will vary significantly with size, construction, layout, materials, etc. This typical range tells the user what he is likely to get if he does no thermal management. 2) θJ-C (max) is defined as juction to case, where case is the large pad on the back of the DFN package. The θJ-C values are generally not published for the PDIP and SOIC packages. The θJ-C for the DFN packages are important to show the low thermal resistance from junction to the die attach pad on the back of the DFN, -- and a guardband has been added to be safe. 3) The θJ-S (typ) is defined as junction to heatsink, where the DFN package is soldered to a thermal substrate that is mounted on a heatsink. The value must be typical because there are a variety of thermal substrates. This value was calculated based on easily available IMS in the U.S. or Europe, and not a premium Japanese IMS. A 4 mil dialectric with a thermal conductivity of 2.2W/mC was assumed. The result was given as typical, and indicates what a user would expect on a typical IMS substrate, and shows the potential low thermal resistance for the DFN package. Copyright © 2007 IXYS CORPORATION All rights reserved 4 IXDF504 / IXDI504 / IXDN504 Pin Description SYMBOL IN A FUNCTION A Channel Input GND Ground IN B B Channel Input OUT B B Channel Output VCC Supply Voltage OUT A A Channel Output DESCRIPTION A channel input signal-TTL or CMOS compatible. The system ground pin. Internally connected to all circuitry, this pin provides ground reference for the entire device. This pin should be connected to a low noise analog ground plane for optimum performance. B channel input signal-TTL or CMOS compatible. B channel driver output. For application purposes, this pin is connected via a resistor to the gate of a MOSFET/IGBT. Positive power-supply voltage input. This pin provides power to the entire device. The range for this voltage is from 4.5V to 30V. A channel criver output. For application purposes, this pin is connected via a resistor to the gate of a MOSFET/IGBT. CAUTION: Follow proper ESD procedures when handling and assembling this component. Pin Configurations IXDF504 1 NC 2 IN A 3 GND 4 INB IXDN504 IXDI504 NC 8 1 NC O UT A 7 2 IN A VS 6 3 GND O UT B 5 4 INB NC 8 1 NC O UT A 7 2 IN A VS 6 3 GND O UT B 5 4 INB 8 Lead PDIP (PI) 8 Pin SOIC (SI) (SIA) IXDF402 8 Lead PDIP (PI) 8 Pin SOIC (SI) (SIA) IXDI402 6 Lead DFN (D1) (Bottom View) 6 Lead DFN (D1) (Bottom View) 6 OUT A IN A 1 5 Vcc 4 OUT B 5 Vcc IN B 3 O UT A 7 VS 6 O UT B 5 6 Lead DFN (D1) (Bottom View) GND 2 4 OUT B 8 8 Lead PDIP (PI) (SIA) 8 Pin SOIC (SI) IXDN402 6 OUT A IN A 1 GND 2 NC 6 OUT A IN A 1 5 GND 2 Vcc 4 OUT B IN B 3 IN B 3 NOTE: Solder tabs on bottoms of DFN packages are grounded Figure 4 - Characteristics Test Diagram Vcc IXD_504 1 10uF 0.01uF NC 2 In A 3 Gnd 4 In B NC 8 7 Out A 6 Vcc 5 Out B Agilent 1147A Current Probe CLOAD IXYS reserves the right to change limits, test conditions, and dimensions. 5 Agilent 1147A Current Probe CLOAD IXDF504 / IXDI504 / IXDN504 Typical Performance Characteristics Fig. 5 Fig. 6 Rise Times vs. Supply Voltage 90 80 70 Fall Time (ns) 70 Rise Time (ns) Fall Times vs. Supply Voltage 80 60 50 10000pF 40 30 50 10000pF 40 30 5400pF 20 5400pF 20 60 10 10 1000pF 1000pF 100pF 0 0 5 10 15 20 25 30 100pF 0 0 35 5 10 Rise / Fall Time vs. Temperature VSUPPLY = 15V CLOAD = 1000pF 25 30 35 Fig. 8 Rise Time vs. Capacitive Load 70 10 5V 9 60 8 Rise Time (ns) Rise / Fall Time (ns) 20 Supply Voltage (V) Supply Voltage (V) Fig. 7 15 7 6 5 4 3 50 15V 30V 40 30 20 2 10 1 0 -50 -30 -10 10 30 50 70 90 110 130 0 100 150 1000 Temperature (C) Fig. 9 Fig. 10 Fall Time vs. Capacitive Load 70 Input Threshold Levels vs. Supply Voltage 2.5 Threshold Level (V) 5V 60 Fall Time (ns) 10000 Load Capacitance (pF) 50 15V 30V 40 30 20 2 Positive going input 1.5 Negative going input 1 0.5 10 0 100 0 1000 10000 0 Load Capacitance (pF) Copyright © 2007 IXYS CORPORATION All rights reserved 5 10 15 20 Supply Voltage (V) 6 25 30 35 IXDF504 / IXDI504 / IXDN504 Fig. 11 Input Threshold Levels vs. Temperature Propagation Delay vs. Supply Voltage Rising Input, CLOAD = 1000pF Fig. 12 VSUPPLY = 15V 35 Propagation Delay Time (ns) Input Threshold Level (V) 3 2.5 2 Positive going input 1.5 Negative going input 1 0.5 30 25 20 15 10 5 0 0 -50 0 50 100 0 150 5 10 Temperature (C) Fig. 13 Fig. 14 Propagation Delay vs. Supply Voltage Falling Input, CLOAD = 1000pF 25 30 35 Propagation Delay vs. Temperature VSUPPLY = 15V CLOAD = 1000pF 35 40 Propagation Delay Time (ns) Propagation Delay Time (ns) 20 Supply Voltage (V) 45 35 30 25 20 15 10 5 0 0 5 10 15 20 25 30 30 Negative going input 25 20 15 Positve going input 10 5 0 -50 35 0 Supply Voltage (V) Fig. 16 Quiescent Current vs. Supply Voltage VIN = 0V 1 0.1 0.01 0 5 10 15 20 25 100 150 30 Quiescent Current vs. Temperature VSUPPLY = 15V 1000 Quiescent Current (uA) 10 50 Temeprature (C) Fig. 15 Quiesent Current (uA) 15 100 10 1 Non-inverting, Input= "0" Inverting Input = "1" 0.1 0.01 -50 35 Supply Voltage (V) -30 -10 10 30 50 70 Temperature (C) 7 90 110 130 150 IXDF504 / IXDI504 / IXDN504 Fig. 18 Fig. 17 Supply Current vs. Capacitive Load VSUPPLY = 5V 100 2MHz 100 Supply Current vs. Frequency VSUPPLY = 5V 10000pF 5400pF Supply Current (mA) Supply Current (mA) 1MHz 10 100kHz 1 10kHz 0.1 0.01 100 1000pF 10 100pF 1 0.1 0.01 1000 10 10000 1000 Fig. 20 Supply Current vs. Capacitive Load VSUPPLY = 15V Supply Current vs. Frequency VSUPPLY = 15V 1000 1000 10000pF 5400pF 1MHz Supply Current (mA) Supply Current (mA) 2MHz 100 100kHz 10 10kHz 1 0.1 0.01 100 100 1000pF 100pF 10 1 0.1 0.01 1000 10000 10 Load Capacitance (pF) Fig. 21 1000 100 1000 Fig. 22 Supply Current vs. Frequency VSUPPLY = 30V 1000 2MHz 10000pF 5400pF Supply Current (mA) 1MHz Supply Current (mA) 10000 Frequency (kHz) Supply Current vs. Capacitive Load VSUPPLY = 30V 100 100kHz 10 10kHz 1 0.1 100 10000 Frequency (kHz) Load Capacitance (pF) Fig. 19 100 1000pF 100 100pF 10 1 0.1 1000 10000 10 Load Capacitance (pF) Copyright © 2007 IXYS CORPORATION All rights reserved 100 1000 Frequency (kHz) 8 10000 IXDF504 / IXDI504 / IXDN504 Fig. 23 Fig. 24 Output Source Current vs. Supply Voltage Output Sink Current vs. Supply Voltage 10 -2 Sink Current (A) 0 Source Current (A) 12 8 6 4 2 -4 -6 -8 -10 -12 0 -14 0 5 10 15 20 25 30 35 0 5 10 Supply Voltage (V) Fig. 25 Fig. 26 Output Source Current vs. Temperature VSUPPLY = 15V 30 35 Output Sink Current vs. Temperature VSUPPLY = 15V Output Sink Current (A) Output Source Current (A) 25 0 5 4 3 2 1 -1 -2 -3 -4 -5 -6 0 -50 0 50 100 -50 150 0 50 100 150 Temperature (C) Temperature (C) Fig. 28 High State Output Resistance vs. Supply Voltage 3 Low State Output Resistance vs. Supply Voltage 3 Output Resistance (ohms) Output Resistance (ohms) 20 Supply Voltage (V) 6 Fig. 27 15 2.5 2 1.5 1 0.5 0 2.5 2 1.5 1 0.5 0 0 5 10 15 20 25 30 35 0 Supply Voltage (V) 5 10 15 20 Supply Voltage (V) 9 25 30 35 IXDF504 / IXDI504 / IXDN504 Supply Bypassing, Grounding Practices And Output Lead inductance When designing a circuit to drive a high speed MOSFET utilizing the IXD_504, it is very important to observe certain design criteria in order to optimize performance of the driver. Particular attention needs to be paid to Supply Bypassing, Grounding, and minimizing the Output Lead Inductance. Say, for example, we are using the IXD_504 to charge a 2500pF capacitive load from 0 to 25 volts in 25ns. Using the formula: IC = C (∆V/∆t), where ∆V=25V C=2500pF & ∆t=25ns, we can determine that to charge 2500pF to 25 volts in 25ns will take a constant current of 2.5A. (In reality, the charging current won’t be constant and will peak somewhere around 4A). SUPPLY BYPASSING In order for our design to turn the load on properly, the IXD_504 must be able to draw this 2.5A of current from the power supply in the 25ns. This means that there must be very low impedance between the driver and the power supply. The most common method of achieving this low impedance is to bypass the power supply at the driver with a capacitance value that is an order of magnitude larger than the load capacitance. Usually, this would be achieved by placing two different types of bypassing capacitors, with complementary impedance curves, very close to the driver itself. (These capacitors should be carefully selected and should have low inductance, low resistance and high-pulse current-service ratings). Lead lengths may radiate at high frequency due to inductance, so care should be taken to keep the lengths of the leads between these bypass capacitors and the IXD_504 to an absolute minimum. GROUNDING In order for the design to turn the load off properly, the IXD_504 must be able to drain this 2.5A of current into an adequate grounding system. There are three paths for returning current that need to be considered: Path #1 is between the IXD_504 and its load. Path #2 is between the IXD_504 and its power supply. Path #3 is between the IXD_504 and whatever logic is driving it. All three of these paths should be as low in resistance and inductance as possible, and thus as short as practical. In addition, every effort should be made to keep these three ground paths distinctly separate. Otherwise, the returning ground current from the load may develop a voltage that would have a detrimental effect on the logic line driving the IXD_504. OUTPUT LEAD INDUCTANCE Of equal importance to Supply Bypassing and Grounding are issues related to the Output Lead Inductance. Every effort should be made to keep the leads between the driver and its load as short and wide as possible. If the driver must be placed farther than 0.2” (5mm) from the load, then the output leads should be treated as transmission lines. In this case, a twistedpair should be considered, and the return line of each twisted pair should be placed as close as possible to the ground pin of the driver, and connected directly to the ground terminal of the load. Copyright © 2007 IXYS CORPORATION All rights reserved 10 IXDF504 / IXDI504 / IXDN504 A2 b b2 b3 c D D1 E E1 e eA eB L E H B C D E e H h L M N D A A1 e B h X 45 N L C ] 0.018 [0.47] 0.137 [3.48] IXYS Corporation 3540 Bassett St; Santa Clara, CA 95054 Tel: 408-982-0700; Fax: 408-496-0670 e-mail: [email protected] www.ixys.com 0.120 [3.05] 0.020 [0.51] [ S0.002^0.000; o S0.05^0.00;o 0.039 [1.00] 0.035 [0.90] 0.157±0.005 [3.99±0.13] 0.197±0.005 [5.00±0.13] 0.019 [0.49] M 0.100 [2.54] IXYS Semiconductor GmbH Edisonstrasse15 ; D-68623; Lampertheim Tel: +49-6206-503-0; Fax: +49-6206-503627 e-mail: [email protected] 11