Fairchild FAN3268 2a low-voltage pmos-nmos bridge driver Datasheet

FAN3268
2A Low-Voltage PMOS-NMOS Bridge Driver
Features
Description


4.5V to 18V Operating Range

Inverting Channel B Biases High-Side PMOS
Device Off (with internal 100kΩ Resistor) when
VDD is below UVLO Threshold






TTL Input Thresholds
The FAN3268 dual 2A gate driver is optimized to drive a
high-side P-channel MOSFET and a low-side N-channel
MOSFET in motor control applications operating from a
voltage rail up to 18V. The driver has TTL input
thresholds and provides buffer and level translation
functions from logic inputs. Internal circuitry provides an
under-voltage lockout function that prevents the output
switching devices from operating if the VDD supply
voltage is below the operating level. Internal 100kΩ
resistors bias the non-inverting output low and the
inverting output to VDD to keep the external MOSFETs
off during startup intervals when logic control signals
may not be present.
Drives High-Side PMOS and Low-Side NMOS in
Motor Control or Buck Step-down Applications
2.4A Sink / 1.6A Source at VOUT=6V
Internal Resistors Turn Driver Off If No Inputs
MillerDrive™ Technology
8-Lead SOIC Package
The FAN3268 driver incorporates MillerDrive™
architecture for the final output stage. This bipolarMOSFET combination provides high current during the
Miller plateau stage of the MOSFET turn-on / turn-off
process to minimize switching loss, while providing railto-rail voltage swing and reverse current capability.
Rated from –40°C to +125°C Ambient
Applications

Motor Control with PMOS / NMOS Half-Bridge
Configuration

Buck Converters with High-Side PMOS Device;
100% Duty Cycle Operation Possible

Logic-Controlled Load Circuits with High-Side
PMOS Switch
The FAN3268 has two independent enable pins that
default to on if not connected. If the enable pin for noninverting channel A is pulled low, OUTA is forced low; if
the enable pin for inverting channel B is pulled low,
OUTB is forced high. If an input is left unconnected,
internal resistors bias the inputs such that the external
MOSFETs are off.
Figure 1. Typical Motor Drive Application
© 2009 Fairchild Semiconductor Corporation
FAN3268 • Rev. 1.0.1
www.fairchildsemi.com
1
FAN3268 —2A Low-Voltage PMOS-NMOS Bridge Driver
January 2011
Part Number
FAN3268TMX
Logic
Input Threshold
Packing Method
TTL
2,500 Units on
Tape & Reel
Non-Inverting Channel and Inverting
Channel + Dual Enables
Package Outline
Figure 2. Pin Configuration (Top View)
Thermal Characteristics(1)
Package
8-Pin Small Outline Integrated Circuit (SOIC)
JL(2)
JT(3)
JA(4)
JB(5)
JT(6)
Units
40
31
89
43
3
°C/W
FAN3268 —2A Low-Voltage PMOS-NMOS Bridge Driver
Ordering Information
Notes:
1.
2.
3.
4.
5.
6.
Estimates derived from thermal simulation; actual values depend on the application.
Theta_JL (JL): Thermal resistance between the semiconductor junction and the bottom surface of all the leads (including any
thermal pad) that are typically soldered to a PCB.
Theta_JT (JT): Thermal resistance between the semiconductor junction and the top surface of the package, assuming it is
held at a uniform temperature by a top-side heatsink.
Theta_JA (ΘJA): Thermal resistance between junction and ambient, dependent on the PCB design, heat sinking, and airflow.
The value given is for natural convection with no heatsink using a 2S2P board, as specified in JEDEC standards JESD51-2,
JESD51-5, and JESD51-7, as appropriate.
Psi_JB (JB): Thermal characterization parameter providing correlation between semiconductor junction temperature and an
application circuit board reference point for the thermal environment defined in Note 4. For the SOIC-8 package, the board
reference is defined as the PCB copper adjacent to pin 6.
Psi_JT (JT): Thermal characterization parameter providing correlation between the semiconductor junction temperature and
the center of the top of the package for the thermal environment defined in Note 4.
© 2009 Fairchild Semiconductor Corporation
FAN3268 • Rev. 1.0.1
www.fairchildsemi.com
2
Pin#
Name
1
ENA
Enable Input for Channel A. Pull pin low to inhibit driver A. ENA has TTL thresholds.
8
ENB
Enable Input for Channel B. Pull pin low to inhibit driver B. ENB has TTL thresholds.
3
GND
Ground. Common ground reference for input and output circuits.
2
INA
Input to Channel A.
4
INB
Input to Channel B.
7
OUTA
Gate Drive Output A: Held low unless required input(s) are present and VDD is above the UVLO
threshold.
OUTB
Gate Drive Output B (inverted from the input): Held high unless required input is present and VDD
is above UVLO threshold.
5
6
VDD
Description
Supply Voltage. Provides power to the IC.
Output Logic
FAN3268 (Channel A)
ENA
0
INA
FAN3268 (Channel B)
OUTA
(7)
0
0
ENB
0
INB
(7)
0
OUTB
1
0
1
0
0
1
1
1(7)
0(7)
0
1(7)
0(7)
1
1(7)
1
1
1(7)
1
0
FAN3268 —2A Low-Voltage PMOS-NMOS Bridge Driver
Pin Definitions
Note:
7. Default input signal if no external connection is made.
© 2009 Fairchild Semiconductor Corporation
FAN3268 • Rev. 1.0.1
www.fairchildsemi.com
3
VDD
VDD
100k
100k
ENA 1
INA
8
ENB
7
OUTA
6
VDD
5
OUTB
2
100k
100k
GND 3
UVLO
VDD_OK
FAN3268 —2A Low-Voltage PMOS-NMOS Bridge Driver
Block Diagram
100k
INB
4
100k
Figure 3. Block Diagram
© 2009 Fairchild Semiconductor Corporation
FAN3268 • Rev. 1.0.1
www.fairchildsemi.com
4
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Symbol
Parameter
Min.
Max.
Unit
-0.3
20.0
V
VDD
VDD to PGND
VEN
ENA, ENB to GND
GND - 0.3 VDD + 0.3
V
VIN
INA, INB to GND
GND - 0.3 VDD + 0.3
V
OUTA, OUTB to GND
GND - 0.3 VDD + 0.3
V
VOUT
TL
Lead Soldering Temperature (10 Seconds)
TJ
Junction Temperature
TSTG
Storage Temperature
ESD
Electrostatic Discharge
Protection Level
+260
ºC
-55
+150
ºC
-65
+150
ºC
Human Body Model, JEDEC JESD22-A114
3.5
kV
2
kV
Charged Device Model, JEDEC JESD22-C101
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to Absolute Maximum Ratings.
Symbol
Parameter
Min.
Max.
Unit
4.5
18.0
V
VDD
Supply Voltage Range
VEN
Enable Voltage (ENA, ENB)
0
VDD
V
VIN
Input Voltage (INA, INB)
0
VDD
V
TA
Operating Ambient Temperature
-40
+125
ºC
FAN3268 —2A Low-Voltage PMOS-NMOS Bridge Driver
Absolute Maximum Ratings
Electrical Characteristics
Unless otherwise noted, VDD=12V and TJ=-40°C to +125°C. Currents are defined as positive into the device and
negative out of the device.
Symbol
Parameter
Conditions
Min.
Typ. Max.
Unit
SUPPLY
VDD
Operating Range
IDD
Supply Current Inputs / EN Not
Connected
VON
Turn-On Voltage
INA=ENA=VDD, INB=ENB=0V
VOFF
Turn-Off Voltage
INA=ENA=VDD, INB=ENB=0V
INPUT
4.5
18.0
V
0.75
1.20
mA
3.5
3.9
4.3
V
3.3
3.7
4.1
V
0.8
1.2
(8)
VIL
INx Logic Low Threshold
VIH
INx Logic High Threshold
VHYS
Logic Hysteresis Voltage
© 2009 Fairchild Semiconductor Corporation
FAN3268 • Rev. 1.0.1
0.2
V
1.6
2.0
V
0.4
0.8
V
www.fairchildsemi.com
5
Unless otherwise noted, VDD=12V and TJ=-40°C to +125°C. Currents are defined as positive into the device and
negative out of the device.
ENABLE
VENL
Enable Logic Low Threshold
EN from 5V to 0V
VENH
Enable Logic High Threshold
EN from 0V to 5V
VHYS
RPU
0.8
1.6
(9)
Logic Hysteresis Voltage
Enable Pull-up Resistance
1.2
(9)
V
2.0
V
0.4
V
100
kΩ
OUTPUT
Out Current, Mid-Voltage, Sinking(9)
Out at VDD/2,
CLOAD=0.1µF, f=1kHz
2.4
A
ISOURCE
Out Current, Mid-Voltage, Sourcing(9)
Out at VDD/2,
CLOAD=0.1µF, f=1kHz
-1.6
A
IPK_SINK
Out Current, Peak, Sinking(9)
CLOAD=0.1µF, f=1kHz
3
A
CLOAD=0.1µF, f=1kHz
-3
A
CLOAD=1000pF
12
22
ns
CLOAD=1000pF
9
17
ns
ISINK
(9)
IPK_SOURCE Out Current, Peak, Sourcing
tRISE
tFALL
tD1
tD2
Output Rise Time(10)
(10)
Output Fall Time
Propagation Delay
(10)
0 - 5VIN, 1V/ns Slew Rate
7
14
25
ns
Propagation Delay
(10)
0 - 5VIN, 1V/ns Slew Rate
10
19
34
ns
FAN3268 —2A Low-Voltage PMOS-NMOS Bridge Driver
Electrical Characteristics (Continued)
Notes:
8. EN inputs have TTL thresholds; refer to the ENABLE section.
9. Not tested in production.
10. See the Timing Diagrams of Figure 4 and Figure 5.
Timing Diagrams
Figure 4. Non-Inverting
© 2009 Fairchild Semiconductor Corporation
FAN3268 • Rev. 1.0.1
Figure 5. Inverting
www.fairchildsemi.com
6
Typical characteristics are provided at TA=25°C and VDD=12V unless otherwise noted.
Figure 6. IDD (Static) vs. Supply Voltage(11)
Figure 7. IDD (No-Load) vs. Frequency
Figure 8. IDD (1nF Load) vs. Frequency
Figure 9. IDD (Static) vs. Temperature(11)
Figure 10. Input Thresholds vs. Supply Voltage
Figure 11. Input Thresholds vs. Temperature
© 2009 Fairchild Semiconductor Corporation
FAN3268 • Rev. 1.0.1
FAN3268 —2A Low-Voltage PMOS-NMOS Bridge Driver
Typical Performance Characteristics
www.fairchildsemi.com
7
Typical characteristics are provided at TA=25°C and VDD=12V unless otherwise noted.
Figure 12. UVLO Threshold vs. Temperature
Figure 13. Propagation Delays vs. Supply Voltage
Figure 14. Propagation Delays vs. Supply Voltage
Figure 15. Propagation Delays vs. Temperature
FAN3268 —2A Low-Voltage PMOS-NMOS Bridge Driver
Typical Performance Characteristics
Figure 16. Propagation Delays vs. Temperature
© 2009 Fairchild Semiconductor Corporation
FAN3268 • Rev. 1.0.1
www.fairchildsemi.com
8
Typical characteristics are provided at TA=25°C and VDD=12V unless otherwise noted.
Figure 17. Fall Time vs. Supply Voltage
Figure 18.
Rise Time vs. Supply Voltage
FAN3268 —2A Low-Voltage PMOS-NMOS Bridge Driver
Typical Performance Characteristics
Figure 19. Rise and Fall Times vs. Temperature
Figure 20. Rise/Fall Waveforms with 1nF Load
© 2009 Fairchild Semiconductor Corporation
FAN3268 • Rev. 1.0.1
Figure 21. Rise/Fall Waveforms with 10nF Load
www.fairchildsemi.com
9
Typical characteristics are provided at TA=25°C and VDD=12V unless otherwise noted.
Figure 22. Quasi-Static Source Current with VDD=12V
Figure 23. Quasi-Static Sink Current with VDD=12V
Figure 24. Quasi-Static Source Current with VDD=8V
Figure 25. Quasi-Static Sink Current with VDD=8V
FAN3268 —2A Low-Voltage PMOS-NMOS Bridge Driver
Typical Performance Characteristics
Note:
11. For any inverting inputs pulled low, non-inverting inputs pulled high, or outputs driven high, static IDD increases by
the current flowing through the corresponding pull-up/down resistor shown in the block diagram in Figure 3.
Test Circuit
Figure 26. Quasi-Static IOUT / VOUT Test Circuit
© 2009 Fairchild Semiconductor Corporation
FAN3268 • Rev. 1.0.1
www.fairchildsemi.com
10
Input Thresholds
The FAN3268 driver has TTL input thresholds and
provides buffer and level translation functions from logic
inputs. The input thresholds meet industry-standard
TTL-logic thresholds, independent of the VDD voltage,
and there is a hysteresis voltage of approximately 0.4V.
These levels permit the inputs to be driven from a range
of input logic signal levels for which a voltage over 2V is
considered logic high. The driving signal for the TTL
inputs should have fast rising and falling edges with a
slew rate of 6V/µs or faster, so a rise time from 0 to 3.3V
should be 550ns or less. With reduced slew rate, circuit
noise could cause the driver input voltage to exceed the
hysteresis voltage and retrigger the driver input, causing
erratic operation.
Figure 27. MillerDrive™ Output Architecture
Under-Voltage Lockout
Internal circuitry provides an under-voltage lockout
function that prevents the output switching devices from
operating if the VDD supply voltage is below the
operating level. When VDD is rising, but below the 3.9V
operational level, internal 100k resistors bias the noninverting output low and the inverting output to VDD to
keep the external MOSFETs off during startup intervals
when logic control signals may not be present. After the
part is active, the supply voltage must drop 0.2V before
the part shuts down. This hysteresis helps prevent
chatter when low VDD supply voltages have noise from
the power switching.
Static Supply Current
In the IDD (static) typical performance characteristics
(see Figure 6), the curve is produced with all inputs /
enables floating (OUT is low) and indicates the lowest
static IDD current for the tested configuration. For other
states, additional current flows through the 100k
resistors on the inputs and outputs shown in the block
diagram (see Figure 3). In these cases, the actual static
IDD current is the value obtained from the curves plus
this additional current.
FAN3268 —2A Low-Voltage PMOS-NMOS Bridge Driver
Applications Information
MillerDrive™ Gate Drive Technology
VDD Bypass Capacitor Guidelines
FAN3268 gate drivers incorporate the MillerDrive™
architecture shown in 0. For the output stage, a
combination of bipolar and MOS devices provide large
currents over a wide range of supply voltage and
temperature variations. The bipolar devices carry the
bulk of the current as OUT swings between one and two
thirds VDD and the MOS devices pull the output to the
high or low rail.
To enable this IC to turn a device on quickly, a local
high-frequency bypass capacitor CBYP with low ESR and
ESL should be connected between the VDD and GND
pins with minimal trace length. This capacitor is in
addition to bulk electrolytic capacitance of 10µF to 47µF
commonly found on driver and controller bias circuits.
A typical criterion for choosing the value of CBYP is to
keep the ripple voltage on the VDD supply to ≤5%. This is
often achieved with a value ≥20 times the equivalent
load capacitance CEQV, defined here as QGATE/VDD.
Ceramic capacitors of 0.1µF to 1µF or larger are
common choices, as are dielectrics, such as X5R and
X7R, with good temperature characteristics and high
pulse current capability.
The purpose of the MillerDrive™ architecture is to speed
up switching by providing high current during the Miller
plateau region when the gate-drain capacitance of the
MOSFET is being charged or discharged as part of the
turn-on / turn-off process.
For applications with zero voltage switching during the
MOSFET turn-on or turn-off interval, the driver supplies
high peak current for fast switching even though the
Miller plateau is not present. This situation often occurs
in synchronous rectifier applications because the body
diode is generally conducting before the MOSFET is
switched on.
If circuit noise affects normal operation, the value of
CBYP may be increased to 50-100 times the CEQV or CBYP
may be split into two capacitors. One should be a larger
value, based on equivalent load capacitance, and the
other a smaller value, such as 1-10nF mounted closest
to the VDD and GND pins to carry the higher frequency
components of the current pulses. The bypass capacitor
must provide the pulsed current from both of the driver
channels and, if the drivers are switching
simultaneously, the combined peak current sourced
from the CBYP would be twice as large as when a single
channel is switching.
The output pin slew rate is determined by VDD voltage
and the load on the output. It is not user adjustable, but
a series resistor can be added if a slower rise or fall time
at the MOSFET gate is needed.
© 2009 Fairchild Semiconductor Corporation
FAN3268 • Rev. 1.0.1
www.fairchildsemi.com
11
Operational Waveforms
The FAN3268 gate driver incorporates fast-reacting
input circuits, short propagation delays, and powerful
output stages capable of delivering current peaks over
2A to facilitate voltage transition times from under 10ns
to over 150ns. The following layout and connection
guidelines are strongly recommended:
Figure 28 shows startup waveforms for non-inverting
channel A. At power-up, the driver output for channel A
remains low until the VDD voltage reaches the UVLO turnon threshold, then OUTA operates in-phase with INA.

Keep high-current output and power ground paths
separate from logic and enable input signals and
signal ground paths. This is especially critical when
dealing with TTL-level logic thresholds at driver
inputs and enable pins.

Keep the driver as close to the load as possible to
minimize the length of high-current traces. This
reduces the series inductance to improve highspeed switching, while reducing the loop area that
can radiate EMI to the driver inputs and surrounding
circuitry.

If the inputs to a channel are not externally
connected, the internal 100k resistors indicated
on block diagrams command a low output (channel
A) or a high output (channel B). In noisy
environments, it may be necessary to tie inputs or
enables of an unused channel to VDD or GND
using short traces to prevent noise from causing
spurious output switching.

Many high-speed power circuits can be susceptible
to noise injected from their own output or other
external sources, possibly causing output retriggering. These effects can be obvious if the
circuit is tested in breadboard or non-optimal circuit
layouts with long input, enable, or output leads. For
best results, make connections to all pins as short
and direct as possible.

The turn-on and turn-off current paths should be
minimized.
Figure 28. Non-Inverting Startup Waveforms
Figure 29 illustrates startup waveforms for inverting
channel B. At power-up, the driver output for channel B
is tied to VDD through an internal 100kΩ resistor until the
VDD voltage reaches the UVLO turn-on threshold, then
OUTB operates out of phase with INB.
FAN3268 —2A Low-Voltage PMOS-NMOS Bridge Driver
Layout and Connection Guidelines
Figure 29. Inverting Startup Waveforms
© 2009 Fairchild Semiconductor Corporation
FAN3268 • Rev. 1.0.1
www.fairchildsemi.com
12
Gate drivers used to switch MOSFETs and IGBTs at
high frequencies can dissipate significant amounts of
power. It is important to determine the driver power
dissipation and the resulting junction temperature in the
application to ensure that the part is operating within
acceptable temperature limits.
The total power dissipation in a gate driver is the sum of
two components, PGATE and PDYNAMIC:
PTOTAL=PGATE + PDYNAMIC
(1)
(2)
where n is the number of driver channels in use
(1 or 2).
Dynamic Pre-drive / Shoot-through Current: A
power loss resulting from internal current
consumption under dynamic operating conditions,
including pin pull-up / pull-down resistors, can be
obtained using the “IDD (No-Load) vs. Frequency”
graphs in Typical Performance Characteristics to
determine the current IDYNAMIC drawn from VDD
under actual operating conditions:
PDYNAMIC=IDYNAMIC • VDD • n
(5)
PDYNAMIC=3mA • 7V • 2=0.042W
(6)
PTOTAL=0.46W
(7)
The SOIC-8 has a junction-to-board thermal
characterization parameter of JB=43°C/W. In a system
application, the localized temperature around the device
is a function of the layout and construction of the PCB
along with airflow across the surfaces. To ensure
reliable operation, the maximum junction temperature of
the device must be prevented from exceeding the
maximum rating of 150°C; with 80% derating, TJ would
be limited to 120°C. Rearranging Equation 4 determines
the board temperature required to maintain the junction
temperature below 120°C:
Gate Driving Loss: The most significant power loss
results from supplying gate current (charge per unit
time) to switch the load MOSFET on and off at the
switching frequency. The power dissipation that
results from driving a MOSFET at a specified gatesource voltage, VGS, with gate charge, QG, at
switching frequency, fSW , is determined by:
PGATE=QG • VGS • fSW • n
PGATE=60nC • 7V • 500kHz • 2=0.42W
TB=TJ - PTOTAL • JB
(8)
TB=120°C – 0.46W • 43°C/W=100°C
(9)
FAN3268 —2A Low-Voltage PMOS-NMOS Bridge Driver
As an example of a power dissipation calculation,
consider an application driving two MOSFETs with a
gate charge of 60nC with VGS=VDD=7V. At a switching
frequency of 500kHz, the total power dissipation is:
Thermal Guidelines
(3)
Once the power dissipated in the driver is determined,
the driver junction rise with respect to circuit board can
be evaluated using the following thermal equation,
assuming JB was determined for a similar thermal
design (heat sinking and air flow):
TJ
=PTOTAL • JB + TB
(4)
where:
TJ =driver junction temperature
JB =(psi) thermal characterization parameter relating
temperature rise to total power dissipation
TB =board temperature in location defined in
Note 1 under Thermal Resistance table.
© 2009 Fairchild Semiconductor Corporation
FAN3268 • Rev. 1.0.1
www.fairchildsemi.com
13
Related Products
Gate
Drive(12)
(Sink/Src)
Part
Number
Type
FAN3111C
Single 1A
+1.1A / -0.9A
CMOS
FAN3111E
Single 1A
+1.1A / -0.9A
External
FAN3100C
Single 2A
+2.5A / -1.8A
FAN3100T
Single 2A
FAN3226C
Input
Threshold
Logic
Package
Single Channel of Dual-Input/Single-Output
SOT23-5, MLP6
Single Non-Inverting Channel with External Reference
SOT23-5, MLP6
CMOS
Single Channel of Two-Input/One-Output
SOT23-5, MLP6
+2.5A / -1.8A
TTL
Single Channel of Two-Input/One-Output
SOT23-5, MLP6
Dual 2A
+2.4A / -1.6A
CMOS
Dual Inverting Channels + Dual Enable
SOIC8, MLP8
FAN3226T
Dual 2A
+2.4A / -1.6A
TTL
Dual Inverting Channels + Dual Enable
SOIC8, MLP8
FAN3227C
Dual 2A
+2.4A / -1.6A
CMOS
Dual Non-Inverting Channels + Dual Enable
SOIC8, MLP8
FAN3227T
Dual 2A
+2.4A / -1.6A
TTL
Dual Non-Inverting Channels + Dual Enable
SOIC8, MLP8
FAN3228C
Dual 2A
+2.4A / -1.6A
CMOS
Dual Channels of Two-Input/One-Output, Pin Config.1
SOIC8, MLP8
FAN3228T
Dual 2A
+2.4A / -1.6A
TTL
Dual Channels of Two-Input/One-Output, Pin Config.1
SOIC8, MLP8
FAN3229C
Dual 2A
+2.4A / -1.6A
CMOS
Dual Channels of Two-Input/One-Output, Pin Config.2
SOIC8, MLP8
FAN3229T
Dual 2A
+2.4A / -1.6A
TTL
Dual Channels of Two-Input/One-Output, Pin Config.2
SOIC8, MLP8
FAN3268T
Dual 2A
+2.4A / -1.6A
TTL
Non-Inverting Channel (NMOS) and Inverting Channel
(PMOS) + Dual Enables
SOIC8
FAN3223C
Dual 4A
+4.3A / -2.8A
CMOS
Dual Inverting Channels + Dual Enable
SOIC8, MLP8
FAN3223T
Dual 4A
+4.3A / -2.8A
TTL
Dual Inverting Channels + Dual Enable
SOIC8, MLP8
FAN3224C
Dual 4A
+4.3A / -2.8A
CMOS
Dual Non-Inverting Channels + Dual Enable
SOIC8, MLP8
FAN3224T
Dual 4A
+4.3A / -2.8A
TTL
Dual Non-Inverting Channels + Dual Enable
SOIC8, MLP8
FAN3225C
Dual 4A
+4.3A / -2.8A
CMOS
Dual Channels of Two-Input/One-Output
SOIC8, MLP8
FAN3225T
Dual 4A
+4.3A / -2.8A
TTL
Dual Channels of Two-Input/One-Output
SOIC8, MLP8
FAN3121C
Single 9A
+9.7A / -7.1A
CMOS
Single Inverting Channel + Enable
SOIC8, MLP8
FAN3121T
Single 9A
+9.7A / -7.1A
TTL
Single Inverting Channel + Enable
SOIC8, MLP8
FAN3122T
Single 9A
+9.7A / -7.1A
CMOS
Single Non-Inverting Channel + Enable
SOIC8, MLP8
FAN3122C
Single 9A
+9.7A / -7.1A
TTL
Single Non-Inverting Channel + Enable
SOIC8, MLP8
(13)
Notes:
12. Typical currents with OUT at 6V and VDD=12V.
13. Thresholds proportional to an externally supplied reference voltage.
© 2009 Fairchild Semiconductor Corporation
FAN3268 • Rev. 1.0.1
www.fairchildsemi.com
14
FAN3268 —2A Low-Voltage PMOS-NMOS Bridge Driver
Table 1.
5.00
4.80
A
0.65
3.81
5
8
B
6.20
5.80
PIN ONE
INDICATOR
1.75
4.00
3.80
1
5.60
4
1.27
(0.33)
0.25
M
1.27
C B A
LAND PATTERN RECOMMENDATION
0.25
0.10
SEE DETAIL A
1.75 MAX
0.25
0.19
C
0.10
0.51
0.33
0.50 x 45°
0.25
R0.10
C
OPTION A - BEVEL EDGE
GAGE PLANE
R0.10
OPTION B - NO BEVEL EDGE
0.36
NOTES: UNLESS OTHERWISE SPECIFIED
8°
0°
0.90
0.406
A) THIS PACKAGE CONFORMS TO JEDEC
MS-012, VARIATION AA, ISSUE C,
B) ALL DIMENSIONS ARE IN MILLIMETERS.
C) DIMENSIONS DO NOT INCLUDE MOLD
FLASH OR BURRS.
D) LANDPATTERN STANDARD: SOIC127P600X175-8M.
E) DRAWING FILENAME: M08AREV13
SEATING PLANE
(1.04)
DETAIL A
SCALE: 2:1
Figure 30. 8-Lead Small Outline Integrated Circuit (SOIC)
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/.
© 2009 Fairchild Semiconductor Corporation
FAN3268 • Rev. 1.0.1
www.fairchildsemi.com
15
FAN3268 —2A Low-Voltage PMOS-NMOS Bridge Driver
Physical Dimensions
FAN3268 —2A Low-Voltage PMOS-NMOS Bridge Driver
© 2009 Fairchild Semiconductor Corporation
FAN3268 • Rev. 1.0.1
www.fairchildsemi.com
16