Fairchild FIN3386 Low voltage 28-bit flat panel display link serializers/deserializer Datasheet

Revised April 2005
FIN3385 • FIN3383 •
FIN3384 • FIN3386
Low Voltage 28-Bit Flat Panel Display Link
Serializers/Deserializers
General Description
Features
The FIN3385 and FIN3383 transform 28 bit wide parallel
LVTTL (Low Voltage TTL) data into 4 serial LVDS (Low
Voltage Differential Signaling) data streams. A phaselocked transmit clock is transmitted in parallel with the data
stream over a separate LVDS link. Every cycle of transmit
clock 28 bits of input LVTTL data are sampled and transmitted.
■ Low power consumption
The FIN3386 and FIN3384 receive and convert the 4/3
serial LVDS data streams back into 28/21 bits of LVTTL
data. Refer to Table 1 for a matrix summary of the Serializers and Deserializers available. For the FIN3385, at a
transmit clock frequency of 85MHz, 28 bits of LVTTL data
are transmitted at a rate of 595Mbps per LVDS channel.
These chipsets are an ideal solution to solve EMI and cable
size problems associated with wide and high-speed TTL
interfaces.
■ Compatible with TIA/EIA-644 specification
■ 20 MHz to 85 MHz shift clock support
■ r1V common-mode range around 1.2V
■ Narrow bus reduces cable size and cost
■ High throughput (up to 2.38 Gbps throughput)
■ Internal PLL with no external component
■ Devices are offered 56-lead TSSOP packages
Ordering Code:
Package Number
Package Description
FIN3383MTD
Order Number
MTD56
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
FIN3384MTD
MTD56
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
FIN3385MTD
MTD56
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
FIN3386MTD
MTD56
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
TABLE 1. Display Panel Link Serializers/Deserializers Chip Matrix
Part
CLK Frequency
LVTTL IN
LVDS OUT
FIN3385
85
28
4
FIN3383
66
28
4
FIN3386
85
4
28
56 TSSOP
FIN3384
66
4
28
56 TSSOP
© 2005 Fairchild Semiconductor Corporation
DS500864
LVDS IN
LVTTL OUT
Package
56 TSSOP
56 TSSOP
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FIN3385 • FIN3383 • FIN3384 • FIN3386 Low Voltage 28-Bit Flat Panel Display Link Serializers/Deserializers
October 2003
FIN3385 • FIN3383 • FIN3384 • FIN3386
Block Diagrams
Functional Diagram for FIN3385 and FIN3383
Receiver Functional Diagram for FIN3386 and FIN3384
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2
FIN3385 • FIN3383 • FIN3384 • FIN3386
TRANSMITTERS
Pin Descriptions
Pin Names
I/O Type Number of Pins
TxIn
I
28/21
TxCLKIn
I
1
Description of Signals
LVTTL Level Input
LVTTL Level Clock Input
The rising edge is for data strobe.
TxOut
O
4/3
TxOut
O
4/3
Negative LVDS Differential Data Output
TxCLKOut
O
1
Positive LVDS Differential Clock Output
TxCLKOut
O
1
Negative LVDS Differential Clock Output
R_FB
I
1
Rising Edge Clock (HIGH), Falling Edge Clock (LOW)
PwrDn
I
1
LVTTL Level Power-Down Input
Assertion (LOW) puts the outputs in High Impedance state.
Power Supply Pin for PLL
Positive LVDS Differential Data Output
PLL VCC
I
1
PLL GND
I
2
Ground Pins for PLL
LVDS VCC
I
1
Power Supply Pin for LVDS Output
LVDS GND
I
3
Ground Pins for LVDS Output
VCC
I
3
Power Supply Pins for LVTTL Input
GND
I
5
Ground pins for LVTTL Input
NC
No Connect
Connection Diagram
Truth Table
Inputs
FIN3383 and FIN3385 (28:4 Transmitter)
Pin Assignment for TSSOP
Outputs
TxIn
TxCLKIn
PwrDn
(Note 1)
TxOutr
Active
Active
H
L/H
L/H
Active
L/H/Z
H
L/H
X (Note 2)
F
Active
H
L
L/H
F
F
H
L
X (Note 2)
X
X
L
Z
Z
TxCLKOutr
H HIGH Logic Level
L LOW Logic Level
X Don’t Care
Z High Impedance
F Floating
Note 1: The outputs of the transmitter or receiver will remain in a
High Impedance state until VCC reaches 2V.
Note 2: TxCLKOutr will settle at a free running frequency when the
part is powered up, PwrDn is HIGH and the TxCLKIn is a steady logic
level (L/H/Z).
3
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FIN3385 • FIN3383 • FIN3384 • FIN3386
RECEIVERS
Pin Descriptions
Pin Names I/O Type
Number
of Pins
Description of Signals
RxIn
I
4/3
RxIn
I
4/3
Negative LVDS Differential Data Input
RxCLKIn
I
1
Negative LVDS Differential Clock Input
Positive LVDS Differential Clock Input
Positive LVDS Differential Data Input
RxCLKIn
I
1
RxOut
O
28/21
RxCLKOut
O
1
LVTTL Clock Output
PwrDn
I
1
LVTTL Level Input
Refer to Transmitter and Receiver Power-Up and Power-Down Operation Truth Table
Power Supply Pin for PLL
LVTTL Level Data Output
Goes HIGH for PwrDn LOW
PLL VCC
I
1
PLL GND
I
2
Ground Pins for PLL
LVDS VCC
I
1
Power Supply Pin for LVDS Input
LVDS GND
I
3
Ground Pins for LVDS Input
VCC
I
4
Power Supply for LVTTL Output
GND
I
5
Ground Pin for LVTTL Output
NC
No Connect
Connection Diagram
FIN3386 and FIN3384 (4:28 Receiver)
Pin Assignment for TSSOP
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4
The outputs of the transmitter remain in the High-Impedance state until the power supply reaches 2V. The following table
shows the operation of the transmitter during power-up and power-down and operation of the PwrDn pin.
Transmitter
PwrDn
Normal
VCC
2V
!2V
!2V
!2V
TxIn
X
X
Active
Active
!2V
!2V
TxOut
Z
Z
Active
X
TxCLKIn
X
X
Active
H/L/Z
TxCLKOutr
Z
Z
Active
(Note 3)
PwrDn
L
L
H
H
H
H
(Note 4)
Receiver
PwrDn
RxInr
X
X
Active
Active
(Note 4)
RxOut
Z
L
L/H
P
H
P
RxCLKInr
X
X
Active
(Note 4)
Active
(Note 4)
RxCLKOut
Z
(Note 5)
Active
(Note 5)
(Note 5)
(Note 5)
PwrDn
L
L
H
H
H
H
VCC
2V
2V
2V
2V
2V
2V
H HIGH Logic Level
L LOW Logic Level
P Last Valid State
X Don’t Care
Z High-Impedance
Note 3: If the transmitter is powered up and PwrDn is inactive HIGH and the clock input goes to any state LOW, HIGH, or Z then the internal PLL will go to a
known low frequency and stay until the clock starts normal operation again.
Note 4: If the input is terminated and un-driven (Z) or shorted or open. (fail safe condition)
Note 5: For PwrDn or fail safe condition the RxCLKOut pin will go LOW for Panel Link devices and HIGH for Channel Link devices.
Note 6: Shorted here means (r inputs are shorted to each other, or r inputs are shorted to each other and Ground or VCC, or either r inputs are shorted to
Ground or VCC) with no other Current/Voltage sources (noise) applied. If the VID is still in the valid range (greater than 100mV) and VCM is in the valid range
(0V to 2.4V) then the input signal is still recognized and the part will respond normally.
5
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FIN3385 • FIN3383 • FIN3384 • FIN3386
Transmitter and Receiver Power-Up/Power-Down Operation Truth Table
FIN3385 • FIN3383 • FIN3384 • FIN3386
Absolute Maximum Ratings(Note 7)
Recommended Operating
Conditions
Power Supply Voltage (VCC)
-0.3V to +4.6V
TTL/CMOS Input/Output Voltage
0.5V to 4.6V
Supply Voltage (VCC)
LVDS Input/Output Voltage
-0.3V to +4.6V
Operating Temperature (TA)(Note 7)
LVDS Output Short Circuit Current (IOSD)
Storage Temperature Range (TSTG)
Maximum Junction Temperature (TJ)
Continuous
Maximum Supply Noise Voltage
65qC to 150qC
150qC
(VCCNPP)
Lead Temperature (TL)
ESD Rating (HBM, 1.5 k:, 100 pF)
!10.0 kV
!6.5 kV
!400V
I/O to GND
All Pins
ESD Rating (MM, 0:, 200 pF)
100 mVP-P (Note 8)
Note 7: Absolute maximum ratings are DC values beyond which the device
may be damaged or have its useful life impaired. The datasheet specifications should be met, without exception, to ensure that the system design is
reliable over its power supply, temperature, and output/input loading variables. Fairchild does not recommend operation outside datasheet specifications.
260qC
(Soldering, 4 seconds)
3.0V to 3.6V
10°C to 70°C
Note 8: 100mV VCC noise should be tested for frequency at least up to
2 MHz. All the specification below should be met under such a noise.
Transmitter DC Electrical Characteristics
Over supply voltage and operating temperature ranges, unless otherwise specified. (Note 9)
Symbol
Parameter
Test Conditions
Min
Typ
Max
Units
V
Transmitter LVTTL Input Characteristics
VIH
Input High Voltage
2.0
VCC
VIL
Input Low Voltage
GND
0.8
V
VIK
Input Clamp Voltage
0.79
1.5
V
IIN
Input Current
1.8
10.0
IIK
18 mA
VIN
0.4V to 4.6V
VIN
GND
10.0
0
250
TBD
PA
Transmitter LVDS Output Characteristics (Note 10)
VOD
Output Differential Voltage
'VOD
VOD Magnitude Change from Differential LOW-to-HIGH
VOS
Offset Voltage
'VOS
Offset Magnitude Change from Differential LOW-to-HIGH
IOS
Short Circuit Output Current
VOUT
IOZ
Disabled Output Leakage Current
DO
RL
100 :, See Figure 1
1.125
1.25
450
mV
35.0
mV
1.375
V
mV
3.5
5.0
mA
0V
r1.0
r10.0
PA
32.5 MHz
31.0
49.5
40.0 MHz
32.0
55.0
66.0 MHz
37.0
60.5
85.0 MHz
42.0
66.0
10.0
55.0
32.5 MHz
29.0
41.8
0V
0V to 4.6V, PwrDn
Transmitter Supply Current
ICCWT
28:4 Transmitter Power Supply Current
100 :,
for Worst Case Pattern (With Load)
RL
(Note 11)
See Figure 3
ICCPDT
Powered Down Supply Current
ICCGT
28:4 Transmitter Supply Current
PwrDn
for 16 Grayscale (Note 11)
Note 9: All Typical values are at TA
25qC and with VCC
0.8V
See Figure 21
40.0 MHz
30.0
44.0
(Note 12)
65.0 MHz
35.0
49.5
85.0 MHz
39.0
55.0
mA
PA
mA
3.3V.
Note 10: Positive current values refer to the current flowing into device and negative values means current flowing out of pins. Voltage are referenced to
ground unless otherwise specified (except 'VOD and VOD).
Note 11: The power supply current for both transmitter and receiver can be different with the number of active I/O channels.
Note 12: The 16-grayscale test pattern tests device power consumption for a “typical” LCD display pattern. The test pattern approximates signal switching
needed to produce groups of 16 vertical strips across the display.
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6
Over supply voltage and operating temperature ranges, unless otherwise specified.
Symbol
Parameter
tTCP
Transmit Clock Period
tTCH
Transmit Clock (TxCLKIn) HIGH Time
tTCL
Transmit Clock Low Time
tCLKT
TxCLKIn Transition Time (Rising and Failing)
tJIT
TxCLKIn Cycle-to-Cycle Jitter
tXIT
TxIn Transition Time
Test Conditions
See Figure 5
(10% to 90%) See Figure 6
Min
Typ
Max
Units
11.76
T
50.0
ns
0.35
0.5
0.65
T
0.35
0.5
0.65
T
6.0
ns
1.0
1.5
3.0
ns
6.0
ns
LVDS Transmitter Timing Characteristics
tTLH
Differential Output Rise Time (20% to 80%)
tTHL
Differential Output Fall Time (80% to 20%)
See Figure 4
0.75
1.5
ns
0.75
1.5
ns
tSTC
TxIn Setup to TxCLNIn
tHTC
TxIn Holds to TCLKIn
tTPDD
Transmitter Power-Down Delay
See Figure 12, (Note 13)
tTCCD
Transmitter Clock Input to Clock Output Delay
(TA
Transmitter Clock Input to Clock Output Delay
See Figure 9
2.8
0.25
0
0.25
ns
See Figure 16
a0.25
a
a0.25
ns
1
2a0.25
2a
2a0.25
ns
fx7
3a0.25
3a
3a0.25
ns
Transmitter Output Data Jitter (f
See Figure 5 (f
2.5
85 MHz)
25qC and with VCC
ns
0
ns
100
3.3V)
5.5
6.8
ns
ns
40 MHz) (Note 14)
tTPPB0
Transmitter Output Pulse Position of Bit 0
tTPPB1
Transmitter Output Pulse Position of Bit 1
tTPPB2
Transmitter Output Pulse Position of Bit 2
tTPPB3
Transmitter Output Pulse Position of Bit 3
tTPPB4
Transmitter Output Pulse Position of Bit 4
4a0.25
4a
4a0.25
ns
tTPPB5
Transmitter Output Pulse Position of Bit 5
5a0.25
5a
5a0.25
ns
tTPPB6
Transmitter Output Pulse Position of Bit 6
6a0.25
6a
6a0.25
ns
ns
Transmitter Output Data Jitter (f
a
65 MHz) (Note 14)
0.2
0
0.2
a0.2
a
a0.2
ns
1
2a0.2
2a
2a0.2
ns
fx7
3a0.2
3a
3a0.2
ns
4a0.2
4a
4a0.2
ns
Transmitter Output Pulse Position of Bit 5
5a0.2
5a
5a0.2
ns
Transmitter Output Pulse Position of Bit 6
6a0.2
6a
6a0.2
ns
ns
tTPPB0
Transmitter Output Pulse Position of Bit 0
tTPPB1
Transmitter Output Pulse Position of Bit 1
tTPPB2
Transmitter Output Pulse Position of Bit 2
tTPPB3
Transmitter Output Pulse Position of Bit 3
tTPPB4
Transmitter Output Pulse Position of Bit 4
tTPPB5
tTPPB6
Transmitter Output Data Jitter (f
See Figure 16
a
85 MHz) (Note 14)
0.2
0
0.2
a0.2
a
a0.2
ns
1
2a0.2
2a
2a0.2
ns
fx7
3a0.2
3a
3a0.2
ns
4a0.2
4a
4a0.2
ns
Transmitter Output Pulse Position of Bit 5
5a0.2
5a
5a0.2
ns
tTPPB6
Transmitter Output Pulse Position of Bit 6
6a0.2
6a
6a0.2
ns
tJCC
FIN3385 Transmitter Clock Out Jitter
40 MHz
350
370
tTPPB0
Transmitter Output Pulse Position of Bit 0
tTPPB1
Transmitter Output Pulse Position of Bit 1
tTPPB2
Transmitter Output Pulse Position of Bit 2
tTPPB3
Transmitter Output Pulse Position of Bit 3
tTPPB4
Transmitter Output Pulse Position of Bit 4
tTPPB5
tTPLLS
See Figure 16
a
f
(Cycle-to-Cycle)
f
65 MHz
210
230
See Figure 20
f
85 MHz
110
150
Transmitter Phase Lock Loop Set Time (Note 15)
See Figure 22, (Note 14)
10.0
ps
ms
Note 13: Outputs of all transmitters stay in 3-STATE until power reaches 2V. Both clock and data output begins to toggle 10ms after VCC reaches 3V and
Power-Down pin is above 1.5V.
Note 14: This output data pulse position works for TTL inputs except the LVDS output bit mapping difference (see Figure 14). Figure 16 shows the skew
between the first data bit and clock output. Also 2-bit cycle delay is guaranteed when the MSB is output from transmitter.
Note 15: This jitter specification is based on the assumption that PLL has a ref clock with cycle-to-cycle input jitter less than 2ns.
7
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FIN3385 • FIN3383 • FIN3384 • FIN3386
Transmitter AC Electrical Characteristics
FIN3385 • FIN3383 • FIN3384 • FIN3386
Receiver DC Electrical Characteristics
Over supply voltage and operating temperature ranges, unless otherwise specified. (Note 16)
Symbol
Parameter
Test Conditions
Min
Typ
Max
Units
V
LVTTL/CMOS DC Characteristics
VIH
Input High Voltage
2.0
VCC
VIL
Input Low Voltage
GND
0.8
VOH
Output High Voltage
IOH
0.4 mA
VOL
Output Low Voltage
IOL
VIK
Input Clamp Voltage
IIK
IIN
Input Current
VIN
IOFF
Input/Output Power Off Leakage Current
VCC
2.7
2mA
18 mA
3.3
0.06
0.3
0.79
1.5
V
10.0
PA
10.0
0V to 4.6V
0V,
All LVTTL Inputs/Outputs 0V to 4.6V
IOS
Output Short Circuit Current
VOUT
60.0
0V
V
V
V
r10.0
PA
120
mA
Receiver LVDS Input Characteristics
VTH
Differential Input Threshold HIGH
Figure 2, Table 2
VTL
Differential Input Threshold LOW
Figure 2, Table 2
VICM
Input Common Mode Range
Figure 2, Table 2
IIN
Input Current
VIN
2.4V, VCC
VIN
0V, VCC
100
100
mV
mV
0.05
3.6V or 0V
3.6V or 0V
2.35
V
r10.0
PA
r10.0
PA
Receiver Supply Current
ICCWR
4:28 Receiver Power Supply Current
for Worst Case Pattern (With Load)
CL
8 pF,
(Note 17)
See Figure 3
32.5 MHz
70.0
40.0 MHz
75.0
66.0 MHz
114
85.0 MHz
ICCWR
3:21 Receiver Power Supply Current
mA
135
32.5 MHz
49.0
60.0
for Worst Case Pattern (With Load)
CL
(Note 17)
See Figure 3
ICCPDT
Powered Down Supply Current
PwrDn
tRCOP
Receiver Clock Output (RxCLKOut) Period
tRCOL
RxCLKOut LOW Time
See Figure 8
4.0
5.0
6.0
ns
tRCOH
RxCLKOut HIGH Time
(f
4.5
5.0
6.5
ns
tRSRC
RxOut Valid Prior to RxCLKOut
(Rising Edge Strobe)
tRHRC
RxOut Valid After RxCLKOut
tROLH
Output Rise Time (20% to 80%)
CL
tROHL
Output Fall Time (80% to 20%)
See Figure 4
tRCCD
Receiver Clock Input to Clock Output Delay
See Figure 20, (Note 18)
8 pF,
40.0 MHz
53.0
65.0
66.0 MHz
78.0
100
85.0 MHz
90.0
115
NA
55.0
T
50.0
0.8V (RxOut stays LOW)
11.76
85MHz)
3.5
TA
25qC and VCC
3.3V
PA
ns
3.5
8 pF,
mA
ns
2.0
3.5
ns
1.8
3.5
ns
3.5
5.0
7.5
ns
tRPDD
Receiver Power-Down Delay
1.0
Ps
tRSPB0
Receiver Input Strobe Position of Bit 0
0.49
0.84
1.19
ns
tRSPB1
Receiver Input Strobe Position of Bit 1
2.17
2.52
2.87
ns
tRSPB2
Receiver Input Strobe Position of Bit 2
3.85
4.20
4.55
ns
tRSPB3
Receiver Input Strobe Position of Bit 3
5.53
5.88
6.23
ns
tRSPB4
Receiver Input Strobe Position of Bit 4
7.21
7.56
7.91
ns
tRSPB5
Receiver Input Strobe Position of Bit 5
8.89
9.24
9.59
ns
tRSPB6
Receiver Input Strobe Position of Bit 6
10.57
10.92
11.27
ns
tRSKM
RxIN Skew Margin
See Figure 17, (Note 19)
tRPLLS
Receiver Phase Lock Loop Set Time
See Figure 11
10.0
ms
See Figure 13
See Figure 17 (f
85MHz)
290
ps
Note 16: All Typical values are at TA 25qC and with V CC 3.3V. Positive current values refer to the current flowing into device and negative values means
current flowing out of pins. Voltage are referenced to ground unless otherwise specified (except 'VOD and VOD).
Note 17: The power supply current for the receiver can be different with the number of active I/O channels.
Note 18: Total channel latency from Sewrializer to deserializer is (T tTCCD). There is the clock period.
Note 19: Receiver skew margin is defined as the valid sampling window after considering potential setup/hold time and minimum/maximum bit position.
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8
Symbol
Parameter
Min
Typ
Max
Units
15.0
T
50.0
ns
10.0
11.0
ns
See Figure 8
10.0
12.2
ns
RxOut Valid Prior to RxCLKOut
(Rising Edge Strobe)
6.5
11.6
ns
RxOut Valid After RxCLKOut
(f
6.0
11.6
5.0
6.3
9.0
See Figure 8, (Note 20)
5.0
7.6
9.0
(Rising Edge Strobe)
4.5
7.3
4.0
6.3
tRCOP
Receiver Clock Output (RxCLKOut) Period
tRCOL
RxCLKOut LOW Time
tRCOH
RxCLKOut HIGH Time
tRSRC
tRHRC
tRCOL
RxCLKOut LOW Time
tRCOH
RxCLKOut HIGH Time
tRSRC
RxOut Valid Prior to RxCLKOut
Test Conditions
See Figure 8
40 MHz)
tRHRC
RxOut Valid After RxCLKOut
(f
tROLH
Output Rise Time (20% to 80%)
CL
66 MHz)
tROHL
Output Fall Time (80% to 20%)
See Figure 8
tRCCD
Receiver Clock Input to Clock Output Delay
8 pF, (Note 20)
See Figure 10, (Note 21)
25qC and VCC
TA
3.3V
ns
ns
ns
ns
ns
2.0
5.0
ns
1.8
5.0
ns
3.5
5.0
7.5
ns
1.0
Ps
tRPDD
Receiver Power-Down Delay
tRSPB0
Receiver Input Strobe Position of Bit 0
1.0
1.4
2.15
ns
tRSPB1
Receiver Input Strobe Position of Bit 1
4.5
5.0
5.8
ns
tRSPB2
Receiver Input Strobe Position of Bit 2
See Figure 17
8.1
8.5
9.15
ns
tRSPB3
Receiver Input Strobe Position of Bit 3
(f
11.6
11.9
12.6
ns
tRSPB4
Receiver Input Strobe Position of Bit 4
15.1
15.6
16.3
ns
tRSPB5
Receiver Input Strobe Position of Bit 5
18.8
19.2
19.9
ns
tRSPB6
Receiver Input Strobe Position of Bit 6
22.5
22.9
23.6
ns
tRSPB0
Receiver Input Strobe Position of Bit 0
0.7
1.1
1.4
ns
tRSPB1
Receiver Input Strobe Position of Bit 1
tRSPB2
Receiver Input Strobe Position of Bit2
See Figure 17
(f
See Figure 13
40 MHz)
3.3
3.6
ns
5.5
5.8
ns
tRSPB3
Receiver Input Strobe Position of Bit 3
tRSPB4
Receiver Input Strobe Position of Bit 4
tRSPB5
tRSPB6
tRSKM
RxIn Skew Margin
f
40 MHz
490
See Figure 17, (Note 22)
f
66 MHz
400
Receiver Phase Lock Loop Set Time
See Figure 11
tRPLLS
65 MHz)
2.9
5.1
7.3
7.7
8.0
ns
9.5
9.9
10.2
ns
Receiver Input Strobe Position of Bit 5
11.7
12.1
12.4
ns
Receiver Input Strobe Position of Bit 6
13.9
14.3
14.6
ns
ps
10.0
ms
Note 20: For the receiver with falling-edge strobe, the definition of setup/hold time will be slightly different from the one with rising-edge strobe. The clock reference point is the time when the clock falling edge passes through 2V. For hold time tRHRC, the clock reference point is the time when falling edge passes
through 0.8V.
Note 21: Total channel latency from Sewrializer to deserializer is (T tTCCD) (2*T tRCCD). There is the clock period.
Note 22: Receiver skew margin is defined as the valid sampling window after considering potential setup/hold time and minimum/maximum bit position.
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Receiver AC Electrical Characteristics (66MHz)
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FIGURE 1. Differential LVDS Output DC Test Circuit
Note A: For all input pulses, tR or tF 1 ns.
Note B: CL includes all probe and jig capacitance.
FIGURE 2. Differential Receiver Voltage Definitions and Propagation Delay and Transition Time Test Circuit
TABLE 2. Receiver Minimum and Maximum Input Threshold Test Voltages
Applied Voltages
(V)
VIA
VIB
Resulting Differential Input Voltage Resulting Common Mode Input Voltage
(mV)
(V)
VID
VIC
1.25
1.15
100
1.2
1.15
1.25
100
1.2
2.4
2.3
100
2.35
2.3
2.4
100
2.35
0.1
0
100
0.05
0
0.1
100
0.05
1.5
0.9
600
1.2
0.9
1.5
600
1.2
2.4
1.8
600
2.1
1.8
2.4
600
2.1
0.6
0
600
0.3
0
0.6
600
0.3
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Note: The worst case test pattern produces a maximum toggling of digital circuits, LVDS I/O and LVTTL/CMOS I/O. Depending on the valid strobe edge of
transmitter, the TxCLKIn can be either rising or falling edge data strobe.
FIGURE 3. “Worst Case” Test Pattern
FIGURE 4. Transmitter LVDS Output Load and Transition Times
FIGURE 5. Transmitter Setup/Hold and HIGH/LOW Times (Rising Edge Strobe)
FIGURE 6. Transmitter Input Clock Transition Time
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AC Loading and Waveforms
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AC Loading and Waveforms
(Continued)
FIGURE 7. Transmitter Outputs Channel-to-Channel Skew
Note: For the receiver with falling-edge strobe, the definition of setup/hold time will be slightly different from the one with rising-edge strobe. The clock reference point is the time when the clock falling edge passes through 2V. For hold time tRHRC, the clock reference point is the time when falling edge passes
through 0.8V.
FIGURE 8. (Receiver) Setup/Hold and HIGH/LOW Times
FIGURE 9. Transmitter Clock In to Clock Out Delay (Rising Edge Strobe)
FIGURE 10. Receiver Clock In to Clock Out Delay (Falling Edge Strobe)
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AC Loading and Waveforms
(Continued)
FIGURE 11. Receiver Phase Lock Loop Set Time
FIGURE 12. Transmitter Power-Down Delay
FIGURE 13. Receiver Power-Down Delay
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AC Loading and Waveforms
(Continued)
Note: The information in this diagram shows the relationship between clock out and the first data bit. A 2-bit cycle delay is guaranteed when the MSB is output from the transmitter.
FIGURE 14. 28 Parallel LVTTL Inputs Mapped to 4 Serial LVDS Outputs
Note: This output data pulse position works for both transmitter with 28 or 21 TTL inputs except the LVDS output bit mapping difference. All the information
in this diagram tells that the skew between the first data bit and clock output. Also 2-bit cycle delay is guaranteed when the MSB is output from transmitter.
FIGURE 15. 21 Parallel LVTTL Inputs Mapped to 3 Serial LVDS Outputs
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AC Loading and Waveforms
(Continued)
FIGURE 16. Transmitter Output Pulse Bit Position
FIGURE 17. Receiver Input Bit Position
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AC Loading and Waveforms
(Continued)
Note: tRSKM is the budget for the cable skew and source clock skew plus ISI (Inter-Symbol Interference).
Note: The minimum and maximum pulse position values are based on the bit position of each of the 7 bits within the LVDS data stream across PVT
(Process, Voltage Supply, and Temperature).
FIGURE 18. Receiver LVDS Input Skew Margin
Note: Test setup used considers no requirement for separation of RMS and deterministic jitter. Other hardware setup such as Wavecrest boxes can be used
if no M1 software is available, but the test methodology in Figure 20 should be followed.
FIGURE 19. Transmitter Clock Out Jitter Measurement Setup
Note: This jitter pattern is used to test the jitter response (Clock Out) of the device over the power supply range with worst jitter r3ns (cycle-to-cycle) clock
input. The specific test methodology is as follows:
•
Switching input data TxIn0 to TxIn20 at 0.5 MHz, and the input clock is shifted to left 3ns and to the right 3ns when data is HIGH.
•
The r3 ns cycle-to-cycle input jitter is the static phase error between the two clock sources. Jumping between two clock sources to simulate the worst
case of clock edge jump (3 ns) from graphical controllers. Cycle-to-cycle jitter at TxCLK out pin should be measured cross VCC range with 100mV noise
(VCC noise frequency 2 MHz).
FIGURE 20. Timing Diagram of Transmitter Clock Input with Jitter
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AC Loading and Waveforms
(Continued)
Note: The 16-grayscale test pattern tests device power consumption for a “typical” LCD display pattern. The test pattern approximates signal switching
needed to produce groups of 16 vertical strips across the display.
FIGURE 21. “16 Grayscale” Test Pattern
FIGURE 22. Transmitter Phase Lock Loop Time
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FIN3385 • FIN3383 • FIN3384 • FIN3386 Low Voltage 28-Bit Flat Panel Display Link Serializers/Deserializers
Physical Dimensions inches (millimeters) unless otherwise noted
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Package Number MTD56
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
2. A critical component in any component of a life support
device or system whose failure to perform can be reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the
user.
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