ASAHI KASEI [AK4384] AK4384 106dB 192kHz 24-Bit 2ch ∆Σ DAC GENERAL DESCRIPTION The AK4384 offers the perfect mix for cost and performance based audio systems. Using AKM's multi bit architecture for its modulator the AK4384 delivers a wide dynamic range while preserving linearity for improved THD+N performance. The AK4384 integrates a combination of SCF and CTF filters increasing performance for systems with excessive clock jitter. The 24 Bit word length and 192kHz sampling rate make this part ideal for a wide range of applications including DVD-Audio. The AK4384 is offered in a space saving 16pin TSSOP package. FEATURES o Sampling Rate Ranging from 8kHz to 192kHz o 128 times Oversampling (Normal Speed Mode) o 64 times Oversampling (Double Speed Mode) o 32 times Oversampling (Quad Speed Mode) o 24-Bit 8 times FIR Digital Filter o SCF with High Tolerance to Clock Jitter o 2nd order Analog LPF o Single Ended Output Buffer o Digital de-emphasis for 32k, 44.1k and 48kHz sampling o Soft mute o Digital Attenuator (Linear 256 steps) o I/F format: 24-Bit MSB justified, 24/20/16-Bit LSB justified or I2S o Master clock: 256fs, 384fs, 512fs, 768fs or 1152fs (Normal Speed Mode) 128fs, 192fs, 256fs or 384fs (Double Speed Mode) 128fs, 192fs (Quad Speed Mode) o THD+N: -94dB o Dynamic Range: 106dB o Power supply: 4.5 to 5.5V o Very Small Package: 16pin TSSOP (6.4mm x 5.0mm) MCLK P/S VDD SMUTE/CSN ACKS/CCLK De-emphasis Control µP Interface VSS Clock Divider VCOM DIF0/CDTI DZFL DZFR LRCK BICK SDTI Audio Data Interface ATT 8X Interpolator ∆Σ Modulator SCF LPF AOUTL ATT 8X Interpolator ∆Σ Modulator SCF LPF AOUTR PDN MS0176-E-00 2002/09 -1- ASAHI KASEI [AK4384] n Ordering Guide -40 ∼ +85°C 16pin TSSOP (0.65mm pitch) Evaluation Board for AK4384 AK4384VT AKD4384 n Pin Layout MCLK 1 16 DZFL BICK 2 15 DZFR SDTI 3 14 VDD LRCK 4 13 VSS PDN 5 12 VCOM SMUTE/CSN 6 11 AOUTL ACKS/CCLK 7 10 AOUTR DIF0/CDTI 8 9 P/S Top View PIN/FUNCTION No. 1 Pin Name MCLK I/O I 2 3 4 5 BICK SDTI LRCK PDN I I I I 6 SMUTE I 7 CSN ACKS I I CCLK DIF0 CDTI P/S I I I I 8 9 Function Master Clock Input Pin An external TTL clock should be input on this pin. Audio Serial Data Clock Pin Audio Serial Data Input Pin L/R Clock Pin Power-Down Mode Pin When at “L”, the AK4384 is in the power-down mode and is held in reset. The AK4384 should always be reset upon power-up. Soft Mute Pin in parallel mode “H”: Enable, “L”: Disable Chip Select Pin in serial mode Auto Setting Mode Pin in parallel mode “L”: Manual Setting Mode, “H”: Auto Setting Mode Control Data Clock Pin in serial mode Audio Data Interface Format Pin in parallel mode Control Data Input Pin in serial mode Parallel/Serial Select Pin (Internal pull-up pin) “L”: Serial control mode, “H”: Parallel control mode 10 AOUTR O Rch Analog Output Pin 11 AOUTL O Lch Analog Output Pin 12 VCOM O Common Voltage Pin, VDD/2 Normally connected to VSS with a 0.1µF ceramic capacitor in parallel with a 10µF electrolytic cap. 13 VSS Ground Pin 14 VDD Power Supply Pin 15 DZFR O Rch Data Zero Input Detect Pin 16 DZFL O Lch Data Zero Input Detect Pin Note: All input pins except pull-up pin should not be left floating. MS0176-E-00 2002/09 -2- ASAHI KASEI [AK4384] ABSOLUTE MAXIMUM RATINGS (VSS=0V; Note 1) Parameter Power Supply Input Current (any pins except for supplies) Input Voltage Ambient Operating Temperature Storage Temperature Symbol VDD IIN VIND Ta Tstg min -0.3 -0.3 -40 -65 max 6.0 ±10 VDD+0.3 85 150 Units V mA V °C °C Note: 1. All voltages with respect to ground. WARNING: Operation at or beyond these limits may results in permanent damage to the device. Normal operation is not guaranteed at these extremes. RECOMMENDED OPERATING CONDITIONS (VSS=0V; Note 1) Parameter Power Supply Symbol VDD min 4.5 typ 5.0 max 5.5 Units V *AKM assumes no responsibility for the usage beyond the conditions in this datasheet. MS0176-E-00 2002/09 -3- ASAHI KASEI [AK4384] ANALOG CHARACTERISTICS (Ta=25°C; VDD=5.0V; fs=44.1kHz; BICK=64fs; Signal Frequency=1kHz; 24bit Input Data; Measurement frequency=20Hz ∼ 20kHz; RL ≥5kΩ; unless otherwise specified) Parameter min typ max Resolution 24 (Note 3) Dynamic Characteristics THD+N fs=44.1kHz 0dBFS -94 -84 BW=20kHz -60dBFS -42 fs=96kHz 0dBFS -92 BW=40kHz -60dBFS -39 fs=192kHz 0dBFS -92 BW=40kHz -60dBFS -39 Dynamic Range (-60dBFS with A-weighted) (Note 4) 100 106 S/N (A-weighted) (Note 5) 100 106 Interchannel Isolation (1kHz) 90 100 Interchannel Gain Mismatch 0.2 0.5 DC Accuracy Gain Drift 100 Output Voltage (Note 6) 3.15 3.40 3.65 Load Resistance (Note 7) 5 Power Supplies Power Supply Current (VDD) 17 27 Normal Operation (PDN = “H”, fs≤96kHz) 20 32 Normal Operation (PDN = “H”, fs=192kHz) 10 100 Power-Down Mode (PDN = “L”) (Note 8) Notes: 3. Measured by Audio Precision (System Two). Refer to the evaluation board manual. 4. 100dB at 16bit data. 5. S/N does not depend on input bit length. 6. Full-scale voltage (0dB). Output voltage scales with the voltage of VREF, AOUT (typ.@0dB) = 3.4Vpp × VDD/5. 7. For AC-load. 8. All digital inputs including clock pins (MCLK, BICK and LRCK) are held VDD or VSS. MS0176-E-00 Units Bits dB dB dB dB dB dB dB dB dB dB ppm/°C Vpp kΩ mA mA µA 2002/09 -4- ASAHI KASEI [AK4384] SHARP ROLL-OFF FILTER CHARACTERISTICS (Ta = 25°C; VDD = 4.5 ∼ 5.5V; fs = 44.1kHz; DEM = OFF; SLOW = “0”) Parameter Symbol min Digital filter PB 0 Passband ±0.05dB (Note 9) -6.0dB Stopband (Note 9) SB 24.1 Passband Ripple PR Stopband Attenuation SA 54 Group Delay (Note 10) GD Digital Filter + LPF FR Frequency Response 20.0kHz fs=44.1kHz FR 40.0kHz fs=96kHz FR 80.0kHz fs=192kHz typ max Units 22.05 20.0 - kHz kHz kHz dB dB 1/fs ± 0.02 19.3 - dB ± 0.03 dB ± 0.03 dB ± 0.03 Notes: 9. The passband and stopband frequencies scale with fs(system sampling rate). For example, PB=0.4535×fs (@±0.05dB), SB=0.546×fs. 10. The calculating delay time which occurred by digital filtering. This time is from setting the 16/24bit data of both channels to input register to the output of analog signal. SLOW ROLL-OFF FILTER CHARACTERISTICS (Ta = 25°C; VDD = 4.5 ~ 5.5V; fs = 44.1kHz; DEM = OFF; SLOW = “1”) Parameter Symbol min typ max Units PB 0 39.2 18.2 8.1 - Digital Filter Passband ±0.04dB -3.0dB Stopband Passband Ripple Stopband Attenuation Group Delay (Note 11) (Note 11) SB PR SA GD (Note 10) 72 - 19.3 - kHz kHz kHz dB dB 1/fs - +0.02/-5 +0.02/-4 +0.02/-5 - dB dB dB typ - max 0.8 0.4 ± 10 Units V V V V µA ± 0.005 Digital Filter + LPF FR FR FR Note: 11. The passband and stopband frequencies scale with fs. For example, PB = 0.185×fs (@±0.04dB), SB = 0.888×fs. Frequency Response 20.0kHz 40.0kHz 80.0kHz fs=44.kHz fs=96kHz fs=192kHz DC CHARACTERISTICS (Ta=25°C; VDD=4.5 ∼ 5.5V) Parameter Symbol High-Level Input Voltage VIH Low-Level Input Voltage VIL High-Level Output Voltage (Iout=-80µA) VOH Low-Level Output Voltage (Iout=80µA) VOL Input Leakage Current (Note 12) Iin Note: 12. P/S pin has internal pull-up device, normally 100kΩ. MS0176-E-00 min 2.2 VDD-0.4 - - 2002/09 -5- ASAHI KASEI [AK4384] SWITCHING CHARACTERISTICS (Ta=25°C; VDD=4.5 ∼ 5.5V; CL=20pF) Parameter Symbol min fCLK 2.048 Master Clock Frequency Duty Cycle dCLK 40 LRCK Frequency Normal Speed Mode fsn 8 Double Speed Mode fsd 60 Quad Speed Mode fsq 120 Duty Cycle Duty 45 Audio Interface Timing BICK Period Normal Speed Mode 1/128fs tBCK Double/Quad Speed Mode 1/64fs tBCK 30 tBCKL BICK Pulse Width Low Pulse Width High 30 tBCKH BICK rising to LRCK Edge (Note 13) 20 tBLR LRCK Edge to BICK rising (Note 13) 20 tLRB SDTI Hold Time 20 tSDH SDTI Setup Time 20 tSDS Control Interface Timing CCLK Period tCCK 200 CCLK Pulse Width Low tCCKL 80 Pulse Width High tCCKH 80 CDTI Setup Time tCDS 40 CDTI Hold Time tCDH 40 CSN “H” Time tCSW 150 tCSS 50 CSN “↓” to CCLK “↑” tCSH 50 CCLK “↑” to CSN “↑” Reset Timing PDN Pulse Width (Note 14) tPD 150 Notes: 13. BICK rising edge must not occur at the same time as LRCK edge. 14. The AK4384 can be reset by bringing PDN= “L”. MS0176-E-00 typ 11.2896 max 36.864 60 Units MHz % 48 96 192 55 kHz kHz kHz % ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 2002/09 -6- ASAHI KASEI [AK4384] n Timing Diagram 1/fCLK VIH MCLK VIL tCLKH tCLKL dCLK=tCLKH x fCLK, tCLKL x fCLK 1/fs VIH LRCK VIL tBCK VIH BICK VIL tBCKH tBCKL Clock Timing VIH LRCK VIL tBLR tLRB VIH BICK VIL tSDS tSDH VIH SDTI VIL Serial Interface Timing MS0176-E-00 2002/09 -7- ASAHI KASEI [AK4384] VIH CSN VIL tCSS tCCKL tCCKH VIH CCLK VIL tCDS CDTI C1 tCDH C0 R/W VIH A4 VIL WRITE Command Input Timing tCSW VIH CSN VIL tCSH VIH CCLK CDTI VIL D3 D2 D1 D0 VIH VIL WRITE Data Input Timing tPD PDN VIL Power-down Timing MS0176-E-00 2002/09 -8- ASAHI KASEI [AK4384] OPERATION OVERVIEW n System Clock The external clocks, which are required to operate the AK4384, are MCLK, LRCK and BICK. The master clock (MCLK) should be synchronized with LRCK but the phase is not critical. The MCLK is used to operate the digital interpolation filter and the delta-sigma modulator. There are two methods to set MCLK frequency. In Manual Setting Mode (ACKS = “0”: Register 00H), the sampling speed is set by DFS0/1(Table 1). The frequency of MCLK at each sampling speed is set automatically. (Table 2~4).After exiting reset (PDN = “↑”), the AK4384 is in Auto Setting Mode. In Auto Setting Mode (ACKS = “1”: Default), as MCLK frequency is detected automatically (Table 5), and the internal master clock becomes the appropriate frequency (Table 6), it is not necessary to set DFS0/1. In parallel mode, the sampling speed can be set by only ACKS pin. The internal DFS0 andDFS1 bits are fixed to “0”. Therefore, when ACKS pin is “L”, the AK4384 operates in Normal Speed Mode. The AK4384 operates in Auto Setting Mode at ACKS = “H”. In parallel mode, the AK4384 does not support 128fs and 192fs of Double Speed Mode. All external clocks (MCLK,BICK and LRCK) should always be present whenever the AK4384 is in the normal operation mode (PDN= ”H”). If these clocks are not provided, the AK4384 may draw excess current and may fall into unpredictable operation. This is because the device utilizes dynamic refreshed logic internally. The AK4384 should be reset by PDN= “L” after threse clocks are provided. If the external clocks are not present, the AK4384 should be in the power-down mode (PDN= “L”). After exiting reset at power-up etc., the AK4384 is in the power-down mode until MCLK and LRCK are input. DFS1 DFS0 Sampling Rate (fs) 0 0 Normal Speed Mode 8kHz~48kHz 0 1 Double Speed Mode 60kHz~96kHz 1 0 Quad Speed Mode Default 120kHz~192kHz Table 1. Sampling Speed (Manual Setting Mode) LRCK fs 32.0kHz 44.1kHz 48.0kHz 256fs 8.1920MHz 11.2896MHz 12.2880MHz 384fs 12.2880MHz 16.9344MHz 18.4320MHz MCLK 512fs 16.3840MHz 22.5792MHz 24.5760MHz 768fs 24.5760MHz 33.8688MHz 36.8640MHz 1152fs 36.8640MHz N/A N/A BICK 64fs 2.0480MHz 2.8224MHz 3.0720MHz Table 2. System Clock Example (Normal Speed Mode @Manual Setting Mode) LRCK fs 88.2kHz 96.0kHz 128fs 11.2896MHz 12.2880MHz MCLK 192fs 256fs 16.9344MHz 22.5792MHz 18.4320MHz 24.5760MHz 384fs 33.8688MHz 36.8640MHz BICK 64fs 5.6448MHz 6.1440MHz Table 3. System Clock Example (Double Speed Mode @Manual Setting Mode) MS0176-E-00 2002/09 -9- ASAHI KASEI [AK4384] LRCK fs 176.4kHz 192.0kHz MCLK 128fs 192fs 22.5792MHz 33.8688MHz 24.5760MHz 36.8640MHz BICK 64fs 11.2896MHz 12.2880MHz Table 4. System Clock Example (Quad Speed Mode @Manual Setting Mode) MCLK 512fs 768fs 256fs 384fs 128fs 192fs Sampling Speed Normal Double Quad Table 5. Sampling Speed (Auto Setting Mode: Default) LRCK fs 32.0kHz 44.1kHz 48.0kHz 88.2kHz 96.0kHz 176.4kHz 192.0kHz 128fs 22.5792 24.5760 192fs 33.8688 36.8640 256fs 22.5792 24.5760 - MCLK (MHz) 384fs 512fs 16.3840 22.5792 24.5760 33.8688 36.8640 - 768fs 24.5760 33.8688 36.8640 - 1152fs 36.8640 - Sampling Speed Normal Double Quad Table 6. System Clock Example (Auto Setting Mode) n Audio Serial Interface Format Data is shifted in via the SDTI pin using BICK and LRCK inputs. The DIF0-2 as shown in Table 7 can select five serial data modes. In all modes the serial data is MSB-first, 2’s compliment format and is latched on the rising edge of BICK. Mode 2 can be used for 16/20 MSB justified formats by zeroing the unused LSBs. Mode 0 1 2 3 4 DIF2 0 0 0 0 1 DIF1 0 0 1 1 0 DIF0 0 1 0 1 0 SDTI Format 16bit LSB Justified 20bit LSB Justified 24bit MSB Justified 24bit I2S Compatible 24bit LSB Justified BICK ≥32fs ≥40fs ≥48fs ≥48fs ≥48fs Figure Figure 1 Figure 2 Figure 3 Figure 4 Figure 2 Default Table 7. Audio Data Formats (Serial mode) Mode 2 3 DIF0 0 1 SDTI Format 24bit MSB Justified 24bit I2S Compatible BICK ≥48fs ≥48fs Figure Figure 3 Figure 4 Table 8. Audio Data Formats (Parallel mode) MS0176-E-00 2002/09 - 10 - ASAHI KASEI [AK4384] LRCK 0 1 10 11 12 13 14 15 0 1 10 11 12 13 14 15 0 1 BICK (32fs) SDTI Mode 0 15 14 6 1 0 5 14 4 15 3 16 2 1 17 0 31 15 0 14 6 5 14 1 4 15 3 16 2 1 17 0 31 15 14 0 1 0 1 0 1 BICK (64fs) SDTI Mode 0 Don’t care 15 14 Don’t care 0 15 14 0 15:MSB, 0:LSB Lch Data Rch Data Figure 1. Mode 0 Timing LRCK 0 1 8 9 10 11 12 31 0 1 8 9 10 11 12 31 BICK (64fs) SDTI Mode 1 Don’t care 19 0 Don’t care 19 0 Don’t care 19 0 19 0 19:MSB, 0:LSB SDTI Mode 4 Don’t care 23 22 21 20 23 22 20 21 23:MSB, 0:LSB Lch Data Rch Data Figure 2. Mode 1,4 Timing LRCK 0 1 2 22 23 24 30 31 0 1 2 22 23 24 30 31 BICK (64fs) SDTI 23 22 1 0 Don’t care 23 22 1 0 Don’t care 23 22 23:MSB, 0:LSB Lch Data Rch Data Figure 3. Mode 2 Timing MS0176-E-00 2002/09 - 11 - ASAHI KASEI [AK4384] LRCK 0 1 2 3 23 24 25 31 0 1 2 3 23 24 25 31 0 1 BICK (64fs) SDTI 0 1 23 22 Don’t care 23 22 1 0 Don’t care 23 23:MSB, 0:LSB Lch Data Rch Data Figure 4. Mode 3 Timing n De-emphasis Filter A digital de-emphasis filter is available for 32, 44.1 or 48kHz sampling rates (tc = 50/15µs) and is enabled or disabled with DEM0 and DEM1. In case of double speed and quad speed mode, the digital de-emphasis filter is always off. DEM1 DEM0 Mode 0 0 1 1 0 1 0 1 44.1kHz OFF 48kHz 32kHz Default Table 9. De-emphasis Filter Control (Normal Speed Mode) n Output Volume The AK4384 includes channel independent digital output volumes (ATT) with 256 levels at linear step including MUTE. These volumes are in front of the DAC and can attenuate the input data from 0dB to –48dB and mute. When changing levels, transitions are executed via soft changes; thus no switching noise occurs during these transitions. The transition time of 1 level and all 256 levels is shown in Table 10. Sampling Speed Normal Speed Mode Double Speed Mode Quad Speed Mode Transition Time 1 Level 255 to 0 4LRCK 1020LRCK 8LRCK 2040LRCK 16LRCK 4080LRCK Table 10. ATT Transition Time MS0176-E-00 2002/09 - 12 - ASAHI KASEI [AK4384] n Zero Detection The AK4384 has channel-independent zeros detect function. When the input data at each channel is continuously zeros for 8192 LRCK cycles, DZF pin of each channel goes to “H”. DZF pin of each channel immediately goes to “L” if input data of each channel is not zero after going DZF “H”. If RSTN bit is “0”, DZF pins of both channels go to “H”. DZF pin of both channels go to “L” at 2~3/fs after RSTN bit returns to “1”. If DZFM bit is set to “1”, DZF pins of both channels go to “H” only when the input data at both channels are continuously zeros for 8192 LRCK cycles. Zero detect function can be disabled by DZFE bit. In this case, DZF pins of both channels are always “L”. DZFB bit can invert the polarity of DZF pin. n Soft Mute Operation Soft mute operation is performed at digital domain. When the SMUTE bit goes to “1”, the output signal is attenuated by -∞ during ATT_DATA×ATT transition time (Table 10) from the current ATT level. When the SMUTE bit is returned to “0”, the mute is cancelled and the output attenuation gradually changes to the ATT level during ATT_DATA×ATT transition time. If the soft mute is cancelled before attenuating to -∞ after starting the operation, the attenuation is discontinued and returned to ATT level by the same cycle. The soft mute is effective for changing the signal source without stopping the signal transmission. SMUTE bit ATT Level (1) (1) (3) Attenuation -∞ GD (2) GD AOUT DZF pin (4) 8192/fs Notes: (1) ATT_DATA×ATT transition time (Table 10). For example, in Normal Speed Mode, this time is 1020LRCK cycles (1020/fs) at ATT_DATA=255. (2) The analog output corresponding to the digital input has a group delay, GD. (3) If the soft mute is cancelled before attenuating to -∞ after starting the operation, the attenuation is discontinued and returned to ATT level by the same cycle. (4) When the input data at each channel is continuously zeros for 8192 LRCK cycles, DZF pin of each channel goes to “H”. DZF pin immediately goes to “L” if input data are not zero after going DZF “H”. Figure 5. Soft Mute and Zero Detection MS0176-E-00 2002/09 - 13 - ASAHI KASEI [AK4384] n System Reset The AK4384 should be reset once by bringing PDN= “L” upon power-up. The AK4384 is powered up and the internal timing starts clocking by LRCK “↑” after exiting reset and power down state by MCLK. The AK4384 is in the power-down mode until MCLK and LRCK are input. n Power-down The AK4384 is placed in the power-down mode by bringing PDN pin “L” and the anlog outputs are floating (Hi-Z). Figure 6 shows an example of the system timing at the power-down and power-up. PDN Internal State Normal Operation Power-down D/A In (Digital) Normal Operation “0” data GD D/A Out (Analog) (1) GD (3) (2) (3) (1) (4) Clock In Don’t care MCLK, LRCK, BICK DZFL/DZFR External MUTE (6) (5) Mute ON Notes: (1) The analog output corresponding to digital input has the group delay (GD). (2) Analog outputs are floating (Hi -Z) at the power-down mode. (3) Click noise occurs at the edge of PDN signal. This noise is output even if “0” data is input. (4) The external clocks (MCLK, BICK and LRCK) can be stopped in the power-down mode (PDN = “L”). (5) Please mute the analog output externally if the click noise (3) influences system application. The timing example is shown in this figure. (6) DZF pins are “L” in the power-down mode (PDN = “L”). Figure 6. Power-down/up Sequence Example MS0176-E-00 2002/09 - 14 - ASAHI KASEI [AK4384] n Reset Function When RSTN=0, DAC is powered down but the internal register values are not initialized. The analog outputs go to VCOM voltage and DZFL/DZFR pins go to “H”. Figure 7 shows the example of reset by RSTN bit. RSTN bit 3~4/fs (6) 2~3/fs (6) Internal RSTN bit Internal State Normal Operation D/A In (Digital) “0” data (1) D/A Out (Analog) Normal Operation Digital Block Power-down GD GD (3) (2) (3) (1) (4) Clock In Don’t care MCLK,LRCK,BICK 2/fs(5) DZF Notes: (1) The analog output corresponding to digital input has the group delay (GD). (2) Analog outputs go to VCOM voltage (VDD/2). (3) Click noise occurs at the edges(“↑ ↓”) of the internal timing of RSTN bit. This noise is output even if “0” data is input. (4) The external clocks (MCLK, BICK and LRCK) can be stopped in the reset mode (RSTN = “L”). (5) DZF pins go to “H” when the RSTN bit becomes “0”, and go to “L” at 2/fs after RSTN bit becomes “1”. (6) There is a delay, 3~4/fs from RSTN bit “0” to the internal RSTN bit “0”, and 2~3/fs from RSTN bit “1” to the internal RSTN “1”. Figure 7. Reset Sequence Example MS0176-E-00 2002/09 - 15 - ASAHI KASEI [AK4384] n Mode Control Interface Some function of the AK4384 can be controlled by pins (parallel control mode) shown in Table 11. The serial control interface is enabled by the P/S pin = “L”. Internal registers may be written by 3-wire µP interface pins, CSN, CCLK and CDTI. The data on this interface consists of Chip Address (2bits, C1/0; fixed to “01”), Read/Write (1bit; fixed to “1”, Write only), Register Address (MSB first, 5bits) and Control Data (MSB first, 8bits). AK4384 latches the data on the rising edge of CCLK, so data should clocked in on the falling edge. The writing of data becomes valid by CSN “↑”. The clock speed of CCLK is 5MHz (max). Function Parallel mode Serial mode X X O O X O O O O O Double sampling mode at 128/192fs De-emphasis SMUTE Zero Detection 16/20/24bit LSB justified format Table 11. . Function list (O: available, X: not available) PDN = “L” resets the registers to their default values. When the state of P/S pin is changed, the AK4384 should be reset by PDN= “L”. The internal timing circuit is reset by RSTN bit, but the registers are not initialized. CSN 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 CCLK CDTI C1 C0 R/W A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 C1-C0: R/W: A4-A0: D7-D0: Chip Address (Fixed to “01”) READ/WRITE (Fixed to “1”, Write only) Register Address Control Data Figure 8. Control I/F Timing *The AK4384 does not support the read command and chip address. C1/0 and R/W are fixed to “011” *When the AK4384 is in the power down mode (PDN = “L”) or the MCLK is not provided, writing into the control register is inhibited. n Register Map Addr 00H 01H 02H 03H 04H Register Name Control 1 Control 2 Control 3 Lch ATT Rch ATT D7 D6 D5 D4 D3 D2 D1 D0 ACKS DZFE 0 ATT7 ATT7 0 DZFM 0 ATT6 ATT6 0 SLOW 0 ATT5 ATT5 DIF2 DFS1 INVL ATT4 ATT4 DIF1 DFS0 INVR ATT3 ATT3 DIF0 DEM1 DZFB ATT2 ATT2 PW DEM0 0 ATT1 ATT1 RSTN SMUTE 0 ATT0 ATT0 Notes: For addresses from 05H to 1FH, data must not be written. When PDN pin goes “L”, the registers are initialized to their default values. When RSTN bit goes “0”, the only internal timing is reset and the registers are not initialized to their default values. All data can be written to the register even if PW or RSTN bit is “0”. MS0176-E-00 2002/09 - 16 - ASAHI KASEI [AK4384] n Register Definitions Addr 00H Register Name D7 D6 D5 D4 D3 D2 D1 D0 Control 1 ACKS 0 0 DIF2 DIF1 DIF0 PW RSTN default 1 0 0 0 1 0 1 1 RSTN: Internal timing reset control 0: Reset. All registers are not initialized. 1: Normal Operation When MCLK frequency or DFS changes, the AK4384 should be reset by PDN pin or RSTN bit. PW: Power down control 0: Power down. All registers are not initialized. 1: Normal Operation DIF2-0: Audio data interface formats (see Table 7) Initial: “010”, Mode 2 ACKS: Master Clock Frequency Auto Setting Mode Enable 0: Disable, Manual Setting Mode 1: Enable, Auto Setting Mode Master clock frequency is detected automatically at ACKS bit “1”. In this case, the setting of DFS1-0 are ignored. When this bit is “0”, DFS1-0 set the sampling speed mode. Addr 01H Register Name D7 D6 D5 D4 D3 D2 D1 D0 Control 2 DZFE DZFM SLOW DFS1 DFS0 DEM1 DEM0 SMUTE default 0 0 0 0 0 0 1 0 SMUTE: Soft Mute Enable 0: Normal operation 1: DAC outputs soft-muted DEM1-0: De-emphasis Response (see Table 9) Initial: “01”, OFF DFS1-0: Sampling speed control 00: Normal speed 01: Double speed 10: Quad speed When changing between Normal/Double Speed Mode and Quad Speed Mode, some click noise occurs. SLOW: Slow Roll-off Filter Enable 0: Sharp Roll-off Filter 1: Slow Roll-off Filter DZFE: Data Zero Detect Enable 0: Disable 1: Enable Zero detect function can be disabled by DZFE bit “0”. In this case, the DZF pins of both channels are always “L”. MS0176-E-00 2002/09 - 17 - ASAHI KASEI [AK4384] DZFM: Data Zero Detect Mode 0: Channel Separated Mode 1: Channel ANDed Mode If the DZFM bit is set to “1”, the DZF pins of both channels go to “H” only when the input data at both channels are continuously zeros for 8192 LRCK cycles. Addr 02H Register Name D7 D6 D5 D4 D3 D2 D1 D0 Control 3 0 0 0 INVL INVR DZFB 0 0 default 0 0 0 0 0 0 0 0 DZFB: Inverting Enable of DZF 0: DZF goes “H” at Zero Detection 1: DZF goes “L” at Zero Detection INVR: Inverting Lch Output Polarity 0: Normal Output 1: Inverted Output INVL: Inverting Rch Output Polarity 0: Normal Output 1: Inverted Output Addr 03H 04H Register Name Lch ATT Rch ATT default D7 ATT7 ATT7 D6 ATT6 ATT6 D5 ATT5 ATT5 D4 ATT4 ATT4 D3 ATT3 ATT3 D2 ATT2 ATT2 D1 ATT1 ATT1 D0 ATT0 ATT0 1 1 1 1 1 1 1 1 ATT = 20 log10 (ATT_DATA / 255) [dB] 00H: Mute MS0176-E-00 2002/09 - 18 - ASAHI KASEI [AK4384] SYSTEM DESIGN Figure 9 and 10 show the system connection diagram. An evaluation board (AKD4384) is available in order to allow an easy study on the layout of a surrounding circuit. Master Clock 1 MCLK DZFL 16 64fs 2 BICK DZFR 15 24bit Audio Data 3 SDTI VDD 14 fs Reset & Power down Mode Setting Digital Ground 0.1u VSS 13 VCOM 12 SMUTE AOUTL 11 7 ACKS AOUTR 10 8 DIF0 P/S 9 4 LRCK 5 PDN 6 AK4384 10u + Analog Supply 5V 10u + Lch MUTE Rch MUTE Lch Out MUTE Rch Out Analog Ground Figure 9. Typical Connection Diagram (Parallel Mode) Master Clock 1 MCLK DZFL 16 64fs 2 BICK DZFR 15 24bit Audio Data 3 SDTI VDD 14 4 LRCK VSS 13 5 PDN VCOM 12 6 CSN AOUTL 11 7 CCLK AOUTR 10 8 CDTI P/S 9 fs Reset & Power down Microcontroller Digital Ground 0.1u AK4384 10u + + Analog Supply 5V 10u Lch MUTE Rch MUTE Lch Out MUTE Rch Out Analog Ground Figure 10. Typical Connection Diagram (Serial Mode) Notes: - LRCK = fs, BICK = 64fs. - When AOUT drives some capacitive load, some resistor should be added in series between AOUT and capacitive load. - All input pins except pull-up pin should not be left floating. MS0176-E-00 2002/09 - 19 - ASAHI KASEI [AK4384] 1. Grounding and Power Supply Decoupling VDD and VSS are supplied from analog supply and should be separated from system digital supply. Decoupling capacitor, especially 0.1µF ceramic capacitor for high frequency should be placed as near to VDD as possible. The differential Voltage between VDD and VSS pins set the analog output range. 2. Analog Outputs The analog outputs are single-ended and centered around the VCOM voltage. The output signal range is typically 3.40Vpp (typ@VDD=5V). The phase of the analog outputs can be inverted channel independently by INVL/INVR bits. The internal switched-capacitor filter and continuous-time filter attenuate the noise generated by the delta-sigma modulator beyond the audio passband. The output voltage is a positive full scale for 7FFFFFH (@24bit) and a negative full scale for 800000H (@24bit). The ideal output is VCOM voltage for 000000H (@24bit). DC offsets on analog outputs are eliminated by AC coupling since analog outputs have DC offsets of VCOM + a few mV. Figure 11 shows an example of the external LPF with 2Vrms output. 820p 3.3k 2.2k +Vop 22u 1.5k Analog Out 1.8k AOUT 10k 820p -Vop fc=111.8kHz, Q=0.714, g=-0.04dB at 40kHz Figure 11. External 2nd order LPF Circuit Example (using op-amp with dual power supplies) MS0176-E-00 2002/09 - 20 - ASAHI KASEI [AK4384] PACKAGE 16pin TSSOP (Unit: mm) *5.0±0.1 9 A 8 1 0.13 M 6.4±0.2 *4.4±0.1 16 1.05±0.05 0.22±0.1 0.65 0.17±0.05 Detail A 0.5±0.2 0.1±0.1 Seating Plane 0.10 NOTE: Dimension "*" does not include mold flash. 0-10° n Package & Lead frame material Package molding compound: Lead frame material: Lead frame surface treatment: Epoxy Cu Solder(Pb free) plate MS0176-E-00 2002/09 - 21 - ASAHI KASEI [AK4384] MARKING AKM 4384VT XXYYY 1) 2) 3) 4) Pin #1 indication Date Code : XXYYY (5 digits) XX: Lot# YYY: Date Code Marketing Code : 4384VT Asahi Kasei Logo IMPORTANT NOTICE • These products and their specifications are subject to change without notice. Before considering any use or application, consult the Asahi Kasei Microsystems Co., Ltd. (AKM) sales office or authorized distributor concerning their current status. • AKM assumes no liability for infringement of any patent, intellectual property, or other right in the application or use of any information contained herein. • Any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. • AKM products are neither intended nor authorized for use as critical components in any safety, life support, or other hazard related device or system, and AKM assumes no responsibility relating to any such use, except with the express written consent of the Representative Director of AKM. As used here: (a) A hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. (b) A critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. • It is the responsibility of the buyer or distributor of an AKM product who distributes, disposes of, or otherwise places the product with a third party to notify that party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold AKM harmless from any and all claims arising from the use of said product in the absence of such notification. MS0176-E-00 2002/09 - 22 -