HFA3127/883 Ultra High Frequency Transistor Array February 1995 Features Description • This Circuit is Processed in Accordance to MIL-STD883 and is Fully Conformant Under the Provisions of Paragraph 1.2.1. The HFA3127/883 is an Ultra High Frequency Transistor Array fabricated on the Intersil Corporation complementary bipolar UHF-1 process. This array consists of five dielectrically isolated transistors on a common monolithic substrate. The high fT (8GHz) and low noise figure (3.5dB) of these transistors make them ideal for high frequency amplifier and mixer applications. • NPN Transistor (fT). . . . . . . . . . . . . . . . . . . . .8GHz (Typ) • NPN Current Gain . . . . . . . . . . . . . . . . . . . . . . . 40 (Min) • NPN Early Voltage (VA) . . . . . . . . . . . . . . . . . . . 20 (Min) The HFA3127/883 is an all-NPN array. Access is provided to each of the terminals of the individual transistors for maximum application flexibility. The monolithic construction of the array provides close electrical and thermal matching of the five transistors. • Noise Figure (50Ω) at 1.0GHz . . . . . . . . . . . 3.5dB (Typ) • Collector-to-Collector Leakage. . . . . . . . . . . <1pA (Typ) • Complete Isolation Between Transistors • Pin Compatible with Industry Standard 3XXX Series SMD 5962-9474901MEA version is also available from Intersil Corporation. Applications Ordering Information • VHF/UHF Amplifiers • VHF/UHF Mixers PART NUMBER • IF Converters HFA3127MJ/883 • Synchronous Detectors TEMPERATURE -55oC to +125oC PACKAGE 16 Lead CerDIP Pinout HFA3127/883 (CERDIP) TOP VIEW 16 1 Q1 2 14 3 4 Q2 13 NC 5 Q5 12 11 6 10 7 8 15 Q3 Q4 9 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999 1 3967 511120 File Number Spec Number Specifications HFA3127/883 Absolute Maximum Ratings Thermal Information Collector to Emitter Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.0V Collector to Base Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.0V Emitter to Base Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5V Collector Current at 100% Duty Cycle, 175oC TJ . . . . . . . . . 11.3mA Storage Temperature Range . . . . . . . . . . . . . . . . . . -65oC to 150oC Junction Temperature (DIE) . . . . . . . . . . . . . . . . . . . . . . . . . +175oC Lead Temperature (Soldering 10s) . . . . . . . . . . . . . . . . . . . . +300oC ESD Rating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . <2000V Thermal Resistance θJA θJC CerDIP Package . . . . . . . . . . . . . . . . . . . 80oC/W 24oC/W Maximum Package Power Dissipation at +75o CerDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.25W Derating Factor Above +75oC CerDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12.5mW/oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Operating Conditions Operating Temperature Range . . . . . . . . . . . . . . . . -55oC to +125oC TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS LIMITS PARAMETER Collector-to-Base Breakdown Voltage Collector-to-Emitter Breakdown Voltage Collector-to-Emitter Breakdown Voltage Emitter-to-Base Breakdown Voltage Collector-Cutoff Current Collector-Cutoff Current Collector-to-Emitter Saturation Voltage Base-to-Emitter Voltage DC Forward Current Transfer Ratio Early Voltage SYMBOL V(BR)CBO V(BR)CEO V(BR)CES V(BR)EBO ICEO ICBO VCE(SAT) VBE hFE VA CONDITIONS IC = 100µA, IE = 0 IC = 100µA, IB = 0 IC = 100µA, Base Shorted tp Emitter IE = 10µA, IC = 0 VCE = 6V, IB = 0 VCB = 8V, IE = 0 IC = 10mA, IB = 1mA IC = 10mA IC = 10mA, VCE = 2V IC = 10mA, VCE = 3.5V GROUP A SUBGROUPS TEMPERATURE MIN MAX UNITS 1 +25oC 12 - V 2, 3 +125oC to -55oC 12 - V 1 +25oC 8 - V 2, 3 +125oC to -55oC 8 - V 1 +25oC 10 - V 2, 3 +125oC to -55oC 10 - V 1 +25oC 5.5 - V 2, 3 +125oC to -55oC 5.5 - V 1 +25oC - 100 nA 2, 3 +125oC to -55oC - 100 nA 1 +25oC - 10 nA 2, 3 +125oC to -55oC - 10 nA 1 +25oC - 0.5 V 2, 3 +125oC to -55oC - 0.5 V 1 +25oC - 0.95 V 2, 3 +125oC to -55oC - 1.05 V 1 +25oC 40 - - 2, 3 +125oC to -55oC 20 - - 1 +25oC 20 - V 2, 3 +125oC to -55oC 20 - V Spec Number 2 511120 Specifications HFA3127/883 TABLE 2. ELECTRICAL PERFORMANCE CHARACTERISTICS Table 2 Intentionally Left Blank. TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS Table 3 Intentionally Left Blank. TABLE 4. ELECTRICAL TEST REQUIREMENTS MIL-STD-883 TEST REQUIREMENTS SUBGROUPS (SEE TABLE 1) Interim Electrical Parameters (Pre Burn-In) 1 Final Electrical Test Parameters 1 (Note 1), 2, 3 Group A Test Requirements 1, 2, 3 Groups C and D Endpoints 1 NOTE: 1. PDA applies to Subgroup 1 only. Spec Number 3 511120 HFA3127/883 Test Circuits (Applies to Table 1) 100µA 100µA 100µA 10µA V V BVCBO V V BVCEO BVCES BVEBO READ 10mA 10mA A A A 8V 6V V 1mA ICEO ICBO VCE(SAT) READ 10mA ADJ. 2V VBE MONITOR MONITOR A A V A R V 2V ADJ. ADJ. HFE ADJUST VA Burn-In Circuit 10.5V ± 0.5V 100 ±5% 0.01µF 5.5V ± 0.5V 0.01µF 16 1 Q1 2 4 Q2 NC 5 13 12 Q5 10 7 8 1K ±5% 11 6 1K ±5% 1K ±5% 14 3 1K ±5% 15 Q3 Q4 9 1K ±5% Spec Number 4 511120 HFA3127/883 Die Characteristics DIE DIMENSIONS: 52 x 52.8 x 15 1mils 1320µm x 1340µm x 381µm ± 25.4µm METALIZATION: Type: Metal 1: AlCu(2%)/TiW Thickness: Metal 1: 8kÅ ± 0.5kÅ Type: Metal 2: AlCu(2%) Thickness: Metal 2: 16kÅ ± 0.8kÅ GLASSIVATION: Type: Nitride Thickness: 4kÅ ± 0.5kÅ WORST CASE CURRENT DENSITY: 3.04 x 105A/cm2 TRANSISTOR COUNT: 5 SUBSTRATE POTENTIAL: Floating Metallization Mask Layout Pad numbers correspond to the 16 pin DIP pinout. HFA3127/883 2 16 1 15 3 14 4 13 5 12 6 11 7 8 9 10 Spec Number 5 511120 HFA3127 DESIGN INFORMATION Ultra High Frequency Transistor Array February 1995 The information contained in this section has been developed through characterization by Intersil Corporation and is for use as application and design information only. No guarantee is implied. Electrical Specifications at TA = +25oC TYP UNITS Noise Figure PARAMETERS f = 1.0GHz, VCE = 5V, IC = 5mA, ZS = 50Ω TEST CONDITIONS 3.5 dB fT Current Gain-Bandwidth Product IC = 1mA, VCE = 5V 5.5 GHz IC = 10mA, VCE = 5V 8 GHz IC = 10mA, VCE = 5V 2.5 GHz 1 pA Power Gain-Bandwidth Product, fMAX Collector-to-Collector Leakage Collector-to-Base Capacitance 0V, 1MHz 1.6 pF Base-to-Emitter Capacitance 0V, 1MHz 2.2 pF Collector-to-Emitter Capacitance 0V, 1MHz 1.9 pF NOTE: Package interlead capacitance is taken into account for all capacitance measurements. 25 IB = 200µA 20 IB = 160µA 100m COLLECTOR CURRENT AND BASE CURRENT (A) COLLECTOR CURRENT (mA) Typical Performance Curves IB =120µA 15 IB = 80µA 10 IB = 40µA 5 VCE = 3V IC 10m IB 1m 100µ 10µ 1µ 100n 10n 0 1 2 3 4 COLLECTOR TO EMITTER VOLTAGE (V) 1n 0.5 5 FIGURE 1. NPN COLLECTOR CURRENT vs COLLECTOR TO EMITTER VOLTAGE 10.0 GAIN BANDWIDTH PRODUCT (GHz) DC CURRENT GAIN 160 140 120 100 80 60 40 20 10µ 1.0 FIGURE 2. NPN COLLECTOR AND BASE CURRENTS vs BASE TO EMITTER VOLTAGE VCE = 3V 0 1µ 0.6 0.7 0.8 0.9 BASE TO EMITTER VOLTAGE (V) 100µ 1m 10m VCE = 3V 8.0 VCE = 5V 6.0 4.0 2.0 0 0.1 100m VCE = 1V 1.0 10 100 COLLECTOR CURRENT (mA) COLLECTOR CURRENT (A) FIGURE 3. NPN DC CURRENT GAIN vs COLLECTOR CURRENT FIGURE 4. NPN GAIN BANDWIDTH PRODUCT vs COLLECTOR CURRENT (UHF 3 x 50 WITH BOND PADS) Spec Number 6 511120 HFA3127 Ceramic Dual-In-Line Frit Seal Packages (CerDIP) c1 F16.3 MIL-STD-1835 GDIP1-T16 (D-2, CONFIGURATION A) LEAD FINISH 16 LEAD CERAMIC DUAL-IN-LINE FRIT SEAL PACKAGE -D- -A- BASE METAL INCHES (c) E b1 M M (b) -Bbbb S C A-B S SECTION A-A D S D BASE PLANE Q -C- SEATING PLANE A α L S1 eA A A b2 e b ccc M C A-B S D S eA/2 c aaa M C A - B S D S SYMBOL MIN MAX MIN MAX NOTES A - 0.200 - 5.08 - b 0.014 0.026 0.36 0.66 2 b1 0.014 0.023 0.36 0.58 3 b2 0.045 0.065 1.14 1.65 - b3 0.023 0.045 0.58 1.14 4 c 0.008 0.018 0.20 0.46 2 c1 0.008 0.015 0.20 0.38 3 D - 0.840 - 21.34 5 E 0.220 0.310 5.59 7.87 5 e 0.100 BSC 2.54 BSC - eA 0.300 BSC 7.62 BSC - 3.81 BSC - eA/2 NOTES: 1. Index area: A notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded area shown. The manufacturer’s identification shall not be used as a pin one identification mark. MILLIMETERS 0.150 BSC L 0.125 0.200 3.18 5.08 - Q 0.015 0.060 0.38 1.52 6 S1 0.005 - 0.13 - 7 α 90o 105o 90o 105o - aaa - 0.015 - 0.38 - bbb - 0.030 - 0.76 - 3. Dimensions b1 and c1 apply to lead base metal only. Dimension M applies to lead plating and finish thickness. ccc - 0.010 - 0.25 - M - 0.0015 - 0.038 2, 3 4. Corner leads (1, N, N/2, and N/2+1) may be configured with a partial lead paddle. For this configuration dimension b3 replaces dimension b2. N 2. The maximum limits of lead dimensions b and c or M shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. 16 16 8 Rev. 0 4/94 5. This dimension allows for off-center lid, meniscus, and glass overrun. 6. Dimension Q shall be measured from the seating plane to the base plane. 7. Measure dimension S1 at all four corners. 8. N is the maximum number of terminal positions. 9. Dimensioning and tolerancing per ANSI Y14.5M - 1982. 10. Controlling dimension: INCH. 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Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (321) 724-7000 FAX: (321) 724-7240 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 ASIA Intersil (Taiwan) Ltd. 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029 Spec Number 7 511120