ADS ADS 834 ADS8344 ¤ 834 4 ¤ 4 SBAS139E – SEPTEMBER 2000 – REVISED SEPTEMBER 2006 16-Bit, 8-Channel Serial Output Sampling ANALOG-TO-DIGITAL CONVERTER FEATURES DESCRIPTION ● PIN FOR PIN WITH ADS7844 The ADS8344 is an 8-channel, 16-bit, sampling Analog-to-Digital (A/D) converter with a synchronous serial interface. Typical power dissipation is 10mW at a 100kHz throughput rate and a +5V supply. The reference voltage (VREF) can be varied between 500mV and VCC, providing a corresponding input voltage range of 0V to VREF. The device includes a shutdown mode that reduces power dissipation to under 15µW. The ADS8344 is tested down to 2.7V operation. ● SINGLE SUPPLY: 2.7V to 5V ● 8-CHANNEL SINGLE-ENDED OR 4-CHANNEL DIFFERENTIAL INPUT ● UP TO 100kHz CONVERSION RATE ● 84dB SINAD ● SERIAL INTERFACE ● QSOP-20 AND SSOP-20 PACKAGES APPLICATIONS ● ● ● ● ● DATA ACQUISITION TEST AND MEASUREMENT EQUIPMENT INDUSTRIAL PROCESS CONTROL PERSONAL DIGITAL ASSISTANTS BATTERY-POWERED SYSTEMS ADS8341 ADS8343 CH2 ADS8344 ADS8345 CH0 CH0 CH1 Low power, high speed, and an on-board multiplexer make the ADS8344 ideal for battery-operated systems such as personal digital assistants, portable multi-channel data loggers, and measurement equipment. The serial interface also provides low-cost isolation for remote data acquisition. The ADS8344 is available in a QSOP-20 or SSOP-20 package and is ensured over the –40°C to +85°C temperature range. 4-Channel Multiplexer SAR CH1 DCLK CH2 CH3 CH3 COM CH4 CH5 8-Channel Multiplexer CS Comparator CDAC CH6 CH7 COM Serial Interface and Control SHDN DIN DOUT BUSY VREF Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. Copyright © 2000-2006, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. www.ti.com ELECTROSTATIC DISCHARGE SENSITIVITY ABSOLUTE MAXIMUM RATINGS(1) +VCC to GND ........................................................................ –0.3V to +6V Analog Inputs to GND ............................................ –0.3V to +VCC + 0.3V Digital Inputs to GND ........................................................... –0.3V to +6V Power Dissipation .......................................................................... 250mW Maximum Junction Temperature ................................................... +150°C Operating Temperature Range ........................................ –40°C to +85°C Storage Temperature Range ......................................... –65°C to +150°C Lead Temperature (soldering, 10s) ............................................... +300°C NOTE: (1) Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to absolute maximum conditions for extended periods may affect device reliability. This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. PACKAGE/ORDERING INFORMATION(1) PRODUCT MINIMUM RELATIVE MAXIMUM SPECIFIED ACCURACY GAIN ERROR TEMPERATURE PACKAGE (LSB) (%) RANGE DESIGNATOR PACKAGE-LEAD ADS8344E " ADS8344N " ADS8344EB " ADS8344NB " ±0.05 " " " ±0.024 " " " 8 " " " 6 " " " –40°C to +85°C " " " –40°C to +85°C " " " DBQ " DB " DBQ " DB " QSOP-20 " SSOP-20 " QSOP-20 " SSOP-20 " PACKAGE DRAWING NUMBER ORDERING NUMBER DBQ " DB " DBQ " DB " ADS8344E ADS8344E/2K5 ADS8344N ADS8344N/1K ADS8344EB ADS8344EB/2K5 ADS8344NB ADS8344NB/1K TRANSPORT MEDIA, QUANTITY Rails, 56 Tape and Reel, Rails, 68 Tape and Reel, Rails, 56 Tape and Reel, Rails, 68 Tape and Reel, 2500 1000 2500 1000 NOTE: (1) For the most current package and ordering information, see the Package Option Addendum at the end of this data sheet, or see the TI web site at www.ti.com. PIN CONFIGURATION PIN DESCRIPTIONS Top View SSOP NAME DESCRIPTION 1 2 3 4 5 6 7 8 9 CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 COM Analog Input Channel 0 Analog Input Channel 1 Analog Input Channel 2 Analog Input Channel 3 Analog Input Channel 4 Analog Input Channel 5 Analog Input Channel 6 Analog Input Channel 7 Ground reference for analog inputs. Sets zero code voltage in single–ended mode. Connect this pin to ground or ground reference point. Shutdown. When LOW, the device enters a very low-power shutdown mode. Voltage Reference Input. See Electrical Characteristics Table for ranges. Power Supply, 2.7V to 5V Ground Ground Serial Data Output. Data is shifted on the falling edge of DCLK. This output is high impedance when CS is HIGH. Busy Output. Busy goes LOW when the DIN control bits are being read and also when the device is converting. The Output is high impedance when CS is HIGH. Serial Data Input. If CS is LOW, data is latched on rising edge of DCLK. Chip Select Input. Active LOW. Data will not be clocked into DIN unless CS is LOW. When CS is HIGH, DOUT is high impedance. External Clock Input. The clock speed determines the conversion rate by the equation fDCLK = 24 • fSAMPLE. Power Supply CH0 1 20 +VCC CH1 2 19 DCLK CH2 3 18 CS CH3 4 17 DIN 10 SHDN CH4 5 16 BUSY 11 VREF 12 13 14 15 +VCC GND GND DOUT 16 BUSY 17 DIN 18 CS 19 DCLK 20 +VCC ADS8344 2 PIN CH5 6 15 DOUT CH6 7 14 GND CH7 8 13 GND COM 9 12 +VCC SHDN 10 11 VREF ADS8344 SBAS139E ELECTRICAL CHARACTERISTICS: +5V At TA = –40°C to +85°C, +VCC = +5V, VREF = +5V, fSAMPLE = 100kHz, and fCLK = 24 • fSAMPLE = 2.4MHz, unless otherwise noted. ADS8344E, N PARAMETER CONDITIONS MIN RESOLUTION ANALOG INPUT Full-Scale Input Span Absolute Input Range Positive Input - Negative Input Positive Input Negative Input 0 –0.2 –0.2 POWER-SUPPLY REQUIREMENTS +VCC Quiescent Current 1.0 20 3 +4.75V < VCC < 5.25V ✻ ✻ ✻ 8 ±2 4 ±0.05 4 ✻ ✻ ✻ ✻ = = = = 5Vp-p 5Vp-p 5Vp-p 5Vp-p at at at at 0.024 0 2.4 2.4 0.5 ✻ ✻ +VCC 5 40 2.5 0.001 3.0 –0.3 3.5 ✻ ✻ ✻ 100 3 ✻ ✻ ✻ Power Dissipation 7.5 –40 ✻ ✻ ✻ ✻ ✻ 0.4 1.5 300 CLK Cycles CLK Cycles kHz ns ns ps MHz MHz MHz V GΩ µA µA µA ✻ 5.5 +0.8 4.75 Bits LSB mV LSB(1) % LSB µVrms LSB(1) dB dB dB dB ✻ ✻ ✻ ✻ ✻ V V V V ✻ Straight Binary Specified Performance 6 ±1 ✻ ±0.024 ✻ ✻ ✻ ✻ ✻ CMOS | IIH | ≤ +5µA | IIL | ≤ +5µA IOH = –250µA IOL = 250µA V V V pF µA ✻ –90 86 92 100 DCLK Static ✻ ✻ ✻ ✻ ✻ ✻ ✻ 500 30 100 2.4 10kHz 10kHz 10kHz 10kHz BITS ✻ 100 VIN VIN VIN VIN UNITS ✻ ✻ 16 SHDN = VDD MAX ✻ ✻ 4.5 fSAMPLE = 100kHz Power-Down Mode(3), CS = +VCC TEMPERATURE RANGE Specified Performance TYP 15 1.2 fSAMPLE = 12.5kHz DCLK Static DIGITAL INPUT/OUTPUT Logic Family Logic Levels VIH VIL VOH VOL Data Format VREF +VCC + 0.2 +1.25 14 Data Transfer Only REFERENCE INPUT Range Resistance Input Current MIN 25 ±1 SAMPLING DYNAMICS Conversion Time Acquisition Time Throughput Rate Multiplexer Settling Time Aperture Delay Aperture Jitter Internal Clock Frequency External Clock Frequency DYNAMIC CHARACTERISTICS Total Harmonic Distortion(2) Signal-to-(Noise + Distortion) Spurious–Free Dynamic Range Channel-to-Channel Isolation MAX 16 Capacitance Leakage Current SYSTEM PERFORMANCE No Missing Codes Integral Linearity Error Offset Error Offset Error Match Gain Error Gain Error Match Noise Power-Supply Rejection TYP ADS8344EB, NB 5.25 2.0 ✻ ✻ ✻ ✻ ✻ V mA µA µA mW ✻ °C ✻ 3 10 +85 ✻ ✻ Same specifications as ADS8344E, N. NOTES: (1) LSB means Least Significant Bit. With VREF equal to +5.0V, one LSB is 76µV. (2) First nine harmonics of the test frequency. (3) Auto power-down mode (PD1 = PD0 = 0) active or SHDN = GND. ADS8344 SBAS139E 3 ELECTRICAL CHARACTERISTICS: +2.7V At TA = –40°C to +85°C, +VCC = +2.7V, VREF = +2.7V, fSAMPLE = 100kHz, and fCLK = 24 • fSAMPLE = 2.4MHz, unless otherwise noted. ADS8344E, N PARAMETER CONDITIONS MIN TYP RESOLUTION ANALOG INPUT Full-Scale Input Span Absolute Input Range SAMPLING DYNAMICS Conversion Time Acquisition Time Throughput Rate Multiplexer Settling Time Aperture Delay Aperture Jitter Internal Clock Frequency External Clock Frequency Positive Input - Negative Input Positive Input Negative Input REFERENCE INPUT Range Resistance Input Current 0 –0.2 –0.2 VREF +VCC + 0.2 +0.2 POWER-SUPPLY REQUIREMENTS +VCC Quiescent Current ✻ ✻ ✻ 1 20 3 +2.7 < VCC < +3.3V 12 ±1 4 ±0.05 4 ✻ ✻ ✻ ✻ SHDN = VDD 0.024 0.024 0 2.4 2.0 2.4 VIN = 2.5Vp-p at 1kHz VIN = 2.5Vp-p at 1kHz VIN = 2.5Vp-p at 1kHz VIN = 2.5Vp-p at 10kHz V V V pF µA 8 0.5 ✻ ±0.024 ✻ ✻ ✻ ✻ 0.5 +VCC DCLK Static 5 13 2.5 0.001 ✻ 40 3 ✻ ✻ ✻ 3.2 ✻ ✻ ✻ ✻ ✻ 0.4 V GΩ µA µA µA V V V V ✻ Straight Binary 1.2 220 CLK Cycles CLK Cycles kHz ns ns ps MHz MHz MHz MHz ✻ 5.5 +0.8 2.7 Bits LSB mV LSB % of FSR LSB µVrms LSB(1) dB dB dB dB ✻ ✻ ✻ ✻ ✻ CMOS +VCC • 0.7 –0.3 +VCC • 0.8 ✻ ✻ ✻ ✻ ✻ ✻ –90 86 92 100 –40 ✻ ✻ ✻ ✻ ✻ ✻ ✻ 500 30 100 2.4 Power Dissipation BITS ✻ 100 Specified Performance UNITS ✻ ✻ 16 4.5 | IIH | ≤ +5µA | IIL | ≤ +5µA IOH = –250µA IOL = 250µA MAX 15 1.2 fSAMPLE = 100kHz Power-Down Mode(3), CS = +VCC TEMPERATURE RANGE Specified Performance TYP ✻ ✻ 14 fSAMPLE = 12.5kHz DCLK Static DIGITAL INPUT/OUTPUT Logic Family Logic Levels VIH VIL VOH VOL Data Format MIN 25 ±1 When used with Internal Clock Data Transfer Only DYNAMIC CHARACTERISTICS Total Harmonic Distortion(2) Signal-to-(Noise + Distortion) Spurious-Free Dynamic Range Channel-to-Channel Isolation MAX 16 Capacitance Leakage Current SYSTEM PERFORMANCE No Missing Codes Integral Linearity Error Offset Error Offset Error Match Gain Error Gain Error Match Noise Power-Supply Rejection ADS8344EB, NB 3.6 1.85 ✻ ✻ ✻ 3 5 +85 ✻ ✻ ✻ ✻ ✻ V mA µA µA mW ✻ °C ✻ Same specifications as ADS8344E, N. NOTES: (1) LSB means Least Significant Bit. With VREF equal to +2.5V, one LSB is 38µV. (2) First nine harmonics of the test frequency. (3) Auto power-down mode (PD1 = PD0 = 0) active or SHDN = GND. 4 ADS8344 SBAS139E TYPICAL CHARACTERISTICS: +5V At TA = +25°C, +VCC = +5V, VREF = +5V, fSAMPLE = 100kHz, and fDCLK = 24 • fSAMPLE = 2.4MHz, unless otherwise noted. FREQUENCY SPECTRUM (4096 Point FFT; fIN = 9.985kHz, –0.2dB) 0 0 –20 –20 –40 –40 Amplitude (dB) –60 –80 –100 –60 –80 –100 –120 –120 –140 –140 –160 –160 0 10 20 30 40 50 0 10 20 30 Frequency (kHz) SIGNAL-TO-NOISE RATIO AND SIGNAL-TO(NOISE+DISTORTION) vs INPUT FREQUENCY SPURIOUS-FREE DYNAMIC RANGE AND TOTAL HARMONIC DISTORTION vs INPUT FREQUENCY 100 50 –100 100 SNR SFDR 90 –90 90 SFDR (dB) SNR and SINAD (dB) 40 Frequency (kHz) 80 SINAD 70 THD(1) 80 –80 THD (dB) Amplitude (dB) FREQUENCY SPECTRUM (4096 Point FFT; fIN = 1.001kHz, –0.2dB) –70 70 NOTE: (1) First Nine Harmonics of the Input Frequency 60 10 100 1 10 Frequency (kHz) Frequency (kHz) EFFECTIVE NUMBER OF BITS vs INPUT FREQUENCY CHANGE IN SIGNAL-TO-(NOISE+DISTORTION) vs TEMPERATURE 15.0 0.4 fIN = 9.985kHz, –0.2dB 14.5 0.2 14.0 Delta from +25°C (dB) Effective Number of Bits –60 100 60 1 13.5 13.0 12.5 12.0 0.0 –0.2 –0.4 –0.6 11.5 11.0 –0.8 1 10 Frequency (kHz) ADS8344 SBAS139E 100 –40 –25 0 20 50 75 100 Temperature (°C) 5 TYPICAL CHARACTERISTICS: +5V (Cont.) At TA = +25°C, +VCC = +5V, VREF = +5V, fSAMPLE = 100kHz, and fDCLK = 24 • fSAMPLE = 2.4MHz, unless otherwise noted. 1 2 0 1 –1 0 –2 –1 –3 –2 –4 0000H 4000H C000H 8000H –3 0000H FFFFH C000H 8000H Output Code WORST CASE CHANNEL-TO-CHANNEL OFFSET MATCH vs TEMPERATURE WORST CASE CHANNEL-TO-CHANNEL GAIN MATCH vs TEMPERATURE 3.0 2.0 2.5 1.5 2.0 1.5 1.0 –50 4000H Output Code Gain Match (LSB) Offset Match (LSB) DIFFERENTIAL LINEARITY ERROR vs CODE 3 DLE (LSB) ILE (LSB) INTEGRAL LINEARITY ERROR vs CODE 2 FFFFH 1.0 0.5 –25 0 25 50 Temperature (°C) 75 0.0 –50 100 CHANGE IN OFFSET vs TEMPERATURE –25 0 25 50 Temperature (°C) 75 100 CHANGE IN GAIN vs TEMPERATURE 3 1.0 Delta from 25°C (LSB) Delta from 25°C (LSB) 2 1 0 –1 0.5 0.0 –2 –3 –50 –25 0 25 Temperature (°C) 6 50 75 100 –0.5 –50 –25 0 25 50 75 100 Temperature (°C) ADS8344 SBAS139E TYPICAL CHARACTERISTICS: +5V (Cont.) At TA = +25°C, +VCC = +5V, VREF = +5V, fSAMPLE = 100kHz, and fDCLK = 24 • fSAMPLE = 2.4MHz, unless otherwise noted. POWER DOWN SUPPLY CURRENT vs TEMPERATURE SUPPLY CURRENT vs TEMPERATURE 3.0 1.8 Supply Current (µA) Supply Current (mA) 1.7 1.6 1.5 2.5 2.0 1.5 1.4 1.3 –50 –25 0 25 Temperature (°C) ADS8344 SBAS139E 50 75 100 1.0 –50 –25 0 25 50 Temperature (°C) 75 100 7 TYPICAL CHARACTERISTICS: +2.7V At TA = +25°C, +VCC = +2.7V, VREF = +2.7V, fSAMPLE = 100kHz, and fDCLK = 24 • fSAMPLE = 2.4MHz, unless otherwise noted. FREQUENCY SPECTRUM (4096 Point FFT; fIN = 9.985kHz, –0.2dB) 0 0 –20 –20 –40 –40 Amplitude (dB) Amplitude (dB) FREQUENCY SPECTRUM (4096 Point FFT; fIN = 1.001kHz, –0.2dB) –60 –80 –100 –60 –80 –100 –120 –120 –140 –140 –160 –160 0 10 20 30 40 0 50 10 20 30 40 50 Frequency (kHz) Frequency (kHz) SIGNAL-TO-NOISE RATIO AND SIGNAL-TO(NOISE+DISTORTION) vs INPUT FREQUENCY SPURIOUS-FREE DYNAMIC RANGE AND TOTAL HARMONIC DISTORTION vs INPUT FREQUENCY 100 100 –100 90 –90 SFDR (dB) SNR and SINAD (dB) 80 70 SINAD 60 70 –70 –60 NOTE: (1) First Nine Harmonics of the Input Frequency 50 1 10 100 1 –50 100 10 Frequency (kHz) Frequency (kHz) EFFECTIVE NUMBER OF BITS vs INPUT FREQUENCY CHANGE IN SIGNAL-TO-(NOISE+DISTORTION) vs TEMPERATURE 15 2.0 14 1.5 Delta from +25°C (dB) Effective Number of Bits –80 THD(1) 60 50 13 12 11 10 9 fIN = 9.985kHz, –0.2dB 1.0 0.5 0.0 –0.5 –1.0 –1.5 8 –2.0 1 10 Frequency (kHz) 8 SFDR 80 THD (dB) SNR 90 100 –40 –25 0 20 50 75 100 Temperature (°C) ADS8344 SBAS139E TYPICAL CHARACTERISTICS: +2.7V (Cont.) At TA = +25°C, +VCC = +2.7V, VREF = +2.7V, fSAMPLE = 100kHz, and fDCLK = 24 • fSAMPLE = 2.4MHz, unless otherwise noted. DIFFERENTIAL LINEARITY ERROR vs CODE 3 2 2 1 1 DLE (LSB) ILE (LSB) INTEGRAL LINEARITY ERROR vs CODE 3 0 0 –1 –1 –2 –2 –3 0000H 4000H C000H 8000H –3 0000H FFFFH 4000H C000H 8000H FFFFH Output Code Output Code WORST CASE CHANNEL-TO-CHANNEL OFFSET MATCH vs TEMPERATURE WORST CASE CHANNEL-TO-CHANNEL GAIN MATCH vs TEMPERATURE 1.2 1.2 Gain Match (LSBS) Offset Match (LSBS) 1.0 0.8 0.6 0.4 1.0 0.8 0.6 0.2 0 –50 –25 0 25 50 75 0.4 –50 100 –25 0 Temperature (°C) Delta from 25°C (LSB) Delta from 25°C (LSB) 1 0 SBAS139E 100 0.3 2 ADS8344 75 CHANGE IN GAIN vs TEMPERATURE CHANGE IN OFFSET vs TEMPERATURE 3 –1 –50 25 50 Temperature (°C) 0.2 0.1 0.0 –0.1 –25 0 25 50 Temperature (°C) 75 100 –0.2 –50 –25 0 25 50 75 100 Temperature (°C) 9 TYPICAL CHARACTERISTICS: +2.7V (Cont.) At TA = +25°C, +VCC = +2.7V, VREF = +2.7V, fSAMPLE = 100kHz, and fDCLK = 24 • fSAMPLE = 2.4MHz, unless otherwise noted. SUPPLY CURRENT vs TEMPERATURE SUPPLY CURRENT vs +VSS 1.25 1.6 1.20 1.5 Supply Current (mA) Supply Current (mA) fSAMPLE = 100kHz, VREF = +VSS 1.15 1.10 1.05 1.00 –50 1.4 1.3 1.2 1.1 1.0 –25 0 25 50 75 100 2.5 3.0 Temperature (°C) 3.5 4.0 4.5 5.0 +VSS (V) POWER DOWN SUPPLY CURRENT vs TEMPERATURE Supply Current (µA) 3.0 2.5 2.0 1.5 1.0 –50 10 –25 0 25 50 Temperature (°C) 75 100 ADS8344 SBAS139E THEORY OF OPERATION ANALOG INPUT See Figure 2 for a block diagram of the input multiplexer on the ADS8344. The differential input of the converter is derived from one of the eight inputs in reference to the COM pin, or four of the eight inputs. Table I and Table II show the relationship between the A2, A1, A0, and SGL/DIF control bits and the configuration of the analog multiplexer. The control bits are provided serially via the DIN pin (see the Digital Interface section of this data sheet for more details). The ADS8344 is a classic Successive Approximation Register (SAR) A/D converter. The architecture is based on capacitive redistribution that inherently includes a sampleand-hold function. The converter is fabricated on a 0.6µs CMOS process. The basic operation of the ADS8344 is shown in Figure 1. The device requires an external reference and an external clock. It operates from a single supply of 2.7V to 5.25V. The external reference can be any voltage between 500mV and +VCC. The value of the reference voltage directly sets the input range of the converter. The average reference input current depends on the conversion rate of the ADS8344. When the converter enters the hold mode, the voltage difference between the +IN and –IN inputs is captured on the internal capacitor array (see Figure 2). The voltage on the –IN input is limited between –0.2V and 1.25V, allowing the input to reject small signals that are common to both the +IN and –IN input. The +IN input has a range of –0.2V to +VCC + 0.2V. The analog input to the converter is differential and is provided via an 8-channel multiplexer. The input can be provided in reference to a voltage on the COM pin (which is generally ground) or differentially by using four of the eight input channels (CH0 - CH7). The particular configuration is selectable via the digital interface. A2 A1 A0 0 0 0 1 0 0 0 0 1 1 0 1 0 1 0 1 1 0 0 1 1 1 1 1 The input current on the analog inputs depends on the conversion rate of the device. During the sample period, the source must charge the internal sampling capacitor (typically 25pF). After the capacitor has been fully charged, there is no further input current. The rate of charge transfer from the analog source to the converter is a function of conversion rate. CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 COM +IN –IN +IN +IN +IN –IN A2 A1 A0 CH0 CH1 –IN 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 +IN –IN –IN +IN –IN +IN –IN +IN –IN +IN –IN –IN CH2 CH3 +IN –IN CH4 CH5 +IN –IN CH6 CH7 +IN –IN –IN +IN +IN –IN +IN –IN +IN TABLE II. Differential Channel Control (SGL/DIF LOW). TABLE I. Single-Ended Channel Selection (SGL/DIF HIGH). +2.7V to +5V ADS8344 Single-ended or differential analog inputs 1µF to 10µF 0.1µF 1 CH0 +VCC 20 2 CH1 DCLK 19 3 CH2 CS 18 Chip Select 4 CH3 DIN 17 Serial Data In 5 CH4 BUSY 16 6 CH5 DOUT 15 7 CH6 GND 14 8 CH7 GND 13 9 COM +VCC 12 10 SHDN VREF 11 Serial/Conversion Clock Serial Data Out External VREF + 1µF 1µF to 10µF FIGURE 1. Basic Operation of the ADS8344. ADS8344 SBAS139E 11 (Least Significant Bit) size and is equal to the reference voltage divided by 65536. Any offset or gain error inherent in the A/D converter will appear to increase, in terms of LSB size, as the reference voltage is reduced. For example, if the offset of a given converter is 2LSBs with a 2.5V reference, then it will typically be 10LSBs with a 0.5V reference. In each case, the actual offset of the device is the same, 76.3µV. A2-A0 (shown 00oB)(1) CH0 CH1 CH2 CH3 CH4 Likewise, the noise or uncertainty of the digitized output will increase with lower LSB size. With a reference voltage of 500mV, the LSB size is 7.6µV. This level is below the internal noise of the device. As a result, the digital output code will not be stable and will vary around a mean value by a number of LSBs. The distribution of output codes will be gaussian and the noise can be reduced by simply averaging consecutive conversion results or applying a digital filter. CH5 CH6 +IN Converter CH7 –IN With a lower reference voltage, care should be taken to provide a clean layout including adequate bypassing, a clean (low-noise, low-ripple) power supply, a low-noise reference, and a low-noise input signal. Because the LSB size is lower, the converter will also be more sensitive to nearby digital signals and electromagnetic interference. The voltage into the VREF input is not buffered and directly drives the Capacitor Digital-to-Analog Converter (CDAC) portion of the ADS8344. Typically, the input current is 13µA with a 2.5V reference. This value will vary by microamps depending on the result of the conversion. The reference current diminishes directly with both conversion rate and reference voltage. As the current from the reference is drawn on each bit decision, clocking the converter more quickly during a given conversion period will not reduce overall current drain from the reference. COM NOTE: (1) See Truth Tables, Table I and Table II for address coding. SGL/DIF (shown HIGH) FIGURE 2. Simplified Diagram of the Analog Input. REFERENCE INPUT The external reference sets the analog input range. The ADS8344 will operate with a reference in the range of 100mV to +VCC. Keep in mind that the analog input is the difference between the +IN input and the –IN input, as shown in Figure 2. For example, in the single-ended mode, a 1.25V reference with the COM pin grounded, the selected input channel (CH0 - CH7) will properly digitize a signal in the range of 0V to 1.25V. If the COM pin is connected to 0.5V, the input range on the selected channel is 0.5V to 1.75V. DIGITAL INTERFACE The ADS8344 has a four-wire serial interface compatible with several microprocessor families (note that the digital inputs are over-voltage tolerant up to +5.5V, regardless of +VCC). Figure 3 shows the typical operation of the ADS8344 digital interface. Most microprocessors communicate using 8-bit transfers; the ADS8344 can complete a conversion with three such transfers, for a total of 24 clock cycles on the DCLK input, provided the timing is as shown in Figure 3. There are several critical items concerning the reference input and its wide-voltage range. As the reference voltage is reduced, the analog voltage weight of each digital output code is also reduced. This is often referred to as the LSB CS tACQ DCLK 1 8 Idle DIN S A2 8 1 Acquire A1 A0 1 8 1 8 Conversion Idle SGL/ PD1 PD0 DIF S (START) A2 Acquire A1 A0 1 Conversion SGL/ PD1 PD0 DIF (START) BUSY DOUT 15 (MSB) 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 (LSB) Zero Filled... 15 14 (MSB) FIGURE 3. Conversion Timing, 24-Clocks per Conversion, 8-Bit Bus Interface. No DCLK Delay Required with Dedicated Serial Port. 12 ADS8344 SBAS139E The first eight clock cycles are used to provide the control byte via the DIN pin. When the converter has enough information about the following conversion to set the input multiplexer appropriately, it enters the acquisition (sample) mode. After four more clock cycles, the control byte is complete and the converter enters the conversion mode. At this point, the input sample-and-hold goes into the Hold mode. The next sixteen clock cycles accomplish the actual A/D conversion. Control Byte See Figure 3 for placement and order of the control bits within the control byte. Tables III and IV give detailed information about these bits. The first bit, the “S” bit, must always be HIGH and indicates the start of the control byte. The ADS8344 will ignore inputs on the DIN pin until the START bit is detected. The next three bits (A2-A0) select the active input channel or channels of the input multiplexer (see Tables I and II and Figure 2). BIT 7 (MSB) BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 (LSB) S A2 A1 A0 — SGL/DIF PD1 PD0 TABLE III. Order of the Control Bits in the Control Byte. BIT NAME 7 DESCRIPTION S Start Bit. Control byte starts with first HIGH bit on DIN. 6-4 A2 - A0 Channel Select Bits. Along with the SGL/DIF bit, these bits control the setting of the multiplexer input, see Tables I and II. 2 SGL/DIF Single-Ended/Differential Select Bit. Along with bits A2 - A0, this bit controls the setting of the multiplexer input, see Tables I and II. PD1 - PD0 Power-Down Mode Select Bits. See Table V for details. 1-0 TABLE IV. Descriptions of the Control Bits within the Control Byte. The SGL/DIF-bit controls the multiplexer input mode: either in single-ended mode, where the selected input channel is referenced to the COM pin, or in differential mode, where the two selected inputs provide a differential input. See Tables I and II and Figure 2 for more information. The last two bits (PD1 - PD0) select the power-down mode and Clock mode, as shown in Table V. If both PD1 and PD0 are HIGH, the device is always powered up. If both PD1 and PD0 are LOW, the device enters a power-down mode between conversions. When a new conversion is initiated, the device will resume normal operation instantly—no delay is needed to allow the device to power up and the very first conversion will be valid. PD1 PD0 0 0 Power-down between conversions. When each conversion is finished, the converter enters a low-power mode. At the start of the next conversion, the device instantly powers up to full power. There is no need for additional delays to assure full operation and the very first conversion is valid. DESCRIPTION 1 0 Selects Internal Clock Mode. 0 1 Reserved for Future Use. 1 1 No power-down between conversions, device always powered. Selects external clock mode. TABLE V. Power-Down Selection. Clock Modes The ADS8344 can be used with an external serial clock or an internal clock to perform the successive-approximation conversion. In both clock modes, the external clock shifts data in and out of the device. Internal clock mode is selected when PD1 is HIGH and PD0 is LOW. If the user decides to switch from one clock mode to the other, an extra conversion cycle will be required before the ADS8344 can switch to the new mode. The extra cycle is required because the PD0 and PD1 control bits need to be written to the ADS8344 prior to the change in clock modes. When power is first applied to the ADS8344, the user must set the desired clock mode. It can be set by writing PD1 = 1 and PD0 = 0 for internal clock mode or PD1 = 1 and PD0 = 1 for external clock mode. After enabling the required clock mode, only then should the ADS8344 be set to powerdown between conversions (i.e., PD1 = PD0 = 0). The ADS8344 maintains the clock mode it was in prior to entering the power-down modes. External Clock Mode In external clock mode, the external clock not only shifts data in and out of the ADS8344, it also controls the A/D conversion steps. BUSY will go HIGH for one clock period after the last bit of the control byte is shifted in. Successive-approximation bit decisions are made and appear at DOUT on each of the next 16 DCLK falling edges (see Figure 3). Figure 4 shows the BUSY timing in external clock mode. CS tCSS tCL tCH tBD tBD tD0 tCSH DCLK tDS DIN tDH PD0 tBDV tBTR BUSY tDV DOUT tTR 15 14 FIGURE 4. Detailed Timing Diagram. ADS8344 SBAS139E 13 Since one clock cycle of the serial clock is consumed with BUSY going HIGH (while the MSB decision is being made), 16 additional clocks must be given to clock out all 16 bits of data; thus, one conversion takes a minimum of 25 clock cycles to fully read the data. Since most microprocessors communicate in 8-bit transfers, this means that an additional transfer must be made to capture the LSB. If CS is LOW when BUSY goes LOW following a conversion, the next falling edge of the external serial clock will write out the MSB on the DOUT line. The remaining bits (D14-D0) will be clocked out on each successive clock cycle following the MSB. If CS is HIGH when BUSY goes LOW then the DOUT line will remain in tri-state until CS goes LOW, as shown in Figure 6. CS does not need to remain LOW once a conversion has started. Note that BUSY is not tri-stated when CS goes HIGH in internal clock mode. There are two ways of handling this requirement. One is where the beginning of the next control byte appears at the same time the LSB is being clocked out of the ADS8344 (see Figure 3). This method allows for maximum throughput and 24 clock cycles per conversion. Data can be shifted in and out of the ADS8344 at clock rates exceeding 2.4MHz, provided that the minimum acquisition time tACQ, is kept above 1.7µs. The other method is shown in Figure 5, which uses 32 clock cycles per conversion; the last seven clock cycles simply shift out zeros on the DOUT line. BUSY and DOUT go into a high-impedance state when CS goes HIGH; after the next CS falling edge, BUSY will go LOW. Digital Timing Figure 4 and Tables VI and VII provide detailed timing for the digital interface of the ADS8344. Internal Clock Mode In internal clock mode, the ADS8344 generates its own conversion clock internally. This relieves the microprocessor from having to generate the SAR conversion clock and allows the conversion result to be read back at the processor’s convenience, at any clock rate from 0MHz to 2.0MHz. BUSY goes LOW at the start of a conversion and then returns HIGH when the conversion is complete. During the conversion, BUSY will remain LOW for a maximum of 8µs. Also, during the conversion, DCLK should remain LOW to achieve the best noise performance. The conversion result is stored in an internal register; the data may be clocked out of this register any time after the conversion is complete. SYMBOL DESCRIPTION MIN tACQ tDS tDH tDO tDV tTR tCSS tCSH tCH tCL tBD tBDV tBTR Acquisition Time DIN Valid Prior to DCLK Rising DIN Hold After DCLK HIGH DCLK Falling to DOUT Valid CS Falling to DOUT Enabled CS Rising to DOUT Disabled CS Falling to First DCLK Rising CS Rising to DCLK Ignored DCLK HIGH DCLK LOW DCLK Falling to BUSY Rising CS Falling to BUSY Enabled CS Rising to BUSY Disabled 1.5 100 10 TYP MAX UNITS µs ns ns ns ns ns ns ns ns ns ns ns ns 200 200 200 100 0 200 200 200 200 200 TABLE VI. Timing Specifications (+VCC = +2.7V to 3.6V, TA = –40°C to +85°C, CLOAD = 50pF). CS tACQ DCLK 1 8 Idle DIN S A2 1 8 Acquire A1 A0 1 1 8 8 Conversion Idle SGL/ DIF PD1 PD0 (START) BUSY DOUT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Zero Filled... 0 (MSB) (LSB) FIGURE 5. External Clock Mode, 32 Clocks Per Conversion. CS tACQ DCLK 1 8 Idle DIN S A2 Acquire A1 A0 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Conversion SGL/ PD1 PD0 DIF (START) BUSY DOUT 15 (MSB) 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Zero Filled... (LSB) FIGURE 6. Internal Clock Mode Timing. 14 ADS8344 SBAS139E SYMBOL DESCRIPTION MIN tACQ tDS tDH tDO tDV tTR tCSS tCSH tCH tCL tBD tBDV tBTR Acquisition Time DIN Valid Prior to DCLK Rising DIN Hold After DCLK HIGH DCLK Falling to DOUT Valid CS Falling to DOUT Enabled CS Rising to DOUT Disabled CS Falling to First DCLK Rising CS Rising to DCLK Ignored DCLK HIGH DCLK LOW DCLK Falling to BUSY Rising CS Falling to BUSY Enabled CS Rising to BUSY Disabled 1.7 50 10 TYP MAX UNITS 100 70 70 50 0 150 150 100 70 70 µs ns ns ns ns ns ns ns ns ns ns ns ns TABLE VII. Timing Specifications (+VCC = +4.75V to +5.25V, TA = –40°C to +85°C, CLOAD = 50pF). Data Format The ADS8344 output data is in straight binary format, as shown in Figure 7. This figure shows the ideal output code for the given input voltage and does not include the effects of offset, gain, or noise. FS = Full-Scale Voltage = VREF 1LSB = VREF/65,536 1LSB 11...111 Output Code 11...110 11...101 00...010 00...001 00...000 FS – 1LSB 0V Input Voltage(1) (V) NOTE: (1) Voltage at converter input, after multiplexer: +IN – (–IN). (See Figure 2.) FIGURE 7. Ideal Input Voltages and Output Codes. remain approximately equal. However, if the DCLK frequency is kept at the maximum rate during a conversion, but conversions are simply done less often, then the difference between the two modes is dramatic. In the latter case, the converter spends an increasing percentage of its time in power-down mode (assuming the auto power-down mode is active). If DCLK is active and CS is LOW while the ADS8344 is in auto power-down mode, the device will continue to dissipate some power in the digital logic. The power can be reduced to a minimum by keeping CS HIGH. Operating the ADS8344 in auto power-down mode will result in the lowest power dissipation, and there is no conversion time “penalty” on power-up. The very first conversion will be valid. SHDN can be used to force an immediate power-down. NOISE The noise floor of the ADS8344 itself is extremely low, as shown in Figures 8 thru 11, and is much lower than competing A/D converters. The ADS8344 was tested at both 5V and 2.7V, and in both the internal and external clock modes. A low-level DC input was applied to the analog-input pins and the converter was put through 5,000 conversions. The digital output of the A/D converter will vary in output code due to the internal noise of the ADS8344. This is true for all 16-bit SAR-type A/D converters. Using a histogram to plot the output codes, the distribution should appear bell-shaped with the peak of the bell curve representing the nominal code for the input value. The ±1σ, ±2σ, and ±3σ distributions will represent the 68.3%, 95.5%, and 99.7%, respectively, of all codes. The transition noise can be calculated by dividing the number of codes measured by 6 and this will yield the ±3σ distribution, or 99.7%, of all codes. Statistically, up to 3 codes could fall outside the distribution when executing 1,000 conversions. The ADS8344, with < 3 output codes for the ±3σ distribution, will yield a < ±0.5LSB transition noise at 5V operation. Remember, to achieve this low-noise performance, the peak-to-peak noise of the input signal and reference must be < 50µV. POWER DISSIPATION There are three power modes for the ADS8344: full-power (PD1 - PD0 = 11B), auto power-down (PD1 - PD0 = 00B), and shutdown (SHDN LOW). The effects of these modes varies depending on how the ADS8344 is being operated. For example, at full conversion rate and 24-clocks per conversion, there is very little difference between full-power mode and auto power-down; a shutdown will not lower power dissipation. When operating at full-speed and 24-clocks per conversion (see Figure 3), the ADS8344 spends most of its time acquiring or converting. There is little time for auto power-down, assuming that this mode is active. Thus, the difference between full-power mode and auto power-down is negligible. If the conversion rate is decreased by simply slowing the frequency of the DCLK input, the two modes ADS8344 SBAS139E 4561 0 242 7FFD 7FFE 7FFF 197 0 8000 8001 Code FIGURE 8. Histogram of 5,000 Conversions of a DC Input at the Code Transition, 5V operation external clock mode. 15 sion results will reduce the transition noise by 1/2 to ±0.25LSBs. Averaging should only be used for input signals with frequencies near DC. For AC signals, a digital filter can be used to low-pass filter and decimate the output codes. This works in a similar manner to averaging: for every decimation by 2, the signal-to-noise ratio will improve 3dB. 4507 LAYOUT 0 251 7FFD 7FFE 7FFF 242 0 8000 8001 Code FIGURE 9. Histogram of 5,000 Conversions of a DC Input at the Code Center, 5V operation internal clock mode. 3511 666 721 50 7FFD 52 7FFE 7FFF 8000 8001 Code FIGURE 10. Histogram of 5,000 Conversions of a DC Input at the Code Transition, 2.7V operation external clock mode. 2868 1137 858 78 7FFD 59 7FFE 7FFF 8000 8001 Code FIGURE 11. Histogram of 5,000 Conversions of a DC Input at the Code Center, 2.7V operation internal clock mode. AVERAGING The noise of the A/D converter can be compensated by averaging the digital codes. By averaging conversion results, transition noise will be reduced by a factor of 1/√n, where n is the number of averages. For example, averaging 4 conver- 16 For optimum performance, care should be taken with the physical layout of the ADS8344 circuitry. This is particularly true if the reference voltage is LOW and/or the conversion rate is HIGH. The basic SAR architecture is sensitive to glitches or sudden changes on the power supply, reference, ground connections, and digital inputs that occur just prior to latching the output of the analog comparator. Thus, during any single conversion for an n-bit SAR converter, there are n “windows” in which large external transient voltages can easily affect the conversion result. Such glitches might originate from switching power supplies, nearby digital logic, and high-power devices. The degree of error in the digital output depends on the reference voltage, layout, and the exact timing of the external event. The error can change if the external event changes in time with respect to the DCLK input. With this in mind, power to the ADS8344 should be clean and well bypassed. A 0.1µF ceramic bypass capacitor should be placed as close to the device as possible. In addition, a 1µF to 10µF capacitor and a 5Ω or 10Ω series resistor may be used to low-pass filter a noisy supply. The reference should be similarly bypassed with a 0.1µF capacitor. Again, a series resistor and large capacitor can be used to low-pass filter the reference voltage. If the reference voltage originates from an op amp, make sure that it can drive the bypass capacitor without oscillation (the series resistor can help in this case). The ADS8344 draws very little current from the reference on average, but it does place larger demands on the reference circuitry over short periods of time (on each rising edge of DCLK during a conversion). The ADS8344 architecture offers no inherent rejection of noise or voltage variation in regards to the reference input. This is of particular concern when the reference input is tied to the power supply. Any noise and ripple from the supply will appear directly in the digital results. While high-frequency noise can be filtered out as discussed in the previous paragraph, voltage variation due to line frequency (50Hz or 60Hz) can be difficult to remove. The GND pin should be connected to a clean ground point. In many cases, this will be the “analog” ground. Avoid connections that are too near the grounding point of a microcontroller or digital signal processor. If needed, run a ground trace directly from the converter to the power-supply entry point. The ideal layout will include an analog ground plane dedicated to the converter and associated analog circuitry. ADS8344 SBAS139E Revision History DATE REVISION 9/06 E PAGE SECTION 2 Package/Ordering Info 4 Electrical Characteristics DESCRIPTION Added quantity to last column. Fixed typo. Changed +2.7V Gain Error minimum value (for EB, NB grade) from ±0.0024 to ±0.024. NOTE: Page numbers for previous revisions may differ from page numbers in the current version. ADS8344 SBAS139E 17 PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish (2) MSL Peak Temp Op Temp (°C) Top-Side Markings (3) (4) ADS8344E ACTIVE SSOP DBQ 20 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 ADS8344E ADS8344E/2K5 ACTIVE SSOP DBQ 20 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 85 ADS8344E ADS8344E/2K5G4 ACTIVE SSOP DBQ 20 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 85 ADS8344E ADS8344EB ACTIVE SSOP DBQ 20 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 85 ADS8344E B ADS8344EB/2K5 ACTIVE SSOP DBQ 20 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 85 ADS8344E B ADS8344EB/2K5G4 ACTIVE SSOP DBQ 20 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 85 ADS8344E B ADS8344EBG4 ACTIVE SSOP DBQ 20 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 85 ADS8344E B ADS8344EG4 ACTIVE SSOP DBQ 20 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 ADS8344E ADS8344N ACTIVE SSOP DB 20 70 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 ADS8344N B ADS8344N/1K ACTIVE SSOP DB 20 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 ADS8344N B ADS8344N/1KG4 ACTIVE SSOP DB 20 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 ADS8344N B ADS8344NB ACTIVE SSOP DB 20 70 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 ADS8344N B ADS8344NB/1K ACTIVE SSOP DB 20 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 ADS8344N B ADS8344NB/1KG4 ACTIVE SSOP DB 20 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 ADS8344N B ADS8344NBG4 ACTIVE SSOP DB 20 70 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 ADS8344N B ADS8344NG4 ACTIVE SSOP DB 20 70 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 ADS8344N B (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Top-Side Marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. 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Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 24-Jul-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 8.0 16.0 Q1 ADS8344E/2K5 SSOP DBQ 20 2500 330.0 16.4 6.5 9.0 2.1 ADS8344EB/2K5 SSOP DBQ 20 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 ADS8344N/1K SSOP DB 20 1000 330.0 16.4 8.2 7.5 2.5 12.0 16.0 Q1 ADS8344NB/1K SSOP DB 20 1000 330.0 16.4 8.2 7.5 2.5 12.0 16.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 24-Jul-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) ADS8344E/2K5 SSOP DBQ 20 2500 367.0 367.0 38.0 ADS8344EB/2K5 SSOP DBQ 20 2500 367.0 367.0 38.0 ADS8344N/1K SSOP DB 20 1000 367.0 367.0 38.0 ADS8344NB/1K SSOP DB 20 1000 367.0 367.0 38.0 Pack Materials-Page 2 MECHANICAL DATA MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 28 PINS SHOWN 0,38 0,22 0,65 28 0,15 M 15 0,25 0,09 8,20 7,40 5,60 5,00 Gage Plane 1 14 0,25 A 0°–ā8° 0,95 0,55 Seating Plane 2,00 MAX 0,10 0,05 MIN PINS ** 14 16 20 24 28 30 38 A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30 DIM 4040065 /E 12/01 NOTES: A. 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