ON NB7L32M 2.5v/3.3v, 14ghz ã·2 clock divider w/cml output and internal termination Datasheet

NB7L32M
2.5V/3.3V, 14GHz ÷2 Clock
Divider w/CML Output and
Internal Termination
Descriptions
The NB7L32M is an integrated ÷2 divider with differential clock
inputs and asynchronous reset.
Differential clock inputs incorporate internal 50 W termination
resistors and accept LVPECL (Positive ECL), CML, or LVDS. The
high frequency reset pin is asserted on the rising edge. Upon
power−up, the internal flip−flops will attain a random state; the reset
allows for the synchronization of multiple NB7L32M’s in a system.
The differential 16 mA CML output provides matching internal
50 W termination which guarantees 400 mV output swing when
externally receiver terminated 50 W to VCC (See Figure 16).
The device is housed in a small 3x3 mm 16 pin QFN package.
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MARKING
DIAGRAM*
16
1
A
L
Y
W
G
Features
•
•
•
•
•
•
•
•
•
Maximum Input Clock Frequency 14 GHz Typical
200 ps Max Propagation Delay
30 ps Typical Rise and Fall Times
< 0.5 ps Maximum (RMS) Random Clock Jitter
Operating Range: VCC = 2.375 V to 3.465 V with VEE = 0 V
CML Output Level (400 mV Peak−to−Peak Output), Differential
Output Only
50 W Internal Input and Output Termination Resistors
Functionally Compatible with Existing 2.5 V / 3.3 V LVEL, LVEP,
EP, and SG Devices
These are Pb−Free Devices
NB7L
32M
ALYWG
QFN−16
MN SUFFIX
CASE 485G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
*For additional marking information, refer to
Application Note AND8002/D.
FUNCTIONAL BLOCK DIAGRAM
R
VCC
R1
VEE
Reset
VTCLK
50 W
CLK
Q
Divide by 2
Q
CLK
50 W
VTCLK
TRUTH TABLE
CLK
CLK
R
Q
Q
x
x
H
L
H
Z
W
L
÷2
÷2
Z = LOW to HIGH Transition
W = HIGH to LOW Transition
x = Don’t Care
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 10 of this data sheet.
© Semiconductor Components Industries, LLC, 2005
November, 2005 − Rev. 0
1
Publication Order Number:
NB7L32M/D
NB7L32M
VTCLK
1
CLK
2
VCC
R
VCC VCC
16
15
14
Exposed Pad (EP)
13
12
VCC
11
Q
NB7L32M
CLK
3
10
Q
VTCLK
4
9
VCC
5
6
7
8
NC
VEE
VEE
VEE
Figure 1. Pin Configuration (Top View)
Table 1. PIN DESCRIPTION
Pin
Name
I/O
Description
1
VTCLK
−
Internal 50 W termination pin. In the differential configuration when the input
termination pin (VTCLK, VTCLK) are connected to a common termination voltage or left open, and if no signal is applied on CLK/CLK input then the device
will be susceptible to self−oscillation.
2
CLK
ECL, CML, LVDS Input
Noninverted differential input. In the differential configuration when the input
termination pin (VTCLK, VTCLK) are connected to a common termination voltage or left open and if no signal is applied on CLK/CLK input, then the device
will be susceptible to self−oscillation.
3
CLK
ECL, CML, LVDS Input
Inverted differential input. In the differential configuration when the input termination pin (VTCLK, VTCLK) are connected to a common termination voltage
or left open and if no signal is applied on CLK/CLK input, then the device will
be susceptible to self−oscillation.
4
VTCLK
−
Internal 50 W termination pin. In the differential configuration when the input
termination pin (VTCLK, VTCLK) are connected to a common termination voltage or left open and if no signal is applied on CLK/CLK input, then the device
will be susceptible to self−oscillation.
5
NC
−
No connect. NC pin must be left open.
6, 7, 8
VEE
−
Negative supply voltage.
9, 12, 13,
14, 16
VCC
−
Positive supply voltage.
10
Q
CML Output
Inverted differential output. Typically terminated with 50 W resistor to VCC.
11
Q
CML Output
Noninverted differential output. Typically terminated with 50 W resistor to VCC.
15
R
LVTTL/LVCMOS
−
EP
−
Reset Input. Internal pulldown to 75 kW to VEE.
Exposed Pad. The thermally exposed pad (EP) on package bottom (see case
drawing) must be attached to a heat−sinking conduit. EP is electrically isolated
from VCC and VEE.
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2
NB7L32M
Table 2. ATTRIBUTES
Characteristics
Value
Internal Input Pulldown Resistor
R1
ESD Protection
Human Body Model
Machine Model
> 500 V
> 30 V
QFN−16
Level 1
Moisture Sensitivity (Note 1)
Flammability Rating
75 kW
Oxygen Index: 28 to 34
UL 94 V−0 @ 0.125 in
Transistor Count
349
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
Table 3. MAXIMUM RATINGS
Symbol
Parameter
Condition 1
Condition 2
Rating
Unit
VCC
Positive Power Supply
VEE = 0 V
3.6
V
VEE
Negative Power Supply
VCC = 0 V
−3.6
V
VI
Positive Input
Negative Input
VEE = 0 V
VCC = 0 V
3.6
−3.6
V
V
VINPP
Differential Input Voltage
2.8
V
IIN
Input Current Through RT (50 W Resistor)
Static
Surge
45
80
mA
mA
Iout
Output Current
Continuous
Surge
25
50
mA
mA
TA
Operating Temperature Range
QFN−16
−40 to +85
°C
Tstg
Storage Temperature Range
−65 to +150
°C
qJA
Thermal Resistance (Junction−to−Ambient)
(Note 2)
0 lfpm
500 lfpm
QFN−16
QFN−16
41.6
35.2
°C/W
°C/W
qJC
Thermal Resistance (Junction−to−Case)
1S2P
QFN−16
4.0
°C/W
Tsol
Wave Solder
<3 sec @ 260°C
265
°C
Pb−Free
VI ≤ VCC
VI ≥ VEE
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit
values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied,
damage may occur and reliability may be affected.
2. JEDEC standard multilayer board − 1S2P (1 signal, 2 power) with 8 filled thermal vias under exposed pad.
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NB7L32M
Table 4. DC CHARACTERISTICS, CLOCK INPUTS, CML OUTPUTS VCC = 2.375 V to 3.465 V, VEE = 0 V,
TA = −40°C to +85°C
Symbol
Characteristic
Min
Typ
Max
Unit
ICC
Power Supply Current (Note 3)
50
65
80
mA
VOH
Output HIGH Voltage (Note 4)
VCC − 40
VCC − 10
VCC
mV
VOL
Output LOW Voltage (Note 4)
VCC − 500
VCC − 400
VCC − 330
mV
RTOUT
Internal Output Termination Resistor
45
50
55
W
RTemp
Coef
Internal I/O Termination Resistor Temperature Coefficient
6.38
mW/°C
DIFFERENTIAL CLK/CLK INPUT DRIVEN SINGLE−ENDED (see Figure 10 and 12)
Vth
Input Threshold Reference Voltage Range (Note 6)
1050
VCC
mV
VIH
Single−ended Input HIGH Voltage
Vth + 150
VCC + 300
mV
VIL
Single−ended Input LOW Voltage
VEE
Vth − 150
mV
DIFFERENTIAL CLK/CLK INPUTS DRIVEN DIFFERENTIALLY (see Figure 11 and 13)
VIHD
Differential Input HIGH Voltage
1200
VCC + 300
mV
VILD
Differential Input LOW Voltage
VEE
VCC − 75
mV
VCMR
Input Common Mode Range (Differential Configuration, Note 7)
1125
VCC
mV
VID
Differential Input Voltage (VIHD − VILD)
150
2500
mV
IIH
Input HIGH Current
CLK/CLK (VTCLK/R/VTCLK/R Open)
0
30
100
mA
IIL
Input LOW Current
CLK/CLK(VTCLK/R/VTCLK/R Open)
−50
0
50
mA
RTIN
Internal Input Termination Resistor
45
50
55
W
LVTTL/LVCMOS RESET INPUT
VIH
Single−ended Input HIGH Voltage
2000
VCC
mV
VIL
Single−ended Input LOW Voltage
VEE
800
mV
IIH
Input HIGH Current
R
0
30
100
mA
IIL
Input LOW Current
R
0
10
100
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
3. Input termination pins open and all outputs loaded with external RL = 50 W receiver termination resistor.
4. CML outputs require RL = 50 W receiver termination resistors to VCC for proper operation. (See Figure 9)
5. Input and output parameters vary 1:1 with VCC.
6. Vth is applied to the complementary input when operating in single−ended mode.
7. VCMR(MIN) varies 1:1 with VEE, VCMR max varies 1:1 with VCC. The VCMR range is referenced to the most positive side of the differential input
signal.
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NB7L32M
Table 6. AC CHARACTERISTICS VCC = 2.375 V to 3.465 V, VEE = 0 V (Note 8)
−40°C
Symbol
Characteristic
VOUTPP
Output Voltage Amplitude (@ VINPP(MIN))
fin ≤ 7 GHz
(See Figures 2, 3, 4, 5, 6, and 7)
fin ≤ 12 GHz
fIN
Maximum Input Clock Frequency
(See Figures 2 and 3)
tPLH,
tPHL
Propagation Delay to
Output Differential (See Figure 8)
tskew
Duty Cycle Skew (Note 9)
Device−to−Device Skew (Note 12)
tRR
Reset Recovery (See Figure 8)
tPW
Minimum Pulse Width
tJITTER
Random Clock Jitter (RMS)
(Note 11)
VINPP
Input Voltage Swing/Sensitivity
(Differential Configuration) (Note 10)
tr
tf
Output Rise/Fall Times @ 1 GHz
(20% − 80%)
CLK to Q
R to Q
R
Min
Typ
190
160
255C
Max
Min
Typ
330
320
190
160
12
14
130
200
155
240
200
300
2
6
20
50
855C
Max
Min
Typ
Max
330
320
190
160
330
320
12
14
12
14
130
200
155
240
200
300
130
200
155
260
200
300
2
6
20
50
2
6
20
50
Unit
mV
GHz
ps
300
135
300
135
300
135
ps
500
210
500
210
500
210
ps
fin ≤ 7 GHz
fin = 12 GHz
0.13
0.14
150
0.5
0.5
2500
30
45
0.13
0.14
150
0.5
0.5
2500
30
45
0.13
0.14
150
30
0.5
0.5
ps
2500
mV
45
ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
8. Measured by forcing VINPP(MIN) from a 50% duty cycle clock source. All loading with an external RL = 50 W to VCC. Input edge rates 40 ps
(20% − 80%).
9. Duty cycle skew is measured between differential outputs using the deviations of the sum of Tpw− and Tpw+ 1 GHz.
10. VINPP(MAX) cannot exceed VCC − VEE. Input voltage swing is a single−ended measurement operating in differential mode.
11. Additive RMS jitter with 50% duty cycle input clock signal.
12. Device−to−device skew is measured between outputs under identical transition @ 1 GHz.
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OUTPUT VOLTAGE AMPLITUDE (mV)
NB7L32M
450
VCC = 3.3 V
400
350
VCC = 2.5 V
300
250
200
150
100
50
0
0
2
4
6
8
10
12
14
INPUT CLOCK FREQUENCY (GHz)
0
+223.61
−5
+125.74
−10
+70.71
Safe Operating Area
−15
+39.76
−20
Typical
−25
+22.36
+12.57
−30
+7.07
−35
+3.98
−40
+2.24
−45
0
2
4
6
8
10
12
14
INPUT VOLTAGE (mVrms)
INPUT POWER (dBm)
Figure 2. Output Voltage Amplitude (VOUTPP) versus Input Clock Frequency (fOUT) at
Ambient Temperature (VINPP = 150 mV)
+1.26
16
INPUT CLOCK FREQUENCY (GHz)
Figure 3. Input Signal Amplitude vs Input Clock Frequency (All Temperatures and Power Supplies;
Guaranteed Output Amplitude of at Least VOUTPP = 160 mV)
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VOLTAGE (50 mV/div)
VOLTAGE (50 mV/div)
NB7L32M
VOLTAGE (50 mV/div)
TIME (190 ps/div)
Figure 5. Typical Output Waveform with
fIN = 7 GHz(VCC = 3.3 V, VINPP = 400 mV, Room
Temperature, VOUTPP = 387 mV, tr = 32 ps,
tf = 29.8 ps, fOUT = 3.499 GHz)
VOLTAGE (50 mV/div)
TIME (190 ps/div)
Figure 4. Typical Output Waveform with
fIN = 7 GHz( VCC = 2.5 V, VINPP = 400 mV,
Room Temperature, VOUTPP = 357 mV,
tr = 33 ps, tf = 30 ps, fOUT = 3.499 GHz)
TIME (52 ps/div)
TIME (52 ps/div)
Figure 6. Typical Output Waveform with
fIN = 14 GHz(VCC = 2.5 V, VINPP = 400 mV,
Room Temperature, VOUTPP = 292 mV,
tr = 25 ps, tf = 27 ps, fOUT = 7.01 GHz)
Figure 7. Typical Output Waveform with
fIN = 14 GHz(VCC = 3.3 V, VINPP = 400 mV,
Room Temperature, VOUTPP = 319 mV,
tr = 25 ps, tf = 26 ps, fOUT = 7.01 GHz)
50%
50%
VOUTPP = VOH(Q) − VOL(Q)
Q
tPLH
tPHL
50%
50%
CLK
R
tRR(MIN)
50%
Figure 8. AC Reference Measurement (Timing Diagram)
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VINPP = VIH(CLK) − VIL(CLK)
NB7L32M
VCC
50 W
50 W
Zo = 50 W
Q
D
Receiver
Device
Driver
Device
Q
Zo = 50 W
D
Figure 9. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8073/D − Termination of CML Logic Devices.)
CLK
CLK
CLK
CLK
Vth
Vth
Figure 10. Differential Input Driven
Single−Ended
VCC
Vthmax
Vth
VCC
VIHmax
VILmax
D
Vthmin
GND
Figure 11. Differential Inputs Driven
Differentially
VIHDmax
VCMmax
VIH
Vth
VIL
VCMR
VILDmax
VID = VIHD − VILD
VIHDtyp
D
D
VIHmin
VILmin
NOTE:
VILDtyp
VIHDmin
VILDmin
VCMmin
GND
VEE v VIN v VCC + 300 mV; VIH > VIL
Figure 12. Vth Diagram
Figure 13. VCMR Diagram
VCC
50 W
50 W
Q
Q
16 mA
VEE
Figure 14. CML Output Structure
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NB7L32M
APPLICATION INFORMATION
All NB7L32M inputs can accept PECL, CML, and LVDS signal levels. The limitations for differential input signal (LVDS,
PECL, or CML) are minimum input swing of 150 mV and the maximum input swing of 2500 mV. Within these conditions,
the input voltage can range from VCC to 1.2 V. Examples interfaces are illustrated below in a 50 W environment (Z = 50 W).
For output termination and interface, refer to application note AND8020/D.
Table 5. INTERFACING OPTIONS
Interfacing Options
Connections
CML
Connect VTD and VTD to VCC (See Figure 15)
LVDS
Connect VTD and VTD Together (See Figure 17)
AC−COUPLED
RSECL, PECL, NECL
Bias VTD and VTD Inputs within Common Mode Range (VCMR) (See Figure 16)
Standard ECL Termination Techniques (See Figure 9)
VCC
VCC
50 W
50 W
Q
Z = 50 W
CML
Driver
D
VCC
Z = 50 W
VCC
Q
VTD
50 W
VTD
50 W
NB7L32M
D
VEE
VEE
Figure 15. CML to NB7L32M Interface
VCC
VCC
Z = 50 W
VBias*
PECL
Driver
Z = 50 W
Recommended RT Values
VCC
C
VBias*
C
D
VTD
50 W
NB7L32M
VTD
50 W
RT
RT
5.0 V 290 W
D
RT
3.3 V 150 W
2.5 V 80 W
VEE
VEE
VEE
*VBias must be within common mode range limits (VCMR)
Figure 16. PECL to NB7L32M Interface
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NB7L32M
APPLICATION INFORMATION
VCC
VCC
Z = 50 W
D
VTD
LVDS
Driver
50 W
NB7L32M
Z = 50 W
VTD
50 W
D
VEE
VEE
Figure 17. LVDS to NB7L32M Interface
ORDERING INFORMATION
Package
Shipping †
NB7L32MMNG
QFN−16
(Pb−Free)
123 Units / Rail
NB7L32MMNR2G
QFN−16
(Pb−Free)
3000 / Tape & Reel
Device
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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NB7L32M
PACKAGE DIMENSIONS
16 PIN QFN
MN SUFFIX
CASE 485G−01
ISSUE B
ÇÇÇ
ÇÇÇ
ÇÇÇ
D
PIN 1
LOCATION
0.15 C
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.25 AND 0.30 MM FROM TERMINAL.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
5. Lmax CONDITION CAN NOT VIOLATE 0.2 MM
MINIMUM SPACING BETWEEN LEAD TIP
AND FLAG
A
B
E
DIM
A
A1
A3
b
D
D2
E
E2
e
K
L
TOP VIEW
0.15 C
(A3)
0.10 C
A
16 X
0.08 C
SIDE VIEW
MILLIMETERS
MIN
MAX
0.80
1.00
0.00
0.05
0.20 REF
0.18
0.30
3.00 BSC
1.65
1.85
3.00 BSC
1.65
1.85
0.50 BSC
0.20
−−−
0.30
0.50
SEATING
PLANE
A1
C
D2
16X
L
5
NOTE 5
16X
e
4
9
1
12
E2
K
16
16X
e
13
b
0.10 C A B
0.05 C
EXPOSED PAD
8
BOTTOM VIEW
NOTE 3
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
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“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
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NB7L32M/D
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