ON NCP4308ADR2G Synchronous rectifier controller Datasheet

NCP4308
Product Preview
Synchronous Rectifier
Controller
The NCP4308 is a synchronous rectifier controller for switch mode
power supplies. The controller enables high efficiency designs for
flyback, quasi resonant flyback and LLC topologies.
Externally adjustable minimum off−time and on−time blanking
periods provides flexibility to drive various MOSFET package types
and PCB layout. A reliable and noise less operation of the SR system is
insured due to the Self Synchronization feature. The NCP4308 also
utilizes Kelvin connection of the driver to the MOSFET to achieve high
efficiency operation at full load.
The precise turn−off threshold, extremely low turn−off delay time
and high sink current capability of the driver allow the maximum
synchronous rectification MOSFET conduction time. The high
accuracy driver and 5 V gate clamp make it ideally suited for directly
driving GaN devices.
Features
• Self−Contained Control of Synchronous Rectifier in CCM, DCM and
•
•
•
•
•
•
•
•
•
•
•
•
•
QR for Flyback or LLC Applications
Precise True Secondary Zero Current Detection
Rugged Current Sense Pin (up to 150 V)
Adjustable Minimum ON−Time
Adjustable Minimum OFF-Time with Ringing Detection
Adjustable Maximum ON−Time for CCM Controlling of Primary
QR Controller
Improved Robust Self Synchronization Capability
8 A / 4 A Peak Current Sink / Source Drive Capability
Operating Voltage Range up to VCC = 35 V
GaN Transistor Driving Capability (options A and C)
Low Startup Current Consumption
Maximum Operation Frequency up to 1 MHz
SOIC-8 and DFN−8 (4x4) and WDFN8 (2x2) Packages
These are Pb−Free Devices
MARKING
DIAGRAMS
8
8
1
SOIC−8
D SUFFIX
CASE 751
NCP4308x
ALYW G
G
1
1
DFN8
MN SUFFIX
CASE 488AF
4308x
ALYWG
G
1
WDFN8
MT SUFFIX
CASE 511AT
4308x
Ex
A
L
Y
W
M
G
ExMG
G
= Specific Device Code
x = A, B, C, D or Q
= Specific Device Code
x = A, 2, C, D or Q
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Date Code
= Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
Typical Applications
•
•
•
•
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Notebook Adapters
High Power Density AC/DC Power Supplies (Cell Phone Chargers)
LCD TVs
All SMPS with High Efficiency Requirements
See detailed ordering and shipping information on page 26 of
this data sheet.
This document contains information on a product under development. ON Semiconductor
reserves the right to change or discontinue this product without notice.
© Semiconductor Components Industries, LLC, 2015
September, 2015 − Rev. P0
1
Publication Order Number:
NCP4308/D
MIN_TON
MIN_TOFF
NCP4308
RTN
D1
MIN_TON
MIN_TOFF
OK1
Figure 1. Typical Application Example − LLC Converter
+Vout
+
Vbulk
TR1
R1
C1
+
C2
C5
D3
+
VCC
FLYBACK
M2
D4
C3
CONTROL
GND
C4
CIRCUITRY
DRV
FB
M1
CS
R2
R3
R4
D5
R5
OK1
Figure 2. Typical Application Example − DCM, CCM or QR Flyback Converter
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2
NCP4308
+Vout
+
Vbulk
TR1
R1
C1
R3
+
C2
C10
D3
VCC
C4
R4
+
PRIMARY
ZCD
SIDE
M2
D4
C3
GND
FLYBACK
C7
CONTROLLER
DRV
M1
R7
COMP CS
R2
R6
R5
C5
R8
C6
Figure 3. Typical Application Example − Primary Side Flyback Converter
+
Vbulk
R4
TR1
R5
C1
+Vout
C2
+
R3
D2
D4
C7
+
VCC
QR
CONTROL
CIRCUITRY
ZCD
C4
DRV
FB CS
M3
D3
GND
D1
R1
C5
M1
R11
R9
R10
R2
R8
R6
OK1
C3
M2
NCP4308
D6
R12
R7
D5
TR2
C6
Figure 4. Typical Application Example − QR Converter − Capability to Force Primary into CCM Under Heavy
Loads utilizing MAX−TON
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NCP4308
PIN FUNCTION DESCRIPTION
ver. A, B, C, D
ver. Q
Pin Name
1
1
VCC
2
2
MIN_TOFF
Adjust the minimum off time period by connecting resistor to ground.
3
3
MIN_TON
Adjust the minimum on time period by connecting resistor to ground.
4
4
NC
Leave this pin opened or tie it to ground.
5
−
NC
Leave this pin opened or tie it to ground.
6
6
CS
Current sense pin detects if the current flows through the SR MOSFET and/or its body
diode. Basic turn−off detection threshold is 0 mV. A resistor in series with this pin can
decrease the turn off threshold if needed.
7
7
GND
Ground connection for the SR MOSFET driver, VCC decoupling capacitor and for minimum on and off time adjust resistors. GND pin should be wired directly to the SR
MOSFET source terminal/soldering point using Kelvin connection. DFN8 exposed flag
should be connected to GND
8
8
DRV
Driver output for the SR MOSFET
−
5
MAX_TON
MIN_TON
Description
Supply voltage pin
Adjust the maximum on time period by connecting resistor to ground.
ELAPSED
ADJ
NC
Minimum ON time
generator
EN
VDD
100mA
CS
CS_ON
CS
detection
DRIVER
CS_OFF
DRV Out
DRV
Control logic
CS_RESET
V DD
RESET
MIN_TOFF
ADJ
Minimum OFF
time generator
ELAPSED
EN
VCC managment
UVLO
NC
VCC
GND
Figure 5. Internal Circuit Architecture − NCP4308A, B, C, D
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NCP4308
ELAPSED
MIN_TON
ADJ
NC
Minimum ON time
generator
EN
VDD
100mA
CS
CS_ON
CS
detection
DRIVER
DRV Out
DRV
CS_OFF
Control logic
CS_RESET
VDD
RESET
MIN_TOFF
ADJ
Minimum OFF
time generator
ELAPSED
EN
VCC managment
UVLO
VCC
ELAPSED
MAX_TON
ADJ
Maximum ON time
generator
GND
EN
Figure 6. Internal Circuit Architecture − NCP4308Q (CCM QR) with MAX_TON
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5
NCP4308
ABSOLUTE MAXIMUM RATINGS
Rating
Supply Voltage
MIN_TON, MIN_TOFF, MAX_TON Input Voltage
Driver Output Voltage
Current Sense Input Voltage
Symbol
Value
Unit
VCC
−0.3 to 37.0
V
VMIN_TON,
VMIN_TOFF,
VMAX_TON
−0.3 to VCC
V
VDRV
−0.3 to 17.0
V
VCS
−4 to 150
V
VCS_DYN
−10 to 150
V
IMIN_TON, IMIN_TOFF,
IMAX_TON
−10 to 10
mA
Junction to Air Thermal Resistance, 1 oz 1 in2 Copper Area, SOIC8
RqJ−A_SOIC8
160
°C/W
Junction to Air Thermal Resistance, 1 oz 1 in2 Copper Area, DFN8
RqJ−A_DFN8
80
°C/W
RqJ−A_WDFN8
160
°C/W
Maximum Junction Temperature
TJMAX
150
°C
Storage Temperature
TSTG
−60 to 150
°C
ESD Capability, Human Body Model, Except Pin 6, per JESD22−A114E
ESDHBM
2000
V
ESD Capability, Human Body Model, Pin 6, per JESD22−A114E
ESDHBM
1000
V
ESD Capability, Machine Model, per JESD22−A115−A
ESDMM
200
V
ESD Capability, Charged Device Model, Except Pin 6, per JESD22−C101F
ESDCDM
750
V
ESD Capability, Charged Device Model, Pin 6, per JESD22−C101F
ESDCDM
250
V
Current Sense Dynamic Input Voltage (tPW = 200 ns)
MIN_TON, MIN_TOFF, MAX_TON, Input Current
Junction to Air Thermal Resistance, 1 oz 1 in2 Copper Area, WDFN8
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. This device meets latch−up tests defined by JEDEC Standard JESD78D Class I.
RECOMMENDED OPERATING CONDITIONS
Parameter
Symbol
Maximum Operating Input Voltage
Min
VCC
Operating Junction Temperature
TJ
−40
Max
Unit
35
V
125
°C
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
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6
NCP4308
ELECTRICAL CHARACTERISTICS
−40°C ≤ TJ ≤ 125°C; VCC = 12 V; CDRV = 0 nF; RMIN_TON = RMIN_TOFF = 10 kW; VCS = −1 to +4 V; fCS = 100 kHz, DCCS = 50%, unless
otherwise noted. Typical values are at TJ = +25°C
Parameter
Test Conditions
Symbol
Min
Typ
Max
Unit
VCCON
8.3
8.8
9.3
V
VCCOFF
7.3
7.8
8.3
SUPPLY SECTION
VCC UVLO (ver. B & C)
VCC rising, VCS = 0 V
VCC falling, VCS = 0 V
VCC UVLO Hysteresis (ver. B & C)
VCC UVLO (ver. A, D & Q)
VCCHYS
1.0
V
VCC rising, VCS = 0 V
VCCON
4.20
4.45
4.70
VCC falling, VCS = 0 V
VCCOFF
3.70
3.95
4.20
VCC UVLO Hysteresis
(ver. A, D & Q)
VCCHYS
0.5
tSTART_DEL
75
125
ms
3.3
4.0
5.6
mA
B, D, Q
3.8
4.5
6.0
A, C
4.5
6.0
7.5
B, D, Q
7.7
9.0
10.7
A, C
20
25
30
Start−up Delay
VCC rising from 0 to VCCON + 1 V @ tr = 10 ms,
VCS = 0 V
Current Consumption,
RMIN_TON = RMIN_TOFF = 0 kW
CDRV = 0 nF, fCS = 500 kHz
A, C
CDRV = 1 nF, fCS = 500 kHz
CDRV = 10 nF, fCS = 500 kHz
V
ICC
B, D, Q
V
40
50
60
1.5
2.0
2.5
mA
ICC_UVLO
75
125
mA
Current Consumption
No switching, VCS = 0 V, RMIN_TON = RMIN_TOFF
= 0 kW
ICC
Current Consumption below UVLO
No switching, VCC = VCCOFF – 0.1 V, VCS = 0 V
DRIVER OUTPUT
Output Voltage Rise−Time
CDRV = 10 nF, 10% to 90% VDRVMAX
tr
40
55
ns
Output Voltage Fall−Time
CDRV = 10 nF, 90% to 10% VDRVMAX
tf
20
35
ns
RDRV_SOURCE
1.2
W
RDRV_SINK
0.5
W
IDRV_SOURCE
4
A
IDRV_SINK
8
A
Driver Source Resistance
Driver Sink Resistance
Output Peak Source Current
Output Peak Sink Current
Maximum Driver Output Voltage
VCC = 35 V, CDRV > 1 nF (ver. B, D and Q)
VDRVMAX
9.0
9.5
10.5
4.3
4.7
5.5
7.2
7.8
8.5
VCC = VCCOFF + 200 mV (ver. C)
4.2
4.7
5.3
VCC = VCCOFF + 200 mV (ver. A)
3.6
4.0
4.4
VCC = VCCOFF + 200 mV (ver. D, Q)
3.8
4.0
4.4
VCC = 35 V, CDRV > 1 nF (ver. A, C)
Minimum Driver Output Voltage
VCC = VCCOFF + 200 mV (ver. B)
VDRVMIN
V
V
CS INPUT
Total Propagation Delay From CS
to DRV Output On
VCS goes down from 4 to −1 V, tf_CS = 5 ns
tPD_ON
35
60
ns
Total Propagation Delay From CS
to DRV Output Off
VCS goes up from −1 to 4 V, tr_CS = 5 ns
tPD_OFF
12
23
ns
CS Bias Current
VCS = −20 mV
Turn On CS Threshold Voltage
Turn Off CS Threshold Voltage
Guaranteed by Design
Turn Off Timer Reset Threshold
Voltage
CS Leakage Current
VCS = 150 V
ICS
−105
−100
−95
mA
−75
−40
mV
0
mV
0.54
V
0.4
mA
VTH_CS_ON
−120
VTH_CS_OFF
−1
VTH_CS_RESET
0.42
ICS_LEAKAGE
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0.48
NCP4308
ELECTRICAL CHARACTERISTICS
−40°C ≤ TJ ≤ 125°C; VCC = 12 V; CDRV = 0 nF; RMIN_TON = RMIN_TOFF = 10 kW; VCS = −1 to +4 V; fCS = 100 kHz, DCCS = 50%, unless
otherwise noted. Typical values are at TJ = +25°C
Parameter
Test Conditions
Symbol
Min
Typ
Max
Unit
MINIMUM tON and tOFF ADJUST
Minimum tON time
RMIN_TON = 0 W
tON_MIN
35
55
75
ns
Minimum tOFF time
RMIN_TOFF = 0 W
tOFF_MIN
190
245
290
ns
Minimum tON time
RMIN_TON = 10 kW
tON_MIN
0.92
1.00
1.08
ms
Minimum tOFF time
RMIN_TOFF = 10 kW
tOFF_MIN
0.92
1.00
1.08
ms
Minimum tON time
RMIN_TON = 50 kW
tON_MIN
4.62
5.00
5.38
ms
Minimum tOFF time
RMIN_TOFF = 50 kW
tOFF_MIN
4.62
5.00
5.38
ms
Maximum tON Time
VMAX_TON = 3 V
tON_MAX
4.3
4.8
5.3
ms
Maximum tON Time
VMAX_TON = 0.3 V
tON_MAX
41
48
55
ms
Maximum tON Output Current
VMAX_TON = 0.3 V
IMAX_TON
−105
−100
−95
mA
MAXIMUM tON ADJUST
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
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NCP4308
TYPICAL CHARACTERISTICS
4.7
9.3
4.6
9.1
VCCON
4.4
8.7
4.3
8.5
4.2
4.1
VCCOFF
4.0
VCCON
8.9
VCC (V)
VCC (V)
4.5
8.3
8.1
VCCOFF
7.9
3.9
7.7
3.8
7.5
7.3
−40 −20
3.7
−40 −20
0
20
40
60
TJ (°C)
80
100
120
Figure 7. VCCON and VCCOFF Levels,
VCS = 0 V, ver. A, D, Q
TJ = 55°C
80
100
120
TJ = 125°C
100
ICC_UVLO (mA)
4
TJ = 0°C
3
TJ = −20°C
TJ = −40°C
2
1
80
60
40
20
0
0
5
10
15
20
25
30
0
−40
35
−20
0
20
40
60
80
100
VCC (V)
TJ (°C)
Figure 9. Current Consumption, CDRV = 0 nF,
fCS = 500 kHz, ver. D
Figure 10. Current Consumption, VCC =
VCCOFF − 0.1 V, VCS = 0 V, ver. D
30
120
60
CDRV = 10 nF
CDRV = 10 nF
25
50
20
40
ICC (mA)
ICC (mA)
40
60
TJ (°C)
120
TJ = 85°C
5
ICC (mA)
20
Figure 8. VCCON and VCCOFF Levels,
VCS = 0 V, ver. B, C
6
TJ = 25°C
0
15
10
30
20
CDRV = 1 nF
5
CDRV = 1 nF
10
CDRV = 0 nF
CDRV = 0 nF
0
−40
−20
0
20
40
60
80
100
0
−40 −20
120
0
20
40
60
80
100
120
TJ (°C)
TJ (°C)
Figure 11. Current Consumption, VCC = 12 V,
VCS = −1 to 4 V, fCS = 500 kHz, ver. A
Figure 12. Current Consumption, VCC = 12 V,
VCS = −1 to 4 V, fCS = 500 kHz, ver. D
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NCP4308
TYPICAL CHARACTERISTICS
0
−90
−92
−0.2
−94
−0.4
−98
ICS (mA)
ICS (mA)
−96
−100
−102
−104
TJ = 125°C
TJ = 85°C
TJ = 55°C
TJ = 25°C
TJ = 0°C
TJ = −20°C
TJ = −40°C
−0.6
−0.8
−1.0
−106
−108
−110
−40
−1.2
−20
0
20
40
60
80
100
−1.4
−1.0 −0.8 −0.6 −0.4 −0.2
120
0.4
0.6
VCS (V)
Figure 13. CS Current, VCS = −20 mV
Figure 14. CS Current, VCC = 12 V
2.5
−50
VTH_CS_ON (mV)
−30
2.0
ICC (mA)
0.2
TJ (°C)
3.0
TJ = 125°C
TJ = 85°C
TJ = 55°C
TJ = 25°C
TJ = 0°C
TJ = −20°C
TJ = −40°C
1.5
1.0
0.5
0
−4
0
−3
−2
0.8 1.0
−70
−90
−110
−130
−1
0
1
2
3
−150
−40 −20
4
0
20
40
60
80
100
VCS (V)
TJ (°C)
Figure 15. Supply Current vs. CS Voltage,
VCC = 12 V
Figure 16. CS Turn−on Threshold
1.0
120
0.60
VTH_CS_RESET (V)
VTH_CS_OFF (mV)
0.5
0
−0.5
−1.0
0.55
0.50
0.45
−1.5
−2.0
−40
−20
0
20
40
60
80
100
0.40
−40
120
−20
0
20
40
60
80
TJ (°C)
TJ (°C)
Figure 17. CS Turn−off Threshold
Figure 18. CS Reset Threshold
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10
100
120
NCP4308
0.80
200
0.75
180
0.70
160
0.65
140
ICS_LEAKAGE (nA)
VTH_CS_RESET (V)
TYPICAL CHARACTERISTICS
0.60
0.55
0.50
0.45
TBD
100
80
60
0.40
40
0.35
0.30
20
0
−40
0
5
10
15
20
25
30
35
−20
0
20
40
60
80
100
VCC (V)
TJ (°C)
Figure 19. CS Reset Threshold
Figure 20. CS Leakage, VCS = 150 V
60
24
55
22
120
20
50
18
tPD_OFF (ns)
tPD_ON (ns)
120
45
40
35
16
14
12
10
30
8
25
6
−20
0
20
40
60
80
100
4
−40
120
−20
0
20
40
60
80
100
120
TJ (°C)
TJ (°C)
Figure 21. Propagation Delay from CS to DRV
Output On
Figure 22. Propagation Delay from CS to DRV
Output Off
75
1.08
70
1.06
65
1.04
tMIN_TON (ms)
tMIN_TON (ns)
20
−40
60
55
50
1.02
1.00
0.98
45
0.96
40
0.94
35
−40
−20
0
20
40
60
80
100
0.92
−40
120
−20
0
20
40
60
80
100
120
TJ (°C)
TJ (°C)
Figure 23. Minimum On−time RMIN_TON = 0 W
Figure 24. Minimum On−time RMIN_TON = 10 kW
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NCP4308
TYPICAL CHARACTERISTICS
5.4
290
5.3
280
270
tMIN_TOFF (ns)
tMIN_TON (ms)
5.2
5.1
5.0
4.9
240
230
210
4.7
4.6
−40
−20
0
20
40
60
80
100
200
190
−40
120
−20
0
20
40
60
80
100
120
TJ (°C)
TJ (°C)
Figure 25. Minimum On−time RMIN_TON = 50 kW
Figure 26. Minimum Off−time RMIN_TOFF = 0 W
1.08
5.4
1.06
5.3
1.04
5.2
tMIN_TOFF (ms)
tMIN_TOFF (ms)
250
220
4.8
1.02
1.00
0.98
5.1
5.0
4.9
0.96
4.8
0.94
4.7
0.92
−40
−20
0
20
40
60
80
100
4.6
−40
120
−20
0
20
40
60
80
100
TJ (°C)
TJ (°C)
Figure 27. Minimum Off−time RMIN_TOFF =
10 kW
Figure 28. Minimum Off−time RMIN_TOFF =
50 kW
1.04
1.08
1.03
1.06
1.02
1.04
tMIN_TOFF (ms)
tMIN_TON (ms)
260
1.01
1.00
0.98
120
1.02
1.00
0.98
0.96
0.96
0.94
0.94
092
0.92
0
5
10
15
20
25
30
0
35
5
10
15
20
25
30
VCC (V)
VCC (V)
Figure 29. Minimum On−time RMIN_TON = 10 kW
Figure 30. Minimum Off−time RMIN_TOFF =
10 kW
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35
NCP4308
TYPICAL CHARACTERISTICS
5.5
10.4
VCC = 12 V, CDRV = 0 nF
VCC = 12 V, CDRV = 1 nF
VCC = 12 V, CDRV = 10 nF
VCC = 35 V, CDRV = 0 nF
VCC = 35 V, CDRV = 1 nF
VCC = 35 V, CDRV = 10 nF
VDRV (V)
10.0
9.8
5.1
VDRV (V)
10.2
VCC = 12 V, CDRV = 0 nF
VCC = 12 V, CDRV = 1 nF
VCC = 12 V, CDRV = 10 nF
VCC = 35 V, CDRV = 0 nF
VCC = 35 V, CDRV = 1 nF
VCC = 35 V, CDRV = 10 nF
5.3
9.6
4.9
4.7
9.4
4.5
9.2
9.0
−40 −20
0
20
40
60
80
4.3
−40 −20
120
100
20
40
60
80
100
120
TJ (°C)
TJ (°C)
Figure 31. Driver and Output Voltage, ver. B, D
and Q
Figure 32. Driver Output Voltage, ver. A and C
50
5.3
TJ = 125°C
TJ = 85°C
TJ = 55°C
TJ = 25°C
45
40
TJ = 0°C
TJ = −20°C
TJ = −40°C
5.2
5.1
tMAX_TON (ms)
35
30
25
20
5.0
4.9
4.8
4.7
15
4.6
10
4.5
5
0
4.4
0
0.5
1.0
1.5
2.0
2.5
4.3
−40
3.0
−20
0
20
40
60
80
100
120
VMAX_TON (V)
TJ (°C)
Figure 33. Maximum On−time, ver. Q
Figure 34. Maximum On−time, VMAX_TON = 3 V,
ver. Q
55
53
51
tMAX_TON (ms)
tMAX_TON (ms)
0
49
47
45
43
41
−40
−20
0
20
40
60
80
100
TJ (°C)
Figure 35. Maximum On−time, VMAX_TON =
0.3 V, ver. Q
www.onsemi.com
13
120
NCP4308
APPLICATION INFORMATION
General description
resistors connected to GND. If needed, blanking periods can
be modulated using additional components.
An extremely fast turn−off comparator, implemented on
the current sense pin, allows for NCP4308 implementation
in CCM applications without any additional components or
external triggering.
An output driver features capability to keep SR transistor
closed even when there is no supply voltage for NCP4308.
SR transistor drain voltage goes up and down during SMPS
operation and this is transferred through drain gate
capacitance to gate and may turn on transistor. NCP4308
uses this pulsing voltage at SR transistor gate (DRV pin) and
uses it internally to provide enough supply to activate
internal driver sink transistor. DRV voltage is pulled low
(not to zero) thanks to this feature and eliminate the risk of
turned on SR transistor before enough VCC is applied to
NCP4308.
Some IC versions include a MAX_TON circuit that helps
a quasi resonant (QR) controller to work in CCM mode
when a heavy load is present like in the example of a
printer’s motor starting up.
The NCP4308 is designed to operate either as a standalone
IC or as a companion IC to a primary side controller to help
achieve efficient synchronous rectification in switch mode
power supplies. This controller features a high current gate
driver along with high−speed logic circuitry to provide
appropriately timed drive signals to a synchronous
rectification MOSFET. With its novel architecture, the
NCP4308 has enough versatility to keep the synchronous
rectification system efficient under any operating mode.
The NCP4308 works from an available voltage with range
from 4 V (A, D & Q options) or 8 V (B & C options) to 35 V
(typical). The wide VCC range allows direct connection to
the SMPS output voltage of most adapters such as
notebooks, cell phone chargers and LCD TV adapters.
Precise turn-off threshold of the current sense comparator
together with an accurate offset current source allows the
user to adjust for any required turn-off current threshold of
the SR MOSFET switch using a single resistor. Compared
to other SR controllers that provide turn-off thresholds in the
range of −10 mV to −5 mV, the NCP4308 offers a turn-off
threshold of 0 mV. When using a low RDS(on) SR (1 mW)
MOSFET our competition, with a −10 mV turn off, will turn
off with 10 A still flowing through the SR FET, while our
0 mV turn off turns off the FET at 0 A; significantly
reducing the turn-off current threshold and improving
efficiency. Many of the competitor parts maintain a drain
source voltage across the MOSFET causing the SR
MOSFET to operate in the linear region to reduce turn−off
time. Thanks to the 8 A sink current of the NCP4308
significantly reduces turn off time allowing for a minimal
drain source voltage to be utilized and efficiency
maximized.
To overcome false triggering issues after turn-on and
turn−off events, the NCP4308 provides adjustable minimum
on-time and off-time blanking periods. Blanking times can
be adjusted independently of IC VCC using external
Current Sense Input
Figure 36 shows the internal connection of the CS
circuitry on the current sense input. When the voltage on the
secondary winding of the SMPS reverses, the body diode of
M1 starts to conduct current and the voltage of M1’s drain
drops approximately to −1 V. The CS pin sources current of
100 mA that creates a voltage drop on the RSHIFT_CS resistor
(resistor is optional, we recommend shorting this resistor).
Once the voltage on the CS pin is lower than VTH_CS_ON
threshold, M1 is turned−on. Because of parasitic
impedances, significant ringing can occur in the application.
To overcome false sudden turn−off due to mentioned
ringing, the minimum conduction time of the SR MOSFET
is activated. Minimum conduction time can be adjusted
using the RMIN_TON resistor.
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14
NCP4308
Figure 36. Current Sensing Circuitry Functionality
Figure 37). Therefore the turn−off current depends on
MOSFET RDSON. The −0.5 mV threshold provides an
optimum switching period usage while keeping enough time
margin for the gate turn-off. The RSHIFT_CS resistor
provides the designer with the possibility to modify
(increase) the actual turn−on and turn−off secondary current
thresholds. To ensure proper switching, the min_tOFF timer
is reset, when the VDS of the MOSFET rings and falls down
past the VTH_CS_RESET. The minimum off−time needs to
expire before another drive pulse can be initiated. Minimum
off−time timer is started again when VDS rises above
VTH_CS_RESET.
The SR MOSFET is turned-off as soon as the voltage on
the CS pin is higher than VTH_CS_OFF (typically −0.5 mV
minus any voltage dropped on the optional RSHIFT_CS). For
the same ringing reason, a minimum off-time timer is
asserted once the VCS goes above VTH_CS_RESET. The
minimum off-time can be externally adjusted using
RMIN_TOFF resistor. The minimum off−time generator can
be re−triggered by MIN_TOFF reset comparator if some
spurious ringing occurs on the CS input after SR MOSFET
turn−off event. This feature significantly simplifies SR
system implementation in flyback converters.
In an LLC converter the SR MOSFET M1 channel
conducts while secondary side current is decreasing (refer to
www.onsemi.com
15
NCP4308
VDS = VCS
ISEC
V TH_CS _RESET – (RSHIFT _CS*ICS )
VTH_CS_OFF – (RSHIFT _CS*ICS )
VTH_CS _ON – (RSHIFT _CS*ICS )
VDRV
Turn−on delay
Turn −off delay
Min ON−time
tMIN_TON
Min t OFF timer was
stopped here because
of VCS<VTH_CS_RESET
Min OFF−time
tMIN_TOFF
t
The tMIN_TON and t MIN_TOFF are adjustable by R MIN_TON and RMIN_TOFF resistors
Figure 37. CS Input Comparators Thresholds and Blanking Periods Timing in LLC
VDS = VCS
ISEC
VTH_CS_RESET – (RSHIFT_CS*ICS )
VTH_CS_OFF – (RSHIFT_CS*ICS )
VTH_CS _ON – (RSHIFT_CS*ICS )
VDRV
Turn−on delay
Turn −off delay
Min ON−time
Min t OFF timer was
stopped here because
of VCS<VTH_CS_RESET
tMIN_TON
Min OFF−time
tMIN_TOFF
t
The tMIN_TON and tMIN_TOFF are adjustable by RMIN_TON and RMIN_TOFF resistors
Figure 38. CS Input Comparators Thresholds and Blanking Periods Timing in Flyback
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16
NCP4308
If no RSHIFT_CS resistor is used, the turn-on, turn-off and
VTH_CS_RESET thresholds are fully given by the CS input
specification (please refer to electrical characteristics table).
The CS pin offset current causes a voltage drop that is equal
to:
V RSHIFT_CS + R SHIFT_CS * I CS
Note that RSHIFT_CS impact on turn-on and VTH_CS_RESET
thresholds is less critical than its effect on the turn−off
threshold.
It should be noted that when using a SR MOSFET in a
through hole package the parasitic inductance of the
MOSFET package leads (refer to Figure 39) causes a
turn−off current threshold increase. The current that flows
through the SR MOSFET experiences a high Di(t)/Dt that
induces an error voltage on the SR MOSFET leads due to
their parasitic inductance. This error voltage is proportional
to the derivative of the SR MOSFET current; and shifts the
CS input voltage to zero when significant current still flows
through the MOSFET channel. As a result, the SR MOSFET
is turned−off prematurely and the efficiency of the SMPS is
not optimized − refer to Figure 40 for a better understanding.
(eq. 1)
Final turn−on and turn off thresholds can be then calculated
as:
V CS_TURN_ON + V TH_CS_ON * ǒR SHIFT_CS * I CSǓ (eq. 2)
V CS_TURN_OFF + V TH_CS_OFF * ǒR SHIFT_CS * I CSǓ (eq. 3)
V CS_RESET + V TH_CS_RESET * ǒR SHIFT_CS * I CSǓ (eq. 4)
Figure 39. SR System Connection Including MOSFET and Layout Parasitic Inductances in LLC Application
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17
NCP4308
Figure 40. Waveforms From SR System Implemented in LLC Application and Using MOSFET in TO220 Package
With Long Leads − SR MOSFET channel Conduction Time is Reduced
current Di/Dt and high operating frequency is to use
lead−less SR MOSFET i.e. SR MOSFET in SMT package.
The parasitic inductance of a SMT package is negligible
causing insignificant CS turn−off threshold shift and thus
minimum impact to efficiency (refer to Figure 41).
Note that the efficiency impact caused by the error voltage
due to the parasitic inductance increases with lower
MOSFETs RDS(on) and/or higher operating frequency.
It is thus beneficial to minimize SR MOSFET package
leads length in order to maximize application efficiency. The
optimum solution for applications with high secondary
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18
NCP4308
Figure 41. Waveforms from SR System Implemented in LLC Application and Using MOSFET in SMT Package with
Minimized Parasitic Inductance − SR MOSFET Channel Conduction Time is Optimized
is not easy task and designer has to paid lot of attention to do
symmetric Kelvin connection.
It can be deduced from the above paragraphs on the
induced error voltage and parameter tables that turn−off
threshold precision is quite critical. If we consider a SR
MOSFET with RDS(on) of 1 mW, the 1 mV error voltage on
the CS pin results in a 1 A turn-off current threshold
difference; thus the PCB layout is very critical when
implementing the SR system. Note that the CS turn-off
comparator is referred to the GND pin. Any parasitic
impedance (resistive or inductive − even on the magnitude
of mW and nH values) can cause a high error voltage that is
then evaluated by the CS comparator. Ideally the CS
turn−off comparator should detect voltage that is caused by
secondary current directly on the SR MOSFET channel
resistance. In reality there will be small parasitic impedance
on the CS path due to the bonding wires, leads and soldering.
To assure the best efficiency results, a Kelvin connection of
the SR controller to the power circuitry should be
implemented. The GND pin should be connected to the SR
MOSFET source soldering point and current sense pin
should be connected to the SR MOSFET drain soldering
point − refer to Figure 39. Using a Kelvin connection will
avoid any impact of PCB layout parasitic elements on the SR
controller functionality; SR MOSFET parasitic elements
will still play a role in attaining an error voltage. Figure 42
and Figure 43 show examples of SR system layouts using
MOSFETs in TO220 and SMT packages. It is evident that
the MOSFET leads should be as short as possible to
minimize parasitic inductances when using packages with
leads (like TO220). Figure 43 shows how to layout design
with two SR MOSFETs in parallel. It has to be noted that it
Figure 42. Recommended Layout When Using SR
MOSFET in TO220 Package
Figure 43. Recommended Layout When Using SR
MOSFET in SMT Package (2x SO8 FL)
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19
NCP4308
VDS = VCS
VTH_CS_RESET
VTH_CS_OFF
VTH_CS_ON
t MIN_TOFF
Not complete
t MIN_TOFF −> IC
is not activated
Min OFF− time
t MIN_TOFF
Complete
t MIN_TOFF
activates IC
t MIN_TOFF is stopped
due to VDS drops
below VTH_CS_RESET
t MIN_TON
Min ON−time
VDRV
VCC
VCCON
t1
t3
t2 t4
t5 t7
t6
t9
t8
t10
t11 t13 t15
t12 t14
Figure 44. NCP4308 Operation after Start−Up Event
Self Synchronization
t7 and t8 allowing the IC to activate a driver output after time
t8.
Self synchronization feature during start−up can be seen
at Figure 44. Figure 44 shows how the minimum off−time
timer is reset when CS voltage is oscillating through
VTH_CS_RESET level. The NCP4308 starts operation at time
t1. Internal logic waits for one complete minimum off−time
period to expire before the NCP4308 can activate the driver
after a start−up event. The minimum off−time timer starts to
run at time t1, because VCS is higher than VTH_CS_RESET.
The timer is then reset, before its set minimum off−time
period expires, at time t2 thanks to CS voltage lower than
VTH_CS_RESET threshold. The aforementioned reset
situation can be seen again at time t3, t4, t5 and t6. A
complete minimum off−time period elapses between times
Minimum tON and tOFF Adjustment
The NCP4308 offers an adjustable minimum on−time and
off−time blanking periods that ease the implementation of a
synchronous rectification system in any SMPS topology.
These timers avoid false triggering on the CS input after the
MOSFET is turned on or off.
The adjustment of minimum tON and tOFF periods are
done based on an internal timing capacitance and external
resistors connected to the GND pin − refer to Figure 45 for
a better understanding.
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20
NCP4308
Figure 45. Internal Connection of the MIN_TON Generator (the MIN_TOFF Works in the Same Way)
10
Current through the MIN_TON adjust resistor can be
calculated as:
8
V ref
(eq. 5)
R MIN_TON
7
tMIN_TON (ms)
I R_MIN_TON +
9
If the internal current mirror creates the same current
through RMIN_TON as used the internal timing capacitor (Ct)
charging, then the minimum on−time duration can be
calculated using this equation.
t MIN_TON + C t
V ref
I R_MIN_TON
+ Ct
V ref
Vref
6
5
4
3
(eq. 6)
2
+ C t @ R MIN_TON
1
0
RMIN_TON
0
The internal capacitor size would be too large if
IR_MIN_TON was used. The internal current mirror uses a
proportional current, given by the internal current mirror
ratio. One can then calculate the MIN_TON and
MIN_TOFF blanking periods using below equations:
(eq. 7)
t MIN_TOFF + 1.00 * 10 −4 * R MIN_TOFF [ms]
(eq. 8)
20
30
40 50 60
RMIN_TON (kW)
70
80
90 100
Figure 46. MIN_TON Adjust Characteristics
10
9
8
tMIN_TOFF (ms)
t MIN_TON + 1.00 * 10 −4 * R MIN_TON [ms]
10
Note that the internal timing comparator delay affects the
accuracy of Equations 7 and 8 when MIN_TON/
MIN_TOFF times are selected near to their minimum
possible values. Please refer to Figures 46 and 47 for
measured minimum on and off time charts.
7
6
5
4
3
2
1
0
0
10
20
30
40 50 60
RMIN_TOFF (kW)
70
80
90 100
Figure 47. MIN_TOFF Adjust Characteristics
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21
NCP4308
The absolute minimum tON duration is internally clamped
to 55 ns and minimum tOFF duration to 245 ns in order to
prevent any potential issues with the MIN_TON and/or
MIN_TOFF pins being shorted to GND.
The NCP4308 features dedicated anti−ringing protection
system that is implemented with a MIN_TOFF blank
generator. The minimum off−time one−shot generator is
restarted in the case when the CS pin voltage crosses
VTH_CS_RESET threshold and MIN_TOFF period is active.
The total off-time blanking period is prolonged due to the
ringing in the application (refer to Figure 37).
Some applications may require adaptive minimum on and
off time blanking periods. With NCP4308 it is possible to
modulate blanking periods by using an external NPN
transistor − refer to Figure 48. The modulation signal can be
derived based on the load current, feedback regulator
voltage or other application parameter.
Figure 48. Possible Connection for MIN_TON and MIN_TOFF Modulation
Maximum tON adjustment
The Internal connection of the MAX_TON feature is
shown in Figure 49. Figure 49 shows a method that allows
for a modification of the maximum on−time according to
output voltage. At a lower VOUT, caused by hard overload
or at startup, the maximum on−time should be longer than at
nominal voltage. Resistor RA can be used to modulate
maximum on−time according to VOUT or any other
parameter.
The operational waveforms at heavy load in QR type
SMPS are shown in Figure 50. After tMAX_TON time is
exceeded, the synchronous switch is turned off and the
secondary current is conducted by the diode. Information
about turned off SR MOSFET is transferred by the DRV pin
through a small pulse transformer to the primary side where
it acts on the ZCD detection circuit to allow the primary
switch to be turned on. Secondary side current disappears
before the primary switch is turned on without a possibility
of cross current condition.
The NCP4308Q offers an adjustable maximum on−time
(like the min_tON and min_tOFF settings shown above) that
can be very useful for QR controllers at high loads. Under
high load conditions the QR controller can operate in CCM
thanks to this feature. The NCP4308Q version has the ability
to turn−off the DRV signal to the SR MOSFET before the
secondary side current reaches zero. The DRV signal from
the NCP4308Q can be fed to the primary side through a
pulse transformer (see Figure 4 for detail) to a transistor on
the primary side to emulate a ZCD event before an actual
ZCD event occurs. This feature helps to keep the minimum
switching frequency up so that there is better energy transfer
through the transformer (a smaller transformer core can be
used). Also another advantage is that the IC controls the SR
MOSFET and turns off from secondary side before the
primary side is turned on in CCM to ensure no cross
conduction. By controlling the SR MOSFET’s turn off
before the primary side turn off, producing a zero cross
conduction operation, this will improve efficiency.
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22
NCP4308
Figure 49. Internal Connection of the MAX_TON Generator, NCP4308Q
VDS = VCS
ISEC
V TH_CS _RESET – (RSHIFT _CS*ICS )
VTH_CS_OFF – (RSHIFT _CS*ICS )
VTH_CS _ON – (RSHIFT _CS*ICS )
Primary virtual ZCD
detection delay
V DRV
Turn−on delay
Turn −off delay
Min ON−time
t MIN _TON
Min OFF−time
tMIN _TOFF
Max ON−time
tMAX _TON
t
The tMIN _TON and tMIN _TOFF are adjustable by R MIN _TON and R MIN _TOFF resistors, t MAX_TON is adjustable by R MAX_TON
Figure 50. Function of MAX_TON Generator in Heavy Load Condition
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23
NCP4308
Power Dissipation Calculation
Therefore, the input capacitance of a MOSFET operating
in ZVS mode is given by the parallel combination of the gate
to source and gate to drain capacitances (i.e. Ciss capacitance
for given gate to source voltage). The total gate charge,
Qg_total, of most MOSFETs on the market is defined for hard
switching conditions. In order to accurately calculate the
driving losses in a SR system, it is necessary to determine the
gate charge of the MOSFET for operation specifically in a
ZVS system. Some manufacturers define this parameter as
Qg_ZVS. Unfortunately, most datasheets do not provide this
data. If the Ciss (or Qg_ZVS) parameter is not available then
it will need to be measured. Please note that the input
capacitance is not linear (as shown Figure 51) and it needs
to be characterized for a given gate voltage clamp level.
It is important to consider the power dissipation in the
MOSFET driver of a SR system. If no external gate resistor
is used and the internal gate resistance of the MOSFET is
very low, nearly all energy losses related to gate charge are
dissipated in the driver. Thus it is necessary to check the SR
driver power losses in the target application to avoid over
temperature and to optimize efficiency.
In SR systems the body diode of the SR MOSFET starts
conducting before SR MOSFET is turned−on, because there
is some delay from VTH_CS_ON detect to turn−on the driver.
On the other hand, the SR MOSFET turn off process always
starts before the drain to source voltage rises up
significantly. Therefore, the MOSFET switch always
operates under Zero Voltage Switching (ZVS) conditions
when in a synchronous rectification system.
The following steps show how to approximately calculate
the power dissipation and DIE temperature of the NCP4308
controller. Note that real results can vary due to the effects
of the PCB layout on the thermal resistance.
Step 2 − Gate Drive Losses Calculation:
Gate drive losses are affected by the gate driver clamp
voltage. Gate driver clamp voltage selection depends on the
type of MOSFET used (threshold voltage versus channel
resistance). The total power losses (driving loses and
conduction losses) should be considered when selecting the
gate driver clamp voltage. Most of today’s MOSFETs for SR
systems feature low RDS(on) for 5 V VGS voltage. The
NCP4308 offers both a 5 V gate clamp and a 10 V gate
clamp for those MOSFET that require higher gate to source
voltage.
The total driving loss can be calculated using the selected
gate driver clamp voltage and the input capacitance of the
MOSFET:
Step 1 − MOSFET Gate−to Source Capacitance:
During ZVS operation the gate to drain capacitance does
not have a Miller effect like in hard switching systems
because the drain to source voltage does not change (or its
change is negligible).
P DRV_total + V CC @ V CLAMP @ C g_ZVS @ f SW (eq. 9)
Where:
VCC
VCLAMP
Cg_ZVS
is the NCP4308 supply voltage
is the driver clamp voltage
is the gate to source capacitance of the
MOSFET in ZVS mode
fsw
is the switching frequency of the target
application
The total driving power loss won’t only be dissipated in
the IC, but also in external resistances like the external gate
resistor (if used) and the MOSFET internal gate resistance
(Figure 50). Because NCP4308 features a clamped driver,
it’s high side portion can be modeled as a regular driver
switch with equivalent resistance and a series voltage
source. The low side driver switch resistance does not drop
immediately at turn−off, thus it is necessary to use an
equivalent value (RDRV_SIN_EQ) for calculations. This
method simplifies power losses calculations and still
provides acceptable accuracy. Internal driver power
dissipation can then be calculated using Equation 10:
C iss + C gs ) C gd
C rss + C gd
C oss + C ds ) C gd
Figure 51. Typical MOSFET Capacitances
Dependency on VDS and VGS Voltages
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24
NCP4308
Figure 52. Equivalent Schematic of Gate Drive Circuitry
P DRV_IC +
1
@ C g_ZVS @ V CLAMP 2 @ f SW @
2
ǒ
R DRV_SINK_EQ
Ǔ
R DRV_SINK_EQ ) R G_EXT ) R g_int
1
) @ C g_ZVS @ V CLAMP 2 @ f SW @
2
ǒ
R DRV_SOURCE_EQ
) C g_ZVS @ V CLAMP @ f SW @ ǒV CC * V CLAMPǓ
Ǔ
(eq. 10)
R DRV_SOURCE_EQ ) R G_EXT ) R g_int
Step 4 − IC Die Temperature Arise Calculation:
Where:
RDRV_SINK_EQ
The die temperature can be calculated now that the total
internal power losses have been determined (driver losses
plus internal IC consumption losses). The package thermal
resistance is specified in the maximum ratings table for a
35 mm thin copper layer with no extra copper plates on any
pin (i.e. just 0.5 mm trace to each pin with standard soldering
points are used).
The DIE temperature is calculated as:
is the NCP4308x driver low side switch
equivalent resistance (0.5 W)
RDRV_SOURCE_EQ is the NCP4308x driver high side switch
equivalent resistance (1.2 W)
is the external gate resistor (if used)
RG_EXT
Rg_int
is the internal gate resistance of the
MOSFET
Step 3 − IC Consumption Calculation:
T DIE + ǒP DRV_IC ) P CCǓ @ R qJ−A ) T A
In this step, power dissipation related to the internal IC
consumption is calculated. This power loss is given by the
ICC current and the IC supply voltage. The ICC current
depends on switching frequency and also on the selected min
tON and tOFF periods because there is current flowing out
from the min tON and tOFF pins. The most accurate method
for calculating these losses is to measure the ICC current
when CDRV = 0 nF and the IC is switching at the target
frequency with given MIN_TON and MIN_TOFF adjust
resistors. IC consumption losses can be calculated as:
P CC + V CC @ I CC
Where:
PDRV_IC
PCC
RqJA
TA
(eq. 11)
www.onsemi.com
25
(eq. 12)
is the IC driver internal power dissipation
is the IC control internal power
dissipation
is the thermal resistance from junction to
ambient
is the ambient temperature
NCP4308
PRODUCT OPTIONS
OPN
Package
UVLO [V]
DRV clamp [V]
Pin 5 function
NCP4308ADR2G
SOIC8
4.5
4.7
NC
NCP4308AMTTWG
WDFN8
4.5
4.7
NC
NCP4308DDR2G
SOIC8
4.5
9.5
NC
NCP4308DMNTWG
DFN8
4.5
9.5
NC
NCP4308DMTTWG
WDFN8
4.5
9.5
NC
NCP4308QDR2G
SOIC8
4.5
9.5
MAX_TON
Usage
LLC, CCM flyback, DCM flyback, QR,
QR with primary side CCM control
QR with forced CCM from secondary side
ORDERING INFORMATION
Device
NCP4308ADR2G
Package
Package marking
Packing
Shipping†
SOIC8
NCP4308A
SOIC−8
(Pb−Free)
2500 /Tape & Reel
WDFN−8
(Pb−Free)
3000 /Tape & Reel
DFN−8
(Pb−Free)
4000 /Tape & Reel
NCP4308DDR2G
NCP4308D
NCP4308QDR2G
NCP4308AMTTWG
NCP4308Q
WDFN8
NCP4308DMTTWG
NCP4308DMNTWG
EA
ED
DFN8
4308D
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
www.onsemi.com
26
NCP4308
PACKAGE DIMENSIONS
SOIC−8 NB
CASE 751−07
ISSUE AK
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
−X−
A
8
5
S
B
0.25 (0.010)
M
Y
M
1
4
K
−Y−
G
C
N
DIM
A
B
C
D
G
H
J
K
M
N
S
X 45 _
SEATING
PLANE
−Z−
0.10 (0.004)
H
M
D
0.25 (0.010)
M
Z Y
S
X
J
S
SOLDERING FOOTPRINT*
1.52
0.060
7.0
0.275
4.0
0.155
0.6
0.024
1.270
0.050
SCALE 6:1
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
www.onsemi.com
27
MILLIMETERS
MIN
MAX
4.80
5.00
3.80
4.00
1.35
1.75
0.33
0.51
1.27 BSC
0.10
0.25
0.19
0.25
0.40
1.27
0_
8_
0.25
0.50
5.80
6.20
INCHES
MIN
MAX
0.189
0.197
0.150
0.157
0.053
0.069
0.013
0.020
0.050 BSC
0.004
0.010
0.007
0.010
0.016
0.050
0 _
8 _
0.010
0.020
0.228
0.244
NCP4308
PACKAGE DIMENSIONS
DFN8 4x4
CASE 488AF
ISSUE C
A
B
D
PIN ONE
REFERENCE
0.15 C
2X
0.15 C
2X
0.10 C
8X
ÉÉ
ÉÉ
ÉÉ
0.08 C
L1
DETAIL A
E
OPTIONAL
CONSTRUCTIONS
ÇÇ
ÇÇ
ÉÉ
TOP VIEW
EXPOSED Cu
ÇÇÇÇ
DETAIL B
A
A1
C
SIDE VIEW
ÇÇ
MOLD CMPD
ÉÉÉ
ÉÉÉ
ÇÇÇ
A3
A1
DETAIL B
(A3)
NOTE 4
ALTERNATE
CONSTRUCTIONS
SEATING
PLANE
D2
DETAIL A
1
ÇÇ
8
K
e
NOTES:
1. DIMENSIONS AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.15 AND 0.30MM FROM TERMINAL TIP.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
5. DETAILS A AND B SHOW OPTIONAL
CONSTRUCTIONS FOR TERMINALS.
L
L
8X
DIM
A
A1
A3
b
D
D2
E
E2
e
K
L
L1
MILLIMETERS
MIN
MAX
0.80
1.00
0.00
0.05
0.20 REF
0.25
0.35
4.00 BSC
1.91
2.21
4.00 BSC
2.09
2.39
0.80 BSC
0.20
−−−
0.30
0.50
−−−
0.15
SOLDERING FOOTPRINT*
L
8X
2.21
4
0.63
E2
5
8X
4.30 2.39
b
0.10 C A B
0.05 C
PACKAGE
OUTLINE
NOTE 3
BOTTOM VIEW
8X
0.80
PITCH
0.35
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
www.onsemi.com
28
NCP4308
PACKAGE DIMENSIONS
WDFN8 2x2, 0.5P
CASE 511AT
ISSUE O
D
L
A
B
L
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.15 AND 0.30 MM FROM TERMINAL TIP.
L1
PIN ONE
REFERENCE
0.10 C
2X
2X
ÍÍÍ
ÍÍÍ
ÍÍÍ
0.10 C
DETAIL A
E
ALTERNATE TERMINAL
CONSTRUCTIONS
ÉÉ
ÉÉ
TOP VIEW
EXPOSED Cu
DETAIL B
0.05 C
0.05 C
A1
A3
SIDE VIEW
e/2
MOLD CMPD
DETAIL B
A
8X
MILLIMETERS
MIN
MAX
0.70
0.80
0.00
0.05
0.20 REF
0.20
0.30
2.00 BSC
2.00 BSC
0.50 BSC
0.40
0.60
--0.15
0.50
0.70
ALTERNATE
CONSTRUCTIONS
C
SEATING
PLANE
RECOMMENDED
SOLDERING FOOTPRINT*
DETAIL A
e
7X
1
DIM
A
A1
A3
b
D
E
e
L
L1
L2
7X
PACKAGE
OUTLINE
0.78
L
4
L2
2.30
8
5
8X
BOTTOM VIEW
b
0.10 C A
0.05 C
0.88
1
B
8X
NOTE 3
0.30
0.50
PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and the
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NCP4308/D