TI CDCD5704 Rambus xdr clock generator Datasheet

CDCD5704
www.ti.com
SCAS823 – DECEMBER 2006
Rambus™ XDR™ CLOCK GENERATOR
FEATURES
•
•
•
•
•
•
•
•
•
•
•
•
High-Speed Clock Support: 300-MHz–667-MHz
Clock Source for XDR Memory Subsystems
and Redwood Logic Interface
Quad (Open-Drain) Differential Output Drivers
Spread-Spectrum Compatible Clock Input Can
Be Distributed to Minimize EMI
Differential or Single-Ended Reference Clock
Input of 100 MHz or 133 MHz
Serial Interface Features: Programmable
Frequency Multiplier, Select Any One to Four
Outputs and Mode of Operation
Supports Frequency Multiplication Factors of:
×3, ×4, ×5, ×6, ×8, ×9/2, ×15/2, ×15/4
All PLL Loop Filter Components Are
Integrated
Low |Cycle-to-Cycle| of 1–6 Cycle Jitter:
– 40 ps: 300–635 MHz
– 30 ps: 636–667 MHz
PLLs Are Powered Down if No Valid REF
Clock (<10 MHz) Is Detected or VDD Is Below
1.6 V
Operates From Single 2.5-V Supply (±0.125 V)
Packaged in TSSOP-28
Commercial Temperature Range 0°C to 70°C
PW PACKAGE
(TOP VIEW)
VDDP
VSSP
ISET
VSS
REFCLK
REFCLKB
VDDC
VSSC
SCL
SDA
EN
ID0
ID1
BYPASS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VDD
CLK0
CLK0B
VSS
CLK1
CLK1B
VDD
VSS
CLK2
CLK2B
VSS
CLK3
CLK3B
VDD
P0043-01
APPLICATIONS
•
XDR Memory Subsystem and Redwood Logic
Interface
DESCRIPTION
The CDCD5704 clock generator provides the necessary clock signals to support an XDR memory subsystem
and Redwood logic interface using a reference clock input with or without spread-spectrum modulation.
Contained in a 28-pin TSSOP package that includes four differential clock outputs, the CDCD5704 provides an
off-the-shelf solution for a broad range of high-performance interface applications.
The block diagram shows the major components of the CDCD5704, which include a phase-locked loop, a
bypass multiplexer, and four differential output buffers (CLK0 to CLK3). All four outputs can be disabled by a
logical low at the input of the EN pin. An output is enabled when EN is high and a value of 1 is in its serial
interface register (RegA–RegD).
The PLL receives a reference clock input signal, REFCLK, and outputs a clock signal at a frequency equal to the
input frequency times the multiplication factor. The PLL output clock signal is fed to the differential output buffers
to drive the enabled clocks. Disabled outputs are set to high impedance.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Rambus, XDR are trademarks of Rambus Inc.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2006, Texas Instruments Incorporated
CDCD5704
www.ti.com
SCAS823 – DECEMBER 2006
The bypass mode routes the input clock REFCLK to the differential output buffers, bypassing the PLL.
To ensure that the CDCD5704 clock generator always performs correctly, the device switches off the PLL and
the outputs are in the high-impedance state, once the clock input is below 10 MHz. If the supply voltage VDD is
less than VPUC, all logic gates are reset, the PLL is powered down, and the outputs are in the high-impedance
state. Therefore, the device only starts its operation if these minimum requirements are met.
Because the CDCD5704 is based on PLL circuitry, it requires a stabilization time to achieve phase-lock of the
PLL. With use of an external reference clock, this signal must be fixed-frequency and fixed-phase prior to the
start of stabilization time.
The device operates from a single 2.5-V supply voltage. The CDCD5704 device is characterized for operation
from 0°C to 70°C.
FUNCTIONAL BLOCK DIAGRAM
VDDP
VDDC
VDD
BYPASS
CLK0
CLK0
MUX
REFCLK
REFCLKB
CLK0
CLK0B
CLK1
PLL 1
300 MHz to 667 MHz
CLk1
CLK1B
CLK2
CLK2
VDDP
VDDC
VDD
SDA
Power
Down
Logic
CLK2B
CLK3
CLK3
Serial Interface
Control Logic
CLK3B
SCL
ID0
ID1
EN
ISET
Current and Voltage
Reference
RSET
VSSP
VSSC
VSS
B0137-01
2
Submit Documentation Feedback
CDCD5704
www.ti.com
SCAS823 – DECEMBER 2006
Table 1. TERMINAL FUNCTIONS
TERMINAL
NAME
TYPE
NO.
DESCRIPTION
BYPASS
14
Input
CLK0
27
Output
If 0, the PLL is bypassed and the PLL is switched off.
Output for Clock0
CLK0B
26
Output
Complementary output for Clock0
CLK1
24
Output
Output for Clock1
CLK1B
23
Output
Complementary output for Clock1
CLK2
20
Output
Output for Clock2
CLK2B
19
Output
Complementary output for Clock2
CLK3
17
Output
Output for Clock3
CLK3B
16
Output
Complementary output for Clock3
EN
11
Input
Output enable; if 0, all outputs are disabled.
ID0
12
Input
Device ID, bit 0
ID1
13
Input
Device ID, bit 1
ISET
3
Output
REFCLK
5
Input
Reference clock input
REFCLKB
6
Input
Complementary reference clock input
SCL
9
Input
Serial interface clock, 3.3-V compatible
Serial interface data, 3.3-V compatible
Set clock driver current with external resistor
SDA
10
Input
VDD
15, 22, 28
Power
2.5-V power supply for outputs
7
Power
2.5-V power supply for core
VDDC
VDDP
1
Power
2.5-V power supply for PLL
4, 18, 21, 25
Ground
Ground
VSSC
8
Ground
Ground for core
VSSP
2
Ground
Ground for PLL
VSS
SERIAL INTERFACE
The following section describes the serial interface programming. In general, the serial interface slave supports
byte-write/-read and word-write/-read protocol as defined in the SMBus or I2C specification.
Serial Interface Operation Requirement
The internal timing of the serial interface logic block in the CDCD5704 requires a timing reference derived from
the input clock (REFCLK). A reference clock must be present at the REFCLK pin for the serial interface to be
operational.
Serial Interface Device Address
A6
A5
A4
A3
A2
A1
A0
W/R
1
1
0
1
1
ID1
ID0
0/1
The device-ID is determined by the external pins ID0 and ID1. They are part of the device 8-bit address.
Therefore, four different devices (00, 01, 10, and 11) can be addressed via the same serial interface. The least
significant bit of the address designates a write or read operation.
R/W Bit:
0 = write to CDCD5704 device
1 = read from CDCD5704 device
Submit Documentation Feedback
3
CDCD5704
www.ti.com
SCAS823 – DECEMBER 2006
Command Code Definition
Bit
Description
C7
1 = byte-write/-read or word-write/-read operation
(C6:C0)
Byte offset for byte-write/-read or word-write/-read operation
Command Code for Byte-Write/-Read
Operation
Hex Code
C7
C6
C5
C4
C3
C2
C1
C0
Byte 0
80h
1
0
0
0
0
0
0
0
Byte 1
81h
1
0
0
0
0
0
0
1
Byte 2
82h
1
0
0
0
0
0
1
0
Hex Code
C7
C6
C5
C4
C3
C2
C1
C0
Word 0: Byte 0 and byte 1
80h
1
0
0
0
0
0
0
0
Word 1: Byte 1 and byte 2
81h
1
0
0
0
0
0
0
1
Command Code for Word-Write/-Read
Operation
Serial Interface Generic Programming Sequence
1
7
1
1
S
Slave Address
Wr
A
S
Start Condition
Sr
Repeated Start Condition
Rd
Read (Bit Value = 1)
Wr
Write (Bit Value = 0)
A
Acknowledge (ACK = 0 and NACK = 1)
P
Stop Condition
PE
8
Data Byte
1
1
A
P
Packet Error
Master-to-Slave Transmission
Slave-to-Master Transmission
M0053-01
Byte-Write Programming Sequence
1
7
1
1
8
1
8
1
1
S
Slave Address
Wr
A
Command Code
A
Data Byte
A
P
Byte-Read Programming Sequence
1
7
1
1
8
1
1
7
1
1
S
Slave Address
Wr
A
Command Code
A
S
Slave Address
Rd
A
...
8
1
1
Data Byte
A
P
1
4
Submit Documentation Feedback
CDCD5704
www.ti.com
SCAS823 – DECEMBER 2006
Word-Write Programming Sequence
1
7
1
1
8
1
8
1
S
Slave Address
Wr
A
Command Code
A
Data Byte Low
A
...
8
1
1
Data Byte High
A
P
Word-Read Programming Sequence
1
7
1
1
8
1
1
7
1
1
S
Slave Address
Wr
A
Command Code
A
S
Slave Address
Rd
A
8
1
8
1
1
Data Byte
A
Data Byte
A
P
...
1
P
S
Bit 6
Bit 7 (MSB)
tw(SCLL)
A
Bit 0 (LSB)
P
tw(SCLH)
tr(SM)
tf(SM)
VIH(SM)
SCLK
VIL(SM)
th(START)
tsu(START)
t(BUS)
th(SDATA)
tsu(SDATA)
tr(SDATA)
tsu(STOP)
tf(SDATA)
VIH(SM)
SDATA
VIL(SM)
T0131-01
Figure 1. Timing Diagram, Serial Control Interface
Submit Documentation Feedback
5
CDCD5704
www.ti.com
SCAS823 – DECEMBER 2006
Serial Interface Configuration Command Bitmap
Byte 0
Bit
Bit Name
Description/Function
Type
Power-Up Condition
7
RES
Reserved
R/W
0
6
MULT2
Multiplication factor, bit 2
R/W
0
5
MULT1
Multiplication factor, bit 1
R/W
0
4
MULT0
Multiplication factor, bit 0
R/W
1
3
RegA
Enable CLK0
R/W
1
2
RegB
Enable CLK1
R/W
1
1
RegC
Enable CLK2
R/W
1
0
RegD
Enable CLK3
R/W
1
Bit
Bit Name
Description/Function
Type
Power-Up Condition
7
RES
Reserved
R/W
0
6
RES
Reserved
R/W
0
5
RES
Reserved
R/W
0
4
RES
Reserved
R/W
0
3
RES
Reserved for vendor option
R/W
0
2
RES
Reserved for vendor option
R/W
0
1
RES
Reserved for vendor option
R/W
0
0
RegTest
Vendor test register. If high, then Vendor Test
R/W
0
Bit
Bit Name
Description/Function
Type
Power-Up Condition
7
REV0
Device revision, bit 4
R
0
6
REV0
Device revision, bit 3
R
0
5
REV0
Device revision, bit 2
R
0
4
REV0
Device revision, bit 1
R
0
3
REV0
Device revision, bit 0
R
0
2
VID2
Vendor ID bit 2
R
0
1
VID1
Vendor ID bit 1
R
1
0
VID0
Vendor ID bit 0
R
1
Byte 1
Byte 2
6
Submit Documentation Feedback
CDCD5704
www.ti.com
SCAS823 – DECEMBER 2006
FUNCTIONAL DESCRIPTION OF THE LOGIC
PLL Multiplication Factor Selection
Mult2
(1)
(2)
Mult1
Mult0
Output Frequency (MHz)
Multiplication
Factor
REFCLK = 100 MHz
REFCLK = 133 MHz
0
0
0
3
300
400
0 (1)
0 (1)
1 (1)
4 (1)
400
533
0
1
0
5
500
667
0
1
1
6
600
800 (2)
1
0
0
8
800 (2)
– (2)
1
0
1
9/2
450
600
1
1
0
15/2
750 (2)
– (2)
1
1
1
15/4
375
500
Default settings after power up
Output at this frequency does not conform to all the ac device characteristics in the Device Characteristics table, or ouput frequency is
not supported.
Modes of Operation
EN
BYPASS
Reg-Test
RegA
RegB
RegC
RegD
CLK0
CLK1
CLK2
CLK3
L
X
X
X
X
X
X
HI-Z
HI-Z
HI-Z
HI-Z
H
X
1
X
X
X
X
H
L
0
X
X
X
X
REFCLK
REFCLK
REFCLK
REFCLK
H
H
0
0
0
0
0
HI-Z
HI-Z
HI-Z
HI-Z
H
H
0
1
0
0
0
PLL CLK
HI-Z
HI-Z
HI-Z
H
H
0
0
1
0
0
HI-Z
PLL CLK
HI-Z
HI-Z
H
H
0
1
1
0
0
PLL CLK
PLL CLK
HI-Z
HI-Z
H
H
0
0
0
1
0
HI-Z
HI-Z
PLL CLK
HI-Z
H
H
0
1
0
1
0
PLL CLK
HI-Z
PLL CLK
HI-Z
H
H
0
0
1
1
0
HI-Z
PLL CLK
PLL CLK
HI-Z
H
H
0
1
1
1
0
PLL CLK
PLL CLK
PLL CLK
HI-Z
H
H
0
0
0
0
1
HI-Z
HI-Z
HI-Z
PLL CLK
H
H
0
1
0
0
1
PLL CLK
HI-Z
HI-Z
PLL CLK
H
H
0
0
1
0
1
HI-Z
PLL CLK
HI-Z
PLL CLK
H
H
0
1
1
0
1
PLL CLK
PLL CLK
HI-Z
PLL CLK
H
H
0
0
0
1
1
HI-Z
HI-Z
PLL CLK
PLL CLK
H
H
0
1
0
1
1
PLL CLK
HI-Z
PLL CLK
PLL CLK
H
H
0
0
1
1
1
HI-Z
PLL CLK
PLL CLK
PLL CLK
H
0 (1)
1 (1)
1 (1)
1 (1)
1 (1)
PLL CLK
PLL CLK
PLL CLK
PLL CLK
H
(1)
RESERVED FOR VENDOR TEST
Default settings after power up
Submit Documentation Feedback
7
CDCD5704
www.ti.com
SCAS823 – DECEMBER 2006
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted) (1)
VDD
Supply voltage range
(2)
VI
Input voltage range
VO
Output voltage range
IIK
Input clamp current, (VI < 0, VI > VDD)
IO
Continuous output current
Thermal resistance, junction-to-ambient
RθJC
Thermal resistance, junction-to-case
RθJB
Thermal resistance, junction-to-board
TJ
Maximum junction temperature
Tstg
Storage temperature range
(3)
UNIT
V
For SCL and SDA
–0.3 to 3.6
For all other inputs
–0.3 to VDD + 0.25
(2)
RθJA
VALUE
–0.3 to 2.8
–0.5 to VDD + 0.5
V
±20
mA
±50
mA
No airflow
94.4
Airflow 150 ft/min
82.8
Airflow 250 ft/min
79.1
Airflow 500 ft/min
(1)
(2)
(3)
(3)
(3)
V
K/W
74
No airflow
31.8
K/W
No airflow
68.9
K/W
125
°C
–65 to 150
°C
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input and output negative voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
The package thermal impedance is calculated in accordance with JESD 51 and JEDEC2S1P (high-k board).
RECOMMENDED DC OPERATING CONDITIONS
MIN
NOM
MAX
UNIT
VDDP
Supply voltage for PLL
2.375
2.5
2.625
V
VDDC
Supply voltage for core
2.375
2.5
2.625
V
VDD
Supply voltage for clock buffers
2.375
2.5
TA
Operating free-air temperature
VIL,CLK
Low-level input voltage, REFCLK/REFCLKB
VIX,CLK
VIH,CLKD
∆VIX,CLK
Difference in crossing-point voltage
VIL SE
Low-level, single-ended input voltage, REFCLK
Vth SE
Single-ended input-voltage threshold, REFCLK
VIH SE
High-level, single-ended input voltage, REFCLK
VIL L
Low-level input voltage, ID0, ID1, EN, BYPASS
VIH L
High-level input voltage, ID0, ID1, EN, BYPASS
VIL SM
Low-level input voltage, SCL, SDA
(2)
VIH SM
High-level input voltage, SCL, SDA
(2)
1.4
(1)
(2)
8
2.625
V
0
70
°C
–0.15
0.15
V
Crossing-point voltage, input voltage threshold, REFCLK/REFCLKB
0.2
0.55
V
High-level input voltage, REFCLK/REFCLKB
0.6
0.95
V
0.15
V
–0.15
(1)
Vth
– 0.3
V
0.35
Vth
0.5 VDD
V
SE + 0.3
2.625
V
–0.15
0.8
V
1.4
2.625
V
–0.15
0.8
V
3.465
V
SE
When using a single-ended clock input, Vth is supplied to the REFCLKB pin. Duty cycle of single-ended REFCLK input is measured at
Vth.
This range of SCL and SDA input high voltage allows the CDCD5704 to co-exist with 3.3 V, 2.5 V, and 1.8 V devices on the same
serial-interface bus system.
Submit Documentation Feedback
CDCD5704
www.ti.com
SCAS823 – DECEMBER 2006
RECOMMENDED AC OPERATING CONDITIONS
MIN
tCYCLE,IN
REFCLK/REFCLKB input cycle time
tCYC,TEST REFCLK/REFCLKB input cycle time for BYPASS
NOM
cycles (2)
DCIN
Input duty cycle over 10,000
tr/tf
Rise and fall time for REFCLK signal from 20% to 80% of input voltage VIN
tcr/tcf
Difference between rise time and fall time of REFCLK signal from 20% to 80%
frequency (3)
fm,IN
SSC frequency modulation repeat
Pm tria
Modulation index (= frequency deviation/center frequency) for triangle modulation (3)
Pm n tria
Modulation index (= frequency deviation/center frequency) for non-triangle modulation (4)
tSR
Input slew rate REFCLK/REFCLKB
UNIT
7
11
ns
4
40
ns
185
ps
Input |cycle-to-cycle| jitter (1)
tJ,IN
MAX
40%
60%
175
700
ps
150
ps
33
kHz
30
0.6%
0.5%
1
4
V/ns
100
kHz
SERIAL INTERFACE TIMING
fSCLK
SCLK frequency (5)
0
th(START)
START hold time (5)
4
µs
4.7
µs
4
µs
4.7
µs
300
ps
250
ps
duration (5)
tw(SCLL)
SCLK low-pulse
tw(SCLH)
SCLK high-pulse duration (5)
tsu(START) START setup time (5)
th(SDATA)
SDATA hold
time (5)
tsu(SDATA) SDATA setup time (5)
tr(SDATA)/
tr(SM)
SDATA/SCLK input rise time (5)
1000
ns
tf(SDATA)/
tf(SM)
SDATA/SCLK input fall time (5)
300
ns
tsu(STOP)
STOP setup time (5)
t(BUS)
Bus free time
(1)
(2)
(3)
(4)
(5)
4
µs
4.7
µs
RefCLK jitter is measured at (VIH(nom) – VIL(nom))/2 and is the absolute value of the worst-case deviation.
Measured at crossing points for differential clock input or at input threshold voltage VTH for single-ended clock input.
If input modulation is used; input modulation is allowed but not required.
The amount of allowed spreading for any non-triangular modulation is determined by the induced downstream tracking skew, which
cannot exceed the skew generated by the specified 0.6% triangular modulation. Typically, the amount of allowed non-triangular
modulation is about 0.5%.
See Figure 1 for the timing behavior of the serial interface.
DEVICE CHARACTERISTICS
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OVERALL PARAMETER
IDD
Supply current (= IVDD + IVDDP + IVDDC)
VPUC
Supply voltage threshold for power-up control
circuit
At 300 MHz and 2.625 V
70
85
At 667 MHz and 2.625 V
90
115
mA
Over complete supply voltage
range
1.1
1.8
2.2
V
Output load; see Figure 3.
0.9
1
1.1
V
0.3
0.325
0.35
V
DC DEVICE CHARACTERISTICS
Differential output crossing-point voltage (1)
VOX
single-ended) (2)
VCOS
Output voltage swing (p-p,
VOL,ABS
Absolute output low voltage (3)
VISET
Reference voltage for swing control current
IREF (4)
(1)
(2)
(3)
(4)
0.85
VDD = 2.375 V to 2.625 V, T = 0°C
to 70°C
0.98
V
1
1.02
V
VOX is measured on external divider as shown in Figure 3.
VCOS = (clock output high voltage – clock output low voltage), at the measurement points shown in Figure 3, excluding overshoot and
undershoot.
VOL,ABS is measured at the clock output of the package, instead of the measurement points of Figure 3.
IREF is equal to VISET/RRC. Tolerance of RRC must be ±1% or smaller.
Submit Documentation Feedback
9
CDCD5704
www.ti.com
SCAS823 – DECEMBER 2006
DEVICE CHARACTERISTICS (continued)
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
IOL/IREF
Ratio of output low current to reference current
IOL,ABS
Minimum current at VOL,ABS (5)
VOL,ABS = 0.85 V
VOL,SDA
SDA output low voltage
VDD = 2.375 V to 2.625 V,
IOH = 4 mA
IOL,SDA
SDA output low current
VDD = 2.375 V to 2.625 V,
VO = 0.8 V
IOZ
Output 3-state current
CLK0 to CLK4
IIR
REFCLK input current
IIL
Logic input current
MIN
TYP
MAX
6.8
7
7.2
45
UNIT
mA
0.4
6
V
mA
±50
µA
VI = 0 V or VDD
±5
µA
VI = 0 V or VDD
±10
µA
AC DEVICE CHARACTERISTICS
CIR
Input capacitance, REFCLK,
REFCLKB (6)
2
7
pF
CIL
Input capacitance logic pins (7)
2
10
pF
tCYCLE
Clock cycle time
3.33
ns
tjit(per)
300 MHz to 667 MHz, possible
SSC is not taken into account
(8)
|Cycle-to-cycle jitter| of 1–6 clock cycles
1.5
10,000 cycles, 300 MHz
to 635 MHz (9)
40
10,000 cycles, 636 MHz
to 667 MHz (9)
30
ps
(10)
L1
SSB phase noise at 1 MHz
300-MHz–667-MHz output
L20
SSB phase noise at 20 MHz
300-MHz–667-MHz output (10)
–115
–97
dBc/Hz
–150
–128
dBc/Hz
∆tskew(o)
Drift in tskew(o) (11)
VDD = 2.375 V to 2.625 V,
T = 0 to 70°C
odc
Output duty cycle
tODC,ERR
|Cycle-to-cycle| duty-cycle error
tERR,SSC
PLL output phase error when tracking SSC
tr/tf
Output rise and fall time
VOUT = 20%–80%
tcr/tcf
Difference between output rise and fall times
VOUT = 20%–80%, fout = 300 MHz
to 667 MHz
ZOUT
Output dynamic impedance (12)
VOL = 0.9 V
tL
Power-up lock time
Time from VDD, VDDP, VDDC
being applied and settled until
clock outputs are settled
3
ms
tL(ω)
PLL lock time after (1) frequency change via
serial interface (programming of SCL and SDA
pins completed) or (2) EN and/or BYPASS
changed state
Time from signals for selecting a
mode of operation (1) or (2)
applied and settled until clock
outputs are settled
3
ms
15
45%
50%
55%
300 MHz to 635 MHz
40
636 MHz to 667 MHz
30
(5)
(6)
(7)
(8)
ps
ps
–100
100
ps
100
300
ps
100
ps
Ω
750
Minimum IOL,ABS is measured at the clock output pins of the package, as shown in Figure 3.
Capacitance measured at frequency = 1 MHz, dc bias = 0.9 V, and VAC < 100 mV
Capacitance measured at frequency = 1 MHz, dc bias = 0.9 V, and VAC < 100 mV
Maximum and minimum output clock cycle times are based on nominal output frequency of 300 MHz and 667 MHz, respectively. For
spread-spectrum-modulated differential or single-ended REFCLK, the output clock tracks the modulation of the input.
(9) Output short-term jitter specification is the absolute value of the worst-case deviation and is defined in the Jitter section.
(10) Device must not exceed the upper limit of L(f) for 1-MHz to 100-MHz offset as shown in the Phase Noise section.
(11) tskew is the timing difference between any two of the four differential clocks and is measured at common-mode voltage. ∆tskew is the
change in tskew when the operating temperature and supply voltage change.
(12) ZOUT is defined at the output pins directly. The value is determined as the ac small-signal impedance at low frequencies (< 100 kHz)
and when output is driving a high state.
10
Submit Documentation Feedback
CDCD5704
www.ti.com
SCAS823 – DECEMBER 2006
PHASE NOISE
For the offset frequency range from 1 MHz to 100 MHz, phase noise of the CDCD5704 does not exceed the
single-sideband phase noise (spectral purity) described by the following equation given by Rambus.
L(f) = 10 log [1 + (50 × 106 / f)2.4] – 138 dBc/Hz
Selected numerical values are in given in the following table.
f = offset frequency
1 (L1)
5
10
15
20 (L20)
40
80
100
MHz
L(f) = SSB phase noise
–97
–114
–121
–125
–128
–134
–137
–138
dBc/Hz
−80
Rambus Spec Range:
1 MHz 3 fOffset 3 20 MHz
−90
Phase Noise − dBc/Hz
−100
667 MHz
−110
−120
Rambus Spec
−130
300 MHz
400 MHz
−140
−150
−160
100k
1M
fOffset − Offset Frequency − Hz
10M
20M
100M
G001
Figure 2. Phase Noise Plot
Submit Documentation Feedback
11
CDCD5704
www.ti.com
SCAS823 – DECEMBER 2006
VTS
R1
CLK
R2
VT = 1.2 V
Z0=50 W
RT
R3
CDCD5704
XCG
VTS
Measurement Points
ISET
R1
CLKB
R2
VT = 1.2 V
Z0=50 W
RT
R3
RRC
S0201-01
NOTE: In the power-up sequence, the rise time for the external voltage applied to the clock output pins (VTS) must be equal
to or longer than the rise time for the supply voltage of the device (VDD, VDDP, VDDC).
VALUE for 50-Ω LINE
VALUE for IOL,ABS
TOLERANCE
UNIT
R1
Termination resistor
PARAMETER
39.2
34
±1%
Ω
R2
Termination resistor
66.5
31.8
±1%
Ω
R3
Termination resistor
93.1
48.7
±1%
Ω
RT
Termination resistor
49.9
28
±1%
Ω
RRC
Swing control resistor
200
147
±1%
Ω
VTS
Source termination voltage
2.5
2.5
±5%
V
VT
Termination voltage
1.2
1.2
±5%
V
Figure 3. Output Test Load
VH
80%
V(t)
VL
tf
20%
tr
T0132-01
Figure 4. Input and Output Waveforms
12
Submit Documentation Feedback
CDCD5704
www.ti.com
SCAS823 – DECEMBER 2006
CLK
Vx+
Vx, nom
Vx–
CLKB
T0133-01
Figure 5. Crossing-Point Voltage
CLK
CLKB
tCYCLE,i
tCYCLE,i+1
tJ = tCYCLE,i – tCYCLE,i+1 Over 10,000 Consecutive Cycles
T0134-01
Figure 6. One-Period Cycle-to-Cycle Jitter
CLK
CLKB
t4CYCLE,i
t4CYCLE,i+1
tJ = t4CYCLE,i – t4CYCLE,i+1 Over 10,000 Consecutive Cycles
T0135-01
Figure 7. Four-Period Cycle-to-Cycle Jitter
Cycle (i)
Cycle (i+1)
CLK
CLKB
tPW+,i
tPW–,i
tPW–,i+1
tCYCLE,i
tPW+,i+1
tCYCLE,i+1
tDC,ERR = tPW+,i – tPW+,i+1 and tPW–,i – tPW–,i+1
T0136-01
Figure 8. Cycle-to-Cycle Duty-Cycle Error
Submit Documentation Feedback
13
CDCD5704
www.ti.com
SCAS823 – DECEMBER 2006
APPLICATION INFORMATION
XDR Memory Subsystem (Source: Rambus)
XDR System Topology
Termination
DRSL: 3.2 GHz
DQ BYTE [2N+1]
XDR
DRAM n
ASIC
XIO
XMC
DQ BYTE [2N]
·
·
·
DQ BYTE [1]
DQ BYTE [0]
PLL
´4
XDR
DRAM 0
RSL: 800 MHz
RQ BUS [0:11]
CFM 400 MHZ
System Clock
XDR
Clock
Generator
CDCD5704
CTM
400 MHZ
To Other Subsystems
M0054-01
14
Submit Documentation Feedback
PACKAGE OPTION ADDENDUM
www.ti.com
8-Jan-2007
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
CDCD5704PW
ACTIVE
TSSOP
PW
28
50
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
CDCD5704PWG4
ACTIVE
TSSOP
PW
28
50
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
CDCD5704PWR
ACTIVE
TSSOP
PW
28
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
CDCD5704PWRG4
ACTIVE
TSSOP
PW
28
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
17-May-2007
TAPE AND REEL INFORMATION
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
Device
CDCD5704PWR
17-May-2007
Package Pins
PW
28
Site
Reel
Diameter
(mm)
Reel
Width
(mm)
A0 (mm)
B0 (mm)
K0 (mm)
P1
(mm)
FRB
330
16
7.0
3.6
1.6
8
TAPE AND REEL BOX INFORMATION
Device
Package
Pins
Site
Length (mm)
Width (mm)
Height (mm)
CDCD5704PWR
PW
28
FRB
342.9
336.6
28.58
Pack Materials-Page 2
W
Pin1
(mm) Quadrant
12
PKGORN
T1TR-MS
P
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
0,65
14
0,10 M
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°– 8°
A
0,75
0,50
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
8
14
16
20
24
28
A MAX
3,10
5,10
5,10
6,60
7,90
9,80
A MIN
2,90
4,90
4,90
6,40
7,70
9,60
DIM
4040064/F 01/97
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-153
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements,
improvements, and other changes to its products and services at any time and to discontinue any product or service without notice.
Customers should obtain the latest relevant information before placing orders and should verify that such information is current and
complete. All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment.
TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s
standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this
warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily
performed.
TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and
applications using TI components. To minimize the risks associated with customer products and applications, customers should
provide adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask
work right, or other TI intellectual property right relating to any combination, machine, or process in which TI products or services
are used. Information published by TI regarding third-party products or services does not constitute a license from TI to use such
products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under
the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of information in TI data books or data sheets is permissible only if reproduction is without alteration and is
accompanied by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an
unfair and deceptive business practice. TI is not responsible or liable for such altered documentation.
Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service
voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business
practice. TI is not responsible or liable for any such statements.
TI products are not authorized for use in safety-critical applications (such as life support) where a failure of the TI product would
reasonably be expected to cause severe personal injury or death, unless officers of the parties have executed an agreement
specifically governing such use. Buyers represent that they have all necessary expertise in the safety and regulatory ramifications
of their applications, and acknowledge and agree that they are solely responsible for all legal, regulatory and safety-related
requirements concerning their products and any use of TI products in such safety-critical applications, notwithstanding any
applications-related information or support that may be provided by TI. Further, Buyers must fully indemnify TI and its
representatives against any damages arising out of the use of TI products in such safety-critical applications.
TI products are neither designed nor intended for use in military/aerospace applications or environments unless the TI products are
specifically designated by TI as military-grade or "enhanced plastic." Only products designated by TI as military-grade meet military
specifications. Buyers acknowledge and agree that any such use of TI products which TI has not designated as military-grade is
solely at the Buyer's risk, and that they are solely responsible for compliance with all legal and regulatory requirements in
connection with such use.
TI products are neither designed nor intended for use in automotive applications or environments unless the specific TI products
are designated by TI as compliant with ISO/TS 16949 requirements. Buyers acknowledge and agree that, if they use any
non-designated products in automotive applications, TI will not be responsible for any failure to meet such requirements.
Following are URLs where you can obtain information on other Texas Instruments products and application solutions:
Products
Applications
Amplifiers
amplifier.ti.com
Audio
www.ti.com/audio
Data Converters
dataconverter.ti.com
Automotive
www.ti.com/automotive
DSP
dsp.ti.com
Broadband
www.ti.com/broadband
Interface
interface.ti.com
Digital Control
www.ti.com/digitalcontrol
Logic
logic.ti.com
Military
www.ti.com/military
Power Mgmt
power.ti.com
Optical Networking
www.ti.com/opticalnetwork
Microcontrollers
microcontroller.ti.com
Security
www.ti.com/security
RFID
www.ti-rfid.com
Telephony
www.ti.com/telephony
Low Power
Wireless
www.ti.com/lpw
Video & Imaging
www.ti.com/video
Wireless
www.ti.com/wireless
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2007, Texas Instruments Incorporated