TI1 ADC14C105 95/105 msps a/d converter Datasheet

ADC14C105
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SNAS409C – MAY 2007 – REVISED MARCH 2013
ADC14C105 14-Bit, 95/105 MSPS A/D Converter
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FEATURES
DESCRIPTION
•
•
The ADC14C105 is a high-performance CMOS
analog-to-digital converter capable of converting
analog input signals into 14-bit digital words at rates
up to 105 Mega Samples Per Second (MSPS). This
converter uses a differential, pipelined architecture
with digital error correction and an on-chip sampleand-hold circuit to minimize power consumption and
the external component count, while providing
excellent dynamic performance. A unique sampleand-hold stage yields a full-power bandwidth of 1
GHz. The ADC14C105 may be operated from a
single +3.0V or +3.3V power supply and consumes
low power.
1
2
•
•
•
•
•
•
1 GHz Full Power Bandwidth
Internal Reference and Sample-and-Hold
Circuit
Low Power Consumption
Data Ready Output Clock
Clock Duty Cycle Stabilizer
Single +3.0V or +3.3V Supply Operation
Power-Down Mode
32-pin WQFN Package, (5x5x0.8mm, 0.5mm
pin-pitch)
APPLICATIONS
•
•
•
•
•
High IF Sampling Receivers
Wireless Base Station Receivers
Test and Measurement Equipment
Communications Instrumentation
Portable Instrumentation
KEY SPECIFICATIONS
•
•
•
•
•
•
Resolution: 14 Bits
Conversion Rate: 105 MSPS
SNR (fIN = 240 MHz): 71 dBFS (typ)
SFDR (fIN = 240 MHz): 82 dBFS (typ)
Full Power Bandwidth: 1 GHz (typ)
Power Consumption
– 350 mW (typ, VA=3.0V)
– 400 mW (typ, VA=3.3V)
A separate +2.5V supply may be used for the digital
output interface which allows lower power operation
with reduced noise. A power-down feature reduces
the power consumption to very low levels while still
allowing fast wake-up time to full operation. The
differential inputs accept a 2V full scale differential
input swing. A stable 1.2V internal voltage reference
is provided, or the ADC14C105 can be operated with
an external 1.2V reference. Output data format (offset
binary versus 2's complement) and duty cycle
stabilizer are pin-selectable. The duty cycle stabilizer
maintains performance over a wide range of clock
duty cycles.
The ADC14C105 is available in a 32-lead WQFN
package and operates over the industrial temperature
range of −40°C to +85°C.
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2007–2013, Texas Instruments Incorporated
ADC14C105
SNAS409C – MAY 2007 – REVISED MARCH 2013
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VRN
VRP
VA
AGND
VIN+
VIN-
D10
D9
25
26
D13 (MSB)
PD
D12
D11
27
28
29
VREF
30
1
24
2
23
3
4
D7
22
DRGND
21
DRDY
20
VDR
19
D6
18
D5
17
D4
ADC14C105
5
6
(Top View)
7
8
D8
*
9
AGND
VA 10
11
CLK
12
OF/DCS
13
D0
14
D1
15
D2
16
D3
AGND
VA
31
32
VCMO
Connection Diagram
Figure 1. WQFN Package
See Package Number RTV0032A
2
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Block Diagram
VIN+
S/H
VIN-
Stage
2
Stage
1
Stage
3
Stage
n
Stage
9
Stage
10
Stage
11
VA
AGND
3
PD
3
Timing
Control
2
2
24
2
2
2
11-Stage Pipeline Converter
3
VD
Digital Correction
DGND
OF/DCS
14
14
D0 - D13
Output
Buffers
Duty
Cycle
Stabilizer
CLK
DRDY
DRGND
VDR
VREF
Internal
reference
driver
Bandgap
reference
VRP
VCMO
VRN
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Pin Descriptions and Equivalent Circuits
Pin No.
Symbol
Equivalent Circuit
Description
ANALOG I/O
5
VA
VIN+
6
VIN-
2
VRP
32
VCMO
Differential analog input pins. The differential full-scale input signal
level is 2VP-P with each input pin signal centered on a common mode
voltage, VCM.
AGND
VA
VA
VA
1
VRN
VA
These pins should each be bypassed to AGND with a low ESL
(equivalent series inductance) 0.1 µF capacitor placed very close to
the pin to minimize stray inductance. A 0.1 µF capacitor should be
placed between VRP and VRN as close to the pins as possible, and a
1 µF capacitor should be placed in parallel.
VRP and VRN should not be loaded. VCMO may be loaded to 1mA for
use as a temperature stable 1.5V reference.
It is recommended to use VCMO to provide the common mode
voltage, VCM, for the differential analog inputs, VIN+ and VIN−.
AGND
AGND
VA
31
Reference Voltage. This device provides an internally developed
1.2V reference. When using the internal reference, VREF should be
decoupled to AGND with a 0.1 µF and a 1 µF low equivalent series
inductance (ESL) capacitor .
This pin may be driven with an external 1.2V reference voltage.
This pin should not be used to source or sink current.
VREF
AGND
VA
12
OF/DCS
AGND
4
This is a four-state pin controlling the input clock mode and output
data format.
OF/DCS = VA, output data format is 2's complement without duty
cycle stabilization applied to the input clock
OF/DCS = AGND, output data format is offset binary, without duty
cycle stabilization applied to the input clock.
OF/DCS = (2/3)*VA, output data is 2's complement with duty cycle
stabilization applied to the input clock
OF/DCS = (1/3)*VA, output data is offset binary with duty cycle
stabilization applied to the input clock.
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Pin Descriptions and Equivalent Circuits (continued)
Pin No.
Symbol
Equivalent Circuit
Description
DIGITAL I/O
11
CLK
30
PD
VA
The clock input pin.
The analog input is sampled on the rising edge of the clock input.
This is a two-state input controlling Power Down.
PD = VA, Power Down is enabled and power dissipation is reduced.
PD = AGND, Normal operation.
AGND
VDR
13-19,
23-29
D0–D13
21
DRDY
VA
Digital data output pins that make up the 14-bit conversion result. D0
(pin 13) is the LSB, while D13 (pin 29) is the MSB of the output
word. Output levels are CMOS compatible.
Data Ready Strobe. The data output transition is synchronized with
the falling edge of this signal. This signal switches at the same
frequency as the CLK input.
DRGND
DGND
ANALOG POWER
3, 8, 10
VA
Positive analog supply pins. These pins should be connected to a
quiet voltage source and be bypassed to AGND with 0.1 µF
capacitors located close to the power pins.
4, 7, 9,
Exposed Pad
AGND
The ground return for the analog supply.
The exposed pad on back of package must be soldered to ground
plane to ensure rated performance.
20
VDR
Positive driver supply pin for the output drivers. This pin should be
connected to a quiet voltage source and be bypassed to DRGND
with a 0.1 µF capacitor located close to the power pin.
22
DRGND
DIGITAL POWER
The ground return for the digital output driver supply. This pins
should be connected to the system digital ground, but not be
connected in close proximity to the ADC's AGND pins.
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
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Absolute Maximum Ratings (1) (2) (3)
−0.3V to 4.2V
Supply Voltage (VA, VDR)
−0.3V to (VA +0.3V)
Voltage on Any Pin (Not to exceed 4.2V)
Input Current at Any Pin other than Supply Pins (4)
±5 mA
Package Input Current (4)
±50 mA
Max Junction Temp (TJ)
+150°C
Thermal Resistance (θJA)
30°C/W
ESD Rating
Human Body Model (5)
Machine Model
(5)
2500V
250V
−65°C to +150°C
Storage Temperature
Soldering process must comply with National Semiconductor's Reflow Temperature Profile specifications. Refer to www.ti.com/packaging. (6)
(1)
(2)
(3)
(4)
(5)
(6)
All voltages are measured with respect to GND = AGND = DRGND = 0V, unless otherwise specified.
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is specified to be functional, but do not ensure specific performance limits. For ensured specifications and test
conditions, see the Electrical Characteristics. The ensured specifications apply only for the test conditions listed. Some performance
characteristics may degrade when the device is not operated under the listed test conditions. Operation of the device beyond the
maximum Operating Ratings is not recommended.
If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
When the input voltage at any pin exceeds the power supplies (that is, VIN < AGND, or VIN > VA), the current at that pin should be
limited to ±5 mA. The ±50 mA maximum package input current rating limits the number of pins that can safely exceed the power
supplies with an input current of ±5 mA to 10.
Human Body Model is 100 pF discharged through a 1.5 kΩ resistor. Machine Model is 220 pF discharged through 0 Ω
Reflow temperature profiles are different for lead-free and non-lead-free packages.
Operating Ratings (1) (2)
−40°C ≤ TA ≤ +85°C
Operating Temperature
Supply Voltage (VA)
+2.7V to +3.6V
Output Driver Supply (VDR)
Clock Duty Cycle
+2.4V to VA
(DCS Enabled)
(DCS disabled)
VCM
(2)
6
45/55 %
1.4V to 1.6V
≤100mV
|AGND-DRGND|
(1)
30/70 %
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is specified to be functional, but do not ensure specific performance limits. For ensured specifications and test
conditions, see the Electrical Characteristics. The ensured specifications apply only for the test conditions listed. Some performance
characteristics may degrade when the device is not operated under the listed test conditions. Operation of the device beyond the
maximum Operating Ratings is not recommended.
All voltages are measured with respect to GND = AGND = DRGND = 0V, unless otherwise specified.
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Converter Electrical Characteristics
Unless otherwise specified, the following specifications apply: AGND = DRGND = 0V, VA = +3.3V, VDR = +2.5V, Internal VREF
= +1.2V, fCLK = 105 MHz, 50% Duty Cycle, DCS disabled, VCM = VCMO, CL = 5 pF/pin. Typical values are for TA = 25°C.
Boldface limits apply for TMIN ≤ TA ≤ TMAX. All other limits apply for TA = 25°C (1) (2)
Parameter
Test Conditions
Typical (3)
Limits
Units
(Limits)
STATIC CONVERTER CHARACTERISTICS
Resolution with No Missing Codes
INL
Integral Non Linearity
±1.8
14
Bits (min)
4
LSB (max)
-4
LSB (min)
1.3
LSB (max)
DNL
Differential Non Linearity
±0.5
-0.9
LSB (min)
PGE
Positive Gain Error
-0.05
±1.25
%FS (max)
NGE
Negative Gain Error
-0.54
±1.25
%FS (max)
TC PGE
Positive Gain Error Tempco
−40°C ≤ TA ≤ +85°C
-8
TC NGE
Negative Gain Error Tempco
−40°C ≤ TA ≤ +85°C
-7
VOFF
Offset Error (VIN+ = VIN-)
TC VOFF
Offset Error Tempco
0.065
−40°C ≤ TA ≤ +85°C
ppm/°C
ppm/°C
±0.55
7.5
%FS (max)
ppm/°C
Under Range Output Code
0
0
Over Range Output Code
16383
16383
REFERENCE AND ANALOG INPUT CHARACTERISTICS
VCMO
Common Mode Output Voltage
1.5
1.4
1.56
V (min)
V (max)
VCM
Analog Input Common Mode Voltage
1.5
1.4
1.6
V (min)
V (max)
CIN
VIN Input Capacitance (each pin to
GND) (4)
VREF
Internal Reference Voltage
TC VREF
Internal Reference Voltage Tempco
VIN = 1.5 Vdc ± 0.5 V
(CLK LOW)
8.5
pF
(CLK HIGH)
3.5
pF
1.18
V
−40°C ≤ TA ≤ +85°C
(5)
18
ppm/°C
1.98
1.89
2.06
V (min)
V (max)
VRP
Internal Reference top
See
VRN
Internal Reference bottom
See (5)
0.98
0.89
1.06
V (min)
V (max)
Ext VREF
External Reference Voltage
See (5)
1.20
1.176
1.224
V (min)
V (max)
(1)
(2)
(3)
(4)
(5)
The inputs are protected as shown below. Input voltage magnitudes above VA or below GND will not damage this device, provided
current is limited per Note 4 of the Absolute Maximum Ratings Table. However, errors in the A/D conversion can occur if the input goes
above 2.6V or below GND as described in the Operating Ratings section. See Figure 2.
With a full scale differential input of 2VP-P , the 14-bit LSB is 122.1 µV.
Typical figures are at TA = 25°C and represent most likely parametric norms at the time of product characterization. The typical
specifications are not ensured.
The input capacitance is the sum of the package/pin capacitance and the sample and hold circuit capacitance.
This parameter is specified by design and/or characterization and is not tested in production.
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Dynamic Converter Electrical Characteristics
Unless otherwise specified, the following specifications apply: AGND = DRGND = 0V, VA = +3.3V, VDR = +2.5V, Internal VREF
= +1.2V, fCLK = 105 MHz, 50% Duty Cycle, DCS disabled, VCM = VCMO, CL = 5 pF/pin, . Typical values are for TA = 25°C.
Boldface limits apply for TMIN ≤ TA ≤ TMAX. All other limits apply for TA = 25°C (1) (2)
Parameter
Test Conditions
Typical (3)
Limits
Units
(Limits) (4)
DYNAMIC CONVERTER CHARACTERISTICS, AIN= -1dBFS
FPBW
SNR
SFDR
ENOB
THD
H2
IMD
(4)
Spurious Free Dynamic Range
Effective Number of Bits
Total Harmonic Disortion
Third Harmonic Distortion
SINAD
(2)
(3)
Signal-to-Noise Ratio
Second Harmonic Distortion
H3
(1)
Full Power Bandwidth
Signal-to-Noise and Distortion Ratio
Intermodulation Distortion
-1 dBFS Input, −3 dB Corner
1.0
GHz
fIN = 10 MHz
74
dBFS
fIN = 70 MHz
73.5
fIN = 240 MHz
71
fIN = 10 MHz
90
fIN = 70 MHz
86
fIN = 240 MHz
82
fIN = 10 MHz
11.9
fIN = 70 MHz
11.8
fIN = 240 MHz
11.4
fIN = 10 MHz
−86
fIN = 70 MHz
−85
fIN = 240 MHz
−79.3
fIN = 10 MHz
−95
fIN = 70 MHz
−90
fIN = 240 MHz
−86
fIN = 10 MHz
−90
fIN = 70 MHz
−86
fIN = 240 MHz
−82
fIN = 10 MHz
73.5
fIN = 70 MHz
73
fIN = 240 MHz
70.4
fIN = 19.5 MHz and 20.5MHz,
each -7 dBFS
-82
dBFS
69.4
dBFS
dBFS
dBFS
78
dBFS
Bits
Bits
11.1
Bits
dBFS
dBFS
-74
dBFS
dBFS
dBFS
-78
dBFS
dBFS
dBFS
-78
dBFS
dBFS
dBFS
68.8
dBFS
dBFS
The inputs are protected as shown below. Input voltage magnitudes above VA or below GND will not damage this device, provided
current is limited per Note 4 of the Absolute Maximum Ratings Table. However, errors in the A/D conversion can occur if the input goes
above 2.6V or below GND as described in the Operating Ratings section. See Figure 2.
With a full scale differential input of 2VP-P , the 14-bit LSB is 122.1 µV.
Typical figures are at TA = 25°C and represent most likely parametric norms at the time of product characterization. The typical
specifications are not ensured.
Parameters specified in dBFS indicate the value that would be attained with a full-scale input signal.
Logic and Power Supply Electrical Characteristics
Unless otherwise specified, the following specifications apply: AGND = DRGND = 0V, VA = +3.3V, VDR = +2.5V, Internal VREF
= +1.2V, fCLK = 105 MHz, 50% Duty Cycle, DCS disabled, VCM = VCMO, CL = 5 pF/pin. Typical values are for TA = 25°C.
Boldface limits apply for TMIN ≤ TA ≤ TMAX. All other limits apply for TA = 25°C (1) (2)
Parameter
Test Conditions
Typical (3)
Limits
Units
(Limits)
DIGITAL INPUT CHARACTERISTICS (CLK, PD)
VIN(1)
Logical “1” Input Voltage
VD = 3.6V
2.0
V (min)
VIN(0)
Logical “0” Input Voltage
VD = 3.0V
0.8
V (max)
(1)
(2)
(3)
8
The inputs are protected as shown below. Input voltage magnitudes above VA or below GND will not damage this device, provided
current is limited per Note 4 of the Absolute Maximum Ratings Table. However, errors in the A/D conversion can occur if the input goes
above 2.6V or below GND as described in the Operating Ratings section. See Figure 2.
With a full scale differential input of 2VP-P , the 14-bit LSB is 122.1 µV.
Typical figures are at TA = 25°C and represent most likely parametric norms at the time of product characterization. The typical
specifications are not ensured.
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Logic and Power Supply Electrical Characteristics (continued)
Unless otherwise specified, the following specifications apply: AGND = DRGND = 0V, VA = +3.3V, VDR = +2.5V, Internal VREF
= +1.2V, fCLK = 105 MHz, 50% Duty Cycle, DCS disabled, VCM = VCMO, CL = 5 pF/pin. Typical values are for TA = 25°C.
Boldface limits apply for TMIN ≤ TA ≤ TMAX. All other limits apply for TA = 25°C(1)(2)
Parameter
Test Conditions
Typical (3)
Limits
Units
(Limits)
IIN(1)
Logical “1” Input Current
VIN = 3.3V
10
µA
IIN(0)
Logical “0” Input Current
VIN = 0V
−10
µA
CIN
Digital Input Capacitance
5
pF
DIGITAL OUTPUT CHARACTERISTICS (D0–D13, DRDY)
VOUT(1)
Logical “1” Output Voltage
IOUT = −0.5 mA , VDR = 2.4V
VOUT(0)
Logical “0” Output Voltage
IOUT = 1.6 mA, VDR = 2.4V
+ISC
Output Short Circuit Source Current
VOUT = 0V
−10
mA
−ISC
Output Short Circuit Sink Current
VOUT = VDR
10
mA
COUT
Digital Output Capacitance
5
pF
2.0
V (min)
0.4
V (max)
POWER SUPPLY CHARACTERISTICS
IA
Analog Supply Current
IDR
(4)
Full Operation
121
(4)
Digital Output Supply Current
Full Operation
Power Consumption
Excludes IDR (4)
400
Power Down Power Consumption
Clock disabled
7.5
141
mA (max)
466
mW (max)
16
mA
mW
IDR is the current consumed by the switching of the output drivers and is primarily determined by load capacitance on the output pins,
the supply voltage, VDR, and the rate at which the outputs are switching (which is signal dependent). IDR=VDR(C0 x f0 + C1 x f1 +....C13 x
f13) where VDR is the output driver power supply voltage, Cn is total capacitance on the output pin, and fn is the average frequency at
which that pin is toggling.
Timing and AC Characteristics
Unless otherwise specified, the following specifications apply: AGND = DRGND = 0V, VA = +3.3V, VDR = +2.5V, Internal VREF
= +1.2V, fCLK = 105 MHz, 50% Duty Cycle, DCS disabled, VCM = VCMO, CL = 5 pF/pin. Typical values are for TA = 25°C.
Timing measurements are taken at 50% of the signal amplitude. Boldface limits apply for TMIN ≤ TA ≤ TMAX. All other limits
apply for TA = 25°C (1) (2)
Limits
Units
(Limits)
Maximum Clock Frequency
105
MHz (max)
Minimum Clock Frequency
20
MHz (min)
Parameter
Typical (3)
Test Conditions
tCH
Clock High Time
4
ns
tCL
Clock Low Time
4
ns
tCONV
Conversion Latency
(4)
7
Clock Cycles
5.76
3
7.3
ns (min)
ns (max)
tOD
Output Delay of CLK to DATA
Relative to rising edge of CLK
tSU
Data Output Setup Time
Relative to DRDY
4.5
3.7
ns (min)
tH
Data Output Hold Time
Relative to DRDY
4.5
3.8
ns (min)
tAD
Aperture Delay
0.6
ns
tAJ
Aperture Jitter
0.1
ps rms
(1)
(2)
(3)
(4)
The inputs are protected as shown below. Input voltage magnitudes above VA or below GND will not damage this device, provided
current is limited per Note 4 of the Absolute Maximum Ratings Table. However, errors in the A/D conversion can occur if the input goes
above 2.6V or below GND as described in the Operating Ratings section. See Figure 2.
With a full scale differential input of 2VP-P , the 14-bit LSB is 122.1 µV.
Typical figures are at TA = 25°C and represent most likely parametric norms at the time of product characterization. The typical
specifications are not ensured.
This parameter is specified by design and/or characterization and is not tested in production.
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Dynamic Converter Electrical Characteristics at 95MSPS
Unless otherwise specified, the following specifications apply: AGND = DRGND = 0V, VA = +3.3V, VDR = +2.5V, Internal VREF
= +1.2V, fCLK = 95 MHz, 50% Duty Cycle, DCS disabled, VCM = VCMO, CL = 5 pF/pin, . Typical values are for TA = 25°C.
Boldface limits apply for TMIN ≤ TA ≤ TMAX. All other limits apply for TA = 25°C (1) (2)
Parameter
Test Conditions
Typical (3)
Limits
Units
(Limits) (4)
DYNAMIC CONVERTER CHARACTERISTICS, AIN= -1dBFS
SNR
SFDR
ENOB
THD
H2
Signal-to-Noise Ratio
Spurious Free Dynamic Range
Effective Number of Bits
Total Harmonic Disortion
Second Harmonic Distortion
H3
Third Harmonic Distortion
SINAD
Signal-to-Noise and Distortion Ratio
fIN = 10 MHz
74
dBFS
fIN = 70 MHz
73.5
dBFS
fIN = 240 MHz
71
dBFS
fIN = 10 MHz
90
dBFS
fIN = 70 MHz
86
dBFS
fIN = 240 MHz
82
dBFS
fIN = 10 MHz
11.9
Bits
fIN = 70 MHz
11.8
Bits
fIN = 240 MHz
11.4
Bits
fIN = 10 MHz
−86
dBFS
fIN = 70 MHz
−85
dBFS
fIN = 240 MHz
−80
dBFS
fIN = 10 MHz
-95
dBFS
fIN = 70 MHz
−90
dBFS
fIN = 240 MHz
−85
dBFS
fIN = 10 MHz
−90
dBFS
fIN = 70 MHz
−86
dBFS
fIN = 240 MHz
−83
dBFS
fIN = 10 MHz
73.5
dBFS
fIN = 70 MHz
73
dBFS
fIN = 240 MHz
70.5
dBFS
POWER SUPPLY CHARACTERISTICS
IA
Analog Supply Current
Full Operation
115
mA (max)
IDR
Digital Output Supply Current
Full Operation (5)
14.5
mA
380
mW (max)
Power Consumption
(1)
(2)
(3)
(4)
(5)
Excludes IDR
(5)
The inputs are protected as shown below. Input voltage magnitudes above VA or below GND will not damage this device, provided
current is limited per Note 4 of the Absolute Maximum Ratings Table. However, errors in the A/D conversion can occur if the input goes
above 2.6V or below GND as described in the Operating Ratings section. See Figure 2.
With a full scale differential input of 2VP-P , the 14-bit LSB is 122.1 µV.
Typical figures are at TA = 25°C and represent most likely parametric norms at the time of product characterization. The typical
specifications are not ensured.
Parameters specified in dBFS indicate the value that would be attained with a full-scale input signal.
IDR is the current consumed by the switching of the output drivers and is primarily determined by load capacitance on the output pins,
the supply voltage, VDR, and the rate at which the outputs are switching (which is signal dependent). IDR=VDR(C0 x f0 + C1 x f1 +....C13 x
f13) where VDR is the output driver power supply voltage, Cn is total capacitance on the output pin, and fn is the average frequency at
which that pin is toggling.
VA
I/O
To Internal Circuitry
AGND
Figure 2.
10
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Specification Definitions
APERTURE DELAY is the time after the falling edge of the clock to when the input signal is acquired or held for
conversion.
APERTURE JITTER (APERTURE UNCERTAINTY) is the variation in aperture delay from sample to sample.
Aperture jitter manifests itself as noise in the output.
CLOCK DUTY CYCLE is the ratio of the time during one cycle that a repetitive digital waveform is high to the
total time of one period. The specification here refers to the ADC clock input signal.
COMMON MODE VOLTAGE (VCM) is the common DC voltage applied to both input terminals of the ADC.
CONVERSION LATENCY is the number of clock cycles between initiation of conversion and when that data is
presented to the output driver stage. Data for any given sample is available at the output pins the Pipeline Delay
plus the Output Delay after the sample is taken. New data is available at every clock cycle, but the data lags the
conversion by the pipeline delay.
DIFFERENTIAL NON-LINEARITY (DNL) is the measure of the maximum deviation from the ideal step size of 1
LSB.
EFFECTIVE NUMBER OF BITS (ENOB, or EFFECTIVE BITS) is another method of specifying Signal-to-Noise
and Distortion Ratio or SINAD. ENOB is defined as (SINAD - 1.76) / 6.02 and says that the converter is
equivalent to a perfect ADC of this (ENOB) number of bits.
FULL POWER BANDWIDTH is a measure of the frequency at which the reconstructed output fundamental
drops 3 dB below its low frequency value for a full scale input.
GAIN ERROR is the deviation from the ideal slope of the transfer function. It can be calculated as:
Gain Error = Positive Full Scale Error − Negative Full Scale Error
(1)
It can also be expressed as Positive Gain Error and Negative Gain Error, which are calculated as:
PGE = Positive Full Scale Error - Offset Error NGE = Offset Error - Negative Full Scale Error
(2)
INTEGRAL NON LINEARITY (INL) is a measure of the deviation of each individual code from a best fit straight
line. The deviation of any given code from this straight line is measured from the center of that code value.
INTERMODULATION DISTORTION (IMD) is the creation of additional spectral components as a result of two
sinusoidal frequencies being applied to the ADC input at the same time. It is defined as the ratio of the power in
the intermodulation products to the total power in the original frequencies. IMD is usually expressed in dBFS.
LSB (LEAST SIGNIFICANT BIT) is the bit that has the smallest value or weight of all bits. This value is VFS/2n,
where “VFS” is the full scale input voltage and “n” is the ADC resolution in bits.
MISSING CODES are those output codes that will never appear at the ADC outputs. The ADC14C105 is
ensured not to have any missing codes.
MSB (MOST SIGNIFICANT BIT) is the bit that has the largest value or weight. Its value is one half of full scale.
NEGATIVE FULL SCALE ERROR is the difference between the actual first code transition and its ideal value of
½ LSB above negative full scale.
OFFSET ERROR is the difference between the two input voltages [(VIN+) – (VIN-)] required to cause a transition
from code 8191 to 8192.
OUTPUT DELAY is the time delay after the falling edge of the clock before the data update is presented at the
output pins.
PIPELINE DELAY (LATENCY) See CONVERSION LATENCY.
POSITIVE FULL SCALE ERROR is the difference between the actual last code transition and its ideal value of
1½ LSB below positive full scale.
POWER SUPPLY REJECTION RATIO (PSRR) is a measure of how well the ADC rejects a change in the power
supply voltage. PSRR is the ratio of the Full-Scale output of the ADC with the supply at the minimum DC supply
limit to the Full-Scale output of the ADC with the supply at the maximum DC supply limit, expressed in dB.
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SIGNAL TO NOISE RATIO (SNR) is the ratio, expressed in dB, of the rms value of the input signal to the rms
value of the sum of all other spectral components below one-half the sampling frequency, not including
harmonics or DC.
SIGNAL TO NOISE PLUS DISTORTION (S/N+D or SINAD) Is the ratio, expressed in dB, of the rms value of the
input signal to the rms value of all of the other spectral components below half the clock frequency, including
harmonics but excluding d.c.
SPURIOUS FREE DYNAMIC RANGE (SFDR) is the difference, expressed in dB, between the rms values of the
input signal and the peak spurious signal, where a spurious signal is any signal present in the output spectrum
that is not present at the input.
TOTAL HARMONIC DISTORTION (THD) is the ratio, expressed in dB, of the rms total of the first six harmonic
levels at the output to the level of the fundamental at the output. THD is calculated as
where f1 is the RMS power of the fundamental (output) frequency and f2 through f7 are the RMS power of the first
six harmonic frequencies in the output spectrum.
SECOND HARMONIC DISTORTION (2ND HARM) is the difference expressed in dB, between the RMS power in
the input frequency at the output and the power in its 2nd harmonic level at the output.
THIRD HARMONIC DISTORTION (3RD HARM) is the difference, expressed in dB, between the RMS power in
the input frequency at the output and the power in its 3rd harmonic level at the output.
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Timing Diagram
Sample N + 8
Sample N + 7
Sample N + 9
|
Sample N + 6
Sample N
Sample N + 10
VIN
tAD
Clock N
Clock N + 7
1
fCLK
|
CLK
tCL
tCH
|
Latency
tOD
|
DRDY
tSU
| |
D0 - D13
Data N - 1
tH
Data N
Data N + 1
Data N + 2
Figure 3. Output Timing
Transfer Characteristic
Figure 4. Transfer Characteristic
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Typical Performance Characteristics DNL, INL
Unless otherwise specified, the following specifications apply: AGND = DRGND = 0V, VA = +3.3V, VDR = +2.5V,
Internal VREF = +1.2V, fCLK = 105 MHz, 50% Duty Cycle, DCS disabled, VCM = VCMO, fIN = 10 MHz, CL = 5 pF/pin.
Typical values are for TA = 25°C.
14
DNL
INL
Figure 5.
Figure 6.
DNL vs. fCLK
INL vs. fCLK
Figure 7.
Figure 8.
DNL vs. Temperature
INL vs. Temperature
Figure 9.
Figure 10.
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Typical Performance Characteristics DNL, INL (continued)
Unless otherwise specified, the following specifications apply: AGND = DRGND = 0V, VA = +3.3V, VDR = +2.5V,
Internal VREF = +1.2V, fCLK = 105 MHz, 50% Duty Cycle, DCS disabled, VCM = VCMO, fIN = 10 MHz, CL = 5 pF/pin.
Typical values are for TA = 25°C.
DNL vs. VA
INL vs. VA
Figure 11.
Figure 12.
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Typical Performance Characteristics
Unless otherwise specified, the following specifications apply: AGND = DRGND = 0V, VA = +3.3V, VDR = +2.5V, Internal VREF
= +1.2V, fCLK = 105 MHz, 50% Duty Cycle, DCS disabled, VCM = VCMO, fIN = 10 MHz, CL = 5 pF/pin. Typical values are for TA
= 25°C.
16
SNR, SINAD, SFDR vs. VA
Distortion vs. VA
Figure 13.
Figure 14.
SNR, SINAD, SFDR vs. VDR
Distortion vs. VDR
Figure 15.
Figure 16.
SNR, SINAD, SFDR vs. fCLK
Distortion vs. fCLK
Figure 17.
Figure 18.
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Typical Performance Characteristics (continued)
Unless otherwise specified, the following specifications apply: AGND = DRGND = 0V, VA = +3.3V, VDR = +2.5V, Internal VREF
= +1.2V, fCLK = 105 MHz, 50% Duty Cycle, DCS disabled, VCM = VCMO, fIN = 10 MHz, CL = 5 pF/pin. Typical values are for TA
= 25°C.
SNR, SINAD, SFDR vs. Clock Duty Cycle
Distortion vs. Clock Duty Cycle
Figure 19.
Figure 20.
SNR, SINAD, SFDR vs. Clock Duty Cycle, DCS Enabled
Distortion vs. Clock Duty Cycle, DCS Enabled
Figure 21.
Figure 22.
SNR, SINAD, SFDR vs. fIN
Distortion vs. fIN
Figure 23.
Figure 24.
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Typical Performance Characteristics (continued)
Unless otherwise specified, the following specifications apply: AGND = DRGND = 0V, VA = +3.3V, VDR = +2.5V, Internal VREF
= +1.2V, fCLK = 105 MHz, 50% Duty Cycle, DCS disabled, VCM = VCMO, fIN = 10 MHz, CL = 5 pF/pin. Typical values are for TA
= 25°C.
18
SNR, SINAD, SFDR vs. Temperature
Distortion vs. Temperature
Figure 25.
Figure 26.
Spectral Response @ 10 MHz Input
Spectral Response @ 70 MHz Input
Figure 27.
Figure 28.
Spectral Response @ 240 MHz Input
Intermodulation Distortion, fIN1= 19.5 MHz, fIN2 = 20.5 MHz
Figure 29.
Figure 30.
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Typical Performance Characteristics (continued)
Unless otherwise specified, the following specifications apply: AGND = DRGND = 0V, VA = +3.3V, VDR = +2.5V, Internal VREF
= +1.2V, fCLK = 105 MHz, 50% Duty Cycle, DCS disabled, VCM = VCMO, fIN = 10 MHz, CL = 5 pF/pin. Typical values are for TA
= 25°C.
Power vs. fCLK
Figure 31.
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FUNCTIONAL DESCRIPTION
Operating on a single +3.3V supply, the ADC14C105 uses a pipeline architecture and has error correction
circuitry to help ensure maximum performance. The differential analog input signal is digitized to 14 bits. The
user has the choice of using an internal 1.2V stable reference, or using an external 1.2V reference. Any external
reference is buffered on-chip to ease the task of driving that pin.
The output word rate is the same as the clock frequency. The analog input is acquired at the rising edge of the
clock and the digital data for a given sample is delayed by the pipeline for 7 clock cycles. The digital outputs are
CMOS compatible signals that are clocked by a synchronous data ready output signal (DRDY, pin 21) at the
same rate as the clock input. Duty cycle stabilization and output data format are selectable using the quad state
function OF/DCS pin (pin 12). The output data can be set for offset binary or two's complement.
Power-down is selectable using the PD pin (pin 30). A logic high on the PD pin reduces the converter power
consumption. For normal operation, the PD pin should be connected to the analog ground (AGND).
Applications Information
OPERATING CONDITIONS
We recommend that the following conditions be observed for operation of the ADC14C105:
2.7V ≤ VA ≤ 3.6V
2.4V ≤ VDR ≤ VA
20 MHz ≤ fCLK ≤ 105 MHz
1.2V internal reference
VREF = 1.2V (for an external reference)
VCM = 1.5V (from VCMO)
ANALOG INPUTS
Signal Inputs
Differential Analog Input Pins
The ADC14C105 has one pair of analog signal input pins, VIN+ and VIN−, which form a differential input pair. The
input signal, VIN, is defined as
VIN = (VIN+) – (VIN−)
(3)
Figure 32 shows the expected input signal range. Note that the common mode input voltage, VCM, should be
1.5V. Using VCMO (pin 32) for VCM will ensure the proper input common mode level for the analog input signal.
The positive peaks of the individual input signals should each never exceed 2.6V. Each analog input pin of the
differential pair should have a maximum peak-to-peak voltage of 1V, be 180° out of phase with each other and
be centered around VCM.The peak-to-peak voltage swing at each analog input pin should not exceed the 1V or
the output data will be clipped.
Figure 32. Expected Input Signal Range
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For single frequency sine waves the full scale error in LSB can be described as approximately
EFS = 16384 ( 1 - sin (90° + dev))
(4)
Where dev is the angular difference in degrees between the two signals having a 180° relative phase relationship
to each other (see Figure 33). For single frequency inputs, angular errors result in a reduction of the effective full
scale input. For complex waveforms, however, angular errors will result in distortion.
Figure 33. Angular Errors Between the Two Input Signals Will Reduce the Output Level or Cause
Distortion
It is recommended to drive the analog inputs with a source impedance less than 100Ω. Matching the source
impedance for the differential inputs will improve even ordered harmonic performance (particularly second
harmonic).
Table 1 indicates the input to output relationship of the ADC14C105.
Table 1. Input to Output Relationship
VIN
VIN
Binary Output
2’s Complement Output
VCM − VREF/2
VCM + VREF/2
00 0000 0000 0000
10 0000 0000 0000
VCM − VREF/4
VCM + VREF/4
01 0000 0000 0000
11 0000 0000 0000
+
−
VCM
VCM
10 0000 0000 0000
00 0000 0000 0000
VCM + VREF/4
VCM − VREF/4
11 0000 0000 0000
01 0000 0000 0000
VCM + VREF/2
VCM − VREF/2
11 1111 1111 1111
01 1111 1111 1111
Negative Full-Scale
Mid-Scale
Positive Full-Scale
Driving the Analog Inputs
The VIN+ and the VIN− inputs of the ADC14C105 have an internal sample-and-hold circuit which consists of an
analog switch followed by a switched-capacitor amplifier.
Figure 34 and Figure 35 show examples of single-ended to differential conversion circuits. The circuit in
Figure 34 works well for input frequencies up to approximately 70MHz, while the circuit in Figure 35 works well
above 70MHz.
VIN
0.1 PF
20:
ADT1-1WT
18 pF
50:
ADC
Input
0.1 PF
0.1 PF
20:
VCMO
Figure 34. Low Input Frequency Transformer Drive Circuit
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VIN
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0.1 PF ETC1-1-13
25:
10 pF
0.1 PF
ETC1-1-13
ADC
Input
25:
VCMO
0.1 PF
Figure 35. High Input Frequency Transformer Drive Circuit
One short-coming of using a transformer to achieve the single-ended to differential conversion is that most RF
transformers have poor low frequency performance. A differential amplifier can be used to drive the analog inputs
for low frequency applications. The amplifier must be fast enough to settle from the charging glitches on the
analog input resulting from the sample-and-hold operation before the clock goes high and the sample is passed
to the ADC core.
The SFDR performance of the converter depends on the external signal conditioning circuity used, as this affects
how quickly the sample-and-hold charging glitch will settle. An external resistor and capacitor network as shown
in Figure 36 should be used to isolate the charging glitches at the ADC input from the external driving circuit and
to filter the wideband noise at the converter input. These components should be placed close to the ADC inputs
because the analog input of the ADC is the most sensitive part of the system, and this is the last opportunity to
filter that input. For Nyquist applications the RC pole should be at the ADC sample rate. The ADC input
capacitance in the sample mode should be considered when setting the RC pole. For wideband undersampling
applications, the RC pole should be set at least 1.5 to 2 times the maximum input frequency to maintain a linear
delay response.
Input Common Mode Voltage
The input common mode voltage, VCM, should be in the range of 1.4V to 1.6V and be a value such that the peak
excursions of the analog signal do not go more negative than ground or more positive than 2.6V. It is
recommended to use VCMO (pin 32) as the input common mode voltage.
If the ADC14C105 is operated with VA=3.6V, a resistor of approximately 1KΩ should be used from the VCMO pin
to AGND.This will help maintain stability over the entire temperature range when using a high supply voltage.
Reference Pins
The ADC14C105 is designed to operate with an internal or external 1.2V reference. The internal 1.2 Volt
reference is the default condition when no external reference input is applied to the VREF pin. If a voltage is
applied to the VREF pin, then that voltage is used for the reference. The VREF pin should always be bypassed to
ground with a 0.1 µF capacitor close to the reference input pin.
It is important that all grounds associated with the reference voltage and the analog input signal make connection
to the ground plane at a single, quiet point to minimize the effects of noise currents in the ground path.
The Reference Bypass Pins (VRP, VCMO, and VRN) are made available for bypass purposes. These pins should
each be bypassed to AGND with a low ESL (equivalent series inductance) 1 µF capacitor placed very close to
the pin to minimize stray inductance. A 0.1 µF capacitor should be placed between VRP and VRN as close to the
pins as possible, and a 1 µF capacitor should be placed in parallel. This configuration is shown in Figure 36. It is
necessary to avoid reference oscillation, which could result in reduced SFDR and/or SNR. VCMO may be loaded
to 1mA for use as a temperature stable 1.5V reference. The remaining pins should not be loaded.
Smaller capacitor values than those specified will allow faster recovery from the power down mode, but may
result in degraded noise performance. Loading any of these pins, other than VCMO may result in performance
degradation.
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The nominal voltages for the reference bypass pins are as follows:
VCMO = 1.5 V
VRP = 2.0 V
VRN = 1.0 V
OF/DCS Pin
Duty cycle stabilization and output data format are selectable using this quad state function pin. When enabled,
duty cycle stabilization can compensate for clock inputs with duty cycles ranging from 30% to 70% and generate
a stable internal clock, improving the performance of the part. With OF/DCS = VA the output data format is 2's
complement and duty cycle stabilization is not used. With OF/DCS = AGND the output data format is offset
binary and duty cycle stabilization is not used. With OF/DCS = (2/3)*VA the output data format is 2's complement
and duty cycle stabilization is applied to the clock. If OF/DCS is (1/3)*VA the output data format is offset binary
and duty cycle stabilization is applied to the clock. While the sense of this pin may be changed "on the fly," doing
this is not recommended as the output data could be erroneous for a few clock cycles after this change is made.
DIGITAL INPUTS
Digital CMOS compatible inputs consist of CLK, and PD.
Clock Input
The CLK controls the timing of the sampling process. To achieve the optimum noise performance, the clock input
should be driven with a stable, low jitter clock signal in the range indicated in the Electrical Table. The clock input
signal should also have a short transition region. This can be achieved by passing a low-jitter sinusoidal clock
source through a high speed buffer gate. This configuration is shown in Figure 36 . The trace carrying the clock
signal should be as short as possible and should not cross any other signal line, analog or digital, not even at
90°. Figure 36 shows the recommended clock input circuit.
The clock signal also drives an internal state machine. If the clock is interrupted, or its frequency is too low, the
charge on the internal capacitors can dissipate to the point where the accuracy of the output data will degrade.
This is what limits the minimum sample rate.
The clock line should be terminated at its source in the characteristic impedance of that line. Take care to
maintain a constant clock line impedance throughout the length of the line. Refer to Application Note (AN-905) for
information on setting characteristic impedance.
It is highly desirable that the the source driving the ADC clock pins only drive that pin. However, if that source is
used to drive other devices, then each driven pin should be AC terminated with a series RC to ground, such that
the resistor value is equal to the characteristic impedance of the clock line and the capacitor value is
(5)
where tPD is the signal propagation rate down the clock line, "L" is the line length and ZO is the characteristic
impedance of the clock line. This termination should be as close as possible to the ADC clock pin but beyond it
as seen from the clock source. Typical tPD is about 150 ps/inch (60 ps/cm) on FR-4 board material. The units of
"L" and tPD should be the same (inches or centimeters).
The duty cycle of the clock signal can affect the performance of the A/D Converter. Because achieving a precise
duty cycle is difficult, the ADC14C105 has a Duty Cycle Stabilizer. It is designed to maintain performance over a
clock duty cycle range of 30% to 70%.
Power-Down (PD)
The PD pin, when high, holds the ADC14C105 in a power-down mode to conserve power when the converter is
not being used. The power consumption in this state is 5 mW if the clock is stopped when PD is high. The output
data pins are undefined and the data in the pipeline is corrupted while in the power down mode.
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The Power Down Mode Exit Cycle time is determined by the value of the components on pins 1, 2, and 32 and is
about 3 ms with the recommended components on the VRP, VCMO and VRN reference bypass pins. These
capacitors loose their charge in the Power Down mode and must be recharged by on-chip circuitry before
conversions can be accurate. Smaller capacitor values allow slightly faster recovery from the power down mode,
but can result in a reduction in SNR, SINAD and ENOB performance.
DIGITAL OUTPUTS
Digital outputs consist of the CMOS signals D0-D13, and DRDY.
The ADC14C105 has 15 CMOS compatible data output pins corresponding to the converted input value and a
data ready (DRDY) signal that should be used to capture the output data. Valid data is present at these outputs
while the PD pin is low. Data should be captured and latched with the rising edge of the DRDY signal.
Be very careful when driving a high capacitance bus. The more capacitance the output drivers must charge for
each conversion, the more instantaneous digital current flows through VDR and DRGND. These large charging
current spikes can cause on-chip ground noise and couple into the analog circuitry, degrading dynamic
performance. Adequate bypassing, limiting output capacitance and careful attention to the ground plane will
reduce this problem. The result could be an apparent reduction in dynamic performance.
2.4 to VA Volts
+3.3V
CHOKE
2 x 0.1 PF
+
10 PF
31
0.1 PF
32
0.1 PF
2
0.1 PF 1
50
VIN
1
0.1 PF
20
ADC14C105
5
18 pF
2
0.1 PF
PD
OF/DCS
20
6
VIN-
30
PD
12
OF/DCC
11
CLK
4
7
9
Clock In
D7
D6
D5
D4
D3
D2
D1
(LSB) D0
VIN+
AGND
AGND
ADT1-1WT
20
V RP
V RN
1 PF
0.1 PF
T1
(MSB) D13
D12
D11
D10
D9
D8
VCMO
DRGND
0.1 PF
VREF
DRDY
29
28
27
26
25
24
23
19
18
17
16
15
14
13
21
74LVTH162374
Output
Word
CLK
22
1 PF
10 PF
V DR
VA 3
VA 8
10
VA
0.1 PF
Figure 36. Application Circuit
POWER SUPPLY CONSIDERATIONS
The power supply pins should be bypassed with a 0.1 µF capacitor and with a 100 pF ceramic chip capacitor
close to each power pin. Leadless chip capacitors are preferred because they have low series inductance.
As is the case with all high-speed converters, the ADC14C105 is sensitive to power supply noise. Accordingly,
the noise on the analog supply pin should be kept below 100 mVP-P.
No pin should ever have a voltage on it that is in excess of the supply voltages, not even on a transient basis. Be
especially careful of this during power turn on and turn off.
The VDR pin provides power for the output drivers and may be operated from a supply in the range of 2.4V to VA.
This enables lower power operation, reduces the noise coupling effects from the digital outputs to the analog
circuitry and simplifies interfacing to lower voltage devices and systems.
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LAYOUT AND GROUNDING
Proper grounding and proper routing of all signals are essential to ensure accurate conversion. Maintaining
separate analog and digital areas of the board, with the ADC14C105 between these areas, is required to achieve
specified performance.
The ground return for the data outputs (DRGND) carries the ground current for the output drivers. The output
current can exhibit high transients that could add noise to the conversion process. To prevent this from
happening, the DRGND pins should NOT be connected to system ground in close proximity to any of the
ADC14C105's other ground pins.
Capacitive coupling between the typically noisy digital circuitry and the sensitive analog circuitry can lead to poor
performance. The solution is to keep the analog circuitry separated from the digital circuitry, and to keep the
clock line as short as possible.
The effects of the noise generated from the ADC output switching can be minimized through the use of 22Ω
resistors in series with each data output line. Locate these resistors as close to the ADC output pins as possible.
Since digital switching transients are composed largely of high frequency components, total ground plane copper
weight will have little effect upon the logic-generated noise. This is because of the skin effect. Total surface area
is more important than is total ground plane area.
Generally, analog and digital lines should cross each other at 90° to avoid crosstalk. To maximize accuracy in
high speed, high resolution systems, however, avoid crossing analog and digital lines altogether. It is important to
keep clock lines as short as possible and isolated from ALL other lines, including other digital lines. Even the
generally accepted 90° crossing should be avoided with the clock line as even a little coupling can cause
problems at high frequencies. This is because other lines can introduce jitter into the clock line, which can lead to
degradation of SNR. Also, the high speed clock can introduce noise into the analog chain.
Best performance at high frequencies and at high resolution is obtained with a straight signal path. That is, the
signal path through all components should form a straight line wherever possible.
Be especially careful with the layout of inductors and transformers. Mutual inductance can change the
characteristics of the circuit in which they are used. Inductors and transformers should not be placed side by
side, even with just a small part of their bodies beside each other. For instance, place transformers for the analog
input and the clock input at 90° to one another to avoid magnetic coupling.
The analog input should be isolated from noisy signal traces to avoid coupling of spurious signals into the input.
Any external component (e.g., a filter capacitor) connected between the converter's input pins and ground or to
the reference input pin and ground should be connected to a very clean point in the ground plane.
All analog circuitry (input amplifiers, filters, reference components, etc.) should be placed in the analog area of
the board. All digital circuitry and dynamic I/O lines should be placed in the digital area of the board. The
ADC14C105 should be between these two areas. Furthermore, all components in the reference circuitry and the
input signal chain that are connected to ground should be connected together with short traces and enter the
ground plane at a single, quiet point. All ground connections should have a low inductance path to ground.
DYNAMIC PERFORMANCE
To achieve the best dynamic performance, the clock source driving the CLK input must have a sharp transition
region and be free of jitter. Isolate the ADC clock from any digital circuitry with buffers, as with the clock tree
shown in Figure 37. The gates used in the clock tree must be capable of operating at frequencies much higher
than those used if added jitter is to be prevented.
As mentioned in LAYOUT AND GROUNDING, it is good practice to keep the ADC clock line as short as possible
and to keep it well away from any other signals. Other signals can introduce jitter into the clock signal, which can
lead to reduced SNR performance, and the clock can introduce noise into other lines. Even lines with 90°
crossings have capacitive coupling, so try to avoid even these 90° crossings of the clock line.
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Copyright © 2007–2013, Texas Instruments Incorporated
Product Folder Links: ADC14C105
25
ADC14C105
SNAS409C – MAY 2007 – REVISED MARCH 2013
www.ti.com
Figure 37. Isolating the ADC Clock from other Circuitry with a Clock Tree
26
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Copyright © 2007–2013, Texas Instruments Incorporated
Product Folder Links: ADC14C105
ADC14C105
www.ti.com
SNAS409C – MAY 2007 – REVISED MARCH 2013
REVISION HISTORY
Changes from Revision B (March 2013) to Revision C
•
Page
Changed layout of National Data Sheet to TI format .......................................................................................................... 26
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Copyright © 2007–2013, Texas Instruments Incorporated
Product Folder Links: ADC14C105
27
PACKAGE OPTION ADDENDUM
www.ti.com
13-Sep-2014
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
ADC14C105CISQ/NOPB
ACTIVE
WQFN
RTV
32
1000
Green (RoHS
& no Sb/Br)
CU SN
Level-3-260C-168 HR
-40 to 85
14C105
ADC14C105CISQE/NOPB
ACTIVE
WQFN
RTV
32
250
Green (RoHS
& no Sb/Br)
CU SN
Level-3-260C-168 HR
-40 to 85
14C105
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
13-Sep-2014
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
21-Mar-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
ADC14C105CISQ/NOPB
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
WQFN
RTV
32
1000
178.0
12.4
5.3
5.3
1.3
8.0
12.0
Q1
ADC14C105CISQE/NOPB WQFN
RTV
32
250
178.0
12.4
5.3
5.3
1.3
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
21-Mar-2013
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
ADC14C105CISQ/NOPB
WQFN
RTV
32
1000
213.0
191.0
55.0
ADC14C105CISQE/NOPB
WQFN
RTV
32
250
213.0
191.0
55.0
Pack Materials-Page 2
MECHANICAL DATA
RTV0032A
SQA32A (Rev B)
www.ti.com
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