SILABS C8051F931-GM Pipelined intstruction architecture executes 70 of instruction in 1 or 2 system clock Datasheet

C8051F93x-C8051F92x
Single/Dual Battery, 0.9–3.6 V, 64/32 kB, SmaRTClock, 10-Bit ADC MCU
Supply Voltage 0.9 to 3.6 V
- One-Cell Mode supports 0.9 to 1.8 V operation
- Two-Cell Mode supports 1.8 to 3.6 V operation
- Built-in dc-dc converter with 1.8 to 3.3 V output for
High-Speed 8051 µC Core
- Pipelined instruction architecture; executes 70% of
instructions in 1 or 2 system clocks
use in one-cell mode
Built-in LDO regulator allows a high analog supply
voltage and low digital core voltage
- 2 built in supply monitors (brownout detectors)
10-Bit Analog to Digital Converter
- ±1 LSB INL; no missing codes
- Programmable throughput up to 300 ksps
- Up to 23 external inputs
- On-Chip Voltage Reference
- On-Chip PGA allows measuring voltages up to twice
the reference voltage
- 16-bit Auto-Averaging Accumulator with Burst Mode
provides increased ADC resolution
- Data dependent windowed interrupt generator
- Built-in temperature sensor
-
Two Comparators
- Programmable hysteresis and response time
- Configurable as wake-up or reset source
- Up to 23 Capacitive Touch Sense Inputs
6-Bit Programmable Current Reference
- Up to ±500 µA. Can be used as a bias or for
-
supports UART operation; 20 MHz low power
oscillator requires very little bias current
External oscillator: Crystal, RC, C, or CMOS Clock
SmaRTClock oscillator: 32 kHz Crystal or internal
self-oscillate mode
Can switch between clock sources on-the-fly; useful
in implementing various power saving modes
+
+
–
–
VOLTAGE
COMPARATORS
CROSSBAR
IREF
DIGITAL I/O
UART
SMBus
2 x SPI
PCA
Timer 0
Timer 1
Timer 2
Timer 3
CRC
Port 0
EMIF
10-bit
300 ksps
ADC
VREG
-
Packages
- 32-pin QFN (5 x 5 mm)
- 24-pin QFN (4 x 4 mm)
- 32-pin LQFP (7 x 7 mm, easy to hand-solder)
Temperature Range: –40 to +85 °C
ANALOG
PERIPHERALS
VREF
current and programmable drive strength-Hardware
SMBus™ (I2C™ Compatible), 2 x SPI™, and UART
serial ports available concurrently
Four general purpose 16-bit counter/timers
Programmable 16-bit counter/timer array with six
capture/compare modules and watchdog timer
Hardware SmaRTClock operates down to 0.9 V and
requires less than 0.5 µA supply current
-
intrusive in-system debug (no emulator required)
Provides breakpoints, single stepping
Inspect/modify memory and registers
Complete development kit
TEMP
SENSOR
Digital Peripherals
- 24 or 16 port I/O; All 5 V tolerant with high sink 
-
generating a custom reference voltage
A
M
U
X
grammable in 1024-byte sectors—1024 bytes are
reserved in the 64 kB devices
Clock Sources
- Internal oscillators: 24.5 MHz, 2% accuracy
On-Chip Debug
- On-chip debug circuitry facilitates full-speed, non-
- Up to 25 MIPS throughput with 25 MHz clock
- Expanded interrupt handler
Memory
- 4352 bytes internal data RAM (256 + 4096)
- 64 kB (‘F93x) or 32 kB (‘F92x) Flash; In-system pro-
Port 2
Port 1
24.5 MHz PRECISION
INTERNAL OSCILLATOR
20 MHz LOW POWER
INTERNAL OSCILLATOR
External Oscillator
HARDWARE SmaRTClock
HIGH-SPEED CONTROLLER CORE
64/32 kB
ISP FLASH
FLEXIBLE
INTERRUPTS
Rev. 1.3 5/12
8051 CPU
(25 MIPS)
DEBUG
CIRCUITRY
4352 B
SRAM
POR
WDT
Copyright © 2012 by Silicon Laboratories
C8051F93x-C8051F92x
C8051F93x-C8051F92x
2
Rev. 1.3
C8051F93x-C8051F92x
Table of Contents
1. System Overview.................................................................................................... 17
1.1. CIP-51™ Microcontroller Core.......................................................................... 20
1.1.1. Fully 8051 Compatible.............................................................................. 20
1.1.2. Improved Throughput ............................................................................... 20
1.1.3. Additional Features .................................................................................. 20
1.2. Port Input/Output............................................................................................... 21
1.3. Serial Ports ....................................................................................................... 22
1.4. Programmable Counter Array ........................................................................... 22
1.5. 10-Bit SAR ADC with 16-bit Auto-Averaging Accumulator and Autonomous Low
Power Burst Mode............................................................................................... 23
1.6. Programmable Current Reference (IREF0) ...................................................... 24
1.7. Comparators ..................................................................................................... 24
2. Ordering Information.............................................................................................. 26
3. Pinout and Package Definitions............................................................................ 27
4. Electrical Characteristics....................................................................................... 45
4.1. Absolute Maximum Specifications .................................................................... 45
4.2. Electrical Characteristics................................................................................... 46
5. 10-Bit SAR ADC with 16-bit Auto-Averaging Accumulator and Autonomous Low
Power Burst Mode ....................................................................................................... 67
5.1. Output Code Formatting ................................................................................... 68
5.2. Modes of Operation .......................................................................................... 69
5.2.1. Starting a Conversion............................................................................... 69
5.2.2. Tracking Modes........................................................................................ 70
5.2.3. Burst Mode ............................................................................................... 71
5.2.4. Settling Time Requirements ..................................................................... 73
5.2.5. Gain Setting.............................................................................................. 74
5.3. 8-Bit Mode......................................................................................................... 74
5.4. Programmable Window Detector ...................................................................... 81
5.4.1. Window Detector In Single-Ended Mode ................................................. 83
5.4.2. ADC0 Specifications................................................................................. 83
5.5. ADC0 Analog Multiplexer.................................................................................. 84
5.6. Temperature Sensor ......................................................................................... 86
5.6.1. Calibration ................................................................................................ 87
5.7. Voltage and Ground Reference Options........................................................... 89
5.8. External Voltage References ............................................................................ 90
5.9. Internal Voltage References ............................................................................. 90
5.10.Analog Ground Reference................................................................................ 90
5.11.Temperature Sensor Enable ............................................................................ 90
5.12.Voltage Reference Electrical Specifications ..................................................... 91
6. Programmable Current Reference (IREF0) .......................................................... 92
6.1. IREF0 Specifications......................................................................................... 92
7. Comparators ........................................................................................................... 93
7.1. Comparator Inputs ............................................................................................ 93
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7.2. Comparator Outputs ......................................................................................... 94
7.3. Comparator Response Time............................................................................. 95
7.4. Comparator Hysterisis ...................................................................................... 95
7.5. Comparator Register Descriptions.................................................................... 96
7.6. Comparator0 and Comparator1 Analog Multiplexers...................................... 100
8. CIP-51 Microcontroller ......................................................................................... 103
8.1. Instruction Set ................................................................................................. 104
8.1.1. Instruction and CPU Timing ................................................................... 104
8.2. CIP-51 Register Descriptions.......................................................................... 109
9. Memory Organization........................................................................................... 112
9.1. Program Memory ............................................................................................ 113
9.1.1. MOVX Instruction and Program Memory ............................................... 113
9.2. Data Memory .................................................................................................. 114
9.2.1. Internal RAM .......................................................................................... 114
9.2.2. External RAM ......................................................................................... 115
10. External Data Memory Interface and On-Chip XRAM........................................ 116
10.1.Accessing XRAM............................................................................................ 116
10.1.1.16-Bit MOVX Example ........................................................................... 116
10.1.2.8-Bit MOVX Example ............................................................................. 116
10.2.Configuring the External Memory Interface for Off-Chip Access.................... 117
10.3.External Memory Interface Port Input/Output Configuration........................... 117
10.4.Multiplexed External Memory Interface .......................................................... 118
10.5.External Memory Interface Operating Modes................................................. 120
10.5.1.Internal XRAM Only ............................................................................... 120
10.5.2.Split Mode without Bank Select.............................................................. 120
10.5.3.Split Mode with Bank Select................................................................... 121
10.5.4.External Only.......................................................................................... 121
10.6.External Memory Interface Timing.................................................................. 121
10.7.EMIF Special Function Registers ................................................................... 122
10.8.EMIF Timing Diagrams................................................................................... 125
10.8.1.Multiplexed 16-bit MOVX: EMI0CF[3:2] = 01, 10, or 11......................... 125
10.8.2.Multiplexed 8-bit MOVX without Bank Select: EMI0CF[3:2] = 01 or 11. 126
11. Special Function Registers ................................................................................. 129
11.1.SFR Paging .................................................................................................... 130
12. Interrupt Handler .................................................................................................. 136
12.1.Enabling Interrupt Sources ............................................................................. 136
12.2.MCU Interrupt Sources and Vectors............................................................... 136
12.3.Interrupt Priorities ........................................................................................... 137
12.4.Interrupt Latency............................................................................................. 137
12.5.Interrupt Register Descriptions ....................................................................... 139
12.6.External Interrupts INT0 and INT1.................................................................. 146
13. Flash Memory ....................................................................................................... 148
13.1.Programming The Flash Memory ................................................................... 148
13.1.1.Flash Lock and Key Functions ............................................................... 148
13.1.2.Flash Erase Procedure .......................................................................... 149
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C8051F93x-C8051F92x
13.1.3.Flash Write Procedure ........................................................................... 149
13.2.Non-volatile Data Storage .............................................................................. 150
13.3.Security Options ............................................................................................. 150
13.4.Determining the Device Part Number at Run Time ........................................ 152
13.5.Flash Write and Erase Guidelines .................................................................. 153
13.5.1.VDD Maintenance and the VDD Monitor ............................................... 153
13.5.2.PSWE Maintenance ............................................................................... 154
13.5.3.System Clock ......................................................................................... 154
13.6.Minimizing Flash Read Current ...................................................................... 155
14. Power Management.............................................................................................. 159
14.1.Normal Mode .................................................................................................. 160
14.2.Idle Mode........................................................................................................ 161
14.3.Stop Mode ...................................................................................................... 161
14.4.Suspend Mode ............................................................................................... 162
14.5.Sleep Mode .................................................................................................... 162
14.6.Configuring Wakeup Sources......................................................................... 163
14.7.Determining the Event that Caused the Last Wakeup.................................... 164
14.8.Power Management Specifications ................................................................ 166
15. Cyclic Redundancy Check Unit (CRC0) ............................................................. 167
15.1.16-bit CRC Algorithm...................................................................................... 167
15.2.32-bit CRC Algorithm...................................................................................... 169
15.3.Preparing for a CRC Calculation .................................................................... 170
15.4.Performing a CRC Calculation ....................................................................... 170
15.5.Accessing the CRC0 Result ........................................................................... 170
15.6.CRC0 Bit Reverse Feature............................................................................. 174
16. On-Chip DC-DC Converter (DC0) ........................................................................ 175
16.1.Startup Behavior............................................................................................. 176
16.2.High Power Applications ............................................................................. 177
16.3.Pulse Skipping Mode...................................................................................... 177
16.4.Enabling the DC-DC Converter ...................................................................... 178
16.5.Minimizing Power Supply Noise ..................................................................... 179
16.6.Selecting the Optimum Switch Size................................................................ 179
16.7.DC-DC Converter Clocking Options ............................................................... 179
16.8.DC-DC Converter Behavior in Sleep Mode .................................................... 180
16.9.DC-DC Converter Register Descriptions ........................................................ 181
16.10.DC-DC Converter Specifications .................................................................. 182
17. Voltage Regulator (VREG0) ................................................................................. 183
17.1.Voltage Regulator Electrical Specifications .................................................... 183
18. Reset Sources....................................................................................................... 184
18.1.Power-On (VBAT Supply Monitor) Reset ....................................................... 185
18.2.Power-Fail (VDD/DC+ Supply Monitor) Reset................................................ 186
18.3.External Reset ................................................................................................ 188
18.4.Missing Clock Detector Reset ........................................................................ 188
18.5.Comparator0 Reset ........................................................................................ 188
18.6.PCA Watchdog Timer Reset .......................................................................... 188
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5
C8051F93x-C8051F92x
18.7.Flash Error Reset ........................................................................................... 189
18.8.SmaRTClock (Real Time Clock) Reset .......................................................... 189
18.9.Software Reset ............................................................................................... 189
19. Clocking Sources ................................................................................................. 191
19.1.Programmable Precision Internal Oscillator ................................................... 192
19.2.Low Power Internal Oscillator......................................................................... 192
19.3.External Oscillator Drive Circuit...................................................................... 192
19.3.1.External Crystal Mode............................................................................ 192
19.3.2.External RC Mode.................................................................................. 194
19.3.3.External Capacitor Mode........................................................................ 195
19.3.4.External CMOS Clock Mode .................................................................. 196
19.4.Special Function Registers for Selecting and Configuring the System Clock 197
20. SmaRTClock (Real Time Clock) .......................................................................... 200
20.1.SmaRTClock Interface ................................................................................... 201
20.1.1.SmaRTClock Lock and Key Functions................................................... 201
20.1.2.Using RTC0ADR and RTC0DAT to Access SmaRTClock Internal Registers
..................................................................................................... 202
20.1.3.RTC0ADR Short Strobe Feature............................................................ 202
20.1.4.SmaRTClock Interface Autoread Feature .............................................. 203
20.1.5.RTC0ADR Autoincrement Feature......................................................... 203
20.2.SmaRTClock Clocking Sources ..................................................................... 206
20.2.1.Using the SmaRTClock Oscillator with a Crystal or 
External CMOS Clock ............................................................................ 206
20.2.2.Using the SmaRTClock Oscillator in Self-Oscillate Mode...................... 206
20.2.3.Programmable Load Capacitance.......................................................... 207
20.2.4.Automatic Gain Control (Crystal Mode Only) and SmaRTClock 
Bias Doubling ......................................................................................... 208
20.2.5.Missing SmaRTClock Detector .............................................................. 210
20.2.6.SmaRTClock Oscillator Crystal Valid Detector ...................................... 210
20.3.SmaRTClock Timer and Alarm Function ........................................................ 210
20.3.1.Setting and Reading the SmaRTClock Timer Value .............................. 210
20.3.2.Setting a SmaRTClock Alarm ................................................................ 211
20.3.3.Software Considerations for using the SmaRTClock Timer and Alarm . 211
21. Port Input/Output.................................................................................................. 216
21.1.Port I/O Modes of Operation........................................................................... 217
21.1.1.Port Pins Configured for Analog I/O....................................................... 217
21.1.2.Port Pins Configured For Digital I/O....................................................... 217
21.1.3.Interfacing Port I/O to 5 V and 3.3 V Logic............................................. 218
21.1.4.Increasing Port I/O Drive Strength ......................................................... 218
21.2.Assigning Port I/O Pins to Analog and Digital Functions................................ 218
21.2.1.Assigning Port I/O Pins to Analog Functions ......................................... 218
21.2.2.Assigning Port I/O Pins to Digital Functions........................................... 220
21.2.3.Assigning Port I/O Pins to External Digital Event Capture Functions .... 220
21.3.Priority Crossbar Decoder .............................................................................. 221
21.4.Port Match ...................................................................................................... 227
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C8051F93x-C8051F92x
21.5.Special Function Registers for Accessing and Configuring Port I/O .............. 229
22. SMBus ................................................................................................................... 238
22.1.Supporting Documents ................................................................................... 239
22.2.SMBus Configuration...................................................................................... 239
22.3.SMBus Operation ........................................................................................... 240
22.3.1.Transmitter Vs. Receiver........................................................................ 240
22.3.2.Arbitration............................................................................................... 241
22.3.3.Clock Low Extension.............................................................................. 241
22.3.4.SCL Low Timeout................................................................................... 241
22.3.5.SCL High (SMBus Free) Timeout .......................................................... 241
22.4.Using the SMBus............................................................................................ 242
22.4.1.SMBus Configuration Register............................................................... 243
22.4.2.SMB0CN Control Register ..................................................................... 246
22.4.3.Hardware Slave Address Recognition ................................................... 249
22.4.4.Data Register ......................................................................................... 251
22.5.SMBus Transfer Modes.................................................................................. 252
22.5.1.Write Sequence (Master) ....................................................................... 252
22.5.2.Read Sequence (Master) ....................................................................... 253
22.5.3.Write Sequence (Slave) ......................................................................... 254
22.5.4.Read Sequence (Slave) ......................................................................... 255
22.6.SMBus Status Decoding................................................................................. 255
23. UART0.................................................................................................................... 260
23.1.Enhanced Baud Rate Generation................................................................... 261
23.2.Operational Modes ......................................................................................... 262
23.2.1.8-Bit UART ............................................................................................. 262
23.2.2.9-Bit UART ............................................................................................. 263
23.3.Multiprocessor Communications .................................................................... 263
24. Enhanced Serial Peripheral Interface (SPI0 and SPI1)...................................... 268
24.1.Signal Descriptions......................................................................................... 269
24.1.1.Master Out, Slave In (MOSI).................................................................. 269
24.1.2.Master In, Slave Out (MISO).................................................................. 269
24.1.3.Serial Clock (SCK) ................................................................................. 269
24.1.4.Slave Select (NSS) ................................................................................ 269
24.2.SPI Master Mode Operation ........................................................................... 270
24.3.SPI Slave Mode Operation ............................................................................. 272
24.4.SPI Interrupt Sources ..................................................................................... 272
24.5.Serial Clock Phase and Polarity ..................................................................... 273
24.6.SPI Special Function Registers ...................................................................... 275
25. Timers.................................................................................................................... 283
25.1.Timer 0 and Timer 1 ....................................................................................... 285
25.1.1.Mode 0: 13-bit Counter/Timer ................................................................ 285
25.1.2.Mode 1: 16-bit Counter/Timer ................................................................ 286
25.1.3.Mode 2: 8-bit Counter/Timer with Auto-Reload...................................... 287
25.1.4.Mode 3: Two 8-bit Counter/Timers (Timer 0 Only)................................. 288
25.2.Timer 2 .......................................................................................................... 293
Rev. 1.3
7
C8051F93x-C8051F92x
25.2.1.16-bit Timer with Auto-Reload................................................................ 293
25.2.2.8-bit Timers with Auto-Reload................................................................ 294
25.2.3.Comparator 0/SmaRTClock Capture Mode ........................................... 295
25.3.Timer 3 .......................................................................................................... 299
25.3.1.16-bit Timer with Auto-Reload................................................................ 299
25.3.2.8-bit Timers with Auto-Reload................................................................ 300
25.3.3.Comparator 1/External Oscillator Capture Mode ................................... 301
26. Programmable Counter Array ............................................................................. 305
26.1.PCA Counter/Timer ........................................................................................ 306
26.2.PCA0 Interrupt Sources.................................................................................. 307
26.3.Capture/Compare Modules ............................................................................ 308
26.3.1.Edge-triggered Capture Mode................................................................ 309
26.3.2.Software Timer (Compare) Mode........................................................... 310
26.3.3.High-Speed Output Mode ...................................................................... 311
26.3.4.Frequency Output Mode ........................................................................ 312
26.3.5. 8-Bit, 9-Bit, 10-Bit and 11-Bit Pulse Width Modulator Modes............... 313
26.3.6. 16-Bit Pulse Width Modulator Mode..................................................... 315
26.4.Watchdog Timer Mode ................................................................................... 316
26.4.1.Watchdog Timer Operation .................................................................... 316
26.4.2.Watchdog Timer Usage ......................................................................... 317
26.5.Register Descriptions for PCA0...................................................................... 318
27. C2 Interface ........................................................................................................... 324
27.1.C2 Interface Registers.................................................................................... 324
27.2.C2 Pin Sharing ............................................................................................... 327
Document Change List............................................................................................. 328
Contact Information.................................................................................................. 330
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C8051F93x-C8051F92x
List of Figures
Figure 1.1. C8051F930 Block Diagram .................................................................... 18
Figure 1.2. C8051F931 Block Diagram .................................................................... 18
Figure 1.3. C8051F920 Block Diagram .................................................................... 19
Figure 1.4. C8051F921 Block Diagram .................................................................... 19
Figure 1.5. Port I/O Functional Block Diagram ......................................................... 21
Figure 1.6. PCA Block Diagram................................................................................ 22
Figure 1.7. ADC0 Functional Block Diagram............................................................ 23
Figure 1.8. ADC0 Multiplexer Block Diagram ........................................................... 24
Figure 1.9. Comparator 0 Functional Block Diagram ............................................... 25
Figure 1.10. Comparator 1 Functional Block Diagram ............................................. 25
Figure 3.1. QFN-32 Pinout Diagram (Top View) ...................................................... 31
Figure 3.2. QFN-24 Pinout Diagram (Top View) ...................................................... 32
Figure 3.3. LQFP-32 Pinout Diagram (Top View)..................................................... 33
Figure 3.4. QFN-32 Package Marking Diagram ....................................................... 34
Figure 3.5. QFN-24 Package Marking Diagram ....................................................... 35
Figure 3.6. LQFP-32 Package Marking Diagram ..................................................... 36
Figure 3.7. QFN-32 Package Drawing ..................................................................... 37
Figure 3.8. Typical QFN-32 Landing Diagram.......................................................... 38
Figure 3.9. QFN-24 Package Drawing ..................................................................... 40
Figure 3.10. Typical QFN-24 Landing Diagram........................................................ 41
Figure 3.11. LQFP-32 Package Diagram ................................................................. 43
Figure 3.12. Typical LQFP-32 Landing Diagram ...................................................... 44
Figure 4.1. Active Mode Current (External CMOS Clock) ........................................ 48
Figure 4.2. Idle Mode Current (External CMOS Clock) ............................................ 49
Figure 4.3. Typical DC-DC Converter Efficiency (High Current, VDD/DC+ = 2 V) ... 50
Figure 4.4. Typical DC-DC Converter Efficiency (High Current, VDD/DC+ = 3 V) ... 51
Figure 4.5. Typical DC-DC Converter Efficiency (Low Current, VDD/DC+ = 2 V).... 52
Figure 4.6. Typical One-Cell Suspend Mode Current............................................... 53
Figure 4.7. Typical VOH Curves, 1.8–3.6 V ............................................................. 55
Figure 4.8. Typical VOH Curves, 0.9–1.8 V ............................................................. 56
Figure 4.9. Typical VOL Curves, 1.8–3.6 V .............................................................. 57
Figure 4.10. Typical VOL Curves, 0.9–1.8 V ............................................................ 58
Figure 5.1. ADC0 Functional Block Diagram............................................................ 67
Figure 5.2. 10-Bit ADC Track and Conversion Example Timing (BURSTEN = 0).... 70
Figure 5.3. Burst Mode Tracking Example with Repeat Count Set to 4 ................... 72
Figure 5.4. ADC0 Equivalent Input Circuits .............................................................. 73
Figure 5.5. ADC Window Compare Example: Right-Justified Single-Ended Data ... 83
Figure 5.6. ADC Window Compare Example: Left-Justified Single-Ended Data...... 83
Figure 5.7. ADC0 Multiplexer Block Diagram ........................................................... 84
Figure 5.8. Temperature Sensor Transfer Function ................................................. 86
Figure 5.9. Temperature Sensor Error with 1-Point Calibration (VREF = 1.68 V) ..... 87
Figure 5.10. Voltage Reference Functional Block Diagram...................................... 89
Figure 7.1. Comparator 0 Functional Block Diagram ............................................... 93
Rev. 1.3
9
C8051F93x-C8051F92x
Figure 7.2. Comparator 1 Functional Block Diagram ............................................... 94
Figure 7.3. Comparator Hysteresis Plot ................................................................... 95
Figure 7.4. CPn Multiplexer Block Diagram............................................................ 100
Figure 8.1. CIP-51 Block Diagram.......................................................................... 103
Figure 9.1. C8051F93x-C8051F92x Memory Map ................................................. 112
Figure 9.2. Flash Program Memory Map................................................................ 113
Figure 10.1. Multiplexed Configuration Example.................................................... 118
Figure 10.2. Multiplexed to Non-Multiplexed Configuration Example..................... 119
Figure 10.3. EMIF Operating Modes ...................................................................... 120
Figure 10.4. Multiplexed 16-bit MOVX Timing........................................................ 125
Figure 10.5. Multiplexed 8-bit MOVX without Bank Select Timing ......................... 126
Figure 10.6. Multiplexed 8-bit MOVX with Bank Select Timing .............................. 127
Figure 13.1. Flash Program Memory Map.............................................................. 150
Figure 14.1. C8051F93x-C8051F92x Power Distribution....................................... 160
Figure 15.1. CRC0 Block Diagram ......................................................................... 167
Figure 15.2. Bit Reverse Register .......................................................................... 174
Figure 16.1. DC-DC Converter Block Diagram....................................................... 175
Figure 16.2. DC-DC Converter Configuration Options ........................................... 178
Figure 18.1. Reset Sources.................................................................................... 184
Figure 18.2. Power-Fail Reset Timing Diagram ..................................................... 185
Figure 18.3. Power-Fail Reset Timing Diagram ..................................................... 186
Figure 19.1. Clocking Sources Block Diagram ....................................................... 191
Figure 19.2. 25 MHz External Crystal Example...................................................... 193
Figure 20.1. SmaRTClock Block Diagram.............................................................. 200
Figure 20.2. Interpreting Oscillation Robustness (Duty Cycle) Test Results.......... 208
Figure 21.1. Port I/O Functional Block Diagram ..................................................... 216
Figure 21.2. Port I/O Cell Block Diagram ............................................................... 217
Figure 21.3. Crossbar Priority Decoder with No Pins Skipped ............................... 222
Figure 21.4. Crossbar Priority Decoder with Crystal Pins Skipped ........................ 223
Figure 22.1. SMBus Block Diagram ....................................................................... 238
Figure 22.2. Typical SMBus Configuration ............................................................. 239
Figure 22.3. SMBus Transaction ............................................................................ 240
Figure 22.4. Typical SMBus SCL Generation......................................................... 243
Figure 22.5. Typical Master Write Sequence ......................................................... 252
Figure 22.6. Typical Master Read Sequence ......................................................... 253
Figure 22.7. Typical Slave Write Sequence ........................................................... 254
Figure 22.8. Typical Slave Read Sequence ........................................................... 255
Figure 23.1. UART0 Block Diagram ....................................................................... 260
Figure 23.2. UART0 Baud Rate Logic .................................................................... 261
Figure 23.3. UART Interconnect Diagram .............................................................. 262
Figure 23.4. 8-Bit UART Timing Diagram............................................................... 262
Figure 23.5. 9-Bit UART Timing Diagram............................................................... 263
Figure 23.6. UART Multi-Processor Mode Interconnect Diagram .......................... 264
Figure 24.1. SPI Block Diagram ............................................................................. 268
Figure 24.2. Multiple-Master Mode Connection Diagram ....................................... 271
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C8051F93x-C8051F92x
Figure 24.3. 3-Wire Single Master and 3-Wire Single Slave Mode Connection Diagram
271
Figure 24.4. 4-Wire Single Master Mode and 4-Wire Slave Mode Connection Diagram
271
Figure 24.5. Master Mode Data/Clock Timing ........................................................ 273
Figure 24.6. Slave Mode Data/Clock Timing (CKPHA = 0) .................................... 274
Figure 24.7. Slave Mode Data/Clock Timing (CKPHA = 1) .................................... 274
Figure 24.8. SPI Master Timing (CKPHA = 0)........................................................ 280
Figure 24.9. SPI Master Timing (CKPHA = 1)........................................................ 280
Figure 24.10. SPI Slave Timing (CKPHA = 0)........................................................ 281
Figure 24.11. SPI Slave Timing (CKPHA = 1)........................................................ 281
Figure 25.1. T0 Mode 0 Block Diagram.................................................................. 286
Figure 25.2. T0 Mode 2 Block Diagram.................................................................. 287
Figure 25.3. T0 Mode 3 Block Diagram.................................................................. 288
Figure 25.4. Timer 2 16-Bit Mode Block Diagram .................................................. 293
Figure 25.5. Timer 2 8-Bit Mode Block Diagram .................................................... 294
Figure 25.6. Timer 2 Capture Mode Block Diagram ............................................... 295
Figure 25.7. Timer 3 16-Bit Mode Block Diagram .................................................. 299
Figure 25.8. Timer 3 8-Bit Mode Block Diagram. ................................................... 300
Figure 25.9. Timer 3 Capture Mode Block Diagram ............................................... 301
Figure 26.1. PCA Block Diagram............................................................................ 305
Figure 26.2. PCA Counter/Timer Block Diagram.................................................... 306
Figure 26.3. PCA Interrupt Block Diagram ............................................................. 307
Figure 26.4. PCA Capture Mode Diagram.............................................................. 309
Figure 26.5. PCA Software Timer Mode Diagram .................................................. 310
Figure 26.6. PCA High-Speed Output Mode Diagram............................................ 311
Figure 26.7. PCA Frequency Output Mode ............................................................ 312
Figure 26.8. PCA 8-Bit PWM Mode Diagram ......................................................... 313
Figure 26.9. PCA 9, 10 and 11-Bit PWM Mode Diagram ....................................... 314
Figure 26.10. PCA 16-Bit PWM Mode.................................................................... 315
Figure 26.11. PCA Module 5 with Watchdog Timer Enabled ................................. 316
Figure 27.1. Typical C2 Pin Sharing....................................................................... 327
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List of Tables
Table 2.1. Product Selection Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 3.1. Pin Definitions for the C8051F92x-C8051F93x . . . . . . . . . . . . . . . . . . . 27
Table 3.2. QFN-32 Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 3.3. PCB Land Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 3.4. QFN-24 Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 3.5. PCB Land Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Table 3.6. LQFP-32 Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Table 3.7. PCB Land Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Table 4.1.Absolute Maximum Ratings ..................................................................... 45
Table 4.2.Global Electrical Characteristics .............................................................. 46
Table 4.3.Port I/O DC Electrical Characteristics ...................................................... 54
Table 4.4.Reset Electrical Characteristics ............................................................... 59
Table 4.5.Power Management Electrical Specifications .......................................... 60
Table 4.6.Flash Electrical Characteristics ............................................................... 60
Table 4.7.Internal Precision Oscillator Electrical Characteristics ............................ 60
Table 4.8.Internal Low-Power Oscillator Electrical Characteristics ......................... 60
Table 4.9.ADC0 Electrical Characteristics ............................................................... 61
Table 4.10.Temperature Sensor Electrical Characteristics ..................................... 62
Table 4.11.Voltage Reference Electrical Characteristics ........................................ 62
Table 4.12.IREF0 Electrical Characteristics ............................................................ 63
Table 4.13.Comparator Electrical Characteristics ................................................... 64
Table 4.14.DC-DC Converter (DC0) Electrical Characteristics ............................... 66
Table 4.15.VREG0 Electrical Characteristics .......................................................... 66
Table 8.1. CIP-51 Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Table 10.1.AC Parameters for External Memory Interface .................................... 128
Table 11.1. Special Function Register (SFR) Memory Map (Page 0x0) . . . . . . . . 129
Table 11.2. Special Function Register (SFR) Memory Map (Page 0xF) . . . . . . . . 130
Table 11.3. Special Function Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
Table 12.1. Interrupt Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
Table 13.1. Flash Security Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
Table 14.1. Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
Table 15.1. Example 16-bit CRC Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
Table 15.2.Example 32-bit CRC Outputs .............................................................. 170
Table 16.1. IPeak Inductor Current Limit Settings . . . . . . . . . . . . . . . . . . . . . . . . . 176
Table 19.1. Recommended XFCN Settings for Crystal Mode . . . . . . . . . . . . . . . . 193
Table 19.2. Recommended XFCN Settings for RC and C modes . . . . . . . . . . . . . 194
Table 20.1.SmaRTClock Internal Registers .......................................................... 201
Table 20.2. SmaRTClock Load Capacitance Settings . . . . . . . . . . . . . . . . . . . . . 207
Table 20.3. SmaRTClock Bias Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
Table 21.1. Port I/O Assignment for Analog Functions . . . . . . . . . . . . . . . . . . . . . 218
Table 21.2. Port I/O Assignment for Digital Functions . . . . . . . . . . . . . . . . . . . . . . 220
Table 21.3. Port I/O Assignment for External Digital Event Capture Functions . . 220
Table 22.1. SMBus Clock Source Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243
12
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Table 22.2. Minimum SDA Setup and Hold Times . . . . . . . . . . . . . . . . . . . . . . . . 244
Table 22.3. Sources for Hardware Changes to SMB0CN . . . . . . . . . . . . . . . . . . . 248
Table 22.4. Hardware Address Recognition Examples (EHACK = 1) . . . . . . . . . . 249
Table 22.5. SMBus Status Decoding With Hardware ACK Generation Disabled
(EHACK = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256
Table 22.6. SMBus Status Decoding With Hardware ACK Generation Enabled
(EHACK = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258
Table 23.1. Timer Settings for Standard Baud Rates 
Using The Internal 24.5 MHz Oscillator . . . . . . . . . . . . . . . . . . . . . . . 267
Table 23.2. Timer Settings for Standard Baud Rates 
Using an External 22.1184 MHz Oscillator . . . . . . . . . . . . . . . . . . . . . 267
Table 24.1. SPI Slave Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282
Table 25.1. Timer 0 Running Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285
Table 26.1. PCA Timebase Input Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306
Table 26.2. PCA0CPM and PCA0PWM Bit Settings for PCA Capture/Compare Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308
Table 26.3. Watchdog Timer Timeout Intervals1 . . . . . . . . . . . . . . . . . . . . . . . . . . 317
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C8051F93x-C8051F92x
List of Registers
SFR Definition 5.1. ADC0CN: ADC0 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
SFR Definition 5.2. ADC0CF: ADC0 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
SFR Definition 5.3. ADC0AC: ADC0 Accumulator Configuration . . . . . . . . . . . . . . . . . 77
SFR Definition 5.4. ADC0PWR: ADC0 Burst Mode Power-Up Time . . . . . . . . . . . . . . 78
SFR Definition 5.5. ADC0TK: ADC0 Burst Mode Track Time . . . . . . . . . . . . . . . . . . . . 79
SFR Definition 5.6. ADC0H: ADC0 Data Word High Byte . . . . . . . . . . . . . . . . . . . . . . 80
SFR Definition 5.7. ADC0L: ADC0 Data Word Low Byte . . . . . . . . . . . . . . . . . . . . . . . 80
SFR Definition 5.8. ADC0GTH: ADC0 Greater-Than High Byte . . . . . . . . . . . . . . . . . . 81
SFR Definition 5.9. ADC0GTL: ADC0 Greater-Than Low Byte . . . . . . . . . . . . . . . . . . 81
SFR Definition 5.10. ADC0LTH: ADC0 Less-Than High Byte . . . . . . . . . . . . . . . . . . . 82
SFR Definition 5.11. ADC0LTL: ADC0 Less-Than Low Byte . . . . . . . . . . . . . . . . . . . . 82
SFR Definition 5.12. ADC0MX: ADC0 Input Channel Select . . . . . . . . . . . . . . . . . . . . 85
SFR Definition 5.13. TOFFH: ADC0 Data Word High Byte . . . . . . . . . . . . . . . . . . . . . 88
SFR Definition 5.14. TOFFL: ADC0 Data Word Low Byte . . . . . . . . . . . . . . . . . . . . . . 88
SFR Definition 5.15. REF0CN: Voltage Reference Control . . . . . . . . . . . . . . . . . . . . . 91
SFR Definition 6.1. IREF0CN: Current Reference Control . . . . . . . . . . . . . . . . . . . . . . 92
SFR Definition 7.1. CPT0CN: Comparator 0 Control . . . . . . . . . . . . . . . . . . . . . . . . . . 96
SFR Definition 7.2. CPT0MD: Comparator 0 Mode Selection . . . . . . . . . . . . . . . . . . . 97
SFR Definition 7.3. CPT1CN: Comparator 1 Control . . . . . . . . . . . . . . . . . . . . . . . . . . 98
SFR Definition 7.4. CPT1MD: Comparator 1 Mode Selection . . . . . . . . . . . . . . . . . . . 99
SFR Definition 7.5. CPT0MX: Comparator0 Input Channel Select . . . . . . . . . . . . . . . 101
SFR Definition 7.6. CPT1MX: Comparator1 Input Channel Select . . . . . . . . . . . . . . . 102
SFR Definition 8.1. DPL: Data Pointer Low Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
SFR Definition 8.2. DPH: Data Pointer High Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
SFR Definition 8.3. SP: Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
SFR Definition 8.4. ACC: Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
SFR Definition 8.5. B: B Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
SFR Definition 8.6. PSW: Program Status Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
SFR Definition 10.1. EMI0CN: External Memory Interface Control . . . . . . . . . . . . . . 122
SFR Definition 10.2. EMI0CF: External Memory Configuration . . . . . . . . . . . . . . . . . 123
SFR Definition 10.3. EMI0TC: External Memory Timing Control . . . . . . . . . . . . . . . . 124
SFR Definition 11.1. SFR Page: SFR Page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
SFR Definition 12.1. IE: Interrupt Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
SFR Definition 12.2. IP: Interrupt Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
SFR Definition 12.3. EIE1: Extended Interrupt Enable 1 . . . . . . . . . . . . . . . . . . . . . . 142
SFR Definition 12.4. EIP1: Extended Interrupt Priority 1 . . . . . . . . . . . . . . . . . . . . . . 143
SFR Definition 12.5. EIE2: Extended Interrupt Enable 2 . . . . . . . . . . . . . . . . . . . . . . 144
SFR Definition 12.6. EIP2: Extended Interrupt Priority 2 . . . . . . . . . . . . . . . . . . . . . . 145
SFR Definition 12.7. IT01CF: INT0/INT1 Configuration . . . . . . . . . . . . . . . . . . . . . . . 147
SFR Definition 13.1. PSCTL: Program Store R/W Control . . . . . . . . . . . . . . . . . . . . . 156
SFR Definition 13.2. FLKEY: Flash Lock and Key . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
SFR Definition 13.3. FLSCL: Flash Scale . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
SFR Definition 13.4. FLWR: Flash Write Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
14
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C8051F93x-C8051F92x
SFR Definition 14.1. PMU0CF: Power Management Unit Configuration1,2 . . . . . . . . 165
SFR Definition 14.2. PCON: Power Management Control Register . . . . . . . . . . . . . . 166
SFR Definition 15.1. CRC0CN: CRC0 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
SFR Definition 15.2. CRC0IN: CRC0 Data Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
SFR Definition 15.3. CRC0DAT: CRC0 Data Output . . . . . . . . . . . . . . . . . . . . . . . . . 172
SFR Definition 15.4. CRC0AUTO: CRC0 Automatic Control . . . . . . . . . . . . . . . . . . . 173
SFR Definition 15.5. CRC0CNT: CRC0 Automatic Flash Sector Count . . . . . . . . . . . 173
SFR Definition 15.6. CRC0FLIP: CRC0 Bit Flip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
SFR Definition 16.1. DC0CN: DC-DC Converter Control . . . . . . . . . . . . . . . . . . . . . . 181
SFR Definition 16.2. DC0CF: DC-DC Converter Configuration . . . . . . . . . . . . . . . . . 182
SFR Definition 17.1. REG0CN: Voltage Regulator Control . . . . . . . . . . . . . . . . . . . . 183
SFR Definition 18.1. VDM0CN: VDD/DC+ Supply Monitor Control . . . . . . . . . . . . . . 187
SFR Definition 18.2. RSTSRC: Reset Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
SFR Definition 19.1. CLKSEL: Clock Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
SFR Definition 19.2. OSCICN: Internal Oscillator Control . . . . . . . . . . . . . . . . . . . . . 198
SFR Definition 19.3. OSCICL: Internal Oscillator Calibration . . . . . . . . . . . . . . . . . . . 198
SFR Definition 19.4. OSCXCN: External Oscillator Control . . . . . . . . . . . . . . . . . . . . 199
SFR Definition 20.1. RTC0KEY: SmaRTClock Lock and Key . . . . . . . . . . . . . . . . . . 204
SFR Definition 20.2. RTC0ADR: SmaRTClock Address . . . . . . . . . . . . . . . . . . . . . . 205
SFR Definition 20.3. RTC0DAT: SmaRTClock Data . . . . . . . . . . . . . . . . . . . . . . . . . 205
Internal Register Definition 20.4. RTC0CN: SmaRTClock Control . . . . . . . . . . . . . . . 212
Internal Register Definition 20.5. RTC0XCN: SmaRTClock Oscillator Control . . . . . . 213
Internal Register Definition 20.6. RTC0XCF: SmaRTClock Oscillator Configuration . 214
Internal Register Definition 20.7. RTC0PIN: SmaRTClock Pin Configuration . . . . . . 214
Internal Register Definition 20.8. CAPTUREn: SmaRTClock Timer Capture . . . . . . . 215
Internal Register Definition 20.9. ALARMn: SmaRTClock Alarm Programmed Value 215
SFR Definition 21.1. XBR0: Port I/O Crossbar Register 0 . . . . . . . . . . . . . . . . . . . . . 224
SFR Definition 21.2. XBR1: Port I/O Crossbar Register 1 . . . . . . . . . . . . . . . . . . . . . 225
SFR Definition 21.3. XBR2: Port I/O Crossbar Register 2 . . . . . . . . . . . . . . . . . . . . . 226
SFR Definition 21.4. P0MASK: Port0 Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . 227
SFR Definition 21.5. P0MAT: Port0 Match Register . . . . . . . . . . . . . . . . . . . . . . . . . . 227
SFR Definition 21.6. P1MASK: Port1 Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . 228
SFR Definition 21.7. P1MAT: Port1 Match Register . . . . . . . . . . . . . . . . . . . . . . . . . . 228
SFR Definition 21.8. P0: Port0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230
SFR Definition 21.9. P0SKIP: Port0 Skip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230
SFR Definition 21.10. P0MDIN: Port0 Input Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 231
SFR Definition 21.11. P0MDOUT: Port0 Output Mode . . . . . . . . . . . . . . . . . . . . . . . . 231
SFR Definition 21.12. P0DRV: Port0 Drive Strength . . . . . . . . . . . . . . . . . . . . . . . . . 232
SFR Definition 21.13. P1: Port1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233
SFR Definition 21.14. P1SKIP: Port1 Skip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233
SFR Definition 21.15. P1MDIN: Port1 Input Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 234
SFR Definition 21.16. P1MDOUT: Port1 Output Mode . . . . . . . . . . . . . . . . . . . . . . . . 234
SFR Definition 21.17. P1DRV: Port1 Drive Strength . . . . . . . . . . . . . . . . . . . . . . . . . 235
SFR Definition 21.18. P2: Port2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235
SFR Definition 21.19. P2SKIP: Port2 Skip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236
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C8051F93x-C8051F92x
SFR Definition 21.20. P2MDIN: Port2 Input Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 236
SFR Definition 21.21. P2MDOUT: Port2 Output Mode . . . . . . . . . . . . . . . . . . . . . . . . 237
SFR Definition 21.22. P2DRV: Port2 Drive Strength . . . . . . . . . . . . . . . . . . . . . . . . . 237
SFR Definition 22.1. SMB0CF: SMBus Clock/Configuration . . . . . . . . . . . . . . . . . . . 245
SFR Definition 22.2. SMB0CN: SMBus Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247
SFR Definition 22.3. SMB0ADR: SMBus Slave Address . . . . . . . . . . . . . . . . . . . . . . 250
SFR Definition 22.4. SMB0ADM: SMBus Slave Address Mask . . . . . . . . . . . . . . . . . 250
SFR Definition 22.5. SMB0DAT: SMBus Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251
SFR Definition 23.1. SCON0: Serial Port 0 Control . . . . . . . . . . . . . . . . . . . . . . . . . . 265
SFR Definition 23.2. SBUF0: Serial (UART0) Port Data Buffer . . . . . . . . . . . . . . . . . 266
SFR Definition 24.1. SPInCFG: SPI Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . 276
SFR Definition 24.2. SPInCN: SPI Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277
SFR Definition 24.3. SPInCKR: SPI Clock Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278
SFR Definition 24.4. SPInDAT: SPI Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279
SFR Definition 25.1. CKCON: Clock Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284
SFR Definition 25.2. TCON: Timer Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289
SFR Definition 25.3. TMOD: Timer Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290
SFR Definition 25.4. TL0: Timer 0 Low Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291
SFR Definition 25.5. TL1: Timer 1 Low Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291
SFR Definition 25.6. TH0: Timer 0 High Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292
SFR Definition 25.7. TH1: Timer 1 High Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292
SFR Definition 25.8. TMR2CN: Timer 2 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296
SFR Definition 25.9. TMR2RLL: Timer 2 Reload Register Low Byte . . . . . . . . . . . . . 297
SFR Definition 25.10. TMR2RLH: Timer 2 Reload Register High Byte . . . . . . . . . . . 297
SFR Definition 25.11. TMR2L: Timer 2 Low Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298
SFR Definition 25.12. TMR2H Timer 2 High Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298
SFR Definition 25.13. TMR3CN: Timer 3 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302
SFR Definition 25.14. TMR3RLL: Timer 3 Reload Register Low Byte . . . . . . . . . . . . 303
SFR Definition 25.15. TMR3RLH: Timer 3 Reload Register High Byte . . . . . . . . . . . 303
SFR Definition 25.16. TMR3L: Timer 3 Low Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304
SFR Definition 25.17. TMR3H Timer 3 High Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304
SFR Definition 26.1. PCA0CN: PCA Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 318
SFR Definition 26.2. PCA0MD: PCA Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319
SFR Definition 26.3. PCA0PWM: PCA PWM Configuration . . . . . . . . . . . . . . . . . . . . 320
SFR Definition 26.4. PCA0CPMn: PCA Capture/Compare Mode . . . . . . . . . . . . . . . 321
SFR Definition 26.5. PCA0L: PCA Counter/Timer Low Byte . . . . . . . . . . . . . . . . . . . 322
SFR Definition 26.6. PCA0H: PCA Counter/Timer High Byte . . . . . . . . . . . . . . . . . . . 322
SFR Definition 26.7. PCA0CPLn: PCA Capture Module Low Byte . . . . . . . . . . . . . . . 323
SFR Definition 26.8. PCA0CPHn: PCA Capture Module High Byte . . . . . . . . . . . . . . 323
C2 Register Definition 27.1. C2ADD: C2 Address . . . . . . . . . . . . . . . . . . . . . . . . . . . 324
C2 Register Definition 27.2. DEVICEID: C2 Device ID . . . . . . . . . . . . . . . . . . . . . . . . 325
C2 Register Definition 27.3. REVID: C2 Revision ID . . . . . . . . . . . . . . . . . . . . . . . . . 325
C2 Register Definition 27.4. FPCTL: C2 Flash Programming Control . . . . . . . . . . . . 326
C2 Register Definition 27.5. FPDAT: C2 Flash Programming Data . . . . . . . . . . . . . . 326
16
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C8051F93x-C8051F92x
1.
System Overview
C8051F93x-C8051F92x devices are fully integrated mixed-signal System-on-a-Chip MCUs. Highlighted
features are listed below. Refer to Table 2.1 for specific product feature selection and part ordering numbers.
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Single/Dual Battery operation with on-chip dc-dc boost converter.
High-speed pipelined 8051-compatible microcontroller core (up to 25 MIPS)
In-system, full-speed, non-intrusive debug interface (on-chip)
True 10-bit 300 ksps 23-channel single-ended ADC with analog multiplexer
6-Bit Programmable Current Reference
Precision programmable 24.5 MHz internal oscillator with spread spectrum technology.
64 kB or 32 kB of on-chip Flash memory
4352 bytes of on-chip RAM
SMBus/I2C, Enhanced UART, and two Enhanced SPI serial interfaces implemented in hardware
Four general-purpose 16-bit timers
Programmable Counter/Timer Array (PCA) with six capture/compare modules and Watchdog Timer
function
On-chip Power-On Reset, VDD Monitor, and Temperature Sensor
Two On-chip Voltage Comparators with 23 Touch Sense inputs.
24 or 16 Port I/O (5 V tolerant)
With on-chip Power-On Reset, VDD monitor, Watchdog Timer, and clock oscillator, the C8051F93xC8051F92x devices are truly stand-alone System-on-a-Chip solutions. The Flash memory can be reprogrammed even in-circuit, providing non-volatile data storage, and also allowing field upgrades of the 8051
firmware. User software has complete control of all peripherals, and may individually shut down any or all
peripherals for power savings.
The on-chip Silicon Labs 2-Wire (C2) Development Interface allows non-intrusive (uses no on-chip
resources), full speed, in-circuit debugging using the production MCU installed in the final application. This
debug logic supports inspection and modification of memory and registers, setting breakpoints, single
stepping, run and halt commands. All analog and digital peripherals are fully functional while debugging
using C2. The two C2 interface pins can be shared with user functions, allowing in-system debugging without occupying package pins.
Each device is specified for 0.9 to 1.8 V or 1.8 to 3.6 V operation over the industrial temperature range 
(–40 to +85 °C). The Port I/O and RST pins are tolerant of input signals up to 5 V. The C8051F930/20 are
available in 32-pin QFN or LQFP packages and the C8051F931/21 are available in a 24-pin QFN package.
Both package options are lead-free and RoHS compliant. See Table 2.1 for ordering information. Block
diagrams are included in Figure 1.1 through Figure 1.4.
Rev. 1.3
17
C8051F93x-C8051F92x
Wake
Reset
C2CK/RST
Debug /
Programming
Hardware
Power Net
UART
256 Byte SRAM
Timers 0,
1, 2, 3
4096 Byte XRAM
VREG
Analog
Power
GND/DC-
DCEN
VBAT
DC/DC
Converter
SPI 0,1
SFR
Bus
Low Power
20 MHz
Oscillator
GND
XTAL2
XTAL3
Port 0
Drivers
P0.0/VREF
P0.1/AGND
P0.2/XTAL1
P0.3/XTAL2
P0.4/TX
P0.5/RX
P0.6/CNVSTR
P0.7/IREF0
Analog Peripherals
IREF0
Internal
External
VREF
VREF
VDD
VREF
Temp
Sensor
A
M
U
X
10-bit
300ksps
ADC
SmaRTClock
Oscillator
XTAL4
Crossbar Control
6-bit
IREF
External
Oscillator
Circuit
XTAL1
Port 2
Drivers
P2.0/A8
P2.1/A9
P2.2/A10
P2.3/A11
P2.4/ALE
P2.5/RD
P2.6/WR
P2.7/C2D
SMBus
SYSCLK
Precision
24.5 MHz
Oscillator
Port 1
Drivers
P1.0/AD0
P1.1/AD1
P1.2/AD2
P1.3/AD3
P1.4/AD4
P1.5/AD5
P1.6/AD6
P1.7/AD7
Priority
Crossbar
Decoder
PCA/
WDT
CRC
Engine
Digital
Power
Port 0
Drivers
P0.0/VREF
P0.1/AGND
P0.2/XTAL1
P0.3/XTAL2
P0.4/TX
P0.5/RX
P0.6/CNVSTR
P0.7/IREF0
Digital Peripherals
64 kB ISP Flash
Program Memory
C2D
VDD/DC+
Port I/O Configuration
CIP-51 8051
Controller Core
Power On
Reset/PMU
GND
CP0, CP0A
System Clock
Configuration
CP1, CP1A
+
-
+
-
Comparators
Figure 1.1. C8051F930 Block Diagram
Wake
Reset
C2CK/RST
Debug /
Programming
Hardware
Power Net
Analog
Power
GND/DC-
DCEN
UART
256 Byte SRAM
Timers 0,
1, 2, 3
4096 Byte XRAM
VBAT
GND
XTAL1
XTAL2
XTAL3
XTAL4
VREG
Digital
Power
SMBus
SPI 0,1
SYSCLK
Low Power
20 MHz
Oscillator
External
Oscillator
Circuit
SmaRTClock
Oscillator
Priority
Crossbar
Decoder
PCA/
WDT
CRC
Engine
Precision
24.5 MHz
Oscillator
DC/DC
Converter
Digital Peripherals
64 kB ISP Flash
Program Memory
C2D
VDD/DC+
Port I/O Configuration
CIP-51 8051
Controller Core
Power On
Reset/PMU
SFR
Bus
Crossbar Control
Analog Peripherals
6-bit
IREF
IREF0
Internal
External
VREF
VREF
Port 2
Drivers
A
M
U
X
10-bit
300ksps
ADC
VDD
VREF
Temp
Sensor
GND
CP0, CP0A
System Clock
Configuration
CP1, CP1A
+
-
+
-
Comparators
Figure 1.2. C8051F931 Block Diagram
18
Port 1
Drivers
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
Rev. 1.3
P2.7/C2D
C8051F93x-C8051F92x
Wake
Reset
C2CK/RST
Debug /
Programming
Hardware
Power Net
UART
256 Byte SRAM
Timers 0,
1, 2, 3
4096 Byte XRAM
VREG
Analog
Power
GND/DC-
DCEN
VBAT
DC/DC
Converter
SPI 0,1
SFR
Bus
Low Power
20 MHz
Oscillator
GND
XTAL2
XTAL3
Port 0
Drivers
P0.0/VREF
P0.1/AGND
P0.2/XTAL1
P0.3/XTAL2
P0.4/TX
P0.5/RX
P0.6/CNVSTR
P0.7/IREF0
Analog Peripherals
IREF0
Internal
External
VREF
VREF
VDD
VREF
Temp
Sensor
A
M
U
X
10-bit
300ksps
ADC
SmaRTClock
Oscillator
XTAL4
Crossbar Control
6-bit
IREF
External
Oscillator
Circuit
XTAL1
Port 2
Drivers
P2.0/A8
P2.1/A9
P2.2/A10
P2.3/A11
P2.4/ALE
P2.5/RD
P2.6/WR
P2.7/C2D
SMBus
SYSCLK
Precision
24.5 MHz
Oscillator
Port 1
Drivers
P1.0/AD0
P1.1/AD1
P1.2/AD2
P1.3/AD3
P1.4/AD4
P1.5/AD5
P1.6/AD6
P1.7/AD7
Priority
Crossbar
Decoder
PCA/
WDT
CRC
Engine
Digital
Power
Port 0
Drivers
P0.0/VREF
P0.1/AGND
P0.2/XTAL1
P0.3/XTAL2
P0.4/TX
P0.5/RX
P0.6/CNVSTR
P0.7/IREF0
Digital Peripherals
32 kB ISP Flash
Program Memory
C2D
VDD/DC+
Port I/O Configuration
CIP-51 8051
Controller Core
Power On
Reset/PMU
GND
CP0, CP0A
System Clock
Configuration
CP1, CP1A
+
-
+
-
Comparators
Figure 1.3. C8051F920 Block Diagram
Wake
Reset
C2CK/RST
Debug /
Programming
Hardware
Power Net
Analog
Power
GND/DC-
DCEN
UART
256 Byte SRAM
Timers 0,
1, 2, 3
4096 Byte XRAM
VBAT
GND
XTAL1
XTAL2
XTAL3
XTAL4
VREG
Digital
Power
SMBus
SPI 0,1
SYSCLK
Low Power
20 MHz
Oscillator
External
Oscillator
Circuit
SmaRTClock
Oscillator
Priority
Crossbar
Decoder
PCA/
WDT
CRC
Engine
Precision
24.5 MHz
Oscillator
DC/DC
Converter
Digital Peripherals
32 kB ISP Flash
Program Memory
C2D
VDD/DC+
Port I/O Configuration
CIP-51 8051
Controller Core
Power On
Reset/PMU
SFR
Bus
Crossbar Control
Analog Peripherals
6-bit
IREF
IREF0
Internal
External
VREF
VREF
Port 2
Drivers
A
M
U
X
10-bit
300ksps
ADC
VDD
VREF
Temp
Sensor
P2.7/C2D
GND
CP0, CP0A
System Clock
Configuration
Port 1
Drivers
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
CP1, CP1A
+
-
+
-
Comparators
Figure 1.4. C8051F921 Block Diagram
Rev. 1.3
19
C8051F93x-C8051F92x
1.1.
CIP-51™ Microcontroller Core
1.1.1. Fully 8051 Compatible
The C8051F93x-C8051F92x family utilizes Silicon Labs' proprietary CIP-51 microcontroller core. The CIP51 is fully compatible with the MCS-51™ instruction set; standard 803x/805x assemblers and compilers
can be used to develop software. The CIP-51 core offers all the peripherals included with a standard 8052.
1.1.2. Improved Throughput
The CIP-51 employs a pipelined architecture that greatly increases its instruction throughput over the standard 8051 architecture. In a standard 8051, all instructions except for MUL and DIV take 12 or 24 system
clock cycles to execute with a maximum system clock of 12-to-24 MHz. By contrast, the CIP-51 core executes 70% of its instructions in one or two system clock cycles, with only four instructions taking more than
four system clock cycles.
The CIP-51 has a total of 109 instructions. The table below shows the total number of instructions that
require each execution time.
Clocks to Execute
1
2
2/3
3
3/4
4
4/5
5
8
Number of Instructions
26
50
5
14
7
3
1
2
1
With the CIP-51's maximum system clock at 25 MHz, it has a peak throughput of 25 MIPS.
1.1.3. Additional Features
The C8051F93x-C8051F92x SoC family includes several key enhancements to the CIP-51 core and
peripherals to improve performance and ease of use in end applications.
The extended interrupt handler provides multiple interrupt sources into the CIP-51 allowing numerous analog and digital peripherals to interrupt the controller. An interrupt driven system requires less intervention
by the MCU, giving it more effective throughput. The extra interrupt sources are very useful when building
multi-tasking, real-time systems.
Eight reset sources are available: power-on reset circuitry (POR), an on-chip VDD monitor (forces reset
when power supply voltage drops below safe levels), a Watchdog Timer, a Missing Clock Detector,
SmaRTClock oscillator fail or alarm, a voltage level detection from Comparator0, a forced software reset,
an external reset pin, and an illegal Flash access protection circuit. Each reset source except for the POR,
Reset Input Pin, or Flash error may be disabled by the user in software. The WDT may be permanently disabled in software after a power-on reset during MCU initialization.
The internal oscillator factory calibrated to 24.5 MHz and is accurate to ±2% over the full temperature and
supply range. The internal oscillator period can also be adjusted by user firmware. An additional 20 MHz
low power oscillator is also available which facilitates low-power operation. An external oscillator drive circuit is included, allowing an external crystal, ceramic resonator, capacitor, RC, or CMOS clock source to
generate the system clock. If desired, the system clock source may be switched on-the-fly between both
internal and external oscillator circuits. An external oscillator can also be extremely useful in low power
applications, allowing the MCU to run from a slow (power saving) source, while periodically switching to
the fast (up to 25 MHz) internal oscillator as needed.
20
Rev. 1.3
C8051F93x-C8051F92x
1.2.
Port Input/Output
Digital and analog resources are available through 24 I/O pins (C8051F930/20) or 16 I/O pins
(C8051F931/21). Port pins are organized as three byte-wide ports. Port pins P0.0–P2.6 can be defined as
digital or analog I/O. Digital I/O pins can be assigned to one of the internal digital resources or used as
general purpose I/O (GPIO). Analog I/O pins are used by the internal analog resources. P2.7 can be used
as GPIO and is shared with the C2 Interface Data signal (C2D). See Section “27. C2 Interface” on
page 324 for more details.
The designer has complete control over which digital and analog functions are assigned to individual Port
pins, limited only by the number of physical I/O pins. This resource assignment flexibility is achieved
through the use of a Priority Crossbar Decoder. See Section “21.3. Priority Crossbar Decoder” on
page 221 for more information on the Crossbar.
All Port I/Os are 5 V tolerant when used as digital inputs or open-drain outputs. For Port I/Os configured as
push-pull outputs, current is sourced from the VDD/DC+ supply. Port I/Os used for analog functions can
operate up to the VDD/DC+ supply voltage. See Section “21.1. Port I/O Modes of Operation” on page 217
for more information on Port I/O operating modes and the electrical specifications chapter for detailed electrical specifications.
XBR0, XBR1,
XBR2, PnSKIP
Registers
Port Match
P0MASK, P0MAT
P1MASK, P1MAT
External Interrupts
EX0 and EX1
Priority
Decoder
Highest
Priority
UART
4
(Internal Digital Signals)
SPI0
SPI1
SMBus
CP0
CP1
Outputs
P0.0
2
Digital
Crossbar
8
4
8
7
T0, T1
P0
I/O
Cells
P0.7
SYSCLK
PCA
Lowest
Priority
PnMDOUT,
PnMDIN Registers
2
P1.0
P1
I/O
Cells
P1.7
2
8
(Port Latches)
P0
8
(P0.0-P0.7)
8
P1
P2.0
P2
I/O
Cell
To EMIF
(P1.0-P1.7)
8
P2
P1.6
To Analog Peripherals
(ADC0, CP0, and CP1 inputs,
VREF, IREF0, AGND)
(P2.0-P2.7)
P2.6
P2.7
P1.7–2.6 only available
on 32-pin devices
P2.7 is available on all
devices
Figure 1.5. Port I/O Functional Block Diagram
Rev. 1.3
21
C8051F93x-C8051F92x
1.3.
Serial Ports
The C8051F93x-C8051F92x Family includes an SMBus/I2C interface, a full-duplex UART with enhanced
baud rate configuration, and two Enhanced SPI interfaces. Each of the serial buses is fully implemented in
hardware and makes extensive use of the CIP-51's interrupts, thus requiring very little CPU intervention.
1.4.
Programmable Counter Array
An on-chip Programmable Counter/Timer Array (PCA) is included in addition to the four 16-bit general purpose counter/timers. The PCA consists of a dedicated 16-bit counter/timer time base with six programmable capture/compare modules. The PCA clock is derived from one of six sources: the system clock divided
by 12, the system clock divided by 4, Timer 0 overflows, an External Clock Input (ECI), the system clock, or
the external oscillator clock source divided by 8.
Each capture/compare module can be configured to operate in a variety of modes: edge-triggered capture,
software timer, high-speed output, pulse width modulator (8, 9, 10, 11, or 16-bit), or frequency output. Additionally, Capture/Compare Module 5 offers watchdog timer (WDT) capabilities. Following a system reset,
Module 5 is configured and enabled in WDT mode. The PCA Capture/Compare Module I/O and External
Clock Input may be routed to Port I/O via the Digital Crossbar.
SYSCLK /12
SYSCLK /4
Timer 0 Overflow
ECI
PCA
CLOCK
MUX
16 -Bit Counter/Timer
SYSCLK
External Clock /8
Capture/ Compare
Module 0
Capture/ Compare
Module 1
Capture/ Compare
Module 2
Capture/ Compare
Module 3
Figure 1.6. PCA Block Diagram
22
Rev. 1.3
Capture/ Compare
Module5 / WDT
CEX5
Port I/O
CEX4
CEX3
CEX2
CEX1
CEX0
ECI
Crossbar
Capture/ Compare
Module 4
C8051F93x-C8051F92x
1.5.
10-Bit SAR ADC with 16-bit Auto-Averaging Accumulator and Autonomous
Low Power Burst Mode
C8051F93x-C8051F92x devices have a 300 ksps, 10-bit successive-approximation-register (SAR) ADC
with integrated track-and-hold and programmable window detector. ADC0 also has an autonomous low
power Burst Mode which can automatically enable ADC0, capture and accumulate samples, then place
ADC0 in a low power shutdown mode without CPU intervention. It also has a 16-bit accumulator that can
automatically average the ADC results, providing an effective 11, 12, or 13 bit ADC result without any additional CPU intervention.
The ADC can sample the voltage at any of the GPIO pins (with the exception of P2.7) and has an on-chip
attenuator that allows it to measure voltages up to twice the voltage reference. Additional ADC inputs
include an on-chip temperature sensor, the VDD/DC+ supply voltage, the VBAT supply voltage, and the
internal digital supply voltage.
VDD
ADC
AD0CM1
AD0CM2
AD0CM0
100
CNVSTR Input
REF
16-Bit Accumulator
SYSCLK
AD0TM
AMP0GN
AD08BE
AD0SC0
AD0SC1
ADC0CF
AD0BUSY (W)
Timer 0 Overflow
Timer 2 Overflow
Timer 3 Overflow
ADC0LTH
ADC0H
AIN+
000
001
010
011
ADC0L
10-Bit
SAR
AD0SC2
From
AMUX0
Start
Conversion
Burst Mode Logic
AD0SC3
ADC0PWR
AD0SC4
ADC0TK
AD0WINT
AD0INT
AD0BUSY
BURSTEN
AD0EN
ADC0CN
AD0WINT
ADC0LTL
32
Window
Compare
Logic
ADC0GTH ADC0GTL
Figure 1.7. ADC0 Functional Block Diagram
Rev. 1.3
23
C8051F93x-C8051F92x
AD0MX4
AD0MX3
AD0MX2
AD0MX1
AM0MX0
ADC0MX
P0.0
Programmable
Attenuator
AIN+
P2.6*
AMUX
Temp
Sensor
ADC0
Gain = 0. 5 or 1
VBAT
Digital Supply
VDD/DC+
*P1.7-P2. 6 only available as
inputs on 32- pin packages
Figure 1.8. ADC0 Multiplexer Block Diagram
1.6.
Programmable Current Reference (IREF0)
C8051F93x-C8051F92x devices include an on-chip programmable current reference (source or sink) with
two output current settings: low power mode and high current mode. The maximum current output in low
power mode is 63 µA (1 µA steps) and the maximum current output in high current mode is 504 µA (8 µA
steps).
1.7.
Comparators
C8051F93x-C8051F92x devices include two on-chip programmable voltage comparators: Comparator 0
(CPT0) which is shown in Figure 1.9; Comparator 1 (CPT1) which is shown in Figure 1.10. The two
comparators operate identically but may differ in their ability to be used as reset or wake-up sources. See
Section “18. Reset Sources” on page 184 and the Section “14. Power Management” on page 159 for
details on reset sources and low power mode wake-up sources, respectively.
The Comparator offers programmable response time and hysteresis, an analog input multiplexer, and two
outputs that are optionally available at the Port pins: a synchronous “latched” output (CP0, CP1), or an
asynchronous “raw” output (CP0A, CP1A). The asynchronous CP0A signal is available even when the
system clock is not active. This allows the Comparator to operate and generate an output when the device
is in some low power modes.
The comparator inputs may be connected to Port I/O pins or to other internal signals. Port pins may also be
used to directly sense capacitive touch switches.
24
Rev. 1.3
CPT0CN
C8051F93x-C8051F92x
CP0EN
CP0OUT
CP0RIF
CP0FIF
VDD
CP0HYP1
CP0HYP0
CP0HYN1
CP0
Interrupt
CP0HYN0
CPT0MD
Analog Input Multiplexer
CP0FIE
CP0RIE
CP0MD1
CP0MD0
Px.x
CP0
Rising-edge
CP0 +
CP0
Falling-edge
Interrupt
Logic
Px.x
CP0
+
SET
D
-
CLR
D
Q
Q
SET
CLR
Q
Q
Px.x
Crossbar
(SYNCHRONIZER)
GND
CP0 -
CP0A
(ASYNCHRONOUS)
Reset
Decision
Tree
Px.x
Figure 1.9. Comparator 0 Functional Block Diagram
CPT0CN
CP1EN
CP1OUT
CP1RIF
VDD
CP1FIF
CP1HYP1
CP1
Interrupt
CP1HYP0
CP1HYN1
CP1HYN0
CPT0MD
Analog Input Multiplexer
CP1FIE
CP1RIE
CP1MD1
CP1MD0
Px.x
CP1
Rising-edge
CP1 +
CP1
Falling-edge
Interrupt
Logic
Px.x
CP1
+
D
-
SET
CLR
Q
Q
D
SET
CLR
Q
Q
Px.x
Crossbar
(SYNCHRONIZER)
CP1 -
GND
(ASYNCHRONOUS)
CP1A
Reset
Decision
Tree
Px.x
Figure 1.10. Comparator 1 Functional Block Diagram
Rev. 1.3
25
C8051F93x-C8051F92x
2.
Ordering Information
Enhanced SPI
Timers (16-bit)
10-bit 300ksps ADC
Programmable Current Reference
Internal Voltage Reference
Temperature Sensor
Analog Comparators
Lead-free (RoHS Compliant)
Package
2
4
 24 



2

QFN-32
C8051F930-F-GQ
C8051F930-GQ*
25 64 4352

1
1
2
4
 24 



2

LQFP-32
C8051F931-F-GM
C8051F931-GM*
25 64 4352

1
1
2
4
 16 



2

QFN-24
C8051F920-F-GM
C8051F920-GM*
25 32 4352

1
1
2
4
 24 



2

QFN-32
C8051F920-F-GQ
C8051F920-GQ*
25 32 4352

1
1
2
4
 24 



2

LQFP-32
C8051F921-F-GM
C8051F921-GM*
25 32 4352

1
1
2
4
 16 



2

QFN-24
Digital Port I/Os
UART
1
Programmable Counter Array
SMBus/I2C
1
RAM (bytes)

Flash Memory (kB)
25 64 4352
MIPS (Peak)
C8051F930-F-GM
C8051F930-GM*
Ordering Part Number
SmaRTClock Real Time Clock
Table 2.1. Product Selection Guide
*Note: Not recommended for new designs.
Starting with silicon revision F, the ordering part numbers have been updated to include the silicon revision
and use this format: "C8051F930-F-GM". Older ordering part numbers of the format "C8051F930-GM" are no
longer recommended for new designs. Package marking diagrams are included as Figure 3.4, Figure 3.5,
and Figure 3.6 to help identify the silicon revision.
26
Rev. 1.3
C8051F93x-C8051F92x
3.
Pinout and Package Definitions
Table 3.1. Pin Definitions for the C8051F92x-C8051F93x
Name
Pin Numbers
‘F920/30 ‘F921/31
Type
Description
VBAT
5
5
P In
Battery Supply Voltage. Must be 0.9 to 1.8 V in single-cell
battery mode and 1.8 to 3.6 V in dual-cell battery mode.
VDD /
3
3
P In
Power Supply Voltage. Must be 1.8 to 3.6 V. This supply
voltage is not required in low power sleep mode. This
voltage must always be > VBAT.
DC+
DC– /
1
1
GND
P Out
Positive output of the dc-dc converter. In single-cell battery
mode, a 1 µF ceramic capacitor is required between DC+
and DC–. This pin can supply power to external devices
when operating in single-cell battery mode.
P In
DC-DC converter return current path. In single-cell battery
mode, this pin is typically not connected to ground.
G
In dual-cell battery mode, this pin must be connected
directly to ground.
Required Ground.
GND
2
2
G
DCEN
4
4
P In
G
RST/
6
6
C2CK
P2.7/
7
7
C2D
DC-DC Enable Pin. In single-cell battery mode, this pin
must be connected to VBAT through a 0.68 µH inductor.
In dual-cell battery mode, this pin must be connected
directly to ground.
D I/O
Device Reset. Open-drain output of internal POR or VDD
monitor. An external source can initiate a system reset by
driving this pin low for at least 15 µs. A 1 k to 5 k pullup
to VDD is recommended. See Reset Sources Section for a
complete description.
D I/O
Clock signal for the C2 Debug Interface.
D I/O
Port 2.7. This pin can only be used as GPIO. The Crossbar
cannot route signals to this pin and it cannot be configured
as an analog input. See Port I/O Section for a complete
description.
D I/O
Bi-directional data signal for the C2 Debug Interface.
XTAL3
10
9
A In
SmaRTClock Oscillator Crystal Input.
See Section 20 for a complete description.
XTAL4
9
8
A Out
SmaRTClock Oscillator Crystal Output.
See Section 20 for a complete description.
*Note: Available only on the C8051F920/30.
Rev. 1.3
27
C8051F93x-C8051F92x
Table 3.1. Pin Definitions for the C8051F92x-C8051F93x (Continued)
Name
P0.0
Pin Numbers
‘F920/30 ‘F921/31
32
24
VREF
P0.1
31
23
22
XTAL1
P0.3
21
XTAL2
A Out
A In
28
20
TX
P0.5
19
RX
P0.6
18
CNVSTR
P0.7
IREF0
17
UART RX Pin. See Port I/O Section.
D I/O or Port 0.6. See Port I/O Section for a complete description.
A In
D In
25
UART TX Pin. See Port I/O Section.
D I/O or Port 0.5. See Port I/O Section for a complete description.
A In
D In
26
External Clock Output. This pin is the excitation driver for an
external crystal or resonator.
External Clock Input. This pin is the external clock input in
external CMOS clock mode.
External Clock Input. This pin is the external clock input in
capacitor or RC oscillator configurations.
See Oscillator Section for complete details.
D I/O or Port 0.4. See Port I/O Section for a complete description.
A In
D Out
27
External Clock Input. This pin is the external oscillator
return for a crystal or resonator. See Oscillator Section.
D I/O or Port 0.3. See Port I/O Section for a complete description.
A In
D In
P0.4
Optional Analog Ground. See ADC0 Section for details.
D I/O or Port 0.2. See Port I/O Section for a complete description.
A In
A In
29
External VREF Input.
Internal VREF Output. External VREF decoupling capacitors
are recommended. See ADC0 Section for details.
D I/O or Port 0.1. See Port I/O Section for a complete description.
A In
G
30
Description
D I/O or Port 0.0. See Port I/O Section for a complete description.
A In
A In
A Out
AGND
P0.2
Type
External Convert Start Input for ADC0. See ADC0 section
for a complete description.
D I/O or Port 0.7. See Port I/O Section for a complete description.
A In
A Out IREF0 Output. See IREF Section for complete description.
*Note: Available only on the C8051F920/30.
28
Rev. 1.3
C8051F93x-C8051F92x
Table 3.1. Pin Definitions for the C8051F92x-C8051F93x (Continued)
Name
P1.0
Pin Numbers
‘F920/30 ‘F921/31
24
16
AD0*
P1.1
23
15
14
AD2*
P1.3
13
AD3*
P1.4
12
AD4*
P1.5
11
AD5*
Address/Data 3.
D I/O or Port 1.4. See Port I/O Section for a complete description.
A In
D I/O
19
Address/Data 2.
D I/O or Port 1.3. See Port I/O Section for a complete description.
A In
May also be used as NSS for SPI1.
D I/O
20
Address/Data 1.
D I/O or Port 1.2. See Port I/O Section for a complete description.
A In
May also be used as MOSI for SPI1.
D I/O
21
Address/Data 0.
D I/O or Port 1.1. See Port I/O Section for a complete description.
A In
May also be used as MISO for SPI1.
D I/O
22
Description
D I/O or Port 1.0. See Port I/O Section for a complete description.
May also be used as SCK for SPI1.
A In
D I/O
AD1*
P1.2
Type
Address/Data 4.
D I/O or Port 1.5. See Port I/O Section for a complete description.
A In
D I/O
Address/Data 5.
P1.6
18
AD6*
P1.7*
AD8*
D I/O or Port 1.6. See Port I/O Section for a complete description.
A In
D I/O
17
AD7*
P2.0*
10
D I/O or Port 1.7. See Port I/O Section for a complete description.
A In
D I/O
16
Address/Data 6.
Address/Data 7.
D I/O or Port 2.0. See Port I/O Section for a complete description.
A In
D I/O
Address/Data 8.
*Note: Available only on the C8051F920/30.
Rev. 1.3
29
C8051F93x-C8051F92x
Table 3.1. Pin Definitions for the C8051F92x-C8051F93x (Continued)
Name
P2.1*
Pin Numbers
‘F920/30 ‘F921/31
15
AD9*
P2.2*
14
AD11*
P2.4*
ALE*
P2.5*
RD*
P2.6*
WR*
Address Latch Enable.
D I/O or Port 2.5. See Port I/O Section for a complete description.
A In
DO
8
Address/Data 11.
D I/O or Port 2.4. See Port I/O Section for a complete description.
A In
DO
11
Address/Data 10.
D I/O or Port 2.3. See Port I/O Section for a complete description.
A In
D I/O
12
Address/Data 9.
D I/O or Port 2.2. See Port I/O Section for a complete description.
A In
D I/O
13
Description
D I/O or Port 2.1. See Port I/O Section for a complete description.
A In
D I/O
AD10*
P2.3*
Type
Read Strobe.
D I/O or Port 2.6. See Port I/O Section for a complete description.
A In
DO
Write Strobe.
*Note: Available only on the C8051F920/30.
30
Rev. 1.3
P0.0/VREF
P0.1/AGND
P0.2/XTAL1
P0.3/XTAL2
P0.4/TX
P0.5/RX
P0.6/CNVSTR
P0.7/IREF0
32
31
30
29
28
27
26
25
C8051F93x-C8051F92x
GND/DC-
1
24
P1.0/AD0
GND
2
23
P1.1/AD1
VDD/DC+
3
22
P1.2/AD2
DCEN
4
21
P1.3/AD3
VBAT
5
20
P1.4/AD4
RST/C2CK
6
19
P1.5/AD5
P2.7/C2D
7
18
P1.6/AD6
P2.6/WR
8
17
P1.7/AD7
C8051F930/20-GM
Top View
9
10
11
12
13
14
15
16
XTAL4
XTAL3
P2.5/RD
P2.4/ALE
P2.3/A11
P2.2/A10
P2.1/A9
P2.0/A8
GND (optional)
Figure 3.1. QFN-32 Pinout Diagram (Top View)
Rev. 1.3
31
P0.0/VREF
P0.1/AGND
P0.2/XTAL1
P0.3/XTAL2
P0.4/TX
P0.5/RX
24
23
22
21
20
19
C8051F93x-C8051F92x
GND/DC-
1
18
P0.6/CNVSTR
GND
2
17
P0.7/IREF0
VDD/DC+
3
16
P1.0
DCEN
4
15
P1.1
VBAT
5
14
P1.2
RST/C2CK
6
13
P1.3
C8051F931/21-GM
Top View
7
8
9
10
11
12
P2.7/C2D
XTAL4
XTAL3
P1.6
P1.5
P1.4
GND (optional)
Figure 3.2. QFN-24 Pinout Diagram (Top View)
32
Rev. 1.3
P0.0 / VREF
P0.1 / AGND
P0.2 / XTAL1
P0.3 / XTAL2
P0.4 / TX
P0.5 / RX
P0.6 / CNVSTR
P0.7 / IREF0
32
31
30
29
28
27
26
25
C8051F93x-C8051F92x
GND / DC-
1
24
P1.0 / AD0
GND
2
23
P1.1 / AD1
VDD / DC+
3
22
P1.2 / AD2
DCEN
4
21
P1.3 / AD3
VBAT
5
20
P1.4 / AD4
RST / C2CK
6
19
P1.5 / AD5
P2.7 / C2D
7
18
P1.6 / AD6
P2.6 / WR
8
17
P1.7 / AD7
9
10
11
12
13
14
15
16
XTAL4
XTAL3
P2.5 / RD
P2.4 / ALE
P2.3 / A11
P2.2 / A10
P2.1 / A9
P2.0 / A8
C8051F930/20-GQ
Top View
Figure 3.3. LQFP-32 Pinout Diagram (Top View)
Rev. 1.3
33
C8051F93x-C8051F92x
First character of the
trace code identifies the
silicon revision
Figure 3.4. QFN-32 Package Marking Diagram
34
Rev. 1.3
C8051F93x-C8051F92x
First character of the
trace code identifies the
silicon revision
Figure 3.5. QFN-24 Package Marking Diagram
Rev. 1.3
35
C8051F93x-C8051F92x
First character of the
trace code identifies the
silicon revision
Figure 3.6. LQFP-32 Package Marking Diagram
36
Rev. 1.3
C8051F93x-C8051F92x
Figure 3.7. QFN-32 Package Drawing
Table 3.2. QFN-32 Package Dimensions
Dimension
Min
Typ
Max
Dimension
Min
Typ
Max
A
A1
b
D
D2
e
E
0.80
0.00
0.18
0.9
0.02
0.25
5.00 BSC
3.30
0.50 BSC
5.00 BSC
1.00
0.05
0.30
E2
L
L1
aaa
bbb
ddd
eee
3.20
0.30
0.00
—
—
—
—
3.30
0.40
—
—
—
—
—
3.40
0.50
0.15
0.15
0.10
0.05
0.08
3.20
3.40
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to the JEDEC Solid State Outline MO-220, variation VHHD except
for custom features D2, E2, and L which are toleranced per supplier designation.
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small
Body Components.
Rev. 1.3
37
C8051F93x-C8051F92x
Figure 3.8. Typical QFN-32 Landing Diagram
38
Rev. 1.3
C8051F93x-C8051F92x
Table 3.3. PCB Land Pattern
Dimension
MIN
MAX
C1
4.80
4.90
C2
4.80
4.90
E
0.50 BSC
X1
0.20
0.30
X2
3.20
3.40
Y1
0.75
0.85
Y2
3.20
3.40
Notes:
General
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. This Land Pattern Design is based on the IPC-7351 guidelines.
Solder Mask Design
1. All metal pads are to be non-solder mask defined (NSMD). Clearance between the
solder mask and the metal pad is to be 60 µm minimum, all the way around the pad.
Stencil Design
1. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should
be used to assure good solder paste release.
2. The stencil thickness should be 0.125 mm (5 mils).
3. The ratio of stencil aperture to land pad size should be 1:1 for all perimeter pads.
4. A 3 x 3 array of 1.0 mm square openings on 1.2 mm pitch should be used for the
center ground pad.
Card Assembly
1. A No-Clean, Type-3 solder paste is recommended.
2. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification
for Small Body Components.
Rev. 1.3
39
C8051F93x-C8051F92x
Figure 3.9. QFN-24 Package Drawing
Table 3.4. QFN-24 Package Dimensions
Dimension
Min
Typ
Max
Dimension
Min
Typ
Max
A
0.70
0.75
0.80
L
0.30
0.40
0.50
A1
0.00
0.02
0.05
L1
0.00
—
0.15
b
0.18
0.25
0.30
aaa
—
—
0.15
bbb
—
—
0.10
ddd
—
—
0.05
D
D2
4.00 BSC
2.55
2.70
2.80
e
0.50 BSC
eee
—
—
0.08
E
4.00 BSC
Z
—
0.24
—
Y
—
0.18
—
E2
2.55
2.70
2.80
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to the JEDEC Solid State Outline MO-220, variation WGGD except
for custom features D2, E2, Z, Y, and L which are toleranced per supplier designation.
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small
Body Components.
40
Rev. 1.3
C8051F93x-C8051F92x
Figure 3.10. Typical QFN-24 Landing Diagram
Rev. 1.3
41
C8051F93x-C8051F92x
Table 3.5. PCB Land Pattern
Dimension
MIN
MAX
C1
3.90
4.00
C2
3.90
4.00
E
0.50 BSC
X1
0.20
0.30
X2
2.70
2.80
Y1
0.65
0.75
Y2
2.70
2.80
Notes:
General
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. This Land Pattern Design is based on the IPC-7351 guidelines.
Solder Mask Design
1. All metal pads are to be non-solder mask defined (NSMD). Clearance
between the solder mask and the metal pad is to be 60 µm minimum, all
the way around the pad.
Stencil Design
1. A stainless steel, laser-cut and electro-polished stencil with trapezoidal
walls should be used to assure good solder paste release.
2. The stencil thickness should be 0.125 mm (5 mils).
3. The ratio of stencil aperture to land pad size should be 1:1 for all
perimeter pads.
4. A 2 x 2 array of 1.0 x 1.0 mm square openings on 1.30 mm pitch should
be used for the center ground pad.
Card Assembly
1. A No-Clean, Type-3 solder paste is recommended.
2. The recommended card reflow profile is per the JEDEC/IPC J-STD-020
specification for Small Body Components.
42
Rev. 1.3
C8051F93x-C8051F92x
Figure 3.11. LQFP-32 Package Diagram
Table 3.6. LQFP-32 Package Dimensions
Dimension
Min
Typ
Max
Dimension
Min
A
—
—
1.60
E
9.00 BSC
A1
0.05
—
0.15
E1
7.00 BSC
A2
1.35
1.40
1.45
L
b
0.30
0.37
0.45
aaa
0.20
c
0.09
—
0.20
bbb
0.20
0.45
Typ
0.60
D
9.00 BSC.
ccc
0.10
D1
7.00 BSC
ddd
0.20
e
0.80 BSC

0º
3.5º
Max
0.75
7º
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to JEDEC outline MS-026, variation BBA.
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body
Components.
Rev. 1.3
43
C8051F93x-C8051F92x
Figure 3.12. Typical LQFP-32 Landing Diagram
Table 3.7. PCB Land Pattern
Dimension
MIN
MAX
C1
8.40
8.50
C2
8.40
8.50
E
0.80 BSC
X1
0.40
0.50
Y1
1.25
1.35
Notes:
General
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. This Land Pattern Design is based on the IPC-7351 guidelines.
Solder Mask Design
1. All metal pads are to be non-solder mask defined (NSMD). Clearance between
the solder mask and the metal pad is to be 60 µm minimum, all the way around
the pad.
Stencil Design
1. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls
should be used to assure good solder paste release.
2. The stencil thickness should be 0.125 mm (5 mils).
3. The ratio of stencil aperture to land pad size should be 1:1 for all perimeter pads.
Card Assembly
1. A No-Clean, Type-3 solder paste is recommended.
2. The recommended card reflow profile is per the JEDEC/IPC J-STD-020
specification for Small Body Components.
44
Rev. 1.3
C8051F93x-C8051F92x
4.
Electrical Characteristics
Throughout the Electrical Characteristics chapter, “VDD” refers to the VDD/DC+ Supply Voltage.
4.1.
Absolute Maximum Specifications
Table 4.1. Absolute Maximum Ratings
Parameter
Conditions
Min
Typ
Max
Units
Ambient temperature under bias
–55
—
125
°C
Storage Temperature
–65
—
150
°C
Voltage on any Port I/O Pin or
RST with respect to GND
VDD > 2.2 V
VDD < 2.2 V
–0.3
–0.3
—
—
5.8
VDD + 3.6
V
Voltage on VBAT with respect to
GND
One-Cell Mode
Two-Cell Mode
–0.3
–0.3
—
—
2.0
4.0
V
Voltage on VDD/DC+ with respect
to GND
–0.3
—
4.0
V
Maximum Total current through
VBAT, DCEN, VDD/DC+ or GND
—
—
500
mA
Maximum output current sunk by
RST or any Port pin
—
—
100
mA
Maximum total current through all
Port pins
—
—
200
mA
DC-DC Converter Output Power
—
—
110
mW
Note: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.
This is a stress rating only and functional operation of the devices at those or any other conditions above those
indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
Rev. 1.3
45
C8051F93x-C8051F92x
4.2.
Electrical Characteristics
Table 4.2. Global Electrical Characteristics
–40 to +85 °C, 25 MHz system clock unless otherwise specified. See "AN358: Optimizing Low Power Operation of the
‘F9xx" for details on how to achieve the supply current specifications listed in this table.
Parameter
Conditions
Min
Typ
Max
Units
Battery Supply Voltage (VBAT) One-Cell Mode
Two-Cell Mode
0.9
1.8
1.2
2.4
1.8
3.6
V
Supply Voltage (VDD/DC+)
One-Cell Mode
Two-Cell Mode
1.8
1.8
1.9
2.4
3.6
3.6
V
Minimum RAM Data 
Retention Voltage1
VDD (not in Sleep Mode)
VBAT (in Sleep Mode)
—
—
1.4
0.3
—
0.5
V
SYSCLK (System Clock)2
0
—
25
MHz
TSYSH (SYSCLK High Time)
18
—
—
ns
TSYSL (SYSCLK Low Time)
18
—
—
ns
Specified Operating 
Temperature Range
–40
—
+85
°C
Digital Supply Current—CPU Active (Normal Mode, fetching instructions from Flash)
VDD = 1.8–3.6 V, F = 24.5 MHz 
(includes precision oscillator current)
—
4.1
5.0
mA
VDD = 1.8–3.6 V, F = 20 MHz
(includes low power oscillator current)
—
3.5
—
mA
VDD = 1.8 V, F = 1 MHz
VDD = 3.6 V, F = 1 MHz
(includes external oscillator/GPIO current)
—
—
295
365
—
—
µA
µA
VDD = 1.8–3.6 V, F = 32.768 kHz 
(includes SmaRTClock oscillator current)
—
90
—
µA
IDD Frequency Sensitivity3, 5, 6 VDD = 1.8–3.6 V, T = 25 °C, F < 10 MHz
(Flash oneshot active, see Section 13.6)
—
226
—
µA/MHz
—
120
—
µA/MHz
IDD 3, 4, 5, 6
VDD = 1.8–3.6 V, T = 25 °C, F > 10 MHz
(Flash oneshot bypassed, see Section 13.6)
Digital Supply Current—CPU Inactive (Idle Mode, not fetching instructions from Flash)
IDD4, 6, 7
IDD Frequency Sensitivity1,6,7
46
VDD = 1.8–3.6 V, F = 24.5 MHz 
(includes precision oscillator current)
—
2.5
3.0
mA
VDD = 1.8–3.6 V, F = 20 MHz
(includes low power oscillator current)
—
1.8
—
mA
VDD = 1.8 V, F = 1 MHz
VDD = 3.6 V, F = 1 MHz
(includes external oscillator/GPIO current)
—
—
165
235
—
—
µA
µA
VDD = 1.8–3.6 V, F = 32.768 kHz (includes
SmaRTClock oscillator current)
—
84
—
µA
VDD = 1.8–3.6 V, T = 25 °C
—
95
—
µA/MHz
Rev. 1.3
C8051F93x-C8051F92x
Table 4.2. Global Electrical Characteristics (Continued)
–40 to +85 °C, 25 MHz system clock unless otherwise specified. See "AN358: Optimizing Low Power Operation of the
‘F9xx" for details on how to achieve the supply current specifications listed in this table.
Parameter
Conditions
Min
Typ
Max
Units
Digital Supply Current—Suspend and Sleep Mode
Digital Supply Current6 
(Suspend Mode)
VDD = 1.8–3.6 V, two-cell mode
—
77
—
µA
Digital Supply Current
(Sleep Mode, SmaRTClock
running)
1.8 V, T = 25 °C
3.0 V, T = 25 °C
3.6 V, T = 25 °C
1.8 V, T = 85 °C
3.0 V, T = 85 °C
3.6 V, T = 85 °C
(includes SmaRTClock oscillator and VBAT
Supply Monitor)
—
—
—
—
—
—
0.60
0.75
0.85
1.30
1.60
1.90
—
—
—
—
—
—
µA
µA
µA
µA
µA
µA
Digital Supply Current
(Sleep Mode)
1.8 V, T = 25 °C
3.0 V, T = 25 °C
3.6 V, T = 25 °C
1.8 V, T = 85 °C
3.0 V, T = 85 °C
3.6 V, T = 85 °C
(includes VBAT supply monitor)
—
—
—
—
—
—
0.05
0.08
0.12
0.75
0.90
1.20
—
—
—
—
—
—
µA
µA
µA
µA
µA
µA
Notes:
1. Based on device characterization data; Not production tested.
2. SYSCLK must be at least 32 kHz to enable debugging.
3. Digital Supply Current depends upon the particular code being executed. The values in this table are obtained with
the CPU executing an “sjmp $” loop, which is the compiled form of a while(1) loop in C. One iteration requires 3
CPU clock cycles, and the Flash memory is read on each cycle. The supply current will vary slightly based on the
physical location of the sjmp instruction and the number of Flash address lines that toggle as a result. In the worst
case, current can increase by up to 30% if the sjmp loop straddles a 128-byte Flash address boundary (e.g.,
0x007F to 0x0080). Real-world code with larger loops and longer linear sequences will have few transitions across
the 128-byte address boundaries.
4. Includes oscillator and regulator supply current.
5. IDD can be estimated for frequencies <10 MHz by simply multiplying the frequency of interest by the frequency
sensitivity number for that range, then adding an offset of 90 µA. When using these numbers to estimate IDD for
>10 MHz, the estimate should be the current at 25 MHz minus the difference in current indicated by the frequency
sensitivity number. For example: VDD = 3.0 V; F = 20 MHz, IDD = 4.1 mA – (25 MHz –
20 MHz) x 0.120 mA/MHz = 3.5 mA.
6. The supply current specifications in Table 4.2 are for two cell mode. The VBAT current in one-cell mode can be
estimated using the following equation:
Supply Voltage  Supply Current (two-cell mode)
VBAT Current (one-cell mode) = ----------------------------------------------------------------------------------------------------------------------------------DC-DC Converter Efficiency  VBAT Voltage
The VBAT Voltage is the voltage at the VBAT pin, typically 0.9 to 1.8 V.
The Supply Current (two-cell mode) is the data sheet specification for supply current.
The Supply Voltage is the voltage at the VDD/DC+ pin, typically 1.8 to 3.3 V (default = 1.9 V).
The DC-DC Converter Efficiency can be estimated using Figure 4.3–Figure 4.5.
7. Idle IDD can be estimated by taking the current at 25 MHz minus the difference in current indicated by the
frequency sensitivity number. For example: VDD = 3.0 V; F = 5 MHz, Idle IDD = 2.5 mA – (25 MHz –
5 MHz) x 0.095 mA/MHz = 0.6 mA.
Rev. 1.3
47
C8051F93x-C8051F92x
4200
4100
F < 10 MHz
Oneshot Enabled
4000
3900
F > 10 MHz
Oneshot Bypassed
3800
3700
3600
3500
3400
< 170 µA/MHz
3300
3200
3100
3000
2900
200 µA/MHz
2800
2700
2600
215 µA/MHz
Supply Current (uA)
2500
2400
2300
2200
2100
2000
1900
1800
1700
1600
1500
1400
240 µA/MHz
1300
1200
1100
1000
900
800
250 µA/MHz
700
600
500
400
300
300 µA/MHz
200
100
0
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Frequency (MHz)
Figure 4.1. Active Mode Current (External CMOS Clock)
48
Rev. 1.3
21
22
23
24
25
C8051F93x-C8051F92x
4200
4100
4000
3900
3800
3700
3600
3500
3400
3300
3200
3100
3000
2900
2800
2700
2600
Supply Current (uA)
2500
2400
2300
2200
2100
2000
1900
1800
1700
1600
1500
1400
1300
1200
1100
1000
900
800
700
600
500
400
300
200
100
0
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
Frequency (MHz)
Figure 4.2. Idle Mode Current (External CMOS Clock)
Rev. 1.3
49
C8051F93x-C8051F92x
6:6(/ 6:6(/ Efficiency (%)
9%$7 9
9%$7 9
9%$7 9
9%$7 9
9%$7 9
9%$7 9
9%$7 9
X+,QGXFWRUSDFNDJH(65 2KPV
9'''& 90LQLPXP3XOVH:LGWK QV 3XOVH6NLSSLQJ'LVDEOHG
1RWH(IILFLHQF\DWKLJKFXUUHQWVPD\EHLPSURYHGE\FKRRVLQJDQ
LQGXFWRUZLWKDORZHU(65
Load Current (mA)
Figure 4.3. Typical DC-DC Converter Efficiency (High Current, VDD/DC+ = 2 V)
50
Rev. 1.3
C8051F93x-C8051F92x
6:6(/ 6:6(/ 9%$7 9
Efficiency (%)
9%$7 9
9%$7 9
9%$7 9
9%$7 9
9%$7 9
9%$7 9
X+,QGXFWRUSDFNDJH(65 2KPV
9'''& 90LQLPXP3XOVH:LGWK QV
3XOVH6NLSSLQJ'LVDEOHG
1RWH(IILFLHQF\DWKLJKFXUUHQWVPD\EHLPSURYHGE\
FKRRVLQJDQLQGXFWRUZLWKDORZHU(65
Load current (mA)
Figure 4.4. Typical DC-DC Converter Efficiency (High Current, VDD/DC+ = 3 V)
Rev. 1.3
51
C8051F93x-C8051F92x
9%$7 9
9%$7 9
Efficiency (%)
9%$7 9
9%$7 9
9%$7 9
9%$7 9
9%$7 9
X+,QGXFWRUSDFNDJH(65 2KPV
6:6(/ 9'''& 90LQLPXP3XOVH:LGWK QV
Load current (mA)
Figure 4.5. Typical DC-DC Converter Efficiency (Low Current, VDD/DC+ = 2 V)
52
Rev. 1.3
C8051F93x-C8051F92x
X+,QGXFWRUSDFNDJH(65 2KPV
6:6(/ 9'''& 9/RDG&XUUHQW X$
0LQ3XOVH:LGWKQV
0LQ3XOVH:LGWKQV
0LQ3XOVH:LGWKQV
0LQ3XOVH:LGWKQV
9%$7&XUUHQW X$
9%$7 9
Figure 4.6. Typical One-Cell Suspend Mode Current
Rev. 1.3
53
C8051F93x-C8051F92x
Table 4.3. Port I/O DC Electrical Characteristics
VDD = 1.8 to 3.6 V, –40 to +85 °C unless otherwise specified.
Parameters
Conditions
Min
Typ
Max
IOH = –3 mA, Port I/O push-pull
VDD – 0.7
—
—
IOH = –10 µA, Port I/O push-pull
VDD – 0.1
—
—
Units
Output High Voltage High Drive Strength, PnDRV.n = 1
IOH = –10 mA, Port I/O push-pull
See Chart
V
Low Drive Strength, PnDRV.n = 0
IOH = –1 mA, Port I/O push-pull
VDD – 0.7
—
—
IOH = –10 µA, Port I/O push-pull
VDD – 0.1
—
—
—
See Chart
—
IOL = 8.5 mA
—
—
0.6
IOL = 10 µA
—
—
0.1
IOL = 25 mA
—
See Chart
—
IOH = –3 mA, Port I/O push-pull
Output Low Voltage High Drive Strength, PnDRV.n = 1
V
Low Drive Strength, PnDRV.n = 0
Input High Voltage
Input Low Voltage
Input Leakage 
Current
54
IOL = 1.4 mA
—
—
0.6
IOL = 10 µA
—
—
0.1
IOL = 4 mA
—
See Chart
—
VDD = 2.0 to 3.6 V
VDD – 0.6
—
—
V
VDD = 0.9 to 2.0 V
0.7 x VDD
—
—
V
VDD = 2.0 to 3.6 V
—
—
0.6
V
VDD = 0.9 to 2.0 V
—
—
0.3 x VDD
V
Weak Pullup Off
—
—
±1
Weak Pullup On, VIN = 0 V, VDD = 1.8 V
—
4
—
Weak Pullup On, Vin = 0 V, VDD = 3.6 V
—
20
30
Rev. 1.3
µA
C8051F93x-C8051F92x
Typical VOH (High Drive Mode)
Voltage
3.6
3.3
VDD = 3.6V
3
VDD = 3.0V
2.7
VDD = 2.4V
2.4
VDD = 1.8V
2.1
1.8
1.5
1.2
0.9
0
5
10
15
20
25
30
35
40
45
50
Load Current (mA)
Typical VOH (Low Drive Mode)
Voltage
3.6
3.3
VDD = 3.6V
3
VDD = 3.0V
2.7
VDD = 2.4V
2.4
VDD = 1.8V
2.1
1.8
1.5
1.2
0.9
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
Load Current (mA)
Figure 4.7. Typical VOH Curves, 1.8–3.6 V
Rev. 1.3
55
C8051F93x-C8051F92x
Typical VOH (High Drive Mode)
1.8
VDD = 1.8V
1.7
1.6
VDD = 1.5V
1.5
1.4
VDD = 1.2V
Voltage
1.3
VDD = 0.9V
1.2
1.1
1
0.9
0.8
0.7
0.6
0.5
0
1
2
3
4
5
6
7
8
9
10
11
12
Load Current (mA)
Typical VOH (Low Drive Mode)
1.8
1.7
VDD = 1.8V
1.6
VDD = 1.5V
1.5
1.4
VDD = 1.2V
Voltage
1.3
1.2
VDD = 0.9V
1.1
1
0.9
0.8
0.7
0.6
0.5
0
1
2
3
Load Current (mA)
Figure 4.8. Typical VOH Curves, 0.9–1.8 V
56
Rev. 1.3
C8051F93x-C8051F92x
Typical VOL (High Drive Mode)
1.8
VDD = 3.6V
1.5
VDD = 3.0V
Voltage
1.2
VDD = 2.4V
VDD = 1.8V
0.9
0.6
0.3
0
-80
-70
-60
-50
-40
-30
-20
-10
0
Load Current (mA)
Typical VOL (Low Drive Mode)
1.8
VDD = 3.6V
1.5
VDD = 3.0V
Voltage
1.2
VDD = 2.4V
VDD = 1.8V
0.9
0.6
0.3
0
-10
-9
-8
-7
-6
-5
-4
-3
-2
-1
0
Load Current (mA)
Figure 4.9. Typical VOL Curves, 1.8–3.6 V
Rev. 1.3
57
C8051F93x-C8051F92x
Typical VOL (High Drive Mode)
0.5
VDD = 1.8V
Voltage
0.4
VDD = 1.5V
VDD = 1.2V
0.3
VDD = 0.9V
0.2
0.1
0
-5
-4
-3
-2
-1
0
Load Current (mA)
Typical VOL (Low Drive Mode)
0.5
Voltage
0.4
0.3
VDD = 1.8V
0.2
VDD = 1.5V
VDD = 1.2V
0.1
VDD = 0.9V
0
-3
-2
-1
0
Load Current (mA)
Figure 4.10. Typical VOL Curves, 0.9–1.8 V
58
Rev. 1.3
C8051F93x-C8051F92x
Table 4.4. Reset Electrical Characteristics
VDD = 1.8 to 3.6 V, –40 to +85 °C unless otherwise specified.
Parameter
Conditions
Min
Typ
Max
Units
—
—
0.6
V
RST Output Low Voltage
IOL = 1.4 mA,
RST Input High Voltage
VDD = 2.0 to 3.6 V
VDD – 0.6
—
—
V
VDD = 0.9 to 2.0 V
0.7 x VDD
—
—
V
VDD = 2.0 to 3.6 V
—
—
0.6
V
VDD = 0.9 to 2.0 V
—
—
0.3 x VDD
V
RST Input Pullup Current
RST = 0.0 V, VDD = 1.8 V
RST = 0.0 V, VDD = 3.6 V
—
4
—
—
20
30
VDD/DC+ Monitor Threshold (VRST)
Early Warning
Reset Trigger
(all power modes except Sleep)
1.8
1.85
1.9
1.7
1.75
1.8
VBAT Ramp Time for
Power On
One-cell Mode: VBAT Ramp 0–0.9 V
Two-cell Mode: VBAT Ramp 0–1.8 V
—
—
3
VBAT Monitor Threshold
(VPOR)
Initial Power-On (VBAT Rising)
Brownout Condition (VBAT Falling)
Recovery from Brownout (VBAT Rising)
—
0.75
—
0.7
0.8
0.9
—
0.95
—
Missing Clock Detector
Timeout
Time from last system clock rising edge
to reset initiation
100
650
1000
µs
Minimum System Clock w/
Missing Clock Detector
Enabled
System clock frequency which triggers
a missing clock detector timeout
—
7
10
kHz
Reset Time Delay
Delay between release of any reset
source and code 
execution at location 0x0000
—
10
—
µs
Minimum RST Low Time to
Generate a System Reset
15
—
—
µs
VDD Monitor Turn-on Time
—
300
—
ns
VDD Monitor Supply 
Current
—
7
—
µA
RST Input Low Voltage
Rev. 1.3
µA
V
ms
V
59
C8051F93x-C8051F92x
Table 4.5. Power Management Electrical Specifications
VDD = 1.8 to 3.6 V, –40 to +85 °C unless otherwise specified.
Parameter
Conditions
Min
Typ
Max
Units
Idle Mode Wake-up Time
2
—
3
SYSCLKs
Suspend Mode Wake-up Time Low power oscillator
—
400
—
ns
Precision oscillator
—
1.3
—
µs
Two-cell mode
—
2
—
µs
One-cell mode
—
10
—
µs
Sleep Mode Wake-up Time
Table 4.6. Flash Electrical Characteristics
VDD = 1.8 to 3.6 V, –40 to +85 °C unless otherwise specified.
Parameter
Flash Size
Conditions
C8051F930/1
C8051F920/1
Min
65536*
32768
1024
Typ
—
—
—
Max
—
—
1024
Endurance
1k
30k
—
Erase Cycle Time
Write Cycle Time
28
57
32
64
36
71
Scratchpad Size
Units
bytes
bytes
bytes
Erase/Write
Cycles
ms
µs
*Note: 1024 bytes at addresses 0xFC00 to 0xFFFF are reserved.
Table 4.7. Internal Precision Oscillator Electrical Characteristics
VDD = 1.8 to 3.6 V; TA = –40 to +85 °C unless otherwise specified; Using factory-calibrated settings.
Parameter
Oscillator Frequency
Oscillator Supply Current 
(from VDD)
Conditions
Min
Typ
Max
Units
–40 to +85 °C, 
VDD = 1.8–3.6 V
24
24.5
25
MHz
25 °C; includes bias current
of 90–100 µA
—
300*
—
µA
*Note: Does not include clock divider or clock tree supply current.
Table 4.8. Internal Low-Power Oscillator Electrical Characteristics
VDD = 1.8 to 3.6 V; TA = –40 to +85 °C unless otherwise specified; Using factory-calibrated settings.
Parameter
Oscillator Frequency
Oscillator Supply Current 
(from VDD)
Conditions
–40 to +85 °C, 
VDD = 1.8–3.6 V
25 °C
No separate bias current
required.
*Note: Does not include clock divider or clock tree supply current.
60
Rev. 1.3
Min
Typ
Max
Units
18
20
22
MHz
—
100*
—
µA
C8051F93x-C8051F92x
Table 4.9. ADC0 Electrical Characteristics
VDD = 1.8 to 3.6V V, VREF = 1.65 V (REFSL[1:0] = 11), –40 to +85 °C unless otherwise specified.
Parameter
Conditions
DC Accuracy
Min
Resolution
Typ
Max
10
Integral Nonlinearity
Units
bits
—
±0.5
±1
LSB
—
±0.5
±1
LSB
Offset Error
—
±<1
±2
LSB
Full Scale Error
—
±1
±2.5
LSB
Differential Nonlinearity
Guaranteed Monotonic
Dynamic performance (10 kHz sine-wave single-ended input, 1 dB below Full Scale, 300 ksps)
Signal-to-Noise Plus Distortion
54
58
—
dB
Signal-to-Distortion
—
73
—
dB
Spurious-Free Dynamic Range
—
75
—
dB
—
—
7.33
MHz
13
11
—
—
—
—
clocks
Track/Hold Acquisition Time
1.5
—
—
µs
Throughput Rate
—
—
300
ksps
0
—
VREF
V
0
—
VDD
V
—
30
28
—
pF
—
5
—
k
Conversion Rate
SAR Conversion Clock
Conversion Time in SAR Clocks
10-bit Mode
8-bit Mode
Analog Inputs
ADC Input Voltage Range
Single Ended (AIN+ – GND)
Absolute Pin Voltage with respect
Single Ended
to GND
Sampling Capacitance
1x Gain
0.5x Gain
Input Multiplexer Impedance
Power Specifications
Power Supply Current 
(VDD supplied to ADC0)
Conversion Mode (300 ksps)
Tracking Mode (0 ksps)
—
—
800
680
—
—
µA
Power Supply Rejection
Internal High Speed VREF
External VREF
—
—
67
74
—
—
dB
Rev. 1.3
61
C8051F93x-C8051F92x
Table 4.10. Temperature Sensor Electrical Characteristics
VDD = 1.8 to 3.6V V, –40 to +85 °C unless otherwise specified.
Parameter
Conditions
Min
Typ
Max
Units
Linearity
—
±1
—
°C
Slope
—
3.40
—
mV/°C
Slope Error*
—
40
—
µV/°C
Offset
Temp = 25 °C
—
1025
—
mV
Offset Error*
Temp = 25 °C
—
18
—
mV
Temperature Sensor Turn-On
Time
—
1.7
—
µs
Supply Current
—
35
—
µA
Max
Units
1.70
V
*Note: Represents one standard deviation from the mean.
Table 4.11. Voltage Reference Electrical Characteristics
VDD = 1.8 to 3.6 V, –40 to +85 °C unless otherwise specified.
Parameter
Output Voltage
Conditions
Min
Typ
Internal High Speed Reference (REFSL[1:0] = 11)
–40 to +85 °C,
1.60
1.65
VDD = 1.8–3.6 V
VREF Turn-on Time
—
—
1.5
µs
Supply Current
—
200
—
µA
1.715
V
Output Voltage
Internal Precision Reference (REFSL[1:0] = 00, REFOE = 1)
–40 to +85 °C,
1.645
1.680
VDD = 1.8–3.6 V
VREF Short-Circuit Current
Load Regulation
VREF Turn-on Time 1
VREF Turn-on Time 2
VREF Turn-on Time 3
—
3.5
—
mA
Load = 0 to 200 µA to AGND
—
400
—
µV/µA
4.7 µF tantalum, 0.1 µF ceramic
bypass, settling to 0.5 LSB
0.1 µF ceramic bypass, settling to
0.5 LSB
—
15
—
ms
—
300
—
µs
no bypass cap, settling to 0.5 LSB
—
25
—
µs
—
15
—
µA
0
—
VDD
V
—
5.25
—
µA
Supply Current
External Reference (REFSL[1:0] = 00, REFOE = 0)
Input Voltage Range
Input Current
62
Sample Rate = 300 ksps; VREF =
3.0 V
Rev. 1.3
C8051F93x-C8051F92x
Table 4.12. IREF0 Electrical Characteristics
VDD = 1.8 to 3.6 V, –40 to +85 °C, unless otherwise specified.
Parameter
Conditions
Min
Typ
Max
Units
Static Performance
Resolution
6
0
0
0.3
0.8
—
—
—
—
VDD – 0.4
VDD – 0.8
VDD
VDD
V
Integral Nonlinearity
—
<±0.2
±1.0
LSB
Differential Nonlinearity
—
<±0.2
±1.0
LSB
Offset Error
—
<±0.1
±0.5
LSB
Low Power Mode, Source
—
—
±5
%
High Current Mode, Source
—
—
±6
%
Low Power Mode, Sink
—
—
±8
%
High Current Mode, Sink
—
—
±8
%
Low Power Mode
Sourcing 20 µA
—
<±1
±3
%
Output Settling Time to 1/2 LSB
—
300
—
ns
Startup Time
—
1
—
µs
IREF0DAT = 000001
—
10
—
µA
IREF0DAT = 111111
—
10
—
µA
IREF0DAT = 000001
—
10
—
µA
IREF0DAT = 111111
—
10
—
µA
IREF0DAT = 000001
—
1
—
µA
IREF0DAT = 111111
—
11
—
µA
IREF0DAT = 000001
—
12
—
µA
IREF0DAT = 111111
—
81
—
µA
Output Compliance Range
Full Scale Error
Absolute Current Error
Low Power Mode, Source
High Current Mode, Source
Low Power Mode, Sink
High Current Mode, Sink
bits
Dynamic Performance
Power Consumption
Net Power Supply Current 
(VDD supplied to IREF0 minus
any output source current)
Low Power Mode, Source
High Current Mode, Source
Low Power Mode, Sink
High Current Mode, Sink
Rev. 1.3
63
C8051F93x-C8051F92x
Table 4.13. Comparator Electrical Characteristics
VDD = 1.8 to 3.6 V, –40 to +85 °C unless otherwise noted.
Parameter
Conditions
Min
Typ
Max
Units
Response Time:
Mode 0, VDD = 2.4 V, VCM* = 1.2 V
CP0+ – CP0– = 100 mV
—
130
—
ns
CP0+ – CP0– = –100 mV
—
200
—
ns
CP0+ – CP0– = 100 mV
—
210
—
ns
CP0+ – CP0– = –100 mV
—
410
—
ns
CP0+ – CP0– = 100 mV
—
420
—
ns
CP0+ – CP0– = –100 mV
—
1200
—
ns
CP0+ – CP0– = 100 mV
—
1750
—
ns
CP0+ – CP0– = –100 mV
—
6200
—
ns
Common-Mode Rejection Ratio
—
1.5
4
mV/V
Inverting or Non-Inverting Input
Voltage Range
–0.25
—
VDD + 0.25
V
Input Capacitance
—
12
—
pF
Input Bias Current
—
1
—
nA
Input Offset Voltage
–7
—
+7
mV
—
0.1
—
mV/V
VDD = 3.6 V
—
0.6
—
µs
VDD = 3.0 V
—
1.0
—
µs
VDD = 2.4 V
—
1.8
—
µs
VDD = 1.8 V
—
10
—
µs
Mode 0
—
23
—
µA
Mode 1
—
8.8
—
µA
Mode 2
—
2.6
—
µA
Mode 3
—
0.4
—
µA
Response Time:
Mode 1, VDD = 2.4 V, VCM* = 1.2 V
Response Time:
Mode 2, VDD = 2.4 V, VCM* = 1.2 V
Response Time:
Mode 3, VDD = 2.4 V, VCM* = 1.2 V
Power Supply
Power Supply Rejection
Power-up Time
Supply Current at DC
*Note: Vcm is the common-mode voltage on CP0+ and CP0–.
64
Rev. 1.3
C8051F93x-C8051F92x
Table 4.13. Comparator Electrical Characteristics
VDD = 1.8 to 3.6 V, –40 to +85 °C unless otherwise noted.
Conditions
Min
Typ
Max
Units
Hysteresis 1
(CPnHYP/N1–0 = 00)
—
0
—
mV
Hysteresis 2
(CPnHYP/N1–0 = 01)
—
8.5
—
mV
Hysteresis 3
(CPnHYP/N1–0 = 10)
—
17
—
mV
Hysteresis 4
(CPnHYP/N1–0 = 11)
—
34
—
mV
Hysteresis 1
(CPnHYP/N1–0 = 00)
—
0
—
mV
Hysteresis 2
(CPnHYP/N1–0 = 01)
—
6.5
—
mV
Hysteresis 3
(CPnHYP/N1–0 = 10)
—
13
—
mV
Hysteresis 4
(CPnHYP/N1–0 = 11)
—
26
—
mV
Hysteresis 1
(CPnHYP/N1–0 = 00)
—
0
1
mV
Hysteresis 2
(CPnHYP/N1–0 = 01)
2
5
10
mV
Hysteresis 3
(CPnHYP/N1–0 = 10)
5
10
20
mV
Hysteresis 4
(CPnHYP/N1–0 = 11)
12
20
30
mV
Hysteresis 1
(CPnHYP/N1–0 = 00)
—
0
—
mV
Hysteresis 2
(CPnHYP/N1–0 = 01)
—
4.5
—
mV
Hysteresis 3
(CPnHYP/N1–0 = 10)
—
9
—
mV
Hysteresis 4
(CPnHYP/N1–0 = 11)
—
17
—
mV
Parameter
Hysteresis
Mode 0
Mode 1
Mode 2
Mode 3
*Note: Vcm is the common-mode voltage on CP0+ and CP0–.
Rev. 1.3
65
C8051F93x-C8051F92x
Table 4.14. DC-DC Converter (DC0) Electrical Characteristics
VBAT = 0.9 to 1.8 V, –40 to +85 °C unless otherwise specified.
Parameter
Conditions
Min
Typ
Max
Units
Input Voltage Range
0.9
—
1.8
V
Input Inductor Value
500
680
900
nH
Input Inductor Current
Rating
250
—
—
mA
—
—
0.5

—
—
4.7
1.0
—
—
µF
1.73
1.83
1.93
2.03
2.30
2.60
2.90
3.18
1.80
1.90
2.00
2.10
2.40
2.70
3.00
3.30
1.87
1.97
2.07
2.17
2.50
2.80
3.10
3.42
V
Inductor DC Resistance
Input Capacitor Value
Output Voltage Range
Source Impedance < 2 
Target Output = 1.8 V
Target Output = 1.9 V
Target Output = 2.0 V
Target Output = 2.1 V
Target Output = 2.4 V
Target Output = 2.7 V
Target Output = 3.0 V
Target Output = 3.3 V
Output Load Regulation
Target Output = 2.0 V, 1 to 30 mA
Target Output = 3.0 V, 1 to 20 mA
—
—
±0.3
±1
—
—
%
Output Current 
(based on output power
spec)
Target Output = 1.8 V
Target Output = 1.9 V
Target Output = 2.0 V
Target Output = 2.1 V
Target Output = 2.4 V
Target Output = 2.7 V
Target Output = 3.0 V
Target Output = 3.3 V
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
36
34
32
30
27
24
21
19
mA
—
—
65
mW
—
—
80
100
—
—
µA
Clocking Frequency
1.6
2.4
3.2
MHz
Maximum DC Load Current
During Startup
—
—
1
mA
Capacitance Connected to
Output
0.8
1.0
2.0
µF
Min
Typ
Max
Units
1.8
—
3.6
V
—
20
—
µA
Output Power
Bias Current
from VBAT supply
from VDD/DC+ supply
Table 4.15. VREG0 Electrical Characteristics
VDD = 1.8 to 3.6 V, –40 to +85 °C unless otherwise specified.
Parameter
Conditions
Input Voltage Range
Bias Current
66
Normal, Idle, Suspend, or Stop Mode
Rev. 1.3
C8051F93x-C8051F92x
5.
10-Bit SAR ADC with 16-bit Auto-Averaging Accumulator and
Autonomous Low Power Burst Mode
The ADC0 on the C8051F93x-C8051F92x is a 300 ksps, 10-bit successive-approximation-register (SAR)
ADC with integrated track-and-hold and programmable window detector. ADC0 also has an autonomous
low power Burst Mode which can automatically enable ADC0, capture and accumulate samples, then
place ADC0 in a low power shutdown mode without CPU intervention. It also has a 16-bit accumulator that
can automatically oversample and average the ADC results.
The ADC is fully configurable under software control via Special Function Registers. The ADC0 operates in
Single-ended mode and may be configured to measure various different signals using the analog multiplexer described in “5.5. ADC0 Analog Multiplexer” on page 84. The voltage reference for the ADC is
selected as described in “5.7. Voltage and Ground Reference Options” on page 89.
VDD
ADC
AD0CM1
AD0CM2
AD0CM0
AD0BUSY (W )
001
Timer 0 Overflow
010
Timer 2 Overflow
011
Timer 3 Overflow
100
CNVSTR Input
ADC0LTH
ADC0H
REF
16-Bit Accumulator
SYSCLK
AD0TM
AMP0GN
AD08BE
AD0SC0
AD0SC1
ADC0CF
000
ADC0L
10-Bit
SAR
AIN+
AD0SC2
From
AMUX0
AD0SC3
ADC0PWR
Start
Conversion
Burst Mode Logic
AD0SC4
ADC0TK
AD0WINT
AD0INT
AD0BUSY
AD0EN
BURSTEN
ADC0CN
AD0WINT
ADC0LTL
32
W indow
Compare
Logic
ADC0GTH ADC0GTL
Figure 5.1. ADC0 Functional Block Diagram
Rev. 1.3
67
C8051F93x-C8051F92x
5.1.
Output Code Formatting
The registers ADC0H and ADC0L contain the high and low bytes of the output conversion code from the
ADC at the completion of each conversion. Data can be right-justified or left-justified, depending on the
setting of the AD0SJST[2:0]. When the repeat count is set to 1, conversion codes are represented as 10bit unsigned integers. Inputs are measured from 0 to VREF x 1023/1024. Example codes are shown below
for both right-justified and left-justified data. Unused bits in the ADC0H and ADC0L registers are set to 0.
Input Voltage
VREF x 1023/1024
VREF x 512/1024
VREF x 256/1024
0
Right-Justified ADC0H:ADC0L
(AD0SJST = 000)
0x03FF
0x0200
0x0100
0x0000
Left-Justified ADC0H:ADC0L
(AD0SJST = 100)
0xFFC0
0x8000
0x4000
0x0000
When the repeat count is greater than 1, the output conversion code represents the accumulated result of
the conversions performed and is updated after the last conversion in the series is finished. Sets of 4, 8,
16, 32, or 64 consecutive samples can be accumulated and represented in unsigned integer format. The
repeat count can be selected using the AD0RPT bits in the ADC0AC register. When a repeat count higher
than 1, the ADC output must be right-justified (AD0SJST = 0xx); unused bits in the ADC0H and ADC0L
registers are set to 0. The example below shows the right-justified result for various input voltages and
repeat counts. Accumulating 2n samples is equivalent to left-shifting by n bit positions when all samples
returned from the ADC have the same value.
Input Voltage
VREF x 1023/1024
VREF x 512/1024
VREF x 511/1024
0
Repeat Count = 4
0x0FFC
0x0800
0x07FC
0x0000
Repeat Count = 16
0x3FF0
0x2000
0x1FF0
0x0000
Repeat Count = 64
0xFFC0
0x8000
0x7FC0
0x0000
The AD0SJST bits can be used to format the contents of the 16-bit accumulator. The accumulated result
can be shifted right by 1, 2, or 3 bit positions. Based on the principles of oversampling and averaging, the
effective ADC resolution increases by 1 bit each time the oversampling rate is increased by a factor of 4.
The example below shows how to increase the effective ADC resolution by 1, 2, and 3 bits to obtain an
effective ADC resolution of 11-bit, 12-bit, or 13-bit respectively without CPU intervention.
Input Voltage
VREF x 1023/1024
VREF x 512/1024
VREF x 511/1024
0
68
Repeat Count = 4
Shift Right = 1
11-Bit Result
0x07F7
0x0400
0x03FE
0x0000
Repeat Count = 16
Shift Right = 2
12-Bit Result
0x0FFC
0x0800
0x04FC
0x0000
Rev. 1.3
Repeat Count = 64
Shift Right = 3
13-Bit Result
0x1FF8
0x1000
0x0FF8
0x0000
C8051F93x-C8051F92x
5.2.
Modes of Operation
ADC0 has a maximum conversion speed of 300 ksps. The ADC0 conversion clock (SARCLK) is a divided
version of the system clock when Burst Mode is disabled (BURSTEN = 0), or a divided version of the low
power oscillator when Burst Mode is enabled (BURSEN = 1). The clock divide value is determined by the
AD0SC bits in the ADC0CF register.
5.2.1. Starting a Conversion
A conversion can be initiated in one of five ways, depending on the programmed states of the ADC0 Start
of Conversion Mode bits (AD0CM2–0) in register ADC0CN. Conversions may be initiated by one of the following:
1.
2.
3.
4.
5.
Writing a 1 to the AD0BUSY bit of register ADC0CN
A Timer 0 overflow (i.e., timed continuous conversions)
A Timer 2 overflow
A Timer 3 overflow
A rising edge on the CNVSTR input signal (pin P0.6)
Writing a 1 to AD0BUSY provides software control of ADC0 whereby conversions are performed "ondemand". During conversion, the AD0BUSY bit is set to logic 1 and reset to logic 0 when the conversion is
complete. The falling edge of AD0BUSY triggers an interrupt (when enabled) and sets the ADC0 interrupt
flag (AD0INT). When polling for ADC conversion completions, the ADC0 interrupt flag (AD0INT) should be
used. Converted data is available in the ADC0 data registers, ADC0H:ADC0L, when bit AD0INT is logic 1.
When Timer 2 or Timer 3 overflows are used as the conversion source, Low Byte overflows are used if
Timer 2/3 is in 8-bit mode; High byte overflows are used if Timer 2/3 is in 16-bit mode. See “25. Timers” on
page 283 for timer configuration.
Important Note About Using CNVSTR: The CNVSTR input pin also functions as Port pin P0.6. When the
CNVSTR input is used as the ADC0 conversion source, Port pin P0.6 should be skipped by the Digital
Crossbar. To configure the Crossbar to skip P0.6, set to 1 Bit 6 in register P0SKIP. See “21. Port Input/Output” on page 216 for details on Port I/O configuration.
Important Note: When operating the device in one-cell mode, there is an option available to automatically
synchronize the start of conversion with the quietest portion of the dc-dc converter switching cycle. Activating this option may help to reduce interference from internal or external power supply noise generated by
the dc-dc converter. Asserting this bit will hold off the start of an ADC conversion initiated by any of the
methods described above until the ADC receives a synchronizing signal from the dc-dc converter. The
delay in initiation of the conversion can be as much as one cycle of the dc-dc converter clock, which is
625 ns at the minimum dc-dc clock frequency of 1.6 MHz. For rev C and later C8051F93x-92x devices, the
synchronization feature also causes the dc-dc converter clock to be used as the ADC0 conversion clock.
The maximum conversion rate will be limited to approximately 170 ksps at the maximum dc-dc converter
clock rate of 3.2 MHz. In this mode, the ADC0 SAR Conversion Clock Divider must be set to 1 by setting
AD0SC[4:0] = 00000b in SFR register ADC0CF. To provide additional flexibility in minimizing noise, the
ADC0 conversion clock provided by the dc-dc converter can be inverted by setting the AD0CKINV bit in the
DC0CF register. For additional information on the synchronization feature, see the description of the SYNC
bit in “SFR Definition 16.1. DC0CN: DC-DC Converter Control” on page 181 and the description of the
AD0CKINV bit in “SFR Definition 16.2. DC0CF: DC-DC Converter Configuration” on page 182. This bit
must be set to 0 in two-cell mode for the ADC to operate.
Rev. 1.3
69
C8051F93x-C8051F92x
5.2.2. Tracking Modes
Each ADC0 conversion must be preceded by a minimum tracking time in order for the converted result to
be accurate. The minimum tracking time is given in Table 4.9. The AD0TM bit in register ADC0CN controls
the ADC0 track-and-hold mode. In its default state when Burst Mode is disabled, the ADC0 input is continuously tracked, except when a conversion is in progress. When the AD0TM bit is logic 1, ADC0 operates in
low-power track-and-hold mode. In this mode, each conversion is preceded by a tracking period of 3 SAR
clocks (after the start-of-conversion signal). When the CNVSTR signal is used to initiate conversions in
low-power tracking mode, ADC0 tracks only when CNVSTR is low; conversion begins on the rising edge of
CNVSTR (see Figure 5.2). Tracking can also be disabled (shutdown) when the device is in low power
standby or sleep modes. Low-power track-and-hold mode is also useful when AMUX settings are frequently changed, due to the settling time requirements described in “5.2.4. Settling Time Requirements” on
page 73.
A. ADC0 Timing for External Trigger Source
CNVSTR
(AD0CM[2:0]=100)
1 2 3 4 5 6 7 8 9 10 11 12 13 14
SAR Clocks
AD0TM=1
AD0TM=0
Write '1' to AD0BUSY,
Timer 0, Timer 2,
Timer 1, Timer 3 Overflow
(AD0CM[2:0]=000, 001,010
011, 101)
Low Power
or Convert
Track or Convert
Low Power
Mode
Convert
Track
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
Low Power
Track
or Convert
Convert
Low Power Mode
1 2 3 4 5 6 7 8 9 10 11 12 13 14
SAR
Clocks
AD0TM=0
Convert
B. ADC0 Timing for Internal Trigger Source
SAR
Clocks
AD0TM=1
Track
Track or
Convert
Convert
Track
Figure 5.2. 10-Bit ADC Track and Conversion Example Timing (BURSTEN = 0)
70
Rev. 1.3
C8051F93x-C8051F92x
5.2.3. Burst Mode
Burst Mode is a power saving feature that allows ADC0 to remain in a low power state between conversions. When Burst Mode is enabled, ADC0 wakes from a low power state, accumulates 1, 4, 8, 16, 32, or
64 using an internal burst mode clock (approximately 25 MHz), then re-enters a low power state. Since the
burst mode clock is independent of the system clock, ADC0 can perform multiple conversions then enter a
low power state within a single system clock cycle, even if the system clock is slow (e.g., 32.768 kHz), or
suspended.
Burst Mode is enabled by setting BURSTEN to logic 1. When in burst mode, AD0EN controls the ADC0
idle power state (i.e. the state ADC0 enters when not tracking or performing conversions). If AD0EN is set
to logic 0, ADC0 is powered down after each burst. If AD0EN is set to logic 1, ADC0 remains enabled after
each burst. On each convert start signal, ADC0 is awakened from its Idle Power State. If ADC0 is powered
down, it will automatically power up and wait the programmable Power-Up Time controlled by the
AD0PWR bits. Otherwise, ADC0 will start tracking and converting immediately. Figure 5.3 shows an example of Burst Mode Operation with a slow system clock and a repeat count of 4.
When burst mode is enabled, a single convert start will initiate a number of conversions equal to the repeat
count. When burst mode is disabled, a convert start is required to initiate each conversion. In both modes,
the ADC0 End of Conversion Interrupt Flag (AD0INT) will be set after “repeat count” conversions have
been accumulated. Similarly, the Window Comparator will not compare the result to the greater-than and
less-than registers until “repeat count” conversions have been accumulated.
In Burst Mode, tracking is determined by the settings in AD0PWR and AD0TK. The default settings for
these registers will work in most applications without modification; however, settling time requirements may
need adjustment in some applications. Refer to “5.2.4. Settling Time Requirements” on page 73 for more
details.
Notes:
•
Setting AD0TM to 1 will insert an additional 3 SAR clocks of tracking before each conversion, regardless of the
settings of AD0PWR and AD0TK.
• When using Burst Mode, care must be taken to issue a convert start signal no faster than once every four SYSCLK periods. This includes external convert start signals.
•
•
A rising edge of external start-of-conversion (CNVSTR) will cause only one ADC conversion in Burst
Mode, regardless of the value of the Repeat Count field. The end-of-conversion interrupt will occur
after the number of conversions specified in Repeat Count have completed. In other words, if Repeat
Count is set to 4, four pulses on CNVSTR will cause an ADC end-of-conversion interrupt. Refer to the
bottom portion of Figure 5.3, “Burst Mode Tracking Example with Repeat Count Set to 4,” on page 72
for an example.
To start multiple conversions in Burst Mode with one external start-of-conversion signal, the external
interrupts (/INT0 or /INT1) or Port Match can be used to trigger an ISR that writes to AD0BUSY. External interrupts are configurable to be active low or active high, edge or level sensitive, but is only available on a limited number of pins. Port Match is only level sensitive, but is available on more port pins
than the external interrupts. Refer to Section “12.6. External Interrupts INT0 and INT1” on
page 146 for details on external interrupts and Section “21.4. Port Match” on page 227 for details on
Port Match.
Rev. 1.3
71
C8051F93x-C8051F92x
System Clock
Convert Start
(AD0BUSY or Timer
Overflow)
Post-Tracking
AD0TM = 01
AD0EN = 0
Powered
Down
Power-Up
and Idle
T C T C T C T C
Powered
Down
Power-Up
and Idle
T C..
Dual-Tracking
AD0TM = 11
AD0EN = 0
Powered
Down
Power-Up
and Track
T C T C T C T C
Powered
Down
Power-Up
and Track
T C..
AD0PWR
Post-Tracking
AD0TM = 01
AD0EN = 1
Idle
T C T C T C T C
Idle
T C T C T C..
Dual-Tracking
AD0TM = 11
AD0EN = 1
Track
T C T C T C T C
Track
T C T C T C..
T = Tracking
C = Converting
Convert Start
(CNVSTR)
Post-Tracking
AD0TM = 01
AD0EN = 0
Powered
Down
Power-Up
and Idle
T C
Powered
Down
Power-Up
and Idle
T C..
Dual-Tracking
AD0TM = 11
AD0EN = 0
Powered
Down
Power-Up
and Track
T C
Powered
Down
Power-Up
and Track
T C..
AD0PWR
Post-Tracking
AD0TM = 01
AD0EN = 1
Idle
T C
Idle
T C
Idle..
Dual-Tracking
AD0TM = 11
AD0EN = 1
Track
T C
Track
T C
Track..
T = Tracking
C = Converting
Figure 5.3. Burst Mode Tracking Example with Repeat Count Set to 4
72
Rev. 1.3
C8051F93x-C8051F92x
5.2.4. Settling Time Requirements
A minimum amount of tracking time is required before each conversion can be performed, to allow the
sampling capacitor voltage to settle. This tracking time is determined by the AMUX0 resistance, the ADC0
sampling capacitance, any external source resistance, and the accuracy required for the conversion. Note
that in low-power tracking mode, three SAR clocks are used for tracking at the start of every conversion.
For many applications, these three SAR clocks will meet the minimum tracking time requirements, and
higher values for the external source impedance will increase the required tracking time.
Figure 5.4 shows the equivalent ADC0 input circuit. The required ADC0 settling time for a given settling
accuracy (SA) may be approximated by Equation 5.1. When measuring the Temperature Sensor output or
VDD with respect to GND, RTOTAL reduces to RMUX. See Table 4.9 for ADC0 minimum settling time requirements as well as the mux impedance and sampling capacitor values.
n
2
t = ln  -------  R TOTAL C SAMPLE
SA
Equation 5.1. ADC0 Settling Time Requirements
Where:
SA is the settling accuracy, given as a fraction of an LSB (for example, 0.25 to settle within 1/4 LSB)
t is the required settling time in seconds
RTOTAL is the sum of the AMUX0 resistance and any external source resistance.
n is the ADC resolution in bits (10).
MUX Select
P0.x
R MUX
C SAMPLE
RCInput= R MUX * C SAMPLE
Note: The value of CSAMPLE depends on the PGA Gain. See Table 4.9 for details.
Figure 5.4. ADC0 Equivalent Input Circuits
Rev. 1.3
73
C8051F93x-C8051F92x
5.2.5. Gain Setting
The ADC has gain settings of 1x and 0.5x. In 1x mode, the full scale reading of the ADC is determined
directly by VREF. In 0.5x mode, the full-scale reading of the ADC occurs when the input voltage is VREF x 2.
The 0.5x gain setting can be useful to obtain a higher input Voltage range when using a small VREF voltage, or to measure input voltages that are between VREF and VDD. Gain settings for the ADC are controlled by the AMP0GN bit in register ADC0CF.
5.3.
8-Bit Mode
Setting the ADC08BE bit in register ADC0CF to 1 will put the ADC in 8-bit mode.In 8-bit mode, only the
8 MSBs of data are converted, allowing the conversion to be completed in two fewer SAR clock cycles
than a 10-bit conversion. This can result in an overall lower power consumption since the system can
spend more time in a low power mode. The two LSBs of a conversion are always 00 in this mode, and the
ADC0L register will always read back 0x00.
74
Rev. 1.3
C8051F93x-C8051F92x
SFR Definition 5.1. ADC0CN: ADC0 Control
Bit
7
6
5
4
3
Name
AD0EN
BURSTEN
AD0INT
Type
R/W
R/W
R/W
W
R/W
Reset
0
0
0
0
0
2
AD0BUSY AD0WINT
SFR Page = 0x0; SFR Address = 0xE8; bit-addressable;
Bit
Name
1
0
ADC0CM
R/W
0
0
0
Function
7
AD0EN
6
BURSTEN
5
AD0INT
4
AD0BUSY
ADC0 Busy.
Writing 1 to this bit initiates an ADC conversion when ADC0CM[2:0] = 000.
3
AD0WINT
ADC0 Window Compare Interrupt Flag.
Set by hardware when the contents of ADC0H:ADC0L fall within the window specified by
ADC0GTH:ADC0GTL and ADC0LTH:ADC0LTL. Can trigger an interrupt. Must be cleared by
software.
2:0
ADC0 Enable.
0: ADC0 Disabled (low-power shutdown).
1: ADC0 Enabled (active and ready for data conversions).
ADC0 Burst Mode Enable.
0: ADC0 Burst Mode Disabled.
1: ADC0 Burst Mode Enabled.
ADC0 Conversion Complete Interrupt Flag.
Set by hardware upon completion of a data conversion (BURSTEN=0), or a burst of conversions (BURSTEN=1). Can trigger an interrupt. Must be cleared by software.
ADC0CM[2:0] ADC0 Start of Conversion Mode Select.
Specifies the ADC0 start of conversion source.
000: ADC0 conversion initiated on write of 1 to AD0BUSY.
001: ADC0 conversion initiated on overflow of Timer 0.
010: ADC0 conversion initiated on overflow of Timer 2.
011: ADC0 conversion initiated on overflow of Timer 3.
1xx: ADC0 conversion initiated on rising edge of CNVSTR.
Rev. 1.3
75
C8051F93x-C8051F92x
SFR Definition 5.2. ADC0CF: ADC0 Configuration
Bit
7
6
5
4
3
2
1
0
Name
AD0SC[4:0]
AD08BE
AD0TM
AMP0GN
Type
R/W
R/W
R/W
R/W
0
0
0
Reset
1
1
1
1
SFR Page = 0x0; SFR Address = 0xBC
Bit
Name
7:3
1
Function
AD0SC[4:0] ADC0 SAR Conversion Clock Divider.
SAR Conversion clock is derived from FCLK by the following equation, where
AD0SC refers to the 5-bit value held in bits AD0SC[4:0]. SAR Conversion clock
requirements are given in Table 4.9.
BURSTEN = 0: FCLK is the current system clock.
BURSTEN = 1: FCLK is the 20 MHz low power oscillator, independent of the system
clock.
FCLK
AD0SC = -------------------- – 1 *
CLK SAR
*Round the result up.
or
FCLK
CLK SAR = ---------------------------AD0SC + 1
2
AD08BE
ADC0 8-Bit Mode Enable.
0: ADC0 operates in 10-bit mode (normal operation).
1: ADC0 operates in 8-bit mode.
1
AD0TM
ADC0 Track Mode.
Selects between Normal or Delayed Tracking Modes.
0: Normal Track Mode: When ADC0 is enabled, conversion begins immediately following the
start-of-conversion signal.
1: Delayed Track Mode: When ADC0 is enabled, conversion begins 3 SAR clock cycles following the start-of-conversion signal. The ADC is allowed to track during this time.
0
76
AMP0GN
ADC0 Gain Control.
0: The on-chip PGA gain is 0.5.
1: The on-chip PGA gain is 1.
Rev. 1.3
C8051F93x-C8051F92x
SFR Definition 5.3. ADC0AC: ADC0 Accumulator Configuration
Bit
7
6
5
Name
Reserved
AD0AE
AD0SJST
AD0RPT
Type
R/W
W
R/W
R/W
Reset
0
0
0
4
0
SFR Page = 0x0; SFR Address = 0xBA
Bit
Name
7
Reserved
3
0
2
0
1
0
0
0
Function
Reserved.
Read = 0b.
6
AD0AE
ADC0 Accumulate Enable.
Enables multiple conversions to be accumulated when burst mode is disabled.
0: ADC0H:ADC0L contain the result of the latest conversion when Burst Mode is
disabled.
1: ADC0H:ADC0L contain the accumulated conversion results when Burst Mode
is disabled. Software must write 0x0000 to ADC0H:ADC0L to clear the accumulated result.
This bit is write-only. Always reads 0b.
5:3
AD0SJST[2:0] ADC0 Accumulator Shift and Justify.
Specifies the format of data read from ADC0H:ADC0L.
000: Right justified. No shifting applied.
001: Right justified. Shifted right by 1 bit.
010: Right justified. Shifted right by 2 bits.
011: Right justified. Shifted right by 3 bits.
100: Left justified. No shifting applied.
All remaining bit combinations are reserved.
2:0
AD0RPT[2:0] ADC0 Repeat Count.
Selects the number of conversions to perform and accumulate in Burst Mode.
This bit field must be set to 000 if Burst Mode is disabled.
000: Perform and Accumulate 1 conversion.
001: Perform and Accumulate 4 conversions.
010: Perform and Accumulate 8 conversions.
011: Perform and Accumulate 16 conversions.
100: Perform and Accumulate 32 conversions.
101: Perform and Accumulate 64 conversions.
All remaining bit combinations are reserved.
Rev. 1.3
77
C8051F93x-C8051F92x
SFR Definition 5.4. ADC0PWR: ADC0 Burst Mode Power-Up Time
Bit
7
6
5
4
Name
Reserved
Type
R
R
R
R
Reset
0
0
0
0
Reserved
2
1
0
AD0PWR[3:0]
SFR Page = 0xF; SFR Address = 0xBA
Bit
Name
7
3
R/W
1
1
1
1
Function
Reserved.
Read = 0b; Must write 0b.
6:4
Unused
Unused.
Read = 0000b; Write = Don’t Care.
3:0
AD0PWR[3:0] ADC0 Burst Mode Power-Up Time.
Sets the time delay required for ADC0 to power up from a low power state.
For BURSTEN = 0:
ADC0 power state controlled by AD0EN.
For BURSTEN = 1 and AD0EN = 1:
ADC0 remains enabled and does not enter a low power state after all conversions are complete.
Conversions can begin immediately following the start-of-conversion signal.
For BURSTEN = 1 and AD0EN = 0:
ADC0 enters a low power state (as specified in Table 5.1) after all conversions
are complete. 
Conversions can begin a programmed delay after the start-of-conversion signal.
The ADC0 Burst Mode Power-Up time is programmed according to the following equation:
Tstartup
AD0PWR = ---------------------- – 1
400ns
or
Tstartup =  AD0PWR + 1 400ns
78
Rev. 1.3
C8051F93x-C8051F92x
SFR Definition 5.5. ADC0TK: ADC0 Burst Mode Track Time
Bit
7
6
5
4
3
1
0
1
0
AD0TK[5:0]
Name
Type
R
R
Reset
0
0
R/W
0
1
SFR Page = 0xF; SFR Address = 0xBD
Bit
Name
7:6
2
Unused
0
1
Function
Unused.
Read = 00b; Write = Don’t Care.
5:0
AD0TK[5:0] ADC0 Burst Mode Track Time.
Sets the time delay between consecutive conversions performed in Burst Mode.
The ADC0 Burst Mode Track time is programmed according to the following 
equation:
Ttrack
AD0TK = 63 –  ----------------- – 1
50ns
or
Ttrack =  64 – AD0TK 50ns
Notes:If AD0TM is set to 1, an additional 3 SAR clock cycles of Track time will be inserted prior to starting the
conversion.
The Burst Mode Track delay is not inserted prior to the first conversion. The required tracking time for the first
conversion should be met by the Burst Mode Power-Up Time.
Rev. 1.3
79
C8051F93x-C8051F92x
SFR Definition 5.6. ADC0H: ADC0 Data Word High Byte
Bit
7
6
5
4
3
Name
ADC0[15:8]
Type
R/W
Reset
0
0
0
0
0
SFR Page = 0x0; SFR Address = 0xBE
Bit
Name
Description
7:0
2
1
0
0
0
0
Read
Write
ADC0[15:8] ADC0 Data Word High Byte. Most Significant Byte of the
16-bit ADC0 Accumulator
formatted according to the
settings in AD0SJST[2:0].
Set the most significant
byte of the 16-bit ADC0
Accumulator to the value
written.
Note: If Accumulator shifting is enabled, the most significant bits of the value read will be zeros. This register
should not be written when the SYNC bit is set to 1.
SFR Definition 5.7. ADC0L: ADC0 Data Word Low Byte
Bit
7
6
5
4
Name
ADC0[7:0]
Type
R/W
Reset
0
0
0
0
SFR Page = 0x0; SFR Address = 0xBD;
Bit
Name
Description
7:0
ADC0[7:0]
ADC0 Data Word Low Byte.
3
2
1
0
0
0
0
0
Read
Write
Least Significant Byte of the
16-bit ADC0 Accumulator
formatted according to the
settings in AD0SJST[2:0].
Set the least significant
byte of the 16-bit ADC0
Accumulator to the value
written.
Note: If Accumulator shifting is enabled, the most significant bits of the value read will be the least significant bits of
the accumulator high byte. This register should not be written when the SYNC bit is set to 1.
80
Rev. 1.3
C8051F93x-C8051F92x
5.4.
Programmable Window Detector
The ADC Programmable Window Detector continuously compares the ADC0 output registers to userprogrammed limits, and notifies the system when a desired condition is detected. This is especially
effective in an interrupt-driven system, saving code space and CPU bandwidth while delivering faster
system response times. The window detector interrupt flag (AD0WINT in register ADC0CN) can also be
used in polled mode. The ADC0 Greater-Than (ADC0GTH, ADC0GTL) and Less-Than (ADC0LTH,
ADC0LTL) registers hold the comparison values. The window detector flag can be programmed to indicate
when measured data is inside or outside of the user-programmed limits, depending on the contents of the
ADC0 Less-Than and ADC0 Greater-Than registers.
SFR Definition 5.8. ADC0GTH: ADC0 Greater-Than High Byte
Bit
7
6
5
4
3
Name
AD0GT[15:8]
Type
R/W
Reset
1
1
1
1
1
SFR Page = 0x0; SFR Address = 0xC4
Bit
Name
7:0
2
1
0
1
1
1
Function
AD0GT[15:8] ADC0 Greater-Than High Byte.
Most Significant Byte of the 16-bit Greater-Than window compare register.
SFR Definition 5.9. ADC0GTL: ADC0 Greater-Than Low Byte
Bit
7
6
5
4
3
Name
AD0GT[7:0]
Type
R/W
Reset
1
1
1
1
SFR Page = 0x0; SFR Address = 0xC3
Bit
Name
7:0
1
2
1
0
1
1
1
Function
AD0GT[7:0] ADC0 Greater-Than Low Byte.
Least Significant Byte of the 16-bit Greater-Than window compare register.
Note: In 8-bit mode, this register should be set to 0x00.
Rev. 1.3
81
C8051F93x-C8051F92x
SFR Definition 5.10. ADC0LTH: ADC0 Less-Than High Byte
Bit
7
6
5
4
3
Name
AD0LT[15:8]
Type
R/W
Reset
0
0
0
0
0
SFR Page = 0x0; SFR Address = 0xC6
Bit
Name
7:0
2
1
0
0
0
0
Function
AD0LT[15:8] ADC0 Less-Than High Byte.
Most Significant Byte of the 16-bit Less-Than window compare register.
SFR Definition 5.11. ADC0LTL: ADC0 Less-Than Low Byte
Bit
7
6
5
4
3
Name
AD0LT[7:0]
Type
R/W
Reset
0
0
0
0
SFR Page = 0x0; SFR Address = 0xC5
Bit
Name
7:0
1
0
0
0
0
Function
AD0LT[7:0] ADC0 Less-Than Low Byte.
Least Significant Byte of the 16-bit Less-Than window compare register.
Note: In 8-bit mode, this register should be set to 0x00.
82
0
2
Rev. 1.3
C8051F93x-C8051F92x
5.4.1. Window Detector In Single-Ended Mode
Figure 5.5
shows
two
example
window
comparisons
for
right-justified
data,
with
ADC0LTH:ADC0LTL = 0x0080 (128d) and ADC0GTH:ADC0GTL = 0x0040 (64d). The input voltage can
range from 0 to VREF x (1023/1024) with respect to GND, and is represented by a 10-bit unsigned integer
value. In the left example, an AD0WINT interrupt will be generated if the ADC0 conversion word
(ADC0H:ADC0L) is within the range defined by ADC0GTH:ADC0GTL and ADC0LTH:ADC0LTL
(if 0x0040 < ADC0H:ADC0L < 0x0080). In the right example, and AD0WINT interrupt will be generated if
the ADC0 conversion word is outside of the range defined by the ADC0GT and ADC0LT registers
(if ADC0H:ADC0L < 0x0040 or ADC0H:ADC0L > 0x0080). Figure 5.6 shows an example using left-justified data with the same comparison values.
ADC0H:ADC0L
ADC0H:ADC0L
Input Voltage
(Px.x - GND)
VREF x (1023/1024)
Input Voltage
(Px.x - GND)
0x03FF
VREF x (1023/1024)
0x03FF
AD0WINT
not affected
AD0WINT=1
0x0081
VREF x (128/1024)
0x0080
0x0081
ADC0LTH:ADC0LTL
VREF x (128/1024)
0x007F
0x0080
0x007F
AD0WINT=1
VREF x (64/1024)
0x0041
0x0040
ADC0GTH:ADC0GTL
VREF x (64/1024)
0x003F
0x0041
0x0040
ADC0GTH:ADC0GTL
AD0WINT
not affected
ADC0LTH:ADC0LTL
0x003F
AD0WINT=1
AD0WINT
not affected
0
0x0000
0
0x0000
Figure 5.5. ADC Window Compare Example: Right-Justified Single-Ended Data
ADC0H:ADC0L
ADC0H:ADC0L
Input Voltage
(Px.x - GND)
VREF x (1023/1024)
Input Voltage
(Px.x - GND)
0xFFC0
VREF x (1023/1024)
0xFFC0
AD0WINT
not affected
AD0WINT=1
0x2040
VREF x (128/1024)
0x2000
0x2040
ADC0LTH:ADC0LTL
VREF x (128/1024)
0x1FC0
0x2000
0x1FC0
AD0WINT=1
0x1040
VREF x (64/1024)
0x1000
0x1040
ADC0GTH:ADC0GTL
VREF x (64/1024)
0x0FC0
0x1000
ADC0GTH:ADC0GTL
AD0WINT
not affected
ADC0LTH:ADC0LTL
0x0FC0
AD0WINT=1
AD0WINT
not affected
0
0x0000
0
0x0000
Figure 5.6. ADC Window Compare Example: Left-Justified Single-Ended Data
5.4.2. ADC0 Specifications
See “4. Electrical Characteristics” on page 45 for a detailed listing of ADC0 specifications.
Rev. 1.3
83
C8051F93x-C8051F92x
5.5.
ADC0 Analog Multiplexer
ADC0 on C8051F93x-C8051F92x has an analog multiplexer, referred to as AMUX0.
AMUX0 selects the positive inputs to the single-ended ADC0. Any of the following may be selected as the
positive input: Port I/O pins, the on-chip temperature sensor, the VBAT Power Supply, Regulated Digital
Supply Voltage (Output of VREG0), VDD/DC+ Supply, or the positive input may be connected to GND. The
ADC0 input channels are selected in the ADC0MX register described in SFR Definition 5.12.
AD0MX1
AM0MX0
AD0MX2
AD0MX3
AD0MX4
ADC0MX
P0.0
Programmable
Attenuator
AIN+
AMUX
P2.6*
Temp
Sensor
ADC0
Gain = 0.5 or 1
VBAT
Digital Supply
VDD/DC+
*P1.7-P2.6 only available as
inputs on 32-pin packages
Figure 5.7. ADC0 Multiplexer Block Diagram
Important Note About ADC0 Input Configuration: Port pins selected as ADC0 inputs should be
configured as analog inputs, and should be skipped by the Digital Crossbar. To configure a Port pin for
analog input, set to 0 the corresponding bit in register PnMDIN and disable the digital driver (PnMDOUT =
0 and Port Latch = 1). To force the Crossbar to skip a Port pin, set to 1 the corresponding bit in register
PnSKIP. See Section “21. Port Input/Output” on page 216 for more Port I/O configuration details.
84
Rev. 1.3
C8051F93x-C8051F92x
SFR Definition 5.12. ADC0MX: ADC0 Input Channel Select
Bit
7
6
5
4
3
2
1
0
AD0MX
Name
Type
R
R
R
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
1
1
1
1
1
SFR Page = 0x0; SFR Address = 0xBB
Bit
Name
Function
7:5
Unused
Unused.
Read = 000b; Write = Don’t Care.
4:0
AD0MX
AMUX0 Positive Input Selection.
Selects the positive input channel for ADC0.
00000:
P0.0
10000:
P2.0 (C8051F920/30 Only)
00001:
P0.1
10001:
P2.1 (C8051F920/30 Only)
00010:
P0.2
10010:
P2.2 (C8051F920/30 Only)
00011:
P0.3
10011:
P2.3 (C8051F920/30 Only)
00100:
P0.4
10100:
P2.4 (C8051F920/30 Only)
00101:
P0.5
10101:
P2.5 (C8051F920/30 Only)
00110:
P0.6
10110:
P2.6 (C8051F920/30 Only)
00111:
P0.7
10111:
Reserved.
01000:
P1.0
11000:
Reserved.
01001:
P1.1
11001:
Reserved.
01010:
P1.2
11010:
Reserved.
01011:
P1.3
11011:
Temperature Sensor*
01100:
P1.4
11100:
01101:
P1.5
VBAT Supply Voltage
(0.9–1.8 V) or (1.8–3.6 V)
01110:
P1.6
11101:
01111:
P1.7 (C8051F920/30
Only)
Digital Supply Voltage
(VREG0 Output, 1.7 V Typical)
11110:
VDD/DC+ Supply Voltage
(1.8–3.6 V)
11111:
Ground
*Note: Before switching the ADC multiplexer from another channel to the temperature sensor, the ADC mux should
select the 'Ground' channel as an intermediate step. The intermediate 'Ground' channel selection step will
discharge any voltage on the ADC sampling capacitor from the previous channel selection. This will prevent
the possibility of a high voltage (> 2V) being presented to the temperature sensor circuit, which can otherwise
impact its long-term reliability.
Rev. 1.3
85
C8051F93x-C8051F92x
5.6.
Temperature Sensor
An on-chip temperature sensor is included on the C8051F93x-C8051F92x which can be directly accessed
via the ADC multiplexer in single-ended configuration. To use the ADC to measure the temperature sensor,
the ADC mux channel should select the temperature sensor. The temperature sensor transfer function is
shown in Figure 5.8. The output voltage (VTEMP) is the positive ADC input when the ADC multiplexer is set
correctly. The TEMPE bit in register REF0CN enables/disables the temperature sensor, as described in
SFR Definition 5.15. While disabled, the temperature sensor defaults to a high impedance state and any
ADC measurements performed on the sensor will result in meaningless data. Refer to Table 4.9 for the
slope and offset parameters of the temperature sensor.
Important Note: Before switching the ADC multiplexer from another channel to the temperature sensor,
the ADC mux should select the 'Ground' channel as an intermediate step. The intermediate 'Ground'
channel selection step will discharge any voltage on the ADC sampling capacitor from the previous
channel selection. This will prevent the possibility of a high voltage (> 2V) being presented to the
temperature sensor circuit, which can otherwise impact its long-term reliability.
VTEMP = Slope x (TempC - 25) + Offset
TempC = 25 + ( V TEMP - Offset) / Slope
Voltage
Slope ( V / deg C)
Offset ( V at 25 Celsius)
Temperature
Figure 5.8. Temperature Sensor Transfer Function
86
Rev. 1.3
C8051F93x-C8051F92x
5.6.1. Calibration
The uncalibrated temperature sensor output is extremely linear and suitable for relative temperature
measurements (see Table 4.10 for linearity specifications). For absolute temperature measurements,
offset and/or gain calibration is recommended. Typically a 1-point (offset) calibration includes the following
steps:
Step 1. Control/measure the ambient temperature (this temperature must be known).
Step 2. Power the device, and delay for a few seconds to allow for self-heating.
Step 3. Perform an ADC conversion with the temperature sensor selected as the positive input
and GND selected as the negative input.
Step 4. Calculate the offset characteristics, and store this value in non-volatile memory for use
with subsequent temperature sensor measurements.
Figure 5.9 shows the typical temperature sensor error assuming a 1-point calibration at 25 °C.
Parameters that affect ADC measurement, in particular the voltage reference value, will also affect
temperature measurement.
Error (degrees C)
A single-point offset measurement of the temperature sensor is performed on each device during
production test. The measurement is performed at 25 °C ±5 °C, using the ADC with the internal high speed
reference buffer selected as the Voltage Reference. The direct ADC result of the measurement is stored in
the SFR registers TOFFH and TOFFL, shown in SFR Definition 5.13 and SFR Definition 5.14.
5.00
5.00
4.00
4.00
3.00
3.00
2.00
2.00
1.00
1.00
0.00
-40.00
-20.00
0.00
40.00
20.00
60.00
80.00
0.00
-1.00
-1.00
-2.00
-2.00
-3.00
-3.00
-4.00
-4.00
-5.00
-5.00
Temperature (degrees C)
Figure 5.9. Temperature Sensor Error with 1-Point Calibration (VREF = 1.68 V)
Rev. 1.3
87
C8051F93x-C8051F92x
SFR Definition 5.13. TOFFH: ADC0 Data Word High Byte
Bit
7
6
5
4
3
2
1
0
TOFF[9:2]
Name
Type
R
R
R
R
R
R
R
R
Reset
Varies
Varies
Varies
Varies
Varies
Varies
Varies
Varies
SFR Page = 0xF; SFR Address = 0x86
Bit
Name
7:0
TOFF[9:2]
Function
Temperature Sensor Offset High Bits.
Most Significant Bits of the 10-bit temperature sensor offset measurement.
SFR Definition 5.14. TOFFL: ADC0 Data Word Low Byte
Bit
7
6
5
4
3
2
1
0
0
0
0
0
0
0
TOFF[1:0]
Name
Type
R
R
Reset
Varies
Varies
SFR Page = 0xF; SFR Address = 0x85
Bit
Name
7:6
TOFF[1:0]
Function
Temperature Sensor Offset Low Bits.
Least Significant Bits of the 10-bit temperature sensor offset measurement.
5:0
88
Unused
Unused.
Read = 0; Write = Don't Care.
Rev. 1.3
C8051F93x-C8051F92x
5.7.
Voltage and Ground Reference Options
The voltage reference MUX is configurable to use an externally connected voltage reference, one of two
internal voltage references, or one of two power supply voltages (see Figure 5.10). The ground reference
MUX allows the ground reference for ADC0 to be selected between the ground pin (GND) or a port pin
dedicated to analog ground (P0.1/AGND).
The voltage and ground reference options are configured using the REF0CN SFR described on page 91.
Electrical specifications are can be found in the Electrical Specifications Chapter.
Important Note About the VREF and AGND Inputs: Port pins are used as the external VREF and AGND
inputs. When using an external voltage reference or the internal precision reference, P0.0/VREF should be
configured as an analog input and skipped by the Digital Crossbar. When using AGND as the ground
reference to ADC0, P0.1/AGND should be configured as an analog input and skipped by the Digital
Crossbar. Refer to Section “21. Port Input/Output” on page 216 for complete Port I/O configuration details.
The external reference voltage must be within the range 0  VREF  VDD/DC+ and the external ground
reference must be at the same DC voltage potential as GND.
REFOE
REFGND
REFSL1
REFSL0
TEMPE
R E F 0C N
T em p S ensor
EN
ADC
Input
M ux
REFOE
EN
VDD
R1
E xternal
V oltage
R eference
C ircuit
Internal 1.68V
R eference
P 0 .0/V R E F
00
V D D /D C +
01
Internal 1.8V
R egulated D igital S upply
GND
10
VREF
(to A D C )
11
4 .7 F
+
0 .1 F
R ecom m ended
B ypass C apacitors
Internal 1.65 V
H igh S peed R eference
GND
0
P 0.1/A G N D
1
G round
(to A D C )
REFGND
Figure 5.10. Voltage Reference Functional Block Diagram
Rev. 1.3
89
C8051F93x-C8051F92x
5.8.
External Voltage References
To use an external voltage reference, REFSL[1:0] should be set to 00 and the internal 1.68 V precision reference should be disabled by setting REFOE to 0. Bypass capacitors should be added as recommended
by the manufacturer of the external voltage reference.
5.9.
Internal Voltage References
For applications requiring the maximum number of port I/O pins, or very short VREF turn-on time, the
1.65 V high-speed reference will be the best internal reference option to choose. The high speed internal
reference is selected by setting REFSL[1:0] to 11. When selected, the high speed internal reference will be
automatically enabled/disabled on an as-needed basis by ADC0.
For applications requiring the highest absolute accuracy, the 1.68 V precision voltage reference will be the
best internal reference option to choose. The 1.68 V precision reference may be enabled and selected by
setting REFOE to 1 and REFSL[1:0] to 00. An external capacitor of at least 0.1 µF is recommended when
using the precision voltage reference.
In applications that leave the precision internal oscillator always running, there is no additional power
required to use the precision voltage reference. In all other applications, using the high speed reference
will result in lower overall power consumption due to its minimal startup time and the fact that it remains in
a low power state when an ADC conversion is not taking place.
Note: When using the precision internal oscillator as the system clock source, the precision voltage reference should not be enabled from a disabled state. To use the precision oscillator and the
precision voltage reference simultaneously, the precision voltage reference should be enabled first
and allowed to settle to its final value (charging the external capacitor) before the precision oscillator is started and selected as the system clock.
For applications with a non-varying power supply voltage, using the power supply as the voltage reference
can provide ADC0 with added dynamic range at the cost of reduced power supply noise rejection. To use
the 1.8 to 3.6 V power supply voltage (VDD/DC+) or the 1.8 V regulated digital supply voltage as the reference source, REFSL[1:0] should be set to 01 or 10, respectively.
5.10. Analog Ground Reference
To prevent ground noise generated by switching digital logic from affecting sensitive analog measurements, a separate analog ground reference option is available. When enabled, the ground reference for
ADC0 during both the tracking/sampling and the conversion periods is taken from the P0.1/AGND pin. Any
external sensors sampled by ADC0 should be referenced to the P0.1/AGND pin. This pin should be connected to the ground terminal of any external sensors sampled by ADC0. If an external voltage reference is
used, the P0.1/AGND pin should be connected to the ground of the external reference and its associated
decoupling capacitor. If the 1.68 V precision internal reference is used, then P0.1/AGND should be connected to the ground terminal of its external decoupling capacitor. The separate analog ground reference
option is enabled by setting REFGND to 1. Note that when sampling the internal temperature sensor, the
internal chip ground is always used for the sampling operation, regardless of the setting of the REFGND
bit. Similarly, whenever the internal 1.65 V high-speed reference is selected, the internal chip ground is
always used during the conversion period, regardless of the setting of the REFGND bit.
5.11. Temperature Sensor Enable
The TEMPE bit in register REF0CN enables/disables the temperature sensor. While disabled, the temperature sensor defaults to a high impedance state and any ADC0 measurements performed on the sensor
result in meaningless data. See Section “5.6. Temperature Sensor” on page 86 for details on temperature
sensor characteristics when it is enabled.
90
Rev. 1.3
C8051F93x-C8051F92x
SFR Definition 5.15. REF0CN: Voltage Reference Control
Bit
7
6
5
4
REFGND
Name
3
REFSL
2
1
TEMPE
0
REFOE
Type
R
R
R/W
R/W
R/W
R/W
R
R/W
Reset
0
0
0
1
1
0
0
0
SFR Page = 0x0; SFR Address = 0xD1
Bit
Name
7:6
Unused
Function
Unused.
Read = 00b; Write = Don’t Care.
5
REFGND Analog Ground Reference.
Selects the ADC0 ground reference.
0: The ADC0 ground reference is the GND pin.
1: The ADC0 ground reference is the P0.1/AGND pin.
4:3
REFSL
Voltage Reference Select.
Selects the ADC0 voltage reference.
00: The ADC0 voltage reference is the P0.0/VREF pin.
01: The ADC0 voltage reference is the VDD/DC+ pin.
10: The ADC0 voltage reference is the internal 1.8 V digital supply voltage.
11: The ADC0 voltage reference is the internal 1.65 V high speed voltage reference.
2
TEMPE
Temperature Sensor Enable.
Enables/Disables the internal temperature sensor.
0: Temperature Sensor Disabled.
1: Temperature Sensor Enabled.
1
Unused
Unused.
Read = 0b; Write = Don’t Care.
0
REFOE
Internal Voltage Reference Output Enable.
Connects/Disconnects the internal voltage reference to the P0.0/VREF pin.
0: Internal 1.68 V Precision Voltage Reference disabled and not connected to
P0.0/VREF.
1: Internal 1.68 V Precision Voltage Reference enabled and connected to
P0.0/VREF.
5.12. Voltage Reference Electrical Specifications
See Table 4.11 on page 62 for detailed Voltage Reference Electrical Specifications.
Rev. 1.3
91
C8051F93x-C8051F92x
6.
Programmable Current Reference (IREF0)
C8051F93x-C8051F92x devices include an on-chip programmable current reference (source or sink) with
two output current settings: Low Power Mode and High Current Mode. The maximum current output in Low
Power Mode is 63 µA (1 µA steps) and the maximum current output in High Current Mode is 504 µA (8 µA
steps).
The current source/sink is controlled though the IREF0CN special function register. It is enabled by setting
the desired output current to a non-zero value. It is disabled by writing 0x00 to IREF0CN. The port I/O pin
associated with ISRC0 should be configured as an analog input and skipped in the Crossbar. See Section
“21. Port Input/Output” on page 216 for more details.
SFR Definition 6.1. IREF0CN: Current Reference Control
Bit
7
6
5
Name
SINK
MODE
IREF0DAT
Type
R/W
R/W
R/W
Reset
0
0
0
4
0
SFR Page = 0x0; SFR Address = 0xB9
Bit
Name
7
SINK
3
0
2
1
0
0
0
0
Function
IREF0 Current Sink Enable.
Selects if IREF0 is a current source or a current sink.
0: IREF0 is a current source.
1: IREF0 is a current sink.
6
MDSEL
IREF0 Output Mode Select.
Selects Low Power or High Current Mode.
0: Low Power Mode is selected (step size = 1 µA).
1: High Current Mode is selected (step size = 8 µA).
5:0
IREF0DAT[5:0]
IREF0 Data Word.
Specifies the number of steps required to achieve the desired output current.
Output current = direction x step size x IREF0DAT.
IREF0 is in a low power state when IREF0DAT is set to 0x00.
6.1.
IREF0 Specifications
See Table 4.12 on page 63 for a detailed listing of IREF0 specifications.
92
Rev. 1.3
C8051F93x-C8051F92x
7.
Comparators
C8051F93x-C8051F92x devices include two on-chip programmable voltage comparators: Comparator 0
(CPT0) is shown in Figure 7.1; Comparator 1 (CPT1) is shown in Figure 7.2. The two comparators operate
identically, but may differ in their ability to be used as reset or wake-up sources. See the Reset Sources
chapter and the Power Management chapter for details on reset sources and low power mode wake-up
sources, respectively.
The Comparator offers programmable response time and hysteresis, an analog input multiplexer, and two
outputs that are optionally available at the Port pins: a synchronous “latched” output (CP0, CP1), or an
asynchronous “raw” output (CP0A, CP1A). The asynchronous CP0A signal is available even when the
system clock is not active. This allows the Comparator to operate and generate an output when the device
is in some low power modes.
7.1.
Comparator Inputs
Each Comparator performs an analog comparison of the voltage levels at its positive (CP0+ or CP1+) and
negative (CP0- or CP1-) input. Both comparators support multiple port pin inputs multiplexed to their positive and negative comparator inputs using analog input multiplexers. The analog input multiplexers are
completely under software control and configured using SFR registers. See Section “7.6. Comparator0 and
Comparator1 Analog Multiplexers” on page 100 for details on how to select and configure Comparator
inputs.
Important Note About Comparator Inputs: The Port pins selected as Comparator inputs should be configured as analog inputs and skipped by the Crossbar. See the Port I/O chapter for more details on how to
configure Port I/O pins as Analog Inputs. The Comparator may also be used to compare the logic level of
digital signals, however, Port I/O pins configured as digital inputs must be driven to a valid logic state
(HIGH or LOW) to avoid increased power consumption.
CPT0CN
CP0EN
CP0OUT
CP0RIF
VDD
CP0FIF
CP0HYP1
CP0
Interrupt
CP0HYP0
CP0HYN1
CP0HYN0
CPT0MD
Analog Input Multiplexer
CP0FIE
CP0RIE
CP0MD1
CP0MD0
Px.x
CP0
Rising-edge
CP0 +
CP0
Falling-edge
Interrupt
Logic
Px.x
CP0
+
D
-
SET
CLR
Q
Q
D
SET
CLR
Q
Q
Px.x
Crossbar
(SYNCHRONIZER)
CP0 -
GND
(ASYNCHRONOUS)
Px.x
CP0A
Reset
Decision
Tree
Figure 7.1. Comparator 0 Functional Block Diagram
Rev. 1.3
93
C8051F93x-C8051F92x
7.2.
Comparator Outputs
When a comparator is enabled, its output is a logic 1 if the voltage at the positive input is higher than the
voltage at the negative input. When disabled, the comparator output is a logic 0. The comparator output is
synchronized with the system clock as shown in Figure 7.2. The synchronous “latched” output (CP0, CP1)
can be polled in software (CPnOUT bit), used as an interrupt source, or routed to a Port pin through the
Crossbar.
The asynchronous “raw” comparator output (CP0A, CP1A) is used by the low power mode wakeup logic
and reset decision logic. See the Power Options chapter and the Reset Sources chapter for more details
on how the asynchronous comparator outputs are used to make wake-up and reset decisions. The
asynchronous comparator output can also be routed directly to a Port pin through the Crossbar, and is
available for use outside the device even if the system clock is stopped.
When using a Comparator as an interrupt source, Comparator interrupts can be generated on rising-edge
and/or falling-edge comparator output transitions. Two independent interrupt flags (CPnRIF and CPnFIF)
allow software to determine which edge caused the Comparator interrupt. The comparator rising-edge and
falling-edge interrupt flags are set by hardware when a corresponding edge is detected regardless of the
interrupt enable state. Once set, these bits remain set until cleared by software.
The rising-edge and falling-edge interrupts can be individually enabled using the CPnRIE and CPnFIE
interrupt enable bits in the CPTnMD register. In order for the CPnRIF and/or CPnFIF interrupt flags to generate an interrupt request to the CPU, the Comparator must be enabled as an interrupt source and global
interrupts must be enabled. See the Interrupt Handler chapter for additional information.
CPT0CN
CP1EN
CP1OUT
CP1RIF
VDD
CP1FIF
CP1HYP1
CP1
Interrupt
CP1HYP0
CP1HYN1
CP1HYN0
CPT0MD
Analog Input Multiplexer
CP1FIE
CP1RIE
CP1MD1
CP1MD0
Px.x
CP1
Rising-edge
CP1 +
CP1
Falling-edge
Interrupt
Logic
Px.x
CP1
+
D
-
SET
CLR
Q
Q
D
SET
CLR
Q
Q
Px.x
Crossbar
(SYNCHRONIZER)
CP1 -
GND
(ASYNCHRONOUS)
Reset
Decision
Tree
Px.x
Figure 7.2. Comparator 1 Functional Block Diagram
94
Rev. 1.3
CP1A
C8051F93x-C8051F92x
7.3.
Comparator Response Time
Comparator response time may be configured in software via the CPTnMD registers described on
“CPT0MD: Comparator 0 Mode Selection” on page 97 and “CPT1MD: Comparator 1 Mode Selection” on
page 99. Four response time settings are available: Mode 0 (Fastest Response Time), Mode 1, Mode 2,
and Mode 3 (Lowest Power). Selecting a longer response time reduces the Comparator active supply
current. The Comparators also have low power shutdown state, which is entered any time the comparator
is disabled. Comparator rising edge and falling edge response times are typically not equal. See
Table 4.13 on page 64 for complete comparator timing and supply current specifications.
7.4.
Comparator Hysterisis
The Comparators feature software-programmable hysterisis that can be used to stabilize the comparator
output while a transition is occurring on the input. Using the CPTnCN registers, the user can program both
the amount of hysteresis voltage (referred to the input voltage) and the positive and negative-going
symmetry of this hysteresis around the threshold voltage (i.e., the comparator negative input).
Figure 7.3 shows that when positive hysterisis is enabled, the comparator output does not transition from
logic 0 to logic 1 until the comparator positive input voltage has exceeded the threshold voltage by an
amount equal to the programmed hysterisis. It also shows that when negative hysterisis is enabled, the
comparator output does not transition from logic 1 to logic 0 until the comparator positive input voltage has
fallen below the threshold voltage by an amount equal to the programmed hysterisis.
The amount of positive hysterisis is determined by the settings of the CPnHYP bits in the CPTnCN register
and the amount of negative hysteresis voltage is determined by the settings of the CPnHYN bits in the
same register. Settings of 20 mV, 10 mV, 5 mV, or 0 mV can be programmed for both positive and negative
hysterisis. See Section “Table 4.13. Comparator Electrical Characteristics” on page 64 for complete
comparator hysterisis specifications.
VIN+
VIN-
CPn+
CPn-
+
CPn
_
OUT
CIRCUIT CONFIGURATION
Positive Hysteresis Voltage
(Programmed with CP0HYP Bits)
VIN-
INPUTS
Negative Hysteresis Voltage
(Programmed by CP0HYN Bits)
VIN+
V OH
OUTPUT
V OL
Negative Hysteresis
Disabled
Positive Hysteresis
Disabled
Maximum
Negative Hysteresis
Maximum
Positive Hysteresis
Figure 7.3. Comparator Hysteresis Plot
Rev. 1.3
95
C8051F93x-C8051F92x
7.5.
Comparator Register Descriptions
The SFRs used to enable and configure the comparators are described in the following register
descriptions. A Comparator must be enabled by setting the CPnEN bit to logic 1 before it can be used.
From an enabled state, a comparator can be disabled and placed in a low power state by clearing the
CPnEN bit to logic 0.
Important Note About Comparator Settings: False rising and falling edges can be detected by the
Comparator while powering on or if changes are made to the hysteresis or response time control bits.
Therefore, it is recommended that the rising-edge and falling-edge flags be explicitly cleared to logic 0 a
short time after the comparator is enabled or its mode bits have been changed. The Comparator Power Up
Time is specified in Section “Table 4.13. Comparator Electrical Characteristics” on page 64.
SFR Definition 7.1. CPT0CN: Comparator 0 Control
Bit
7
6
5
4
3
2
Name
CP0EN
CP0OUT
CP0RIF
CP0FIF
CP0HYP[1:0]
CP0HYN[1:0]
Type
R/W
R
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
1
0
0
0
SFR Page= 0x0; SFR Address = 0x9B
Bit
Name
7
CP0EN
Function
Comparator0 Enable Bit.
0: Comparator0 Disabled.
1: Comparator0 Enabled.
6
CP0OUT
Comparator0 Output State Flag.
0: Voltage on CP0+ < CP0–.
1: Voltage on CP0+ > CP0–.
5
CP0RIF
Comparator0 Rising-Edge Flag. Must be cleared by software.
0: No Comparator0 Rising Edge has occurred since this flag was last cleared.
1: Comparator0 Rising Edge has occurred.
4
CP0FIF
Comparator0 Falling-Edge Flag. Must be cleared by software.
0: No Comparator0 Falling-Edge has occurred since this flag was last cleared.
1: Comparator0 Falling-Edge has occurred.
3-2
CP0HYP[1:0] Comparator0 Positive Hysteresis Control Bits.
00: Positive Hysteresis Disabled.
01: Positive Hysteresis = 5 mV.
10: Positive Hysteresis = 10 mV.
11: Positive Hysteresis = 20 mV.
1-0
CP0HYN[1:0] Comparator0 Negative Hysteresis Control Bits.
00: Negative Hysteresis Disabled.
01: Negative Hysteresis = 5 mV.
10: Negative Hysteresis = 10 mV.
11: Negative Hysteresis = 20 mV.
96
Rev. 1.3
C8051F93x-C8051F92x
SFR Definition 7.2. CPT0MD: Comparator 0 Mode Selection
Bit
7
6
Name
5
4
CP0RIE
CP0FIE
3
2
1
0
CP0MD[1:0]
Type
R/W
R
R/W
R/W
R
R
Reset
1
0
0
0
0
0
R/W
1
0
SFR Page = All Pages; SFR Address = 0x9D
Bit
Name
7
Reserved
6
Unused
Unused.
Read = 0b, Write = don’t care.
5
CP0RIE
Comparator0 Rising-Edge Interrupt Enable.
0: Comparator0 Rising-edge interrupt disabled.
1: Comparator0 Rising-edge interrupt enabled.
4
CP0FIE
Comparator0 Falling-Edge Interrupt Enable.
0: Comparator0 Falling-edge interrupt disabled.
1: Comparator0 Falling-edge interrupt enabled.
3:2
Unused
Unused.
Read = 00b, Write = don’t care.
1:0
Function
Reserved. Read = 1b, Must Write 1b.
CP0MD[1:0] Comparator0 Mode Select
These bits affect the response time and power consumption for Comparator0.
00: Mode 0 (Fastest Response Time, Highest Power Consumption)
01: Mode 1
10: Mode 2
11: Mode 3 (Slowest Response Time, Lowest Power Consumption)
Rev. 1.3
97
C8051F93x-C8051F92x
SFR Definition 7.3. CPT1CN: Comparator 1 Control
Bit
7
6
5
4
3
2
Name
CP1EN
CP1OUT
CP1RIF
CP1FIF
CP1HYP[1:0]
CP1HYN[1:0]
Type
R/W
R
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
1
0
0
0
SFR Page= 0x0; SFR Address = 0x9A
Bit
Name
7
CP1EN
Function
Comparator1 Enable Bit.
0: Comparator1 Disabled.
1: Comparator1 Enabled.
6
CP1OUT
Comparator1 Output State Flag.
0: Voltage on CP1+ < CP1–.
1: Voltage on CP1+ > CP1–.
5
CP1RIF
Comparator1 Rising-Edge Flag. Must be cleared by software.
0: No Comparator1 Rising Edge has occurred since this flag was last cleared.
1: Comparator1 Rising Edge has occurred.
4
CP1FIF
Comparator1 Falling-Edge Flag. Must be cleared by software.
0: No Comparator1 Falling-Edge has occurred since this flag was last cleared.
1: Comparator1 Falling-Edge has occurred.
3:2
CP1HYP[1:0] Comparator1 Positive Hysteresis Control Bits.
00: Positive Hysteresis Disabled.
01: Positive Hysteresis = 5 mV.
10: Positive Hysteresis = 10 mV.
11: Positive Hysteresis = 20 mV.
1:0
CP1HYN[1:0] Comparator1 Negative Hysteresis Control Bits.
00: Negative Hysteresis Disabled.
01: Negative Hysteresis = 5 mV.
10: Negative Hysteresis = 10 mV.
11: Negative Hysteresis = 20 mV.
98
Rev. 1.3
C8051F93x-C8051F92x
SFR Definition 7.4. CPT1MD: Comparator 1 Mode Selection
Bit
7
6
Name
5
4
CP1RIE
CP1FIE
3
2
1
0
CP1MD[1:0]
Type
R/W
R
R/W
R/W
R
R
Reset
1
0
0
0
0
0
R/W
1
0
SFR Page = 0x0; SFR Address = 0x9C
Bit
Name
7
Reserved
6
Unused
Unused.
Read = 00b, Write = don’t care.
5
CP1RIE
Comparator1 Rising-Edge Interrupt Enable.
0: Comparator1 Rising-edge interrupt disabled.
1: Comparator1 Rising-edge interrupt enabled.
4
CP1FIE
Comparator1 Falling-Edge Interrupt Enable.
0: Comparator1 Falling-edge interrupt disabled.
1: Comparator1 Falling-edge interrupt enabled.
3:2
Unused
Unused.
Read = 00b, Write = don’t care.
1:0
Function
Reserved. Read = 1b, Must Write 1b.
CP1MD[1:0] Comparator1 Mode Select
These bits affect the response time and power consumption for Comparator1.
00: Mode 0 (Fastest Response Time, Highest Power Consumption)
01: Mode 1
10: Mode 2
11: Mode 3 (Slowest Response Time, Lowest Power Consumption)
Rev. 1.3
99
C8051F93x-C8051F92x
7.6.
Comparator0 and Comparator1 Analog Multiplexers
Comparator0 and Comparator1 on C8051F93x-C8051F92x devices have analog input multiplexers to connect Port I/O pins and internal signals the comparator inputs; CP0+/CP0- are the positive and negative
input multiplexers for Comparator0 and CP1+/CP1- are the positive and negative input multiplexers for
Comparator1.
The comparator input multiplexers directly support capacitive touch switches. When the Capacitive Touch
Sense Compare input is selected on the positive or negative multiplexer, any Port I/O pin connected to the
other multiplexer can be directly connected to a capacitive touch switch with no additional external components. The Capacitive Touch Sense Compare provides the appropriate reference level for detecting when
the capacitive touch switches have charged or discharged through the on-chip Rsense resistor. The Comparator outputs can be routed to Timer2 or Timer3 for capturing sense capacitor’s charge and discharge
time. See Section “25. Timers” on page 283 for details.
Any of the following may be selected as comparator inputs: Port I/O pins, Capacitive Touch Sense Compare, VDD/DC+ Supply Voltage, Regulated Digital Supply Voltage (Output of VREG0), the VBAT Supply
voltage or ground. The Comparator’s supply voltage divided by 2 is also available as an input; the resistors
used to divide the voltage only draw current when this setting is selected. The Comparator input multiplexers are configured using the CPT0MX and CPT1MX registers described in SFR Definition 7.5 and SFR
Definition 7.6.
P0.1
P0.3
P0.5
P0.7
P1.1
P1.3
P1.5
P1.7*
P2.1*
P2.3*
P2.5*
VDD/DC+ CPnOUT
R
R
R
Capacitive
Touch
Sense
Compare
(1/3 or 2/3) x VDD/DC+
CPnInput
MUX
P0.0
P0.2
P0.4
P0.6
CPnOUT
P1.0
P1.2
P1.4
Rsense
P1.6
Only enabled when
P2.0*
Capacitive Touch
P2.2*
Sense Compare is
P2.4*
selected on CPn+
P2.6*
Input MUX.
Capacitive
VDD/DC+ CPnOUT
Touch
Sense
R
R
Compare
(1/3 or 2/3) x VDD/DC+
R
VDD/DC+
R
R
CMXnP1
CMXnP0
CMXnN1
CMXnN0
CMXnP3
CMXnP2
CMXnN3
CMXnN2
CPTnMX
CPnOUT
Rsense
CPn+
Input
MUX
VDD/DC+
½ x VDD/DC+
Digital Supply
R
R
Only enabled when
Capacitive Touch
Sense Compare is
selected on CPnInput MUX.
VDD/DC+
+
GND
½ x VDD/DC+
VBAT
VDD/DC+
GND
*P1.7-P2.5 only available as
inputs on 32-pin packages
*P2.0-P2.6 only available as
inputs on 32-pin packages
Figure 7.4. CPn Multiplexer Block Diagram
Important Note About Comparator Input Configuration: Port pins selected as comparator inputs should
be configured as analog inputs, and should be skipped by the Digital Crossbar. To configure a Port pin for
analog input, set to 0 the corresponding bit in register PnMDIN and disable the digital driver (PnMDOUT =
0 and Port Latch = 1). To force the Crossbar to skip a Port pin, set to 1 the corresponding bit in register
PnSKIP. See Section “21. Port Input/Output” on page 216 for more Port I/O configuration details.
100
Rev. 1.3
C8051F93x-C8051F92x
SFR Definition 7.5. CPT0MX: Comparator0 Input Channel Select
Bit
7
6
5
4
3
CMX0N[3:0]
Name
2
1
0
CMX0P[3:0]
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
1
1
1
1
1
1
1
1
SFR Page = 0x0; SFR Address = 0x9F
Bit
Name
7:4
3:0
CMX0N
CMX0P
Function
Comparator0 Negative Input Selection.
Selects the negative input channel for Comparator0.
0000:
P0.1
1000:
P2.1 (C8051F920/30 Only)
0001:
P0.3
1001:
P2.3 (C8051F920/30 Only)
0010:
P0.5
1010:
P2.5 (C8051F920/30 Only)
0011:
P0.7
1011:
Reserved
0100:
P1.1
1100:
Capacitive Touch Sense 
Compare
0101:
P1.3
1101:
VDD/DC+ divided by 2
0110:
P1.5
1110:
Digital Supply Voltage
0111:
P1.7 (C8051F920/30
Only)
1111:
Ground
Comparator0 Positive Input Selection.
Selects the positive input channel for Comparator0.
0000:
P0.0
1000:
P2.0 (C8051F920/30 Only)
0001:
P0.2
1001:
P2.2 (C8051F920/30 Only)
0010:
P0.4
1010:
P2.4 (C8051F920/30 Only)
0011:
P0.6
1011:
P2.6 (C8051F920/30 Only)
0100:
P1.0
1100:
Capacitive Touch Sense 
Compare
0101:
P1.2
1101:
VDD/DC+ divided by 2
0110:
P1.4
1110:
VBAT Supply Voltage
0111:
P1.6
1111:
VDD/DC+ Supply Voltage
Rev. 1.3
101
C8051F93x-C8051F92x
SFR Definition 7.6. CPT1MX: Comparator1 Input Channel Select
Bit
7
6
5
4
3
CMX1N[3:0]
Name
2
1
0
CMX1P[3:0]
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
1
1
1
1
1
1
1
1
SFR Page = 0x0; SFR Address = 0x9E
Bit
Name
7:4
3:0
102
CMX1N
CMX1P
Function
Comparator1 Negative Input Selection.
Selects the negative input channel for Comparator1.
0000:
P0.1
1000:
P2.1 (C8051F920/30 Only)
0001:
P0.3
1001:
P2.3 (C8051F920/30 Only)
0010:
P0.5
1010:
P2.5 (C8051F920/30 Only)
0011:
P0.7
1011:
Reserved
0100:
P1.1
1100:
Capacitive Touch Sense 
Compare
0101:
P1.3
1101:
VDD/DC+ divided by 2
0110:
P1.5
1110:
Digital Supply Voltage
0111:
P1.7 (C8051F920/30
Only)
1111:
Ground
Comparator1 Positive Input Selection.
Selects the positive input channel for Comparator1.
0000:
P0.0
1000:
P2.0 (C8051F920/30 Only)
0001:
P0.2
1001:
P2.2 (C8051F920/30 Only)
0010:
P0.4
1010:
P2.4 (C8051F920/30 Only)
0011:
P0.6
1011:
P2.6 (C8051F920/30 Only)
0100:
P1.0
1100:
Capacitive Touch Sense 
Compare
0101:
P1.2
1101:
VDD/DC+ divided by 2
0110:
P1.4
1110:
VBAT Supply Voltage
0111:
P1.6
1111:
VDD/DC+ Supply Voltage
Rev. 1.3
C8051F93x-C8051F92x
8.
CIP-51 Microcontroller
The MCU system controller core is the CIP-51 microcontroller. The CIP-51 is fully compatible with the
MCS-51™ instruction set; standard 803x/805x assemblers and compilers can be used to develop software. The MCU family has a superset of all the peripherals included with a standard 8051. The CIP-51
also includes on-chip debug hardware (see description in Section 27), and interfaces directly with the analog and digital subsystems providing a complete data acquisition or control-system solution in a single integrated circuit.
The CIP-51 Microcontroller core implements the standard 8051 organization and peripherals as well as
additional custom peripherals and functions to extend its capability (see Figure 8.1 for a block diagram).
The CIP-51 includes the following features:
-
- Fully Compatible with MCS-51 Instruction
Set
- 25 MIPS Peak Throughput with 25 MHz
Clock
- 0 to 25 MHz Clock Frequency
Extended Interrupt Handler
Reset Input
Power Management Modes
On-chip Debug Logic
Program and Data Memory Security
Performance
The CIP-51 employs a pipelined architecture that greatly increases its instruction throughput over the standard 8051 architecture. In a standard 8051, all instructions except for MUL and DIV take 12 or 24 system
clock cycles to execute, and usually have a maximum system clock of 12 MHz. By contrast, the CIP-51
core executes 70% of its instructions in one or two system clock cycles, with no instructions taking more
than eight system clock cycles.
DATA BUS
D8
TMP2
B REGISTER
STACK POINTER
SRAM
ADDRESS
REGISTER
PSW
D8
D8
D8
ALU
SRAM
D8
D8
TMP1
ACCUMULATOR
D8
D8
D8
DATA BUS
DATA BUS
SFR_ADDRESS
BUFFER
D8
D8
DATA POINTER
D8
SFR
BUS
INTERFACE
SFR_CONTROL
SFR_WRITE_DATA
SFR_READ_DATA
DATA BUS
PC INCREMENTER
PROGRAM COUNTER (PC)
PRGM. ADDRESS REG.
PIPELINE
RESET
MEM_CONTROL
A16
MEMORY
INTERFACE
MEM_READ_DATA
SYSTEM_IRQs
D8
STOP
POWER CONTROL
REGISTER
MEM_WRITE_DATA
D8
CONTROL
LOGIC
CLOCK
IDLE
MEM_ADDRESS
D8
INTERRUPT
INTERFACE
EMULATION_IRQ
D8
Figure 8.1. CIP-51 Block Diagram
Rev. 1.3
103
C8051F93x-C8051F92x
With the CIP-51's maximum system clock at 25 MHz, it has a peak throughput of 25 MIPS. The CIP-51 has
a total of 109 instructions. The table below shows the total number of instructions that require each execution time.
Clocks to Execute
1
2
2/3
3
3/4
4
4/5
5
8
Number of Instructions
26
50
5
14
7
3
1
2
1
Programming and Debugging Support
In-system programming of the Flash program memory and communication with on-chip debug support
logic is accomplished via the Silicon Labs 2-Wire Development Interface (C2).
The on-chip debug support logic facilitates full speed in-circuit debugging, allowing the setting of hardware
breakpoints, starting, stopping and single stepping through program execution (including interrupt service
routines), examination of the program's call stack, and reading/writing the contents of registers and memory. This method of on-chip debugging is completely non-intrusive, requiring no RAM, Stack, timers, or
other on-chip resources. C2 details can be found in Section “27. C2 Interface” on page 324.
The CIP-51 is supported by development tools from Silicon Labs and third party vendors. Silicon Labs provides an integrated development environment (IDE) including editor, debugger and programmer. The IDE's
debugger and programmer interface to the CIP-51 via the C2 interface to provide fast and efficient in-system device programming and debugging. Third party macro assemblers and C compilers are also available.
8.1.
Instruction Set
The instruction set of the CIP-51 System Controller is fully compatible with the standard MCS-51™ instruction set. Standard 8051 development tools can be used to develop software for the CIP-51. All CIP-51
instructions are the binary and functional equivalent of their MCS-51™ counterparts, including opcodes,
addressing modes and effect on PSW flags. However, instruction timing is different than that of the standard 8051.
8.1.1. Instruction and CPU Timing
In many 8051 implementations, a distinction is made between machine cycles and clock cycles, with
machine cycles varying from 2 to 12 clock cycles in length. However, the CIP-51 implementation is based
solely on clock cycle timing. All instruction timings are specified in terms of clock cycles.
Due to the pipelined architecture of the CIP-51, most instructions execute in the same number of clock
cycles as there are program bytes in the instruction. Conditional branch instructions take one less clock
cycle to complete when the branch is not taken as opposed to when the branch is taken. Table 8.1 is the
CIP-51 Instruction Set Summary, which includes the mnemonic, number of bytes, and number of clock
cycles for each instruction.
104
Rev. 1.3
C8051F93x-C8051F92x
Table 8.1. CIP-51 Instruction Set Summary
Mnemonic
ADD A, Rn
ADD A, direct
ADD A, @Ri
ADD A, #data
ADDC A, Rn
ADDC A, direct
ADDC A, @Ri
ADDC A, #data
SUBB A, Rn
SUBB A, direct
SUBB A, @Ri
SUBB A, #data
INC A
INC Rn
INC direct
INC @Ri
DEC A
DEC Rn
DEC direct
DEC @Ri
INC DPTR
MUL AB
DIV AB
DA A
ANL A, Rn
ANL A, direct
ANL A, @Ri
ANL A, #data
ANL direct, A
ANL direct, #data
ORL A, Rn
ORL A, direct
ORL A, @Ri
ORL A, #data
ORL direct, A
ORL direct, #data
XRL A, Rn
XRL A, direct
XRL A, @Ri
XRL A, #data
XRL direct, A
XRL direct, #data
Description
Arithmetic Operations
Add register to A
Add direct byte to A
Add indirect RAM to A
Add immediate to A
Add register to A with carry
Add direct byte to A with carry
Add indirect RAM to A with carry
Add immediate to A with carry
Subtract register from A with borrow
Subtract direct byte from A with borrow
Subtract indirect RAM from A with borrow
Subtract immediate from A with borrow
Increment A
Increment register
Increment direct byte
Increment indirect RAM
Decrement A
Decrement register
Decrement direct byte
Decrement indirect RAM
Increment Data Pointer
Multiply A and B
Divide A by B
Decimal adjust A
Logical Operations
AND Register to A
AND direct byte to A
AND indirect RAM to A
AND immediate to A
AND A to direct byte
AND immediate to direct byte
OR Register to A
OR direct byte to A
OR indirect RAM to A
OR immediate to A
OR A to direct byte
OR immediate to direct byte
Exclusive-OR Register to A
Exclusive-OR direct byte to A
Exclusive-OR indirect RAM to A
Exclusive-OR immediate to A
Exclusive-OR A to direct byte
Exclusive-OR immediate to direct byte
Rev. 1.3
Bytes
Clock
Cycles
1
2
1
2
1
2
1
2
1
2
1
2
1
1
2
1
1
1
2
1
1
1
1
1
1
2
2
2
1
2
2
2
1
2
2
2
1
1
2
2
1
1
2
2
1
4
8
1
1
2
1
2
2
3
1
2
1
2
2
3
1
2
1
2
2
3
1
2
2
2
2
3
1
2
2
2
2
3
1
2
2
2
2
3
105
C8051F93x-C8051F92x
Table 8.1. CIP-51 Instruction Set Summary (Continued)
Mnemonic
CLR A
CPL A
RL A
RLC A
RR A
RRC A
SWAP A
MOV A, Rn
MOV A, direct
MOV A, @Ri
MOV A, #data
MOV Rn, A
MOV Rn, direct
MOV Rn, #data
MOV direct, A
MOV direct, Rn
MOV direct, direct
MOV direct, @Ri
MOV direct, #data
MOV @Ri, A
MOV @Ri, direct
MOV @Ri, #data
MOV DPTR, #data16
MOVC A, @A+DPTR
MOVC A, @A+PC
MOVX A, @Ri
MOVX @Ri, A
MOVX A, @DPTR
MOVX @DPTR, A
PUSH direct
POP direct
XCH A, Rn
XCH A, direct
XCH A, @Ri
XCHD A, @Ri
CLR C
CLR bit
SETB C
SETB bit
CPL C
CPL bit
ANL C, bit
106
Description
Clear A
Complement A
Rotate A left
Rotate A left through Carry
Rotate A right
Rotate A right through Carry
Swap nibbles of A
Data Transfer
Move Register to A
Move direct byte to A
Move indirect RAM to A
Move immediate to A
Move A to Register
Move direct byte to Register
Move immediate to Register
Move A to direct byte
Move Register to direct byte
Move direct byte to direct byte
Move indirect RAM to direct byte
Move immediate to direct byte
Move A to indirect RAM
Move direct byte to indirect RAM
Move immediate to indirect RAM
Load DPTR with 16-bit constant
Move code byte relative DPTR to A
Move code byte relative PC to A
Move external data (8-bit address) to A
Move A to external data (8-bit address)
Move external data (16-bit address) to A
Move A to external data (16-bit address)
Push direct byte onto stack
Pop direct byte from stack
Exchange Register with A
Exchange direct byte with A
Exchange indirect RAM with A
Exchange low nibble of indirect RAM with A
Boolean Manipulation
Clear Carry
Clear direct bit
Set Carry
Set direct bit
Complement Carry
Complement direct bit
AND direct bit to Carry
Rev. 1.3
Bytes
Clock
Cycles
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
1
2
1
2
2
2
2
3
2
3
1
2
2
3
1
1
1
1
1
1
2
2
1
2
1
1
1
2
2
2
1
2
2
2
2
3
2
3
2
2
2
3
3
3
3
3
3
3
2
2
1
2
2
2
1
2
1
2
1
2
2
1
2
1
2
1
2
2
C8051F93x-C8051F92x
Table 8.1. CIP-51 Instruction Set Summary (Continued)
Mnemonic
ANL C, /bit
ORL C, bit
ORL C, /bit
MOV C, bit
MOV bit, C
JC rel
JNC rel
JB bit, rel
JNB bit, rel
JBC bit, rel
ACALL addr11
LCALL addr16
RET
RETI
AJMP addr11
LJMP addr16
SJMP rel
JMP @A+DPTR
JZ rel
JNZ rel
CJNE A, direct, rel
CJNE A, #data, rel
CJNE Rn, #data, rel
CJNE @Ri, #data, rel
DJNZ Rn, rel
DJNZ direct, rel
NOP
Description
AND complement of direct bit to Carry
OR direct bit to carry
OR complement of direct bit to Carry
Move direct bit to Carry
Move Carry to direct bit
Jump if Carry is set
Jump if Carry is not set
Jump if direct bit is set
Jump if direct bit is not set
Jump if direct bit is set and clear bit
Program Branching
Absolute subroutine call
Long subroutine call
Return from subroutine
Return from interrupt
Absolute jump
Long jump
Short jump (relative address)
Jump indirect relative to DPTR
Jump if A equals zero
Jump if A does not equal zero
Compare direct byte to A and jump if not equal
Compare immediate to A and jump if not equal
Compare immediate to Register and jump if not
equal
Compare immediate to indirect and jump if not
equal
Decrement Register and jump if not zero
Decrement direct byte and jump if not zero
No operation
Rev. 1.3
Bytes
Clock
Cycles
2
2
2
2
2
2
2
3
3
3
2
2
2
2
2
2/3
2/3
3/4
3/4
3/4
2
3
1
1
2
3
2
1
2
2
3
3
3
4
5
5
3
4
3
3
2/3
2/3
4/5
3/4
3
3/4
3
4/5
2
3
1
2/3
3/4
1
107
C8051F93x-C8051F92x
Notes on Registers, Operands and Addressing Modes:
Rn—Register R0–R7 of the currently selected register bank.
@Ri—Data RAM location addressed indirectly through R0 or R1.
rel—8-bit, signed (twos complement) offset relative to the first byte of the following instruction. Used by
SJMP and all conditional jumps.
direct—8-bit internal data location’s address. This could be a direct-access Data RAM location (0x00–
0x7F) or an SFR (0x80–0xFF).
#data—8-bit constant
#data16—16-bit constant
bit—Direct-accessed bit in Data RAM or SFR
addr11—11-bit destination address used by ACALL and AJMP. The destination must be within the
same 2 kB page of program memory as the first byte of the following instruction.
addr16—16-bit destination address used by LCALL and LJMP. The destination may be anywhere within
the 8 kB program memory space.
There is one unused opcode (0xA5) that performs the same function as NOP.
All mnemonics copyrighted © Intel Corporation 1980.
108
Rev. 1.3
C8051F93x-C8051F92x
8.2.
CIP-51 Register Descriptions
Following are descriptions of SFRs related to the operation of the CIP-51 System Controller. Reserved bits
should not be set to logic l. Future product versions may use these bits to implement new features in which
case the reset value of the bit will be logic 0, selecting the feature's default state. Detailed descriptions of
the remaining SFRs are included in the sections of the data sheet associated with their corresponding system function.
SFR Definition 8.1. DPL: Data Pointer Low Byte
Bit
7
6
5
4
Name
DPL[7:0]
Type
R/W
Reset
0
0
0
0
SFR Page = All Pages; SFR Address = 0x82
Bit
Name
7:0
DPL[7:0]
3
2
1
0
0
0
0
0
Function
Data Pointer Low.
The DPL register is the low byte of the 16-bit DPTR. DPTR is used to access indirectly addressed Flash memory or XRAM.
SFR Definition 8.2. DPH: Data Pointer High Byte
Bit
7
6
5
4
Name
DPH[7:0]
Type
R/W
Reset
0
0
0
0
SFR Page = All Pages; SFR Address = 0x83
Bit
Name
7:0
DPH[7:0]
3
2
1
0
0
0
0
0
Function
Data Pointer High.
The DPH register is the high byte of the 16-bit DPTR. DPTR is used to access indirectly addressed Flash memory or XRAM.
Rev. 1.3
109
C8051F93x-C8051F92x
SFR Definition 8.3. SP: Stack Pointer
Bit
7
6
5
4
Name
SP[7:0]
Type
R/W
Reset
0
0
0
0
SFR Page = All Pages; SFR Address = 0x81
Bit
Name
7:0
SP[7:0]
3
2
1
0
0
1
1
1
Function
Stack Pointer.
The Stack Pointer holds the location of the top of the stack. The stack pointer is incremented before every PUSH operation. The SP register defaults to 0x07 after reset.
SFR Definition 8.4. ACC: Accumulator
Bit
7
6
5
4
Name
ACC[7:0]
Type
R/W
Reset
0
0
0
0
3
2
1
0
0
0
0
0
SFR Page = All Pages; SFR Address = 0xE0; Bit-Addressable
Bit
Name
Function
7:0
ACC[7:0]
Accumulator.
This register is the accumulator for arithmetic operations.
SFR Definition 8.5. B: B Register
Bit
7
6
5
4
Name
B[7:0]
Type
R/W
Reset
0
0
0
0
3
2
1
0
0
0
0
0
SFR Page = All Pages; SFR Address = 0xF0; Bit-Addressable
Bit
Name
Function
7:0
B[7:0]
B Register.
This register serves as a second accumulator for certain arithmetic operations.
110
Rev. 1.3
C8051F93x-C8051F92x
SFR Definition 8.6. PSW: Program Status Word
Bit
7
6
5
Name
CY
AC
F0
Type
R/W
R/W
R/W
Reset
0
0
0
4
3
2
1
0
RS[1:0]
OV
F1
PARITY
R/W
R/W
R/W
R
0
0
0
0
0
SFR Page = All Pages; SFR Address = 0xD0; Bit-Addressable
Bit
Name
Function
7
CY
Carry Flag.
This bit is set when the last arithmetic operation resulted in a carry (addition) or a borrow (subtraction). It is cleared to logic 0 by all other arithmetic operations.
6
AC
Auxiliary Carry Flag.
This bit is set when the last arithmetic operation resulted in a carry into (addition) or a
borrow from (subtraction) the high order nibble. It is cleared to logic 0 by all other arithmetic operations.
5
F0
User Flag 0.
This is a bit-addressable, general purpose flag for use under software control.
4:3
RS[1:0]
Register Bank Select.
These bits select which register bank is used during register accesses.
00: Bank 0, Addresses 0x00-0x07
01: Bank 1, Addresses 0x08-0x0F
10: Bank 2, Addresses 0x10-0x17
11: Bank 3, Addresses 0x18-0x1F
2
OV
Overflow Flag.
This bit is set to 1 under the following circumstances:
• An ADD, ADDC, or SUBB instruction causes a sign-change overflow.
• A MUL instruction results in an overflow (result is greater than 255).
• A DIV instruction causes a divide-by-zero condition.
The OV bit is cleared to 0 by the ADD, ADDC, SUBB, MUL, and DIV instructions in all
other cases.
1
F1
User Flag 1.
This is a bit-addressable, general purpose flag for use under software control.
0
PARITY
Parity Flag.
This bit is set to logic 1 if the sum of the eight bits in the accumulator is odd and cleared
if the sum is even.
Rev. 1.3
111
C8051F93x-C8051F92x
9.
Memory Organization
The memory organization of the CIP-51 System Controller is similar to that of a standard 8051. There are
two separate memory spaces: program memory and data memory. Program and data memory share the
same address space but are accessed via different instruction types. The memory organization of the
C8051F93x-C8051F92x device family is shown in Figure 9.1
PR OG RAM /DA TA M EM O R Y
(FLA SH)
DATA M EM O RY
(R AM )
INTERN AL DATA ADDR ESS SPACE
C8051F930/1
U pper 128 R AM
0x03FF
0x0000
0xFFFF
Scrachpad M em ory
(D ATA only)
R ESER VED
0xFC00
0xFBFF
64KB FLASH
(In-System
Program m able in 1024
Byte Sectors)
Special Function
R egisters
(Indirect Addressing O nly) (D irect Addressing O nly)
(D irect and Indirect
Addressing)
Bit Addressable
G eneral Purpose
R egisters
0x0000
Low er 128 RAM
(D irect and Indirect
Addressing)
EXTERNAL DATA ADDR ESS SPACE
C8051F920/1
0x03FF
0x0000
0x1FFF
Scrachpad M em ory
(D ATA only)
O ff-chip XR AM space
(only available on 32-pin
devices)
0x7FFF
0x1000
32KB FLASH
0x0FFF
(In-System
Program m able in 1024
Byte Sectors)
XR AM - 4096 Bytes
(accessable using M O VX
instruction)
0x0000
0x0000
Figure 9.1. C8051F93x-C8051F92x Memory Map
112
0
Rev. 1.3
F
C8051F93x-C8051F92x
9.1.
Program Memory
The CIP-51 core has a 64 kB program memory space. The C8051F93x-C8051F92x implements 64 kB
(C8051F930/1) or 32 kB (C8051F920/1) of this program memory space as in-system, re-programmable
Flash memory, organized in a contiguous block from addresses 0x0000 to 0xFBFF (C8051F930/1) or
0x7FFF (C8051F920/1). The address 0xFBFF (C8051F930/1) or 0x7FFF (C8051F920/1) serves as the
security lock byte for the device. Any addresses above the lock byte are reserved.
C8051F930/1
(SFLE=0)
C8051F920/1
(SFLE=0)
0xFFFF
0xFFFF
Reserved Area
0xFBFF
0xFBFE
Lock Byte Page
Unpopulated
Address Space
(Reserved)
0xF800
0xF7FF
0x8000
Lock Byte
C8051F930/1
C8051F920/1
(SFLE=1)
0x7FFE
Lock Byte Page
Flash Memory Space
0x7C00
0x7BFF
0x03FF
Scratchpad
(Data Only)
0x7FFF
0x0000
FLASH memory organized in
1024-byte pages
0xFC00
Lock Byte
Flash Memory Space
0x0000
0x0000
Figure 9.2. Flash Program Memory Map
9.1.1. MOVX Instruction and Program Memory
The MOVX instruction in an 8051 device is typically used to access external data memory. On the
C8051F93x-C8051F92x devices, the MOVX instruction is normally used to read and write on-chip XRAM,
but can be re-configured to write and erase on-chip Flash memory space. MOVC instructions are always
used to read Flash memory, while MOVX write instructions are used to erase and write Flash. This Flash
access feature provides a mechanism for the C8051F93x-C8051F92x to update program code and use
the program memory space for non-volatile data storage. Refer to Section “13. Flash Memory” on
page 148 for further details.
Rev. 1.3
113
C8051F93x-C8051F92x
9.2.
Data Memory
The C8051F93x-C8051F92x device family includes 4352 bytes of RAM data memory. 256 bytes of this
memory is mapped into the internal RAM space of the 8051. 4096 bytes of this memory is on-chip “external” memory. The data memory map is shown in Figure 9.1 for reference.
9.2.1. Internal RAM
There are 256 bytes of internal RAM mapped into the data memory space from 0x00 through 0xFF. The
lower 128 bytes of data memory are used for general purpose registers and scratch pad memory. Either
direct or indirect addressing may be used to access the lower 128 bytes of data memory. Locations 0x00
through 0x1F are addressable as four banks of general purpose registers, each bank consisting of eight
byte-wide registers. The next 16 bytes, locations 0x20 through 0x2F, may either be addressed as bytes or
as 128 bit locations accessible with the direct addressing mode.
The upper 128 bytes of data memory are accessible only by indirect addressing. This region occupies the
same address space as the Special Function Registers (SFR) but is physically separate from the SFR
space. The addressing mode used by an instruction when accessing locations above 0x7F determines
whether the CPU accesses the upper 128 bytes of data memory space or the SFRs. Instructions that use
direct addressing will access the SFR space. Instructions using indirect addressing above 0x7F access the
upper 128 bytes of data memory. Figure 9.1 illustrates the data memory organization of the C8051F93xC8051F92x.
9.2.1.1. General Purpose Registers
The lower 32 bytes of data memory, locations 0x00 through 0x1F, may be addressed as four banks of general-purpose registers. Each bank consists of eight byte-wide registers designated R0 through R7. Only
one of these banks may be enabled at a time. Two bits in the program status word, RS0 (PSW.3) and RS1
(PSW.4), select the active register bank (see description of the PSW in SFR Definition 8.6). This allows
fast context switching when entering subroutines and interrupt service routines. Indirect addressing modes
use registers R0 and R1 as index registers.
9.2.1.2. Bit Addressable Locations
In addition to direct access to data memory organized as bytes, the sixteen data memory locations at 0x20
through 0x2F are also accessible as 128 individually addressable bits. Each bit has a bit address from
0x00 to 0x7F. Bit 0 of the byte at 0x20 has bit address 0x00 while bit7 of the byte at 0x20 has bit address
0x07. Bit 7 of the byte at 0x2F has bit address 0x7F. A bit access is distinguished from a full byte access by
the type of instruction used (bit source or destination operands as opposed to a byte source or destination).
The MCS-51™ assembly language allows an alternate notation for bit addressing of the form XX.B where
XX is the byte address and B is the bit position within the byte. For example, the instruction:
MOV
C, 22.3h
moves the Boolean value at 0x13 (bit 3 of the byte at location 0x22) into the Carry flag.
114
Rev. 1.3
C8051F93x-C8051F92x
9.2.1.3. Stack
A programmer's stack can be located anywhere in the 256-byte data memory. The stack area is designated using the Stack Pointer (SP) SFR. The SP will point to the last location used. The next value pushed
on the stack is placed at SP+1 and then SP is incremented. A reset initializes the stack pointer to location
0x07. Therefore, the first value pushed on the stack is placed at location 0x08, which is also the first register (R0) of register bank 1. Thus, if more than one register bank is to be used, the SP should be initialized
to a location in the data memory not being used for data storage. The stack depth can extend up to
256 bytes.
9.2.2. External RAM
There are 4096 bytes of on-chip RAM mapped into the external data memory space. All of these address
locations may be accessed using the external move instruction (MOVX) and the data pointer (DPTR), or
using MOVX indirect addressing mode (such as @R1) in combination with the EMI0CN register. Additional
off-chip memory or memory-mapped devices may be mapped to the external memory address space and
accessed using the external memory interface. See Section “10. External Data Memory Interface and OnChip XRAM” on page 116 for further details.
Rev. 1.3
115
C8051F93x-C8051F92x
10. External Data Memory Interface and On-Chip XRAM
The C8051F92x-C8051F93x MCUs include on-chip RAM mapped into the external data memory space
(XRAM). 32-pin devices (C8051F930 and C8051F920) also have an External Data Memory Interface
which can be used to access off-chip memories and memory-mapped devices connected to the GPIO
ports. The external memory space may be accessed using the external move instruction (MOVX) with the
target address specified in either the data pointer (DPTR), or with the target address low byte in R0 or R1
and the target address high byte in the External Memory Interface Control Register (EMI0CN, shown in
SFR Definition 10.1).
When using the MOVX instruction to access on-chip RAM, no additional initialization is required and the
MOVX instruction execution time is as specified in the CIP-51 chapter. When using the MOVX instruction
to access off-chip RAM or memory-mapped devices, then both the Port I/O and EMIF should be configured
for communication with external devices (See Section 10.2) and MOVX instruction timing is based on the
value programmed in the External Memory Interface Timing Control Register (EMI0TC, see “External
Memory Interface Timing” on page 121).
Important Note: MOVX write operations can be configured to target Flash memory, instead of XRAM. See
Section “13. Flash Memory” on page 148 for more details. The MOVX instruction accesses XRAM by
default.
10.1. Accessing XRAM
The XRAM memory space is accessed using the MOVX instruction. The MOVX instruction has two forms,
both of which use an indirect addressing method. The first method uses the Data Pointer, DPTR, a 16-bit
register which contains the effective address of the XRAM location to be read from or written to. The
second method uses R0 or R1 in combination with the EMI0CN register to generate the effective XRAM
address. Examples of both of these methods are given below.
10.1.1. 16-Bit MOVX Example
The 16-bit form of the MOVX instruction accesses the memory location pointed to by the contents of the
DPTR register. The following series of instructions reads the value of the byte at address 0x1234 into the
accumulator A:
MOV
MOVX
DPTR, #1234h
A, @DPTR
; load DPTR with 16-bit address to read (0x1234)
; load contents of 0x1234 into accumulator A

The above example uses the 16-bit immediate MOV instruction to set the contents of DPTR. Alternately,
the DPTR can be accessed through the SFR registers DPH, which contains the upper 8-bits of DPTR, and
DPL, which contains the lower 8-bits of DPTR.
10.1.2. 8-Bit MOVX Example
The 8-bit form of the MOVX instruction uses the contents of the EMI0CN SFR to determine the upper 8-bits
of the effective address to be accessed and the contents of R0 or R1 to determine the lower 8-bits of the
effective address to be accessed. The following series of instructions read the contents of the byte at
address 0x1234 into the accumulator A.
MOV
MOV
MOVX
116
EMI0CN, #12h
R0, #34h
a, @R0
; load high byte of address into EMI0CN
; load low byte of address into R0 (or R1)
; load contents of 0x1234 into accumulator A
Rev. 1.3
C8051F93x-C8051F92x
10.2. Configuring the External Memory Interface for Off-Chip Access
Configuring the External Memory Interface for off-chip memory space access consists of four steps:
1. Configure the Output Modes of the associated port pins as either push-pull or open-drain
(push-pull is most common) and skip the associated pins in the Crossbar (if necessary).
See Section “21. Port Input/Output” on page 216 to determine which port pins are associated
with the External Memory Interface.
2. Configure port latches to “park” the EMIF pins in a dormant state (usually by setting them to
logic 1).
3. Select the memory mode (on-chip only, split mode without bank select, split mode with bank
select, or off-chip only).
4. Set up timing to interface with off-chip memory or peripherals.
Each of these five steps is explained in detail in the following sections. The configuration selection bits are
located in the EMI0CF register shown in SFR Definition 10.2.
10.3. External Memory Interface Port Input/Output Configuration
When the External Memory Interface is used for off-chip access, the associated port pins are shared
between the EMIF and the GPIO port latches. The Crossbar should be configured not to assign any
signals to the associated port pins. In most configurations, the RD, WR, and ALE pins need to be skipped
in the Crossbar to ensure they are controlled by their port latches. See Section “21. Port Input/Output” on
page 216 to determine which port pins are associated with the External Memory Interface.
The External Memory Interface claims the associated Port pins for memory operations ONLY during the
execution of an off-chip MOVX instruction. Once the MOVX instruction has completed, control of the Port
pins reverts to the Port latches. The Port latches should be explicitly configured to “park” the
External Memory Interface pins in a dormant state, most commonly by setting them to a logic 1.
During the execution of the MOVX instruction, the External Memory Interface will explicitly disable the
drivers on all Port pins that are acting as Inputs (Data[7:0] during a READ operation, for example). For port
pins acting as Outputs (Data[7:0] during a WRITE operation, for example), the External memory interface
will not automatically enable the output driver. The output mode (whether the pin is configured as OpenDrain or Push-Pull) of bi-directional and output only pins should be configured to the desired mode when
the pin is being used as an output.
The Output mode of the Port pins while controlled by the GPIO latch is unaffected by the External Memory
Interface operation, and remains controlled by the PnMDOUT registers. In most cases, the output
modes of all EMIF pins should be configured for push-pull mode.
Rev. 1.3
117
C8051F93x-C8051F92x
10.4. Multiplexed External Memory Interface
For a Multiplexed external memory interface, the Data Bus and the lower 8-bits of the Address Bus share
the same Port pins: AD[7:0]. For most devices with an 8-bit interface, the upper address bits are not used
and can be used as GPIO if the external memory interface is used in 8-bit non-banked mode. If the
external memory interface is used in 8-bit banked mode, or 16-bit mode, then the address pins will be
driven with the upper 4 address bits and cannot be used as GPIO.
GPIO (4-bit)
E
M
I
F
A[11:8]
LEDs/Switches
ADDRESS BUS (12-bit or 8-bit)
VDD
(Optional)
Ethernet
Controller
(8-bit Interface)
8
AD[7:0]
DATA BUS
AD[7:0]
CS
WR
RD
ALE
WR
RD
ALE
Figure 10.1. Multiplexed Configuration Example
Many devices with a slave parallel memory interface, such as SRAM chips, only support a non-multiplexed
memory bus. When interfacing to such a device, an external latch (74HC373 or equivalent logic gate) can
be used to hold the lower 8-bits of the RAM address during the second half of the memory cycle when the
address/data bus contains data. The external latch, controlled by the ALE (Address Latch Enable) signal,
is automatically driven by the External Memory Interface logic. An example SRAM interface showing
multiplexed to non-multiplexed conversion is shown in Figure 10.2.
This example is showing that the external MOVX operation can be broken into two phases delineated by
the state of the ALE signal. During the first phase, ALE is high and the lower 8-bits of the Address Bus are
presented to AD[7:0]. During this phase, the address latch is configured such that the Q outputs reflect the
states of the D inputs. When ALE falls, signaling the beginning of the second phase, the address latch
outputs remain fixed and are no longer dependent on the latch inputs. Later in the second phase, the Data
Bus controls the state of the AD[7:0] port at the time RD or WR is asserted.
See Section “10.6. External Memory Interface Timing” on page 121 for detailed timing diagrams.
118
Rev. 1.3
C8051F93x-C8051F92x
A[11:8]
ADDRESS BUS
A[11:8]
74HC373
E
M
I
F
ALE
AD[7:0]
G
D
ADDRESS/DATA BUS
Q
A[7:0]
VDD
4K X 8
SRAM
(Optional)
8
I/O[7:0]
CE
WE
OE
WR
RD
Figure 10.2. Multiplexed to Non-Multiplexed Configuration Example
Rev. 1.3
119
C8051F93x-C8051F92x
10.5. External Memory Interface Operating Modes
The external data memory space can be configured in one of four operating modes, shown in Figure 10.3,
based on the EMIF Mode bits in the EMI0CF register (SFR Definition 10.2). These modes are summarized
below. Timing diagrams for the different modes can be found in Section “10.6. External Memory Interface
Timing” on page 121.
10.5.1. Internal XRAM Only
When EMI0CF.[3:2] are set to 00, all MOVX instructions will target the internal XRAM space on the device.
Memory accesses to addresses beyond the populated space will wrap, and will always target on-chip
XRAM. As an example, if the entire address space is consecutively written and the data pointer is
incremented after each write, the write pointer will always point to the first byte of on-chip XRAM after the
last byte of on-chip XRAM has been written.
•
8-bit MOVX operations use the contents of EMI0CN to determine the high-byte of the effective address
and R0 or R1 to determine the low-byte of the effective address.
16-bit MOVX operations use the contents of the 16-bit DPTR to determine the effective address.
•
10.5.2. Split Mode without Bank Select
When EMI0CF.[3:2] are set to 01, the XRAM memory map is split into two areas, on-chip space and offchip space.
•
•
•
Effective addresses below the on-chip XRAM boundary will access on-chip XRAM space.
Effective addresses above the on-chip XRAM boundary will access off-chip space.
8-bit MOVX operations use the contents of EMI0CN to determine whether the memory access is onchip or off-chip. However, in the “No Bank Select” mode, an 8-bit MOVX operation will not drive the
upper 4-bits A[11:8] of the Address Bus during an off-chip access. This allows the user to manipulate the upper address bits at will by setting the Port state directly via the port latches. This behavior
is in contrast with “Split Mode with Bank Select” described below. The lower 8-bits of the Address Bus
A[7:0] are driven, determined by R0 or R1.
16-bit MOVX operations use the contents of DPTR to determine whether the memory access is onchip or off-chip, and unlike 8-bit MOVX operations, the full 12-bits of the Address Bus A[11:0] are
driven during the off-chip transaction.
•
EMI0CF[3:2] = 00
EMI0CF[3:2] = 01
0xFFFF
EMI0CF[3:2] = 10
EMI0CF[3:2] = 11
0xFFFF
0xFFFF
0xFFFF
On-Chip XRAM
On-Chip XRAM
Off-Chip
Memory
(No Bank Select)
On-Chip XRAM
Off-Chip
Memory
(Bank Select)
Off-Chip
Memory
On-Chip XRAM
On-Chip XRAM
On-Chip XRAM
On-Chip XRAM
0x0000
On-Chip XRAM
0x0000
0x0000
Figure 10.3. EMIF Operating Modes
120
Rev. 1.3
0x0000
C8051F93x-C8051F92x
10.5.3. Split Mode with Bank Select
When EMI0CF.[3:2] are set to 10, the XRAM memory map is split into two areas, on-chip space and offchip space.
•
•
•
•
Effective addresses below the on-chip XRAM boundary will access on-chip XRAM space.
Effective addresses above the on-chip XRAM boundary will access off-chip space.
8-bit MOVX operations use the contents of EMI0CN to determine whether the memory access is onchip or off-chip. The upper 4-bits of the Address Bus A[11:8] are determined by EMI0CN, and the lower
8-bits of the Address Bus A[7:0] are determined by R0 or R1. All 12-bits of the Address Bus A[11:0]
are driven in “Bank Select” mode.
16-bit MOVX operations use the contents of DPTR to determine whether the memory access is onchip or off-chip, and the full 12-bits of the Address Bus A[11:0] are driven during the off-chip transaction.
10.5.4. External Only
When EMI0CF[3:2] are set to 11, all MOVX operations are directed to off-chip space. On-chip XRAM is not
visible to the CPU. This mode is useful for accessing off-chip memory located between 0x0000 and the onchip XRAM boundary.
•
•
8-bit MOVX operations ignore the contents of EMI0CN. The upper Address bits A[11:8] are not driven
(identical behavior to an off-chip access in “Split Mode without Bank Select” described above). This
allows the user to manipulate the upper address bits at will by setting the Port state directly. The lower
8-bits of the effective address A[7:0] are determined by the contents of R0 or R1.
16-bit MOVX operations use the contents of DPTR to determine the effective address A[11:0]. The full
12-bits of the Address Bus A[11:0] are driven during the off-chip transaction.
10.6. External Memory Interface Timing
The timing parameters of the External Memory Interface can be configured to enable connection to
devices having different setup and hold time requirements. The Address Setup time, Address Hold time,
RD and WR strobe widths, and in multiplexed mode, the width of the ALE pulse are all programmable in
units of SYSCLK periods through EMI0TC, shown in SFR Definition 10.3, and EMI0CF[1:0].
The timing for an off-chip MOVX instruction can be calculated by adding 4 SYSCLK cycles to the timing
parameters defined by the EMI0TC register. Assuming non-multiplexed operation, the minimum execution
time for an off-chip XRAM operation is 5 SYSCLK cycles (1 SYSCLK for RD or WR pulse + 4 SYSCLKs).
For multiplexed operations, the Address Latch Enable signal will require a minimum of 2 additional
SYSCLK cycles. Therefore, the minimum execution time of an off-chip XRAM operation in multiplexed
mode is 7 SYSCLK cycles (2 SYSCLKs for ALE, 1 for RD or WR + 4 SYSCLKs). The programmable setup
and hold times default to the maximum delay settings after a reset.
Table 10.1 lists the ac parameters for the External Memory Interface, and Figure 10.1 through Figure 10.6
show the timing diagrams for the different External Memory Interface modes and MOVX operations. See
Section “21. Port Input/Output” on page 216 to determine which port pins are mapped to the ADDR[11:8],
AD[7:0], ALE, RD, and WR signals.
Rev. 1.3
121
C8051F93x-C8051F92x
10.7. EMIF Special Function Registers
The special function registers used by the EMIF are EMI0CN, EMI0CF, and EMI0TC. These registers are
described in the following register descriptions.
SFR Definition 10.1. EMI0CN: External Memory Interface Control
Bit
7
6
5
4
3
2
1
0
PGSEL[4:0]
Name
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
SFR Page = 0x0; SFR Address = 0xAA
Bit
Name
7:5
Unused
Function
Unused.
Read = 000b; Write = Don’t Care
4:0
PGSEL
XRAM Page Select.
The EMI0CN register provides the high byte of the 16-bit external data memory
address when using an 8-bit MOVX command, effectively selecting a 256-byte page
of RAM. Since the upper (unused) bits of the register are always zero, the PGSEL
determines which page of XRAM is accessed. When the MSB of PGSEL is set to 1
and the EMIF is configured for one of the two split-modes, 8-bit MOVX instructions
target off-chip memory.
For Example:
If EMI0CN = 0x01, addresses 0x0100 through 0x01FF of on-chip memory will be
accessed.
If EMI0CN = 0x0F, addresses 0x0F00 through 0x0FFF of on-chip memory will be
accessed.
If EMI0CN = 0x11, addresses 0x0100 through 0x01FF of off-chip memory will be
accessed.
If EMI0CN = 0x1F, addresses 0x0F00 through 0x0FFF of off-chip memory will be
accessed.
122
Rev. 1.3
C8051F93x-C8051F92x
SFR Definition 10.2. EMI0CF: External Memory Configuration
Bit
7
6
5
4
3
2
1
EMD[1:0]
Name
0
EALE[1:0]
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
1
1
SFR Page = 0x0; SFR Address = 0xAB
Bit
Name
7:4
Unused
3:2
EMD
Function
Unused.
Read = 0000b. Write = Don’t Care.
EMIF Operating Mode Select.
Selects the operating mode of the External Memory Interface. See Section
“10.5. External Memory Interface Operating Modes” on page 120.
00: Internal Only.
01: Split Mode without Bank Select.
10: Split Mode with Bank Select.
11: External Only.
1:0
EALE
ALE Pulse Width Select Bits.
Selects the ALE pulse width.
00: ALE high and ALE low pulse width = 1 SYSCLK cycle.
01: ALE high and ALE low pulse width = 2 SYSCLK cycles.
10: ALE high and ALE low pulse width = 3 SYSCLK cycles.
11: ALE high and ALE low pulse width = 4 SYSCLK cycles.
Rev. 1.3
123
C8051F93x-C8051F92x
SFR Definition 10.3. EMI0TC: External Memory Timing Control
Bit
7
6
5
4
EAS[1:0]
Name
3
2
1
EWR[3:0]
0
EAH[1:0]
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
1
1
1
1
1
1
1
1
SFR Page = 0x0; SFR Address = 0xAF
Bit
Name
7:4
EAS
Address Setup Time Select Bits.
EWR
RD and WR Pulse Width Select.
3:2
Function
Controls the timing parameter TACS.
00: Address Setup Time = 0 SYSCLK cycles.
01: Address Setup Time = 1 SYSCLK cycles.
10: Address Setup Time = 2 SYSCLK cycles.
11: Address Setup Time = 3 SYSCLK cycles.
Controls the timing parameter TACW.
0000: WR and RD pulse width = 1 SYSCLK cycle.
0001: WR and RD pulse width = 2 SYSCLK cycles.
0010: WR and RD pulse width = 3 SYSCLK cycles.
0011: WR and RD pulse width = 4 SYSCLK cycles.
0100: WR and RD pulse width = 5 SYSCLK cycles.
0101: WR and RD pulse width = 6 SYSCLK cycles.
0110: WR and RD pulse width = 7 SYSCLK cycles.
0111: WR and RD pulse width = 8 SYSCLK cycles.
1000: WR and RD pulse width = 9 SYSCLK cycles.
1001: WR and RD pulse width = 10 SYSCLK cycles.
1010: WR and RD pulse width = 11 SYSCLK cycles.
1011: WR and RD pulse width = 12 SYSCLK cycles.
1100: WR and RD pulse width = 13 SYSCLK cycles.
1101: WR and RD pulse width = 14 SYSCLK cycles.
1110: WR and RD pulse width = 15 SYSCLK cycles.
1111: WR and RD pulse width = 16 SYSCLK cycles.
1:0
EAH
Address Hold Time Select Bits.
Controls the timing parameter TACH.
00: Address Hold Time = 0 SYSCLK cycles.
01: Address Hold Time = 1 SYSCLK cycles.
10: Address Hold Time = 2 SYSCLK cycles.
11: Address Hold Time = 3 SYSCLK cycles.
124
Rev. 1.3
C8051F93x-C8051F92x
10.8. EMIF Timing Diagrams
10.8.1. Multiplexed 16-bit MOVX: EMI0CF[3:2] = 01, 10, or 11
Muxed 16-bit WRITE
ADDR[11:8]
AD[7:0]
EMIF ADDRESS (4 MSBs) from DPH
EMIF ADDRESS (8 LSBs) from
DPL
T
ALEH
ADDR[11:8]
EMIF WRITE DATA
AD[7:0]
T
ALEL
ALE
ALE
T
T
WDS
T
ACS
WDH
T
T
ACW
ACH
/WR
/WR
/RD
/RD
Muxed 16-bit READ
ADDR[11:8]
AD[7:0]
EMIF ADDRESS (4 MSBs) from DPH
EMIF ADDRESS (8 LSBs) from
DPL
T
ALEH
ADDR[11:8]
EMIF READ DATA
T
T
ALEL
RDS
AD[7:0]
T
RDH
ALE
ALE
T
ACS
T
ACW
T
ACH
/RD
/RD
/WR
/WR
Note: See the Port Input/Output chapter to determine which port pins are mapped to the
ADDR[11:8], AD[7:0], ALE, /RD, and /WR signals.
Figure 10.4. Multiplexed 16-bit MOVX Timing
Rev. 1.3
125
C8051F93x-C8051F92x
10.8.2. Multiplexed 8-bit MOVX without Bank Select: EMI0CF[3:2] = 01 or 11.
Muxed 8-bit WRITE Without Bank Select
ADDR[11:8]
AD[7:0]
ADDR[11:8]
Port Latch Controlled (GPIO)
EMIF ADDRESS (8 LSBs) from
R0 or R1
T
ALEH
EMIF WRITE DATA
AD[7:0]
T
ALEL
ALE
ALE
T
T
WDS
T
ACS
WDH
T
T
ACW
ACH
/WR
/WR
/RD
/RD
Muxed 8-bit READ Without Bank Select
ADDR[11:8]
AD[7:0]
ADDR[11:8]
Port Latch Controlled (GPIO)
EMIF ADDRESS (8 LSBs) from
R0 or R1
T
ALEH
EMIF READ DATA
T
T
ALEL
RDS
T
RDH
ALE
ALE
T
ACS
T
ACW
T
ACH
/RD
/RD
/WR
/WR
Note: See the Port Input/Output chapter to determine which port pins are mapped to the
ADDR[11:8], AD[7:0], ALE, /RD, and /WR signals.
Figure 10.5. Multiplexed 8-bit MOVX without Bank Select Timing
126
AD[7:0]
Rev. 1.3
C8051F93x-C8051F92x
10.8.2.1.Multiplexed 8-bit MOVX with Bank Select: EMI0CF[3:2] = 10.
Muxed 8-bit WRITE with Bank Select
ADDR[11:8]
AD[7:0]
EMIF ADDRESS (4 MSBs) from EMI0CN
EMIF ADDRESS (8 LSBs) from
R0 or R1
T
ALEH
ADDR[11:8]
EMIF WRITE DATA
AD[7:0]
T
ALEL
ALE
ALE
T
T
WDS
T
ACS
WDH
T
T
ACW
ACH
/WR
/WR
/RD
/RD
Muxed 8-bit READ with Bank Select
ADDR[11:8]
AD[7:0]
EMIF ADDRESS (4 MSBs) from EMI0CN
EMIF ADDRESS (8 LSBs) from
R0 or R1
T
ALEH
ADDR[11:8]
EMIF READ DATA
T
T
ALEL
RDS
AD[7:0]
T
RDH
ALE
ALE
T
ACS
T
ACW
T
ACH
/RD
/RD
/WR
/WR
Note: See the Port Input/Output chapter to determine which port pins are mapped to the
ADDR[11:8], AD[7:0], ALE, /RD, and /WR signals.
Figure 10.6. Multiplexed 8-bit MOVX with Bank Select Timing
Rev. 1.3
127
C8051F93x-C8051F92x
Table 10.1. AC Parameters for External Memory Interface
Parameter
Description
Min
Max
Units
TACS
Address/Control Setup Time
0
3 x TSYSCLK
ns
TACW
Address/Control Pulse Width
1 x TSYSCLK
16 x TSYSCLK
ns
TACH
Address/Control Hold Time
0
3 x TSYSCLK
ns
TALEH
Address Latch Enable High Time
1 x TSYSCLK
4 x TSYSCLK
ns
TALEL
Address Latch Enable Low Time
1 x TSYSCLK
4 x TSYSCLK
ns
TWDS
Write Data Setup Time
1 x TSYSCLK
19 x TSYSCLK
ns
TWDH
Write Data Hold Time
0
3 x TSYSCLK
ns
TRDS
Read Data Setup Time
20
—
ns
TRDH
Read Data Hold Time
0
—
ns
Note: TSYSCLK is equal to one period of the device system clock (SYSCLK).
128
Rev. 1.3
C8051F93x-C8051F92x
11. Special Function Registers
The direct-access data memory locations from 0x80 to 0xFF constitute the special function registers
(SFRs). The SFRs provide control and data exchange with the C8051F93x-C8051F92x's resources and
peripherals. The CIP-51 controller core duplicates the SFRs found in a typical 8051 implementation as well
as implementing additional SFRs used to configure and access the sub-systems unique to the
C8051F93x-C8051F92x. This allows the addition of new functionality while retaining compatibility with the
MCS-51™ instruction set. Table 11.1 and Table 11.2 list the SFRs implemented in the C8051F93xC8051F92x device family.
The SFR registers are accessed anytime the direct addressing mode is used to access memory locations
from 0x80 to 0xFF. SFRs with addresses ending in 0x0 or 0x8 (e.g. P0, TCON, SCON0, IE, etc.) are bitaddressable as well as byte-addressable. All other SFRs are byte-addressable only. Unoccupied
addresses in the SFR space are reserved for future use. Accessing these areas will have an indeterminate
effect and should be avoided. Refer to the corresponding pages of the data sheet, as indicated in
Table 11.3, for a detailed description of each register.
Table 11.1. Special Function Register (SFR) Memory Map (Page 0x0)
F8
F0
E8
E0
D8
D0
C8
C0
B8
B0
A8
A0
98
90
88
80
SPI0CN
PCA0L
PCA0H PCA0CPL0 PCA0CPH0
B
P0MDIN
P1MDIN
P2MDIN SMB0ADR
ADC0CN PCA0CPL1 PCA0CPH1 PCA0CPL2 PCA0CPH2
ACC
XBR0
XBR1
XBR2
IT01CF
PCA0CN PCA0MD PCA0CPM0 PCA0CPM1 PCA0CPM2
PSW
REF0CN PCA0CPL5 PCA0CPH5 P0SKIP
TMR2CN REG0CN TMR2RLL TMR2RLH
TMR2L
SMB0CN SMB0CF SMB0DAT ADC0GTL ADC0GTH
IP
IREF0CN ADC0AC ADC0MX
ADC0CF
SPI1CN OSCXCN OSCICN
OSCICL
IE
CLKSEL
EMI0CN
EMI0CF RTC0ADR
P2
SPI0CFG SPI0CKR SPI0DAT P0MDOUT
SCON0
SBUF0
CPT1CN
CPT0CN
CPT1MD
P1
TMR3CN TMR3RLL TMR3RLH
TMR3L
TCON
TMOD
TL0
TL1
TH0
P0
SP
DPL
DPH
SPI1CFG
0(8)
1(9)
2(A)
3(B)
4(C)
(bit addressable)
Rev. 1.3
PCA0CPL4
SMB0ADM
PCA0CPL3
PCA0CPM3
P1SKIP
TMR2H
ADC0LTL
ADC0L
PMU0CF
RTC0DAT
P1MDOUT
CPT0MD
TMR3H
TH1
SPI1CKR
5(D)
PCA0CPH4 VDM0CN
EIP1
EIP2
PCA0CPH3 RSTSRC
EIE1
EIE2
PCA0CPM4 PCA0PWM
P2SKIP
P0MAT
PCA0CPM5
P1MAT
ADC0LTH
P0MASK
ADC0H
P1MASK
FLSCL
FLKEY
RTC0KEY
EMI0TC
P2MDOUT SFRPAGE
CPT1MX
CPT0MX
DC0CF
DC0CN
CKCON
PSCTL
SPI1DAT
PCON
6(E)
7(F)
129
C8051F93x-C8051F92x
11.1. SFR Paging
To accommodate more than 128 SFRs in the 0x80 to 0xFF address space, SFR paging has been
implemented. By default, all SFR accesses target SFR Page 0x0 to allow access to the registers listed in
Table 11.1. During device initialization, some SFRs located on SFR Page 0xF may need to be accessed.
Table 11.2 lists the SFRs accessible from SFR Page 0x0F. Some SFRs are accessible from both pages,
including the SFRPAGE register. SFRs accessible only from Page 0xF are in bold.
The following procedure should be used when accessing SFRs from Page 0xF:
Step 1.
Step 2.
Step 3.
Step 4.
Step 5.
Step 6.
Save the current interrupt state (EA_save = EA).
Disable Interrupts (EA = 0).
Set SFRPAGE = 0xF.
Access the SFRs located on SFR Page 0xF.
Set SFRPAGE = 0x0.
Restore interrupt state (EA = EA_save).
Table 11.2. Special Function Register (SFR) Memory Map (Page 0xF)
F8
F0
E8
E0
D8
D0
C8
C0
B8
B0
A8
A0
98
90
88
80
B
EIP1
EIP2
ACC
EIE1
EIE2
P2DRV
SFRPAGE
PSW
ADC0PWR
IE
P2
CLKSEL
P1
CRC0DAT
P0DRV
P0
SP
0(8)
1(9)
(bit addressable)
130
ADC0TK
P1DRV
CRC0CN
CRC0IN
CRC0FLIP
DPL
2(A)
DPH
3(B)
TOFFL
5(D)
4(C)
Rev. 1.3
CRC0AUTO CRC0CNT
TOFFH
6(E)
PCON
7(F)
C8051F93x-C8051F92x
SFR Definition 11.1. SFR Page: SFR Page
Bit
7
6
5
4
3
Name
SFRPAGE[7:0]
Type
R/W
Reset
0
0
0
0
SFR Page = All Pages; SFR Address = 0xA7
Bit
Name
0
2
1
0
0
0
0
Function
7:0 SFRPAGE[7:0] SFR Page.
Specifies the SFR Page used when reading, writing, or modifying special function
registers.
Table 11.3. Special Function Registers
SFRs are listed in alphabetical order. All undefined SFR locations are reserved
Register
Address
SFR Page
Description
ACC
0xE0
All
Accumulator
110
ADC0AC
0xBA
0x0
ADC0 Accumulator Configuration
77
ADC0CF
0xBC
0x0
ADC0 Configuration
76
ADC0CN
0xE8
0x0
ADC0 Control
75
ADC0GTH
0xC4
0x0
ADC0 Greater-Than Compare High
81
ADC0GTL
0xC3
0x0
ADC0 Greater-Than Compare Low
81
ADC0H
0xBE
0x0
ADC0 High
80
ADC0L
0xBD
0x0
ADC0 Low
80
ADC0LTH
0xC6
0x0
ADC0 Less-Than Compare Word High
82
ADC0LTL
0xC5
0x0
ADC0 Less-Than Compare Word Low
82
ADC0MX
0xBB
0x0
AMUX0 Channel Select
85
ADC0PWR
0xBA
0xF
ADC0 Burst Mode Power-Up Time
78
ADC0TK
0xBD
0xF
ADC0 Tracking Control
79
B
0xF0
All
B Register
110
CKCON
0x8E
0x0
Clock Control
284
CLKSEL
0xA9
All
Clock Select
197
CPT0CN
0x9B
0x0
Comparator0 Control
97
CPT0MD
0x9D
0x0
Comparator0 Mode Selection
97
CPT0MX
0x9F
0x0
Comparator0 Mux Selection
101
CPT1CN
0x9A
0x0
Comparator1 Control
98
Rev. 1.3
Page
131
C8051F93x-C8051F92x
Table 11.3. Special Function Registers (Continued)
SFRs are listed in alphabetical order. All undefined SFR locations are reserved
Register
Address
SFR Page
CPT1MD
0x9C
0x0
Comparator1 Mode Selection
99
CPT1MX
0x9E
0x0
Comparator1 Mux Selection
102
CRC0AUTO
0x96
0xF
CRC0 Automatic Control
173
CRC0CN
0x92
0xF
CRC0 Control
171
CRC0CNT
0x97
0xF
CRC0 Automatic Flash Sector Count
173
CRC0DAT
0x91
0xF
CRC0 Data
172
CRC0FLIP
0x95
0xF
CRC0 Flip
174
CRC0IN
0x93
0xF
CRC0 Input
172
DC0CF
0x96
0x0
DC0 (DC-DC Converter) Configuration
182
DC0CN
0x97
0x0
DC0 (DC-DC Converter) Control
181
DPH
0x83
All
Data Pointer High
109
DPL
0x82
All
Data Pointer Low
109
EIE1
0xE6
All
Extended Interrupt Enable 1
142
EIE2
0xE7
All
Extended Interrupt Enable 2
144
EIP1
0xF6
0x0
Extended Interrupt Priority 1
143
EIP2
0xF7
0x0
Extended Interrupt Priority 2
145
EMI0CF
0xAB
0x0
EMIF Configuration
123
EMI0CN
0xAA
0x0
EMIF Control
122
EMI0TC
0xAF
0x0
EMIF Timing Control
124
FLKEY
0xB7
0x0
Flash Lock And Key
157
FLSCL
0xB6
0x0
Flash Scale
157
IE
0xA8
All
Interrupt Enable
140
IP
0xB8
0x0
Interrupt Priority
141
IREF0CN
0xB9
0x0
Current Reference IREF Control
92
IT01CF
0xE4
0x0
INT0/INT1 Configuration
147
OSCICL
0xB3
0x0
Internal Oscillator Calibration
198
OSCICN
0xB2
0x0
Internal Oscillator Control
198
OSCXCN
0xB1
0x0
External Oscillator Control
199
P0
0x80
All
Port 0 Latch
230
P0DRV
0xA4
0xF
Port 0 Drive Strength
232
P0MASK
0xC7
0x0
Port 0 Mask
227
P0MAT
0xD7
0x0
Port 0 Match
227
P0MDIN
0xF1
0x0
Port 0 Input Mode Configuration
231
P0MDOUT
0xA4
0x0
Port 0 Output Mode Configuration
231
132
Description
Rev. 1.3
Page
C8051F93x-C8051F92x
Table 11.3. Special Function Registers (Continued)
SFRs are listed in alphabetical order. All undefined SFR locations are reserved
Register
Address
SFR Page
Description
P0SKIP
0xD4
0x0
Port 0 Skip
230
P1
0x90
All
Port 1 Latch
233
P1DRV
0xA5
0xF
Port 1 Drive Strength
235
P1MASK
0xBF
0x0
Port 1 Mask
228
P1MAT
0xCF
0x0
Port 1 Match
228
P1MDIN
0xF2
0x0
Port 1 Input Mode Configuration
234
P1MDOUT
0xA5
0x0
Port 1 Output Mode Configuration
234
P1SKIP
0xD5
0x0
Port 1 Skip
233
P2
0xA0
All
Port 2 Latch
235
P2DRV
0xA6
0xF
Port 2 Drive Strength
237
P2MDIN
0xF3
0x0
Port 2 Input Mode Configuration
236
P2MDOUT
0xA6
0x0
Port 2 Output Mode Configuration
237
P2SKIP
0xD6
0x0
Port 2 Skip
236
PCA0CN
0xD8
0x0
PCA0 Control
318
PCA0CPH0
0xFC
0x0
PCA0 Capture 0 High
323
PCA0CPH1
0xEA
0x0
PCA0 Capture 1 High
323
PCA0CPH2
0xEC
0x0
PCA0 Capture 2 High
323
PCA0CPH3
0xEE
0x0
PCA0 Capture 3 High
323
PCA0CPH4
0xFE
0x0
PCA0 Capture 4 High
323
PCA0CPH5
0xD3
0x0
PCA0 Capture 5 High
323
PCA0CPL0
0xFB
0x0
PCA0 Capture 0 Low
323
PCA0CPL1
0xE9
0x0
PCA0 Capture 1 Low
323
PCA0CPL2
0xEB
0x0
PCA0 Capture 2 Low
323
PCA0CPL3
0xED
0x0
PCA0 Capture 3 Low
323
PCA0CPL4
0xFD
0x0
PCA0 Capture 4 Low
323
PCA0CPL5
0xD2
0x0
PCA0 Capture 5 Low
323
PCA0CPM0
0xDA
0x0
PCA0 Module 0 Mode Register
321
PCA0CPM1
0xDB
0x0
PCA0 Module 1 Mode Register
321
PCA0CPM2
0xDC
0x0
PCA0 Module 2 Mode Register
321
PCA0CPM3
0xDD
0x0
PCA0 Module 3 Mode Register
321
PCA0CPM4
0xDE
0x0
PCA0 Module 4 Mode Register
321
PCA0CPM5
0xCE
0x0
PCA0 Module 5 Mode Register
321
PCA0H
0xFA
0x0
PCA0 Counter High
322
PCA0L
0xF9
0x0
PCA0 Counter Low
322
Rev. 1.3
Page
133
C8051F93x-C8051F92x
Table 11.3. Special Function Registers (Continued)
SFRs are listed in alphabetical order. All undefined SFR locations are reserved
Register
Address
SFR Page
PCA0MD
0xD9
0x0
PCA0 Mode
319
PCA0PWM
0xDF
0x0
PCA0 PWM Configuration
320
PCON
0x87
0x0
Power Control
166
PMU0CF
0xB5
0x0
PMU0 Configuration
165
PSCTL
0x8F
0x0
Program Store R/W Control
156
PSW
0xD0
All
Program Status Word
111
REF0CN
0xD1
0x0
Voltage Reference Control
91
REG0CN
0xC9
0x0
Voltage Regulator (VREG0) Control
183
RSTSRC
0xEF
0x0
Reset Source Configuration/Status
190
RTC0ADR
0xAC
0x0
RTC0 Address
205
RTC0DAT
0xAD
0x0
RTC0 Data
205
RTC0KEY
0xAE
0x0
RTC0 Key
204
SBUF0
0x99
0x0
UART0 Data Buffer
266
SCON0
0x98
0x0
UART0 Control
265
SFRPAGE
0xA7
All
SFR Page
131
SMB0ADM
0xF5
0x0
SMBus Slave Address Mask
250
SMB0ADR
0xF4
0x0
SMBus Slave Address
250
SMB0CF
0xC1
0x0
SMBus0 Configuration
245
SMB0CN
0xC0
0x0
SMBus0 Control
247
SMB0DAT
0xC2
0x0
SMBus0 Data
251
SP
0x81
All
Stack Pointer
110
SPI0CFG
0xA1
0x0
SPI0 Configuration
276
SPI0CKR
0xA2
0x0
SPI0 Clock Rate Control
278
SPI0CN
0xF8
0x0
SPI0 Control
277
SPI0DAT
0xA3
0x0
SPI0 Data
279
SPI1CFG
0x84
0x0
SPI1 Configuration
276
SPI1CKR
0x85
0x0
SPI1 Clock Rate Control
278
SPI1CN
0xB0
0x0
SPI1 Control
277
SPI1DAT
0x86
0x0
SPI1 Data
279
TCON
0x88
0x0
Timer/Counter Control
289
TH0
0x8C
0x0
Timer/Counter 0 High
292
TH1
0x8D
0x0
Timer/Counter 1 High
292
TL0
0x8A
0x0
Timer/Counter 0 Low
291
TL1
0x8B
0x0
Timer/Counter 1 Low
291
134
Description
Rev. 1.3
Page
C8051F93x-C8051F92x
Table 11.3. Special Function Registers (Continued)
SFRs are listed in alphabetical order. All undefined SFR locations are reserved
Register
Address
SFR Page
Description
TMOD
0x89
0x0
Timer/Counter Mode
290
TMR2CN
0xC8
0x0
Timer/Counter 2 Control
296
TMR2H
0xCD
0x0
Timer/Counter 2 High
298
TMR2L
0xCC
0x0
Timer/Counter 2 Low
298
TMR2RLH
0xCB
0x0
Timer/Counter 2 Reload High
297
TMR2RLL
0xCA
0x0
Timer/Counter 2 Reload Low
297
TMR3CN
0x91
0x0
Timer/Counter 3 Control
302
TMR3H
0x95
0x0
Timer/Counter 3 High
304
TMR3L
0x94
0x0
Timer/Counter 3 Low
304
TMR3RLH
0x93
0x0
Timer/Counter 3 Reload High
303
TMR3RLL
0x92
0x0
Timer/Counter 3 Reload Low
303
TOFFH
0x86
0xF
Temperature Offset High
88
TOFFL
0x85
0xF
Temperature Offset Low
88
VDM0CN
0xFF
0x0
VDD Monitor Control
187
XBR0
0xE1
0x0
Port I/O Crossbar Control 0
224
XBR1
0xE2
0x0
Port I/O Crossbar Control 1
225
XBR2
0xE3
0x0
Port I/O Crossbar Control 2
226
Rev. 1.3
Page
135
C8051F93x-C8051F92x
12. Interrupt Handler
The C8051F93x-C8051F92x microcontroller family includes an extended interrupt system supporting multiple interrupt sources and two priority levels. The allocation of interrupt sources between on-chip peripherals and external input pins varies according to the specific version of the device. Refer to Table 12.1,
“Interrupt Summary,” on page 138 for a detailed listing of all interrupt sources supported by the device.
Refer to the data sheet section associated with a particular on-chip peripheral for information regarding
valid interrupt conditions for the peripheral and the behavior of its interrupt-pending flag(s).
Each interrupt source has one or more associated interrupt-pending flag(s) located in an SFR or an indirect register. When a peripheral or external source meets a valid interrupt condition, the associated interrupt-pending flag is set to logic 1. If both global interrupts and the specific interrupt source is enabled, a
CPU interrupt request is generated when the interrupt-pending flag is set.
As soon as execution of the current instruction is complete, the CPU generates an LCALL to a predetermined address to begin execution of an interrupt service routine (ISR). Each ISR must end with an RETI
instruction, which returns program execution to the next instruction that would have been executed if the
interrupt request had not occurred. If interrupts are not enabled, the interrupt-pending flag is ignored by the
hardware and program execution continues as normal. (The interrupt-pending flag is set to logic 1 regardless of the interrupt's enable/disable state.)
Some interrupt-pending flags are automatically cleared by hardware when the CPU vectors to the ISR.
However, most are not cleared by the hardware and must be cleared by software before returning from the
ISR. If an interrupt-pending flag remains set after the CPU completes the return-from-interrupt (RETI)
instruction, a new interrupt request will be generated immediately and the CPU will re-enter the ISR after
the completion of the next instruction.
12.1. Enabling Interrupt Sources
Each interrupt source can be individually enabled or disabled through the use of an associated interrupt
enable bit in the Interrupt Enable and Extended Interrupt Enable SFRs. However, interrupts must first be
globally enabled by setting the EA bit (IE.7) to logic 1 before the individual interrupt enables are recognized. Setting the EA bit to logic 0 disables all interrupt sources regardless of the individual interruptenable settings. Note that interrupts which occur when the EA bit is set to logic 0 will be held in a pending
state, and will not be serviced until the EA bit is set back to logic 1.
12.2. MCU Interrupt Sources and Vectors
The CPU services interrupts by generating an LCALL to a predetermined address (the interrupt vector
address) to begin execution of an interrupt service routine (ISR). The interrupt vector addresses associated with each interrupt source are listed in Table 12.1 on page 138. Software should ensure that the interrupt vector for each enabled interrupt source contains a valid interrupt service routine.
Software can simulate an interrupt by setting any interrupt-pending flag to logic 1. If interrupts are enabled
for the flag, an interrupt request will be generated and the CPU will vector to the ISR address associated
with the interrupt-pending flag.
136
Rev. 1.3
C8051F93x-C8051F92x
12.3. Interrupt Priorities
Each interrupt source can be individually programmed to one of two priority levels: low or high. A low priority interrupt service routine can be preempted by a high priority interrupt. A high priority interrupt cannot be
preempted. If a high priority interrupt preempts a low priority interrupt, the low priority interrupt will finish
execution after the high priority interrupt completes. Each interrupt has an associated interrupt priority bit in
in the Interrupt Priority and Extended Interrupt Priority registers used to configure its priority level. Low priority is the default.
If two interrupts are recognized simultaneously, the interrupt with the higher priority is serviced first. If both
interrupts have the same priority level, a fixed priority order is used to arbitrate. See Table 12.1 on
page 138 to determine the fixed priority order used to arbitrate between simultaneously recognized interrupts.
12.4. Interrupt Latency
Interrupt response time depends on the state of the CPU when the interrupt occurs. Pending interrupts are
sampled and priority decoded each system clock cycle. Therefore, the fastest possible response time is 7
system clock cycles: 1 clock cycle to detect the interrupt, 1 clock cycle to execute a single instruction, and
5 clock cycles to complete the LCALL to the ISR. If an interrupt is pending when a RETI is executed, a single instruction is executed before an LCALL is made to service the pending interrupt. Therefore, the maximum response time for an interrupt (when no other interrupt is currently being serviced or the new interrupt
is of greater priority) occurs when the CPU is performing an RETI instruction followed by a DIV as the next
instruction. In this case, the response time is 19 system clock cycles: 1 clock cycle to detect the interrupt,
5 clock cycles to execute the RETI, 8 clock cycles to complete the DIV instruction and 5 clock cycles to execute the LCALL to the ISR. If the CPU is executing an ISR for an interrupt with equal or higher priority, the
new interrupt will not be serviced until the current ISR completes, including the RETI and following instruction.
Rev. 1.3
137
C8051F93x-C8051F92x
Interrupt
Vector
Priority
Pending Flag
Order
Cleared by HW?
Interrupt Source
Bit addressable?
Table 12.1. Interrupt Summary
Enable Flag
Priority
Control
IE0 (TCON.1)
TF0 (TCON.5)
IE1 (TCON.3)
TF1 (TCON.7)
RI0 (SCON0.0)
TI0 (SCON0.1)
TF2H (TMR2CN.7)
TF2L (TMR2CN.6)
SPIF (SPI0CN.7)
WCOL (SPI0CN.6)
MODF (SPI0CN.5)
RXOVRN (SPI0CN.4)
Y
Y
Y
Y
Y
Y
Y
Y
Always
Enabled
EX0 (IE.0)
ET0 (IE.1)
EX1 (IE.2)
ET1 (IE.3)
Y
N
ES0 (IE.4)
PS0 (IP.4)
Y
N
ET2 (IE.5)
PT2 (IP.5)
Y
N
7
SI (SMB0CN.0)
Y
N
0x0043
8
ALRM (RTC0CN.2)*
N
N
ADC0 Window Comparator
0x004B
9
AD0WINT (ADC0CN.3)
Y
N
ADC0 End of Conversion
0x0053
10
AD0INT (ADC0STA.5)
Y
N
Programmable Counter Array
0x005B
11
Y
N
Comparator0
0x0063
12
N
N
Comparator1
0x006B
13
N
N
Timer 3 Overflow
0x0073
14
N
N
VDD/DC+ Supply Monitor
Early Warning
0x007B
15
VDDOK (VDM0CN.5)1
Port Match
0x0083
16
None
SmaRTClock Oscillator Fail
0x008B
17
OSCFAIL (RTC0CN.5)2
N
N
18
SPIF (SPI1CN.7)
WCOL (SPI1CN.6)
MODF (SPI1CN.5)
RXOVRN (SPI1CN.4)
N
N
Reset
0x0000
Top
External Interrupt 0 (INT0)
Timer 0 Overflow
External Interrupt 1 (INT1)
Timer 1 Overflow
0x0003
0x000B
0x0013
0x001B
0
1
2
3
UART0
0x0023
4
Timer 2 Overflow
0x002B
5
SPI0
0x0033
6
SMB0
0x003B
SmaRTClock Alarm
SPI1
0x0093
None
CF (PCA0CN.7)
CCFn (PCA0CN.n)
CP0FIF (CPT0CN.4)
CP0RIF (CPT0CN.5)
CP1FIF (CPT1CN.4)
CP1RIF (CPT1CN.5)
TF3H (TMR3CN.7)
TF3L (TMR3CN.6)
N/A N/A
Always
Highest
PX0 (IP.0)
PT0 (IP.1)
PX1 (IP.2)
PT1 (IP.3)
ESPI0 (IE.6) PSPI0 (IP.6)
ESMB0
(EIE1.0)
EARTC0
(EIE1.1)
EWADC0
(EIE1.2)
EADC0
(EIE1.3)
EPCA0
(EIE1.4)
ECP0
(EIE1.5)
ECP1
(EIE1.6)
ET3
(EIE1.7)
EWARN
(EIE2.0)
EMAT
(EIE2.1)
ERTC0F
(EIE2.2)
PSMB0
(EIP1.0)
PARTC0
(EIP1.1)
PWADC0
(EIP1.2)
PADC0
(EIP1.3)
PPCA0
(EIP1.4)
PCP0
(EIP1.5)
PCP1
(EIP1.6)
PT3
(EIP1.7)
PWARN
(EIP2.0)
PMAT
(EIP2.1)
PFRTC0F
(EIP2.2)
ESPI1
(EIE2.3)
PSPI1
(EIP2.3)
Notes:
1. Indicates a read-only interrupt pending flag. The interrupt enable may be used to prevent software from
vectoring to the associated interrupt service routine.
2. Indicates a register located in an indirect memory space.
138
Rev. 1.3
C8051F93x-C8051F92x
12.5. Interrupt Register Descriptions
The SFRs used to enable the interrupt sources and set their priority level are described in the following
register descriptions. Refer to the data sheet section associated with a particular on-chip peripheral for
information regarding valid interrupt conditions for the peripheral and the behavior of its interrupt-pending
flag(s).
Rev. 1.3
139
C8051F93x-C8051F92x
SFR Definition 12.1. IE: Interrupt Enable
Bit
7
6
5
4
3
2
1
0
Name
EA
ESPI0
ET2
ES0
ET1
EX1
ET0
EX0
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
SFR Page = All Pages; SFR Address = 0xA8; Bit-Addressable
Bit
Name
Function
7
EA
6
ESPI0
5
ET2
Enable Timer 2 Interrupt.
This bit sets the masking of the Timer 2 interrupt.
0: Disable Timer 2 interrupt.
1: Enable interrupt requests generated by the TF2L or TF2H flags.
4
ES0
Enable UART0 Interrupt.
This bit sets the masking of the UART0 interrupt.
0: Disable UART0 interrupt.
1: Enable UART0 interrupt.
3
ET1
Enable Timer 1 Interrupt.
This bit sets the masking of the Timer 1 interrupt.
0: Disable all Timer 1 interrupt.
1: Enable interrupt requests generated by the TF1 flag.
2
EX1
Enable External Interrupt 1.
This bit sets the masking of External Interrupt 1.
0: Disable external interrupt 1.
1: Enable interrupt requests generated by the INT1 input.
1
ET0
Enable Timer 0 Interrupt.
This bit sets the masking of the Timer 0 interrupt.
0: Disable all Timer 0 interrupt.
1: Enable interrupt requests generated by the TF0 flag.
0
EX0
Enable External Interrupt 0.
This bit sets the masking of External Interrupt 0.
0: Disable external interrupt 0.
1: Enable interrupt requests generated by the INT0 input.
140
Enable All Interrupts.
Globally enables/disables all interrupts. It overrides individual interrupt mask settings.
0: Disable all interrupt sources.
1: Enable each interrupt according to its individual mask setting.
Enable Serial Peripheral Interface (SPI0) Interrupt.
This bit sets the masking of the SPI0 interrupts.
0: Disable all SPI0 interrupts.
1: Enable interrupt requests generated by SPI0.
Rev. 1.3
C8051F93x-C8051F92x
SFR Definition 12.2. IP: Interrupt Priority
Bit
7
Name
6
5
4
3
2
1
0
PSPI0
PT2
PS0
PT1
PX1
PT0
PX0
Type
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
1
0
0
0
0
0
0
0
SFR Page = 0x0; SFR Address = 0xB8; Bit-Addressable
Bit
Name
Function
7
Unused
Unused.
Read = 1b, Write = don't care.
6
PSPI0
5
PT2
Timer 2 Interrupt Priority Control.
This bit sets the priority of the Timer 2 interrupt.
0: Timer 2 interrupt set to low priority level.
1: Timer 2 interrupt set to high priority level.
4
PS0
UART0 Interrupt Priority Control.
This bit sets the priority of the UART0 interrupt.
0: UART0 interrupt set to low priority level.
1: UART0 interrupt set to high priority level.
3
PT1
Timer 1 Interrupt Priority Control.
This bit sets the priority of the Timer 1 interrupt.
0: Timer 1 interrupt set to low priority level.
1: Timer 1 interrupt set to high priority level.
2
PX1
External Interrupt 1 Priority Control.
This bit sets the priority of the External Interrupt 1 interrupt.
0: External Interrupt 1 set to low priority level.
1: External Interrupt 1 set to high priority level.
1
PT0
Timer 0 Interrupt Priority Control.
This bit sets the priority of the Timer 0 interrupt.
0: Timer 0 interrupt set to low priority level.
1: Timer 0 interrupt set to high priority level.
0
PX0
External Interrupt 0 Priority Control.
This bit sets the priority of the External Interrupt 0 interrupt.
0: External Interrupt 0 set to low priority level.
1: External Interrupt 0 set to high priority level.
Serial Peripheral Interface (SPI0) Interrupt Priority Control.
This bit sets the priority of the SPI0 interrupt.
0: SPI0 interrupt set to low priority level.
1: SPI0 interrupt set to high priority level.
Rev. 1.3
141
C8051F93x-C8051F92x
SFR Definition 12.3. EIE1: Extended Interrupt Enable 1
Bit
7
6
5
4
3
2
1
0
Name
ET3
ECP1
ECP0
EPCA0
EADC0
EWADC0
ERTC0A
ESMB0
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
SFR Page = All Pages; SFR Address = 0xE6
Bit
Name
Function
7
ET3
6
ECP1
Enable Comparator1 (CP1) Interrupt.
This bit sets the masking of the CP1 interrupt.
0: Disable CP1 interrupts.
1: Enable interrupt requests generated by the CP1RIF or CP1FIF flags.
5
ECP0
Enable Comparator0 (CP0) Interrupt.
This bit sets the masking of the CP0 interrupt.
0: Disable CP0 interrupts.
1: Enable interrupt requests generated by the CP0RIF or CP0FIF flags.
4
EPCA0
Enable Programmable Counter Array (PCA0) Interrupt.
This bit sets the masking of the PCA0 interrupts.
0: Disable all PCA0 interrupts.
1: Enable interrupt requests generated by PCA0.
3
EADC0
Enable ADC0 Conversion Complete Interrupt.
This bit sets the masking of the ADC0 Conversion Complete interrupt.
0: Disable ADC0 Conversion Complete interrupt.
1: Enable interrupt requests generated by the AD0INT flag.
Enable Timer 3 Interrupt.
This bit sets the masking of the Timer 3 interrupt.
0: Disable Timer 3 interrupts.
1: Enable interrupt requests generated by the TF3L or TF3H flags.
2
EWADC0 Enable Window Comparison ADC0 Interrupt.
This bit sets the masking of ADC0 Window Comparison interrupt.
0: Disable ADC0 Window Comparison interrupt.
1: Enable interrupt requests generated by ADC0 Window Compare flag (AD0WINT).
1
ERTC0A
Enable SmaRTClock Alarm Interrupts.
This bit sets the masking of the SmaRTClock Alarm interrupt.
0: Disable SmaRTClock Alarm interrupts.
1: Enable interrupt requests generated by a SmaRTClock Alarm.
0
ESMB0
Enable SMBus (SMB0) Interrupt.
This bit sets the masking of the SMB0 interrupt.
0: Disable all SMB0 interrupts.
1: Enable interrupt requests generated by SMB0.
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SFR Definition 12.4. EIP1: Extended Interrupt Priority 1
Bit
7
6
5
4
3
2
1
0
Name
PT3
PCP1
PCP0
PPCA0
PADC0
PWADC0
PRTC0A
PSMB0
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
SFR Page = All Pages; SFR Address = 0xF6
Bit
Name
Function
7
PT3
Timer 3 Interrupt Priority Control.
This bit sets the priority of the Timer 3 interrupt.
0: Timer 3 interrupts set to low priority level.
1: Timer 3 interrupts set to high priority level.
6
PCP1
Comparator1 (CP1) Interrupt Priority Control.
This bit sets the priority of the CP1 interrupt.
0: CP1 interrupt set to low priority level.
1: CP1 interrupt set to high priority level.
5
PCP0
Comparator0 (CP0) Interrupt Priority Control.
This bit sets the priority of the CP0 interrupt.
0: CP0 interrupt set to low priority level.
1: CP0 interrupt set to high priority level.
4
PPCA0
Programmable Counter Array (PCA0) Interrupt Priority Control.
This bit sets the priority of the PCA0 interrupt.
0: PCA0 interrupt set to low priority level.
1: PCA0 interrupt set to high priority level.
3
PADC0
ADC0 Conversion Complete Interrupt Priority Control.
This bit sets the priority of the ADC0 Conversion Complete interrupt.
0: ADC0 Conversion Complete interrupt set to low priority level.
1: ADC0 Conversion Complete interrupt set to high priority level.
2
PWADC0 ADC0 Window Comparator Interrupt Priority Control.
This bit sets the priority of the ADC0 Window interrupt.
0: ADC0 Window interrupt set to low priority level.
1: ADC0 Window interrupt set to high priority level.
1
PRTC0A
SmaRTClock Alarm Interrupt Priority Control.
This bit sets the priority of the SmaRTClock Alarm interrupt.
0: SmaRTClock Alarm interrupt set to low priority level.
1: SmaRTClock Alarm interrupt set to high priority level.
0
PSMB0
SMBus (SMB0) Interrupt Priority Control.
This bit sets the priority of the SMB0 interrupt.
0: SMB0 interrupt set to low priority level.
1: SMB0 interrupt set to high priority level.
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SFR Definition 12.5. EIE2: Extended Interrupt Enable 2
Bit
7
6
5
4
Name
3
2
1
0
ESPI1
ERTC0F
EMAT
EWARN
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
SFR Page = All Pages;SFR Address = 0xE7
Bit
Name
7:4
Unused
Function
Unused.
Read = 0000b. Write = Don’t care.
3
2
ESPI1
Enable Serial Peripheral Interface (SPI1) Interrupt.
This bit sets the masking of the SPI1 interrupts.
0: Disable all SPI1 interrupts.
1: Enable interrupt requests generated by SPI1.
ERTC0F Enable SmaRTClock Oscillator Fail Interrupt.
This bit sets the masking of the SmaRTClock Alarm interrupt.
0: Disable SmaRTClock Alarm interrupts.
1: Enable interrupt requests generated by SmaRTClock Alarm.
1
0
EMAT
Enable Port Match Interrupts.
This bit sets the masking of the Port Match Event interrupt.
0: Disable all Port Match interrupts.
1: Enable interrupt requests generated by a Port Match.
EWARN Enable VDD/DC+ Supply Monitor Early Warning Interrupt.
This bit sets the masking of the VDD/DC+ Supply Monitor Early Warning interrupt.
0: Disable the VDD/DC+ Supply Monitor Early Warning interrupt.
1: Enable interrupt requests generated by VDD/DC+ Supply Monitor.
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SFR Definition 12.6. EIP2: Extended Interrupt Priority 2
Bit
7
6
5
4
Name
3
2
1
0
PSPI1
PRTC0F
PMAT
PWARN
Type
R
R
R
R
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
SFR Page = All Pages; SFR Address = 0xF7
Bit
Name
7:4
Unused
Function
Unused.
Read = 0000b. Write = Don’t care.
3
2
1
0
PSPI1
Serial Peripheral Interface (SPI1) Interrupt Priority Control.
This bit sets the priority of the SPI1 interrupt.
0: SP1 interrupt set to low priority level.
1: SPI1 interrupt set to high priority level.
PRTC0F SmaRTClock Oscillator Fail Interrupt Priority Control.
This bit sets the priority of the SmaRTClock Alarm interrupt.
0: SmaRTClock Alarm interrupt set to low priority level.
1: SmaRTClock Alarm interrupt set to high priority level.
PMAT
Port Match Interrupt Priority Control.
This bit sets the priority of the Port Match Event interrupt.
0: Port Match interrupt set to low priority level.
1: Port Match interrupt set to high priority level.
PWARN VDD/DC+ Supply Monitor Early Warning Interrupt Priority Control.
This bit sets the priority of the VDD/DC+ Supply Monitor Early Warning interrupt.
0: VDD/DC+ Supply Monitor Early Warning interrupt set to low priority level.
1: VDD/DC+ Supply Monitor Early Warning interrupt set to high priority level.
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12.6. External Interrupts INT0 and INT1
The INT0 and INT1 external interrupt sources are configurable as active high or low, edge or level sensitive. The IN0PL (INT0 Polarity) and IN1PL (INT1 Polarity) bits in the IT01CF register select active high or
active low; the IT0 and IT1 bits in TCON (Section “25.1. Timer 0 and Timer 1” on page 285) select level or
edge sensitive. The table below lists the possible configurations.
IT0
IN0PL
INT0 Interrupt
IT1
IN1PL
INT1 Interrupt
1
0
Active low, edge sensitive
1
0
Active low, edge sensitive
1
1
Active high, edge sensitive
1
1
Active high, edge sensitive
0
0
Active low, level sensitive
0
0
Active low, level sensitive
0
1
Active high, level sensitive
0
1
Active high, level sensitive
INT0 and INT1 are assigned to Port pins as defined in the IT01CF register (see SFR Definition 12.7). Note
that INT0 and INT0 Port pin assignments are independent of any Crossbar assignments. INT0 and INT1
will monitor their assigned Port pins without disturbing the peripheral that was assigned the Port pin via the
Crossbar. To assign a Port pin only to INT0 and/or INT1, configure the Crossbar to skip the selected pin(s).
This is accomplished by setting the associated bit in register XBR0 (see Section “21.3. Priority Crossbar
Decoder” on page 221 for complete details on configuring the Crossbar).
IE0 (TCON.1) and IE1 (TCON.3) serve as the interrupt-pending flags for the INT0 and INT1 external interrupts, respectively. If an INT0 or INT1 external interrupt is configured as edge-sensitive, the corresponding
interrupt-pending flag is automatically cleared by the hardware when the CPU vectors to the ISR. When
configured as level sensitive, the interrupt-pending flag remains logic 1 while the input is active as defined
by the corresponding polarity bit (IN0PL or IN1PL); the flag remains logic 0 while the input is inactive. The
external interrupt source must hold the input active until the interrupt request is recognized. It must then
deactivate the interrupt request before execution of the ISR completes or another interrupt request will be
generated.
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SFR Definition 12.7. IT01CF: INT0/INT1 Configuration
Bit
7
6
Name
IN1PL
IN1SL[2:0]
IN0PL
IN0SL[2:0]
Type
R/W
R/W
R/W
R/W
Reset
0
0
5
0
4
0
3
0
2
0
1
0
0
1
SFR Page = 0x0; SFR Address = 0xE4
Bit
Name
7
IN1PL
6:4
3
2:0
Function
INT1 Polarity.
0: INT1 input is active low.
1: INT1 input is active high.
IN1SL[2:0] INT1 Port Pin Selection Bits.
These bits select which Port pin is assigned to INT1. Note that this pin assignment is
independent of the Crossbar; INT1 will monitor the assigned Port pin without disturbing the peripheral that has been assigned the Port pin via the Crossbar. The Crossbar
will not assign the Port pin to a peripheral if it is configured to skip the selected pin.
000: Select P0.0
001: Select P0.1
010: Select P0.2
011: Select P0.3
100: Select P0.4
101: Select P0.5
110: Select P0.6
111: Select P0.7
IN0PL
INT0 Polarity.
0: INT0 input is active low.
1: INT0 input is active high.
IN0SL[2:0] INT0 Port Pin Selection Bits.
These bits select which Port pin is assigned to INT0. Note that this pin assignment is
independent of the Crossbar; INT0 will monitor the assigned Port pin without disturbing the peripheral that has been assigned the Port pin via the Crossbar. The Crossbar
will not assign the Port pin to a peripheral if it is configured to skip the selected pin.
000: Select P0.0
001: Select P0.1
010: Select P0.2
011: Select P0.3
100: Select P0.4
101: Select P0.5
110: Select P0.6
111: Select P0.7
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13. Flash Memory
On-chip, re-programmable Flash memory is included for program code and non-volatile data storage. The
Flash memory can be programmed in-system through the C2 interface or by software using the MOVX
write instruction. Once cleared to logic 0, a Flash bit must be erased to set it back to logic 1. Flash bytes
would typically be erased (set to 0xFF) before being reprogrammed. The write and erase operations are
automatically timed by hardware for proper execution; data polling to determine the end of the write/erase
operations is not required. Code execution is stalled during Flash write/erase operations. Refer to
Table 4.6 for complete Flash memory electrical characteristics.
13.1. Programming The Flash Memory
The simplest means of programming the Flash memory is through the C2 interface using programming
tools provided by Silicon Laboratories or a third party vendor. This is the only means for programming a
non-initialized device. For details on the C2 commands to program Flash memory, see Section “27. C2
Interface” on page 324.
The Flash memory can be programmed by software using the MOVX write instruction with the address and
data byte to be programmed provided as normal operands. Before programming Flash memory using
MOVX, Flash programming operations must be enabled by: (1) setting the PSWE Program Store Write
Enable bit (PSCTL.0) to logic 1 (this directs the MOVX writes to target Flash memory); and (2) Writing the
Flash key codes in sequence to the Flash Lock register (FLKEY). The PSWE bit remains set until cleared
by software. For detailed guidelines on programming Flash from firmware, please see Section “13.5. Flash
Write and Erase Guidelines” on page 153.
To ensure the integrity of the Flash contents, the on-chip VDD Monitor must be enabled and
enabled as a reset source in any system that includes code that writes and/or erases Flash memory from software. Furthermore, there should be no delay between enabling the VDD Monitor and
enabling the VDD Monitor as a reset source. Any attempt to write or erase Flash memory while the
VDD Monitor is disabled, or not enabled as a reset source, will cause a Flash Error device reset.
13.1.1. Flash Lock and Key Functions
Flash writes and erases by user software are protected with a lock and key function. The Flash Lock and
Key Register (FLKEY) must be written with the correct key codes, in sequence, before Flash operations
may be performed. The key codes are: 0xA5, 0xF1. The timing does not matter, but the codes must be
written in order. If the key codes are written out of order, or the wrong codes are written, Flash writes and
erases will be disabled until the next system reset. Flash writes and erases will also be disabled if a Flash
write or erase is attempted before the key codes have been written properly. The Flash lock resets after
each write or erase; the key codes must be written again before a following Flash operation can be performed. The FLKEY register is detailed in SFR Definition 13.2.
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13.1.2. Flash Erase Procedure
The Flash memory is organized in 1024-byte pages. The erase operation applies to an entire page (setting
all bytes in the page to 0xFF). To erase an entire 1024-byte page, perform the following steps:
1.
2.
3.
4.
5.
6.
Save current interrupt state and disable interrupts.
Set the PSEE bit (register PSCTL).
Set the PSWE bit (register PSCTL).
Write the first key code to FLKEY: 0xA5.
Write the second key code to FLKEY: 0xF1.
Using the MOVX instruction, write a data byte to any location within the 1024-byte page to be
erased.
7. Clear the PSWE and PSEE bits.
8. Restore previous interrupt state.
Steps 4–6 must be repeated for each 1024-byte page to be erased.
Notes:
1. Future 16 and 8 kB derivatives in this product family will use a 512-byte page size. To maintain code
compatibility across the entire family, the erase procedure should be performed on each 512-byte section of
memory.
2. Flash security settings may prevent erasure of some Flash pages, such as the reserved area and the page
containing the lock bytes. For a summary of Flash security settings and restrictions affecting Flash erase
operations, please see Section “13.3. Security Options” on page 150.
3. 8-bit MOVX instructions cannot be used to erase or write to Flash memory at addresses higher than 0x00FF.
13.1.3. Flash Write Procedure
A write to Flash memory can clear bits to logic 0 but cannot set them; only an erase operation can set bits
to logic 1 in Flash. A byte location to be programmed should be erased before a new value is written.
The recommended procedure for writing a single byte in Flash is as follows:
1.
2.
3.
4.
5.
6.
7.
Save current interrupt state and disable interrupts.
Ensure that the Flash byte has been erased (has a value of 0xFF).
Set the PSWE bit (register PSCTL).
Clear the PSEE bit (register PSCTL).
Write the first key code to FLKEY: 0xA5.
Write the second key code to FLKEY: 0xF1.
Using the MOVX instruction, write a single data byte to the desired location within the 1024byte sector.
8. Clear the PSWE bit.
9. Restore previous interrupt state.
Steps 5–7 must be repeated for each byte to be written.
Notes:
1. Future 16 and 8 kB derivatives in this product family will use a 512-byte page size. To maintain code
compatibility across the entire family, the erase procedure should be performed on each 512-byte section of
memory.
2. Flash security settings may prevent writes to some areas of Flash, such as the reserved area. For a summary
of Flash security settings and restrictions affecting Flash write operations, please see Section “13.3. Security
Options” on page 150.
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13.2. Non-volatile Data Storage
The Flash memory can be used for non-volatile data storage as well as program code. This allows data
such as calibration coefficients to be calculated and stored at run time. Data is written using the MOVX
write instruction and read using the MOVC instruction. Note: MOVX read instructions always target XRAM.
An additional 1024-byte scratchpad is available for non-volatile data storage. It is accessible at addresses
0x0000 to 0x03FF when SFLE is set to 1. The scratchpad area cannot be used for code execution.
13.3. Security Options
The CIP-51 provides security options to protect the Flash memory from inadvertent modification by software as well as to prevent the viewing of proprietary program code and constants. The Program Store
Write Enable (bit PSWE in register PSCTL) and the Program Store Erase Enable (bit PSEE in register
PSCTL) bits protect the Flash memory from accidental modification by software. PSWE must be explicitly
set to 1 before software can modify the Flash memory; both PSWE and PSEE must be set to 1 before software can erase Flash memory. Additional security features prevent proprietary program code and data
constants from being read or altered across the C2 interface.
A Security Lock Byte located at the last byte of Flash user space offers protection of the Flash program
memory from access (reads, writes, or erases) by unprotected code or the C2 interface. The Flash security
mechanism allows the user to lock n 1024-byte Flash pages, starting at page 0 (addresses 0x0000 to
0x03FF), where n is the 1s complement number represented by the Security Lock Byte. The page containing the Flash Security Lock Byte is unlocked when no other Flash pages are locked (all bits of
the Lock Byte are 1) and locked when any other Flash pages are locked (any bit of the Lock Byte is
0). See the C8051F930 example below.
Security Lock Byte:
ones Complement:
Flash pages locked:
11111101b
00000010b
3 (First two Flash pages + Lock Byte Page)
0x0000 to 0x07FF (first two Flash pages) and
Addresses locked:
0xF800 to 0xFBFF (Lock Byte Page)
64KB Flash Device
(SFLE = 0)
32KB Flash Device
(SFLE = 0)
0xFFFF
0xFFFF
Reserved
Unpopulated
Address Space
(Reserved)
0xFC00
0xFBFF
Lock Byte
0xFBFE
Lock Byte Page
0xF800
Locked when
any other
Flash pages
are locked
0x8000
Lock Byte
Lock Byte Page
Flash
memory
organized in
1024-byte
pages
0x7FFF
0x7FFE
0x7C00
Unlocked Flash Pages
64/32KB Flash Device
(SFLE = 1)
Unlocked Flash Pages
0x0000
Access limit
set according
to the Flash
security lock
byte
0x03FF
Scratchpad Area
(Data Only)
0x0000
Figure 13.1. Flash Program Memory Map
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C8051F93x-C8051F92x
The level of Flash security depends on the Flash access method. The three Flash access methods that
can be restricted are reads, writes, and erases from the C2 debug interface, user firmware executing on
unlocked pages, and user firmware executing on locked pages. Table 13.1 summarizes the Flash security
features of the C8051F93x-C8051F92x devices.
Table 13.1. Flash Security Summary
Action
C2 Debug
Interface
User Firmware executing from:
an unlocked page
a locked page
Permitted
Permitted
Permitted
Not Permitted
FEDR
Permitted
Read or Write page containing Lock Byte
(if no pages are locked)
Permitted
Permitted
Permitted
Read or Write page containing Lock Byte
(if any page is locked)
Not Permitted
FEDR
Permitted
Read contents of Lock Byte
(if no pages are locked)
Permitted
Permitted
Permitted
Read contents of Lock Byte
(if any page is locked)
Not Permitted
FEDR
Permitted
Permitted
FEDR
FEDR
Erase page containing Lock Byte - Unlock all pages
(if any page is locked)
Only by C2DE
FEDR
FEDR
Lock additional pages
(change 1s to 0s in the Lock Byte)
Not Permitted
FEDR
FEDR
Unlock individual pages
(change 0s to 1s in the Lock Byte)
Not Permitted
FEDR
FEDR
Read, Write or Erase Reserved Area
Not Permitted
FEDR
FEDR
Read, Write or Erase unlocked pages
(except page with Lock Byte)
Read, Write or Erase locked pages
(except page with Lock Byte)
Erase page containing Lock Byte
(if no pages are locked)

C2DE—C2 Device Erase (Erases all Flash pages including the page containing the Lock Byte)
FEDR—Not permitted; Causes Flash Error Device Reset (FERROR bit in RSTSRC is '1' after reset)
- All prohibited operations that are performed via the C2 interface are ignored (do not cause device reset).
- Locking any Flash page also locks the page containing the Lock Byte.
- Once written to, the Lock Byte cannot be modified except by performing a C2 Device Erase.
- If user code writes to the Lock Byte, the Lock does not take effect until the next device reset.
- The scratchpad is locked when all other Flash pages are locked.
- The scratchpad is erased when a Flash Device Erase command is performed.
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13.4. Determining the Device Part Number at Run Time
In many applications, user software may need to determine the MCU part number at run time in order to
determine the hardware capabilities. The part number can be determined by reading the value of the Flash
byte at address 0xFFFE.

The value of the Flash byte at address 0xFFFE can be decoded as follows:

0x56—C8051F930
0x5E—C8051F931
0xB1—C8051F920
0xB3—C8051F921
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13.5. Flash Write and Erase Guidelines
Any system which contains routines which write or erase Flash memory from software involves some risk
that the write or erase routines will execute unintentionally if the CPU is operating outside its specified
operating range of VDD, system clock frequency, or temperature. This accidental execution of Flash modifying code can result in alteration of Flash memory contents causing a system failure that is only recoverable by re-Flashing the code in the device.
To help prevent the accidental modification of Flash by firmware, the VDD Monitor must be enabled and
enabled as a reset source on C8051F92x-C8051F93x devices for the Flash to be successfully modified. If
either the VDD Monitor or the VDD Monitor reset source is not enabled, a Flash Error Device Reset
will be generated when the firmware attempts to modify the Flash.
The following guidelines are recommended for any system that contains routines which write or erase
Flash from code.
13.5.1. VDD Maintenance and the VDD Monitor
1. If the system power supply is subject to voltage or current "spikes," add sufficient transient
protection devices to the power supply to ensure that the supply voltages listed in the Absolute
Maximum Ratings table are not exceeded.
2. Make certain that the maximum VBAT ramp time specification of 3 ms is met. This specification is outlined in Table 4.4 on page 59. On silicon revision F and later revisions, if the system
cannot meet this rise time specification, then add an external VDD brownout circuit to the RST
pin of the device that holds the device in reset until VDD reaches the minimum device operating voltage and re-asserts RST if VDD drops below the minimum device operating voltage.
3. Keep the on-chip VDD Monitor enabled and enable the VDD Monitor as a reset source as
early in code as possible. This should be the first set of instructions executed after the Reset
Vector. For C-based systems, this will involve modifying the startup code added by the 'C'
compiler. See your compiler documentation for more details. Make certain that there are no
delays in software between enabling the VDD Monitor and enabling the VDD Monitor as a
reset source. Code examples showing this can be found in “AN201: Writing to Flash from
Firmware," available from the Silicon Laboratories web site.
Notes: 
On C8051F93x-C8051F92x devices, both the VDD Monitor and the VDD Monitor reset source
must be enabled to write or erase Flash without generating a Flash Error Device Reset.
On C8051F93x-C8051F92x devices, both the VDD Monitor and the VDD Monitor reset source
are enabled by hardware after a power-on reset.
4. As an added precaution, explicitly enable the VDD Monitor and enable the VDD Monitor as a
reset source inside the functions that write and erase Flash memory. The VDD Monitor enable
instructions should be placed just after the instruction to set PSWE to a '1', but before the
Flash write or erase operation instruction.
5. Make certain that all writes to the RSTSRC (Reset Sources) register use direct assignment
operators and explicitly DO NOT use the bit-wise operators (such as AND or OR). For example, "RSTSRC = 0x02" is correct, but "RSTSRC |= 0x02" is incorrect.
6. Make certain that all writes to the RSTSRC register explicitly set the PORSF bit to a '1'. Areas
to check are initialization code which enables other reset sources, such as the Missing Clock
Detector or Comparator, for example, and instructions which force a Software Reset. A global
search on "RSTSRC" can quickly verify this.
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13.5.2. PSWE Maintenance
7. Reduce the number of places in code where the PSWE bit (b0 in PSCTL) is set to a 1. There
should be exactly one routine in code that sets PSWE to a 1 to write Flash bytes and one routine in code that sets both PSWE and PSEE both to a 1 to erase Flash pages.
8. Minimize the number of variable accesses while PSWE is set to a 1. Handle pointer address
updates and loop maintenance outside the "PSWE = 1;... PSWE = 0;" area. Code examples
showing this can be found in “AN201: Writing to Flash from Firmware," available from the Silicon Laboratories web site.
9. Disable interrupts prior to setting PSWE to a 1 and leave them disabled until after PSWE has
been reset to 0. Any interrupts posted during the Flash write or erase operation will be serviced in priority order after the Flash operation has been completed and interrupts have been
re-enabled by software.
10. Make certain that the Flash write and erase pointer variables are not located in XRAM. See
your compiler documentation for instructions regarding how to explicitly locate variables in different memory areas.
11. Add address bounds checking to the routines that write or erase Flash memory to ensure that
a routine called with an illegal address does not result in modification of the Flash.
13.5.3. System Clock
12. If operating from an external crystal, be advised that crystal performance is susceptible to
electrical interference and is sensitive to layout and to changes in temperature. If the system is
operating in an electrically noisy environment, use the internal oscillator or use an external
CMOS clock.
13. If operating from the external oscillator, switch to the internal oscillator during Flash write or
erase operations. The external oscillator can continue to run, and the CPU can switch back to
the external oscillator after the Flash operation has completed.
Additional Flash recommendations and example code can be found in “AN201: Writing to Flash from Firmware," available from the Silicon Laboratories website.
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13.6. Minimizing Flash Read Current
The Flash memory in the C8051F93x-C8051F92x devices is responsible for a substantial portion of the
total digital supply current when the device is executing code. Below are suggestions to minimize Flash
read current.
1. Use idle, suspend, or sleep modes while waiting for an interrupt, rather than polling the interrupt flag. Idle mode is particularly well-suited for use in implementing short pauses, since the
wake-up time is no more than three system clock cycles. See the Power Management chapter
for details on the various low-power operating modes.
2. C8051F93x-C8051F92x devices have a one-shot timer that saves power when operating at
system clock frequencies of 10 MHz or less. The one-shot timer generates a minimum-duration enable signal for the Flash sense amps on each clock cycle in which the Flash memory is
accessed. This allows the Flash to remain in a low power state for the remainder of the long
clock cycle.
At clock frequencies above 10 MHz, the system clock cycle becomes short enough that the
one-shot timer no longer provides a power benefit. Disabling the one-shot timer at higher frequencies reduces power consumption. The one-shot is enabled by default, and it can be disabled (bypassed) by setting the BYPASS bit (FLSCL.6) to logic 1. To re-enable the one-shot,
clear the BYPASS bit to logic 0. See the note in SFR Definition 13.3. FLSCL: Flash Scale for
more information on how to properly clear the BYPASS bit.
3. Flash read current depends on the number of address lines that toggle between sequential
Flash read operations. In most cases, the difference in power is relatively small (on the order
of 5%).
The Flash memory is organized in rows. Each row in the C8051F9xx Flash contains 128
bytes. A substantial current increase can be detected when the read address jumps from one
row in the Flash memory to another. Consider a 3-cycle loop (e.g., SJMP $, or while(1);) which
straddles a 128-byte Flash row boundary. The Flash address jumps from one row to another
on two of every three clock cycles. This can result in a current increase of up 30% when compared to the same 3-cycle loop contained entirely within a single row.
To minimize the power consumption of small loops, it is best to locate them within a single row,
if possible. To check if a loop is contained within a Flash row, divide the starting address of the
first instruction in the loop by 128. If the remainder (result of modulo operation) plus the length
of the loop is less than 127, then the loop fits inside a single Flash row. Otherwise, the loop will
be straddling two adjacent Flash rows. If a loop executes in 20 or more clock cycles, then the
transitions from one row to another will occur on relatively few clock cycles, and any resulting
increase in operating current will be negligible.
Note: Future 16 and 8 kB derivatives in this product family will use a Flash memory that is organized in rows of 64
bytes each. To maintain code compatibility across the entire family, it is best to locate small loops within a single
64-byte segment.
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C8051F93x-C8051F92x
SFR Definition 13.1. PSCTL: Program Store R/W Control
Bit
7
6
5
4
3
Name
2
1
0
SFLE
PSEE
PSWE
Type
R
R
R
R
R
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
SFR Page =0x0; SFR Address = 0x8F
Bit
Name
7:3
Unused
Function
Unused.
Read = 00000b, Write = don’t care.
2
SFLE
Scratchpad Flash Memory Access Enable.
When this bit is set, Flash MOVC reads and MOVX writes from user software are
directed to the Scratchpad Flash sector. Flash accesses outside the address range
0x0000-0x03FF should not be attempted and may yield undefined results when SFLE
is set to 1.
0: Flash access from user software directed to the Program/Data Flash sector.
1: Flash access from user software directed to the Scratchpad Sector.
1
PSEE
Program Store Erase Enable.
Setting this bit (in combination with PSWE) allows an entire page of Flash program
memory to be erased. If this bit is logic 1 and Flash writes are enabled (PSWE is logic
1), a write to Flash memory using the MOVX instruction will erase the entire page that
contains the location addressed by the MOVX instruction. The value of the data byte
written does not matter.
0: Flash program memory erasure disabled.
1: Flash program memory erasure enabled.
0
PSWE
Program Store Write Enable.
Setting this bit allows writing a byte of data to the Flash program memory using the
MOVX write instruction. The Flash location should be erased before writing data.
0: Writes to Flash program memory disabled.
1: Writes to Flash program memory enabled; the MOVX write instruction targets Flash
memory.
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SFR Definition 13.2. FLKEY: Flash Lock and Key
Bit
7
6
5
4
3
Name
FLKEY[7:0]
Type
R/W
Reset
0
0
0
0
SFR Page = 0x0; SFR Address = 0xB6
Bit
Name
7:0
0
2
1
0
0
0
0
Function
FLKEY[7:0] Flash Lock and Key Register.
Write:
This register provides a lock and key function for Flash erasures and writes. Flash
writes and erases are enabled by writing 0xA5 followed by 0xF1 to the FLKEY register. Flash writes and erases are automatically disabled after the next write or erase is
complete. If any writes to FLKEY are performed incorrectly, or if a Flash write or erase
operation is attempted while these operations are disabled, the Flash will be permanently
locked from writes or erasures until the next device reset. If an application never
writes to Flash, it can intentionally lock the Flash by writing a non-0xA5 value to
FLKEY from software.
Read:
When read, bits 1–0 indicate the current Flash lock state.
00: Flash is write/erase locked.
01: The first key code has been written (0xA5).
10: Flash is unlocked (writes/erases allowed).
11: Flash writes/erases disabled until the next reset.
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C8051F93x-C8051F92x
SFR Definition 13.3. FLSCL: Flash Scale
Bit
7
6
5
4
3
2
1
0
BYPASS
Name
Type
R
R/W
R
R
R
R
R
R
Reset
0
0
0
0
0
0
0
0
SFR Page = 0x0; SFR Address = 0xB6
Bit
Name
Function
7
Reserved
Reserved. Always Write to 0.
6
BYPASS
Flash Read Timing One-Shot Bypass.
0: The one-shot determines the Flash read time. This setting should be used for operating frequencies less than 10 MHz.
1: The system clock determines the Flash read time. This setting should be used for
frequencies greater than 10 MHz.
5:0
Reserved
Reserved. Always Write to 000000.
Note: When changing the BYPASS bit from 1 to 0, the third opcode byte fetched from program memory is
indeterminate. Therefore, the operation which clears the BYPASS bit should be immediately followed by a
benign 3-byte instruction whose third byte is a don’t care. An example of such an instruction is a 3-byte MOV
that targets the FLWR register. When programming in ‘C’, the dummy value written to FLWR should be a nonzero value to prevent the compiler from generating a 2-byte MOV instruction.
SFR Definition 13.4. FLWR: Flash Write Only
Bit
7
6
5
4
Name
FLWR[7:0]
Type
W
Reset
0
0
0
0
SFR Page = 0x0; SFR Address = 0xE5
Bit
Name
7:0
3
2
1
0
0
0
0
0
Function
FLWR[7:0] Flash Write Only.
All writes to this register have no effect on system operation.
158
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C8051F93x-C8051F92x
14. Power Management
C8051F93x-C8051F92x devices support 5 power modes: Normal, Idle, Stop, Suspend, and Sleep. The
power management unit (PMU0) allows the device to enter and wake-up from the available power modes.
A brief description of each power mode is provided in Table 14.1. Detailed descriptions of each mode can
be found in the following sections.
Table 14.1. Power Modes
Power Mode
Description
Wake-Up
Sources
Power Savings
N/A
Excellent MIPS/mW
Normal
Device fully functional
Idle
All peripherals fully functional.
Very easy to wake up.
Any Interrupt.
Good
No Code Execution
Stop
Legacy 8051 low power mode.
A reset is required to wake up.
Any Reset.
Good
No Code Execution
Precision Oscillator Disabled
Suspend
Similar to Stop Mode, but very fast
wake-up time and code resumes
execution at the next instruction.
SmaRTClock,
Port Match,
Comparator0,
RST pin.
Very Good
No Code Execution
All Internal Oscillators Disabled
System Clock Gated
Sleep
Ultra Low Power and flexible
wake-up sources. Code resumes
execution at the next instruction.
Comparator0 only functional in
two-cell mode.
SmaRTClock,
Port Match,
Comparator0,
RST pin.
Excellent
Power Supply Gated
All Oscillators except SmaRTClock Disabled
In battery powered systems, the system should spend as much time as possible in sleep mode in order to
preserve battery life. When a task with a fixed number of clock cycles needs to be performed, the device
should switch to normal mode, finish the task as quickly as possible, and return to sleep mode. Idle mode
and suspend modes provide a very fast wake-up time; however, the power savings in these modes will not
be as much as in sleep Mode. Stop Mode is included for legacy reasons; the system will be more power
efficient and easier to wake up when idle, suspend, or sleep mode are used.
Although switching power modes is an integral part of power management, enabling/disabling individual
peripherals as needed will help lower power consumption in all power modes. Each analog peripheral can
be disabled when not in use or placed in a low power mode. Digital peripherals such as timers or serial
busses draw little power whenever they are not in use. Digital peripherals draw no power in Sleep Mode.
Rev. 1.3
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C8051F93x-C8051F92x
14.1. Normal Mode
The MCU is fully functional in Normal Mode. Figure 14.1 shows the on-chip power distribution to various
peripherals. There are three supply voltages powering various sections of the chip: VBAT, VDD/DC+, and
the 1.8 V internal core supply. VREG0, PMU0 and the SmaRTClock are always powered directly from the
VBAT pin. All analog peripherals are directly powered from the VDD/DC+ pin, which is an output in one-cell
mode and an input in two-cell mode. All digital peripherals and the CIP-51 core are powered from the 1.8 V
internal core supply. The RAM is also powered from the core supply in Normal mode.
VBAT
One-cell: 0.9 to 1.8 V
Two-cell: 1.8 to 3.6 V
DC0
VDD/DC+
One-cell or Two-cell: 1.8 to 3.6 V
Note: VDD/DC+ must be > VBAT
1.9 V
typical
GPIO
Analog Peripherals
One-Cell Active/
Idle/Stop/Suspend
One-Cell Sleep
VREF
VREG0
A
M
U
X
IREF0
10-bit
300 ksps
ADC
+
TEMP
SENSOR
Sleep
Active/Idle/
Stop/Suspend 1.8 V
-
+
VOLTAGE
COMPARATORS
Digital Peripherals
UART
PMU0
SmaRTClock
CIP-51
Core
RAM
Flash
SPI
Timers
SMBus
Figure 14.1. C8051F93x-C8051F92x Power Distribution
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C8051F93x-C8051F92x
14.2. Idle Mode
Setting the Idle Mode Select bit (PCON.0) causes the CIP-51 to halt the CPU and enter Idle mode as soon
as the instruction that sets the bit completes execution. All internal registers and memory maintain their
original data. All analog and digital peripherals can remain active during Idle mode.
Note: To ensure the MCU enters a low power state upon entry into Idle Mode, the one-shot circuit should be
enabled by clearing the BYPASS bit (FLSCL.6) to logic 0. See the note in SFR Definition 13.3. FLSCL:
Flash Scale for more information on how to properly clear the BYPASS bit.
Idle mode is terminated when an enabled interrupt is asserted or a reset occurs. The assertion of an
enabled interrupt will cause the Idle Mode Selection bit (PCON.0) to be cleared and the CPU to resume
operation. The pending interrupt will be serviced and the next instruction to be executed after the return
from interrupt (RETI) will be the instruction immediately following the one that set the Idle Mode Select bit.
If Idle mode is terminated by an internal or external reset, the CIP-51 performs a normal reset sequence
and begins program execution at address 0x0000.
If enabled, the Watchdog Timer (WDT) will eventually cause an internal watchdog reset and thereby terminate the Idle mode. This feature protects the system from an unintended permanent shutdown in the event
of an inadvertent write to the PCON register. If this behavior is not desired, the WDT may be disabled by
software prior to entering the idle mode if the WDT was initially configured to allow this operation. This provides the opportunity for additional power savings, allowing the system to remain in the Idle mode indefinitely, waiting for an external stimulus to wake up the system. Refer to Section “18.6. PCA Watchdog Timer
Reset” on page 188 for more information on the use and configuration of the WDT.
14.3. Stop Mode
Setting the Stop Mode Select bit (PCON.1) causes the CIP-51 to enter Stop mode as soon as the instruction that sets the bit completes execution. In Stop mode the precision internal oscillator and CPU are
stopped; the state of the low power oscillator and the external oscillator circuit is not affected. Each analog
peripheral (including the external oscillator circuit) may be shut down individually prior to entering Stop
Mode. Stop mode can only be terminated by an internal or external reset. On reset, the CIP-51 performs
the normal reset sequence and begins program execution at address 0x0000.
If enabled, the Missing Clock Detector will cause an internal reset and thereby terminate the Stop mode.
The Missing Clock Detector should be disabled if the CPU is to be put to in STOP mode for longer than the
MCD timeout of 100 µs.
Stop Mode is a legacy 8051 power mode; it will not result in optimal power savings. Sleep or Suspend
mode will provide more power savings if the MCU needs to be inactive for a long period of time.
On C8051F930, C8051F931, C8051F920, and C8051F921 devices, the Precision Oscillator Bias is not
automatically disabled and should be disabled by software to achieve the lowest possible Stop mode current.
Note: To ensure the MCU enters a low power state upon entry into Stop Mode, the one-shot circuit should be
enabled by clearing the BYPASS bit (FLSCL.6) to logic 0. See the note in SFR Definition 13.3. FLSCL:
Flash Scale for more information on how to properly clear the BYPASS bit.
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C8051F93x-C8051F92x
14.4. Suspend Mode
Setting the Suspend Mode Select bit (PMU0CF.6) causes the system clock to be gated off and all internal
oscillators disabled. All digital logic (timers, communication peripherals, interrupts, CPU, etc.) stops
functioning until one of the enabled wake-up sources occurs.
Important Notes:
•
•
•
When entering Suspend Mode, the global clock divider must be set to "divide by 1" by setting
CLKDIV[2:0] = 000b in the CLKSEL register.
The one-shot circuit should be enabled by clearing the BYPASS bit (FLSCL.6) to logic 0. See
the note in SFR Definition 13.3. FLSCL: Flash Scale for more information on how to properly
clear the BYPASS bit.
Upon wake-up from suspend mode, PMU0 requires two system clocks in order to update the
PMU0CF wake-up flags. All flags will read back a value of '0' during the first two system clocks
following a wake-up from suspend mode.
The following wake-up sources can be configured to wake the device from Suspend Mode:
•
•
•
•
SmaRTClock Oscillator Fail
SmaRTClock Alarm
Port Match Event
Comparator0 Rising Edge
In addition, a noise glitch on RST that is not long enough to reset the device will cause the device to exit
suspend. In order for the MCU to respond to the pin reset event, software must not place the device back
into suspend mode for a period of 15 µs. The PMU0CF register may be checked to determine if the wakeup was due to a falling edge on the /RST pin. If the wake-up source is not due to a falling edge on RST,
there is no time restriction on how soon software may place the device back into suspend mode. A 4.7 k
pullup resistor to VDD/DC+ is recommend for RST to prevent noise glitches from waking the device.
14.5. Sleep Mode
Setting the Sleep Mode Select bit (PMU0CF.6) turns off the internal 1.8 V regulator (VREG0) and switches
the power supply of all on-chip RAM to the VBAT pin (see Figure 14.1). Power to most digital logic on the
chip is disconnected; only PMU0 and the SmaRTClock remain powered. Analog peripherals remain
powered in two-cell mode and lose their supply in one-cell mode because the dc-dc converter is disabled.
In two-cell mode, only the Comparators remain functional when the device enters Sleep Mode. All other
analog peripherals (ADC0, IREF0, External Oscillator, etc.) should be disabled prior to entering Sleep
Mode.
Important Notes:
•
•
When entering Sleep Mode, the global clock divider must be set to "divide by 1" by setting
CLKDIV[2:0] = 000b in the CLKSEL register.
Per device errata, for Revision D and prior silicon, the CLKSEL register must select “low power
oscillator divided by 2” as the system clock source and wait for CLKRDY to be set prior to
entering Sleep Mode.
GPIO pins configured as digital outputs will retain their output state during sleep mode. In two-cell mode,
they will maintain the same current drive capability in sleep mode as they have in normal mode. In one-cell
mode, the VDD/DC+ supply will drop to the level of VBAT, which will reduce the output high-voltage level
and the source and sink current drive capability.
162
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GPIO pins configured as digital inputs can be used during sleep mode as wakeup sources using the port
match feature. In two-cell mode, they will maintain the same input level specs in sleep mode as they have
in normal mode. In one-cell mode, the VDD supply will drop to the level of VBAT, which will lower the
switching threshold and increase the propagation delay.
Note: By default, the VDD/DC+ supply is connected to VBAT upon entry into Sleep Mode (one-cell mode). If the
VDDSLP bit (DC0CF.1) is set to logic 1, the VDD/DC+ supply will float in Sleep Mode. This allows the
decoupling capacitance on the VDD/DC+ supply to maintain the supply rail until the capacitors are discharged.
For relatively short sleep intervals, this can result in substantial power savings because the decoupling
capacitance is not continuously charged and discharged.
RAM and SFR register contents are preserved in Sleep mode as long as the voltage on VBAT does not fall
below VPOR. The PC counter and all other volatile state information is preserved allowing the device to
resume code execution upon waking up from Sleep mode. The following wake-up sources can be
configured to wake the device from Sleep mode:
•
•
•
•
SmaRTClock Oscillator Fail
SmaRTClock Alarm
Port Match Event
Comparator0 Rising Edge.
The Comparator0 Rising Edge wakeup is only valid in two-cell mode. The comparator requires a supply
voltage of at least 1.8 V to operate properly.
In addition, any falling edge on RST (due to a pin reset or a noise glitch) will cause the device to exit sleep
mode. In order for the MCU to respond to the pin reset event, software must not place the device back into
sleep mode for a period of 15 µs. The PMU0CF register may be checked to determine if the wake-up was
due to a falling edge on the RST pin. If the wake-up source is not due to a falling edge on RST, there is no
time restriction on how soon software may place the device back into sleep mode. A 4.7 k pullup resistor
to VDD/DC+ is recommend for RST to prevent noise glitches from waking the device.
14.6. Configuring Wakeup Sources
Before placing the device in a low power mode, one or more wakeup sources should be enabled so that
the device does not remain in the low power mode indefinitely. For idle mode, this includes enabling any
interrupt. For stop mode, this includes enabling any reset source or relying on the RST pin to reset the
device.
Wake-up sources for suspend and sleep modes are configured through the PMU0CF register. Wake-up
sources are enabled by writing 1 to the corresponding wake-up source enable bit. Wake-up sources must
be re-enabled each time the device is placed in Suspend or Sleep mode, in the same write that places the
device in the low power mode.
The reset pin is always enabled as a wake-up source. On the falling edge of RST, the device will be
awaken from sleep mode. The device must remain awake for more than 15 µs in order for the reset to take
place.
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C8051F93x-C8051F92x
14.7. Determining the Event that Caused the Last Wakeup
When waking from idle mode, the CPU will vector to the interrupt which caused it to wake up. When
waking from stop mode, the RSTSRC register may be read to determine the cause of the last reset.
Upon exit from suspend or sleep mode, the wake-up flags in the PMU0CF register can be read to
determine the event which caused the device to wake up. After waking up, the wake-up flags will continue
to be updated if any of the wake-up events occur. Wake-up flags are always updated, even if they are not
enabled as wake-up sources.
All wake-up flags enabled as wake-up sources in PMU0CF must be cleared before the device can enter
suspend or sleep mode. After clearing the wake-up flags, each of the enabled wake-up events should be
checked in the individual peripherals to ensure that a wake-up event did not occur while the wake-up flags
were being cleared.
164
Rev. 1.3
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SFR Definition 14.1. PMU0CF: Power Management Unit Configuration1,2
Bit
7
6
5
4
3
2
1
0
Name
SLEEP
SUSPEND
CLEAR
RSTWK
RTCFWK
RTCAWK
PMATWK
CPT0WK
Type
W
W
W
R
R/W
R/W
R/W
R/W
Reset
0
0
0
Varies
Varies
Varies
Varies
Varies
SFR Page = 0x0; SFR Address = 0xB5
Bit
Name
Description
7
SLEEP
6
SUSPEND
5
Write
Read
Sleep Mode Select
Writing 1 places the
device in Sleep Mode.
N/A
Suspend Mode Select
Writing 1 places the
device in Suspend Mode.
N/A
CLEAR
Wake-up Flag Clear
Writing 1 clears all wakeup flags.
N/A
4
RSTWK
Reset Pin Wake-up Flag
N/A
Set to 1 if a glitch has
been detected on RST.
3
RTCFWK
SmaRTClock Oscillator
Fail Wake-up Source
Enable and Flag
0: Disable wake-up on
SmaRTClock Osc. Fail.
1: Enable wake-up on
SmaRTClock Osc. Fail.
Set to 1 if the SmaRTClock Oscillator has failed.
2
RTCAWK
SmaRTClock Alarm
Wake-up Source Enable
and Flag
0: Disable wake-up on
SmaRTClock Alarm.
1: Enable wake-up on
SmaRTClock Alarm.
Set to 1 if a SmaRTClock
Alarm has occurred.
1
PMATWK
Port Match Wake-up
Source Enable and Flag
0: Disable wake-up on
Port Match Event.
1: Enable wake-up on 
Port Match Event.
Set to 1 if a Port Match
Event has occurred.
0
CPT0WK
Comparator0 Wake-up
Source Enable and Flag
0: Disable wake-up on
Comparator0 rising edge.
1: Enable wake-up on
Comparator0 rising edge.
Set to 1 if Comparator0
rising edge caused the last
wake-up.
Notes:
1. Read-modify-write operations (ORL, ANL, etc.) should not be used on this register. Wake-up sources must
be re-enabled each time the SLEEP or SUSPEND bits are written to 1.
2. The Low Power Internal Oscillator cannot be disabled and the MCU cannot be placed in Suspend or Sleep
Mode if any wake-up flags are set to 1. Software should clear all wake-up sources after each reset and after
each wake-up from suspend or sleep modes.
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C8051F93x-C8051F92x
SFR Definition 14.2. PCON: Power Management Control Register
Bit
7
6
5
4
3
2
1
0
Name
GF[5:0]
STOP
IDLE
Type
R/W
W
W
0
0
Reset
0
0
0
0
SFR Page = All Pages; SFR Address = 0x87
Bit
Name
Description
7:2
GF[5:0]
1
0
0
Write
Read
General Purpose Flags
Sets the logic value.
Returns the logic value.
STOP
Stop Mode Select
Writing 1 places the
device in Stop Mode.
N/A
IDLE
Idle Mode Select
Writing 1 places the
device in Idle Mode.
N/A
14.8. Power Management Specifications
See Table 4.5 on page 60 for detailed Power Management Specifications.
166
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15. Cyclic Redundancy Check Unit (CRC0)
C8051F93x-C8051F92x devices include a cyclic redundancy check unit (CRC0) that can perform a CRC
using a 16-bit or 32-bit polynomial. CRC0 accepts a stream of 8-bit data written to the CRC0IN register.
CRC0 posts the 16-bit or 32-bit result to an internal register. The internal result register may be accessed
indirectly using the CRC0PNT bits and CRC0DAT register, as shown in Figure 15.1. CRC0 also has a bit
reverse register for quick data manipulation.
8
CRC0CN
CRC0IN
8
Automatic CRC
Controller
Flash
Memory
CRC0AUTO
CRC0SEL
CRC0INIT
CRC0VAL
CRC0PNT1
CRC0PNT0
CRC Engine
CRC0CNT
32
RESULT
CRC0FLIP
Write
8
8
8
8
4 to 1 MUX
8
CRC0DAT
CRC0FLIP
Read
Figure 15.1. CRC0 Block Diagram
15.1. 16-bit CRC Algorithm
The C8051F93x-C8051F92x CRC unit calculates the 16-bit CRC MSB-first, using a poly of 0x1021. The
following describes the 16-bit CRC algorithm performed by the hardware:
1. XOR the input with the most-significant bits of the current CRC result. If this is the first iteration
of the CRC unit, the current CRC result will be the set initial value 
(0x0000 or 0xFFFF).
2a. If the MSB of the CRC result is set, left-shift the CRC result and XOR the result with the
selected polynomial (0x1021).
2b. If the MSB of the CRC result is not set, left-shift the CRC result.
Repeat steps 2a/2b for the number of input bits (8). The algorithm is also described in the following
example.
Rev. 1.3
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C8051F93x-C8051F92x
The 16-bit C8051F93x-C8051F92x CRC algorithm can be described by the following code:
unsigned short UpdateCRC (unsigned short CRC_acc, unsigned char CRC_input)
{
unsigned char i;
// loop counter
#define POLY 0x1021
// Create the CRC "dividend" for polynomial arithmetic (binary arithmetic
// with no carries)
CRC_acc = CRC_acc ^ (CRC_input << 8);
// "Divide" the poly into the dividend using CRC XOR subtraction
// CRC_acc holds the "remainder" of each divide
//
// Only complete this division for 8 bits since input is 1 byte
for (i = 0; i < 8; i++)
{
// Check if the MSB is set (if MSB is 1, then the POLY can "divide"
// into the "dividend")
if ((CRC_acc & 0x8000) == 0x8000)
{
// if so, shift the CRC value, and XOR "subtract" the poly
CRC_acc = CRC_acc << 1;
CRC_acc ^= POLY;
}
else
{
// if not, just shift the CRC value
CRC_acc = CRC_acc << 1;
}
}
// Return the final remainder (CRC value)
return CRC_acc;
}
The following table lists several input values and the associated outputs using the 16-bit C8051F93xC8051F92x CRC algorithm:
Table 15.1. Example 16-bit CRC Outputs
168
Input
Output
0x63
0xBD35
0x8C
0xB1F4
0x7D
0x4ECA
0xAA, 0xBB, 0xCC
0x6CF6
0x00, 0x00, 0xAA, 0xBB, 0xCC
0xB166
Rev. 1.3
C8051F93x-C8051F92x
15.2. 32-bit CRC Algorithm
The C8051F93x-C8051F92x CRC unit calculates the 32-bit CRC using a poly of 0x04C11DB7. The CRC32 algorithm is "reflected", meaning that all of the input bytes and the final 32-bit output are bit-reversed in
the processing engine. The following is a description of a simplified CRC algorithm that produces results
identical to the hardware:
Step 1. XOR the least-significant byte of the current CRC result with the input byte. If this is the
first iteration of the CRC unit, the current CRC result will be the set initial value
(0x00000000 or 0xFFFFFFFF).
Step 2. Right-shift the CRC result.
Step 3. If the LSB of the CRC result is set, XOR the CRC result with the reflected polynomial
(0xEDB88320).
Step 4. Repeat at Step 2 for the number of input bits (8).
For example, the 32-bit 'F93x/92x CRC algorithm can be described by the following code:
unsigned long UpdateCRC (unsigned long CRC_acc, unsigned char CRC_input)
{
unsigned char i; // loop counter
#define POLY 0xEDB88320 // bit-reversed version of the poly 0x04C11DB7
// Create the CRC "dividend" for polynomial arithmetic (binary arithmetic
// with no carries)
CRC_acc = CRC_acc ^ CRC_input;
// "Divide" the poly into the dividend using CRC XOR subtraction
// CRC_acc holds the "remainder" of each divide
//
// Only complete this division for 8 bits since input is 1 byte
for (i = 0; i < 8; i++)
{
// Check if the MSB is set (if MSB is 1, then the POLY can "divide"
// into the "dividend")
if ((CRC_acc & 0x00000001) == 0x00000001)
{
// if so, shift the CRC value, and XOR "subtract" the poly
CRC_acc = CRC_acc >> 1;
CRC_acc ^= POLY;
}
else
{
// if not, just shift the CRC value
CRC_acc = CRC_acc >> 1;
}
}
// Return the final remainder (CRC value)
return CRC_acc;
}
The following table lists several input values and the associated outputs using the 32-bit 'F93x/92x CRC
algorithm (an initial value of 0xFFFFFFFF is used):
Rev. 1.3
169
C8051F93x-C8051F92x
Table 15.2. Example 32-bit CRC Outputs
Input
Output
0x63
0xF9462090
0xAA, 0xBB, 0xCC
0x41B207B3
0x00, 0x00, 0xAA, 0xBB, 0xCC
0x78D129BC
15.3. Preparing for a CRC Calculation
To prepare CRC0 for a CRC calculation, software should select the desired polynomial and set the initial
value of the result. Two polynomials are available: 0x1021 (16-bit) and 0x04C11DB7 (32-bit). The CRC0
result may be initialized to one of two values: 0x00000000 or 0xFFFFFFFF. The following steps can be
used to initialize CRC0.
1. Select a polynomial (Set CRC0SEL to 0 for 32-bit or 1 for 16-bit).
2. Select the initial result value (Set CRC0VAL to 0 for 0x00000000 or 1 for 0xFFFFFFFF).
3. Set the result to its initial value (Write 1 to CRC0INIT).
15.4. Performing a CRC Calculation
Once CRC0 is initialized, the input data stream is sequentially written to CRC0IN, one byte at a time. The
CRC0 result is automatically updated after each byte is written. The CRC engine may also be configured to
automatically perform a CRC on one or more Flash sectors. The following steps can be used to automatically perform a CRC on Flash memory.
1.
2.
3.
4.
Prepare CRC0 for a CRC calculation as shown above.
Write the index of the starting page to CRC0AUTO.
Set the AUTOEN bit in CRC0AUTO.
Write the number of Flash sectors to perform in the CRC calculation to CRC0CNT. 
Note: Each Flash sector is 1024 bytes.
5. Write any value to CRC0CN (or OR its contents with 0x00) to initiate the CRC calculation. The
CPU will not execute code any additional code until the CRC operation completes.
See the note in SFR Definition 15.1. CRC0CN: CRC0 Control for more information on
how to properly initiate a CRC calculation.
6. Clear the AUTOEN bit in CRC0AUTO.
7. Read the CRC result using the procedure below.
15.5. Accessing the CRC0 Result
The internal CRC0 result is 32-bits (CRC0SEL = 0b) or 16-bits (CRC0SEL = 1b). The CRC0PNT bits
select the byte that is targeted by read and write operations on CRC0DAT and increment after each read or
write. The calculation result will remain in the internal CR0 result register until it is set, overwritten, or additional data is written to CRC0IN.
170
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SFR Definition 15.1. CRC0CN: CRC0 Control
Bit
7
6
5
4
3
2
CRC0SEL CRC0INIT CRC0VAL
Name
Type
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
SFR Page = 0xF; SFR Address = 0x92
Bit
Name
7:5
Unused
1
0
CRC0PNT[1:0]
R/W
0
0
Function
Unused.
Read = 000b; Write = Don’t Care.
4
CRC0SEL
CRC0 Polynomial Select Bit.
This bit selects the CRC0 polynomial and result length (32-bit or 16-bit).
0: CRC0 uses the 32-bit polynomial 0x04C11DB7 for calculating the CRC result.
1: CRC0 uses the 16-bit polynomial 0x1021 for calculating the CRC result.
3
CRC0INIT
CRC0 Result Initialization Bit.
Writing a 1 to this bit initializes the entire CRC result based on CRC0VAL.
2
CRC0VAL
CRC0 Set Value Initialization Bit.
This bit selects the set value of the CRC result.
0: CRC result is set to 0x00000000 on write of 1 to CRC0INIT.
1: CRC result is set to 0xFFFFFFFF on write of 1 to CRC0INIT.
1:0 CRC0PNT[1:0] CRC0 Result Pointer.
Specifies the byte of the CRC result to be read/written on the next access to
CRC0DAT. The value of these bits will auto-increment upon each read or write.
For CRC0SEL = 0:
00: CRC0DAT accesses bits 7–0 of the 32-bit CRC result.
01: CRC0DAT accesses bits 15–8 of the 32-bit CRC result.
10: CRC0DAT accesses bits 23–16 of the 32-bit CRC result.
11: CRC0DAT accesses bits 31–24 of the 32-bit CRC result.
For CRC0SEL = 1:
00: CRC0DAT accesses bits 7–0 of the 16-bit CRC result.
01: CRC0DAT accesses bits 15–8 of the 16-bit CRC result.
10: CRC0DAT accesses bits 7–0 of the 16-bit CRC result.
11: CRC0DAT accesses bits 15–8 of the 16-bit CRC result.
Note: Upon initiation of an automatic CRC calculation, the third opcode byte fetched from program memory is
indeterminate. Therefore, writes to CRC0CN that initiate a CRC operation must be immediately followed by a
benign 3-byte instruction whose third byte is a don’t care. An example of such an instruction is a 3-byte MOV
that targets the CRC0FLIP register. When programming in ‘C’, the dummy value written to CRC0FLIP should
be a non-zero value to prevent the compiler from generating a 2-byte MOV instruction.
Rev. 1.3
171
C8051F93x-C8051F92x
SFR Definition 15.2. CRC0IN: CRC0 Data Input
Bit
7
6
5
4
3
Name
CRC0IN[7:0]
Type
R/W
Reset
0
0
0
0
0
SFR Page = 0xF; SFR Address = 0x93
Bit
Name
7:0
CRC0IN[7:0]
2
1
0
0
0
0
Function
CRC0 Data Input.
Each write to CRC0IN results in the written data being computed into the existing
CRC result according to the CRC algorithm described in Section 15.1
SFR Definition 15.3. CRC0DAT: CRC0 Data Output
Bit
7
6
5
4
3
Name
CRC0DAT[7:0]
Type
R/W
Reset
0
0
0
0
SFR Page = 0xF; SFR Address = 0x91
Bit
Name
0
2
1
0
0
0
0
Function
7:0 CRC0DAT[7:0] CRC0 Data Output.
Each read or write performed on CRC0DAT targets the CRC result bits pointed to
by the CRC0 Result Pointer (CRC0PNT bits in CRC0CN).
172
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SFR Definition 15.4. CRC0AUTO: CRC0 Automatic Control
Bit
7
6
Name
AUTOEN
CRCDONE
5
4
3
2
1
CRC0ST[5:0]
R/W
Type
Reset
0
1
0
AUTOEN
R/W
0
SFR Page = 0xF; SFR Address = 0x96
Bit
Name
7
0
0
0
0
0
Function
Automatic CRC Calculation Enable.
When AUTOEN is set to 1, any write to CRC0CN will initiate an automatic CRC
starting at Flash sector CRC0ST and continuing for CRC0CNT sectors.
6
CRCDONE
CRCDONE Automatic CRC Calculation Complete.
Set to 0 when a CRC calculation is in progress. Note that code execution is
stopped during a CRC calculation, therefore reads from firmware will always
return 1.
5:0
CRC0ST[5:0]
Automatic CRC Calculation Starting Flash Sector.
These bits specify the Flash sector to start the automatic CRC calculation. The
starting address of the first Flash sector included in the automatic CRC calculation
is CRC0ST x 1024.
SFR Definition 15.5. CRC0CNT: CRC0 Automatic Flash Sector Count
Bit
7
6
5
4
2
1
R/W
Type
Reset
0
CRC0CNT[5:0]
Name
0
0
0
0
SFR Page = 0xF; SFR Address = 0x97
Bit
Name
7:6
3
Unused
R/W
0
0
0
0
Function
Unused.
Read = 00b; Write = Don’t Care.
5:0
CRC0CNT[5:0] Automatic CRC Calculation Flash Sector Count.
These bits specify the number of Flash sectors to include in an automatic CRC
calculation. The starting address of the last Flash sector included in the automatic
CRC calculation is (CRC0ST+CRC0CNT) x 1024.
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C8051F93x-C8051F92x
15.6. CRC0 Bit Reverse Feature
CRC0 includes hardware to reverse the bit order of each bit in a byte as shown in Figure 15.2. Each byte
of data written to CRC0FLIP is read back bit reversed. For example, if 0xC0 is written to CRC0FLIP, the
data read back is 0x03. Bit reversal is a useful mathematical function used in algorithms such as the FFT.
CRC0FLIP
Write
CRC0FLIP
Read
Figure 15.2. Bit Reverse Register
SFR Definition 15.6. CRC0FLIP: CRC0 Bit Flip
Bit
7
6
5
4
3
Name
CRC0FLIP[7:0]
Type
R/W
Reset
0
0
0
0
SFR Page = 0xF; SFR Address = 0x95
Bit
Name
7:0
CRC0FLIP[7:0]
0
2
1
0
0
0
0
Function
CRC0 Bit Flip.
Any byte written to CRC0FLIP is read back in a bit-reversed order, i.e. the written
LSB becomes the MSB. For example:
If 0xC0 is written to CRC0FLIP, the data read back will be 0x03.
If 0x05 is written to CRC0FLIP, the data read back will be 0xA0.
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16. On-Chip DC-DC Converter (DC0)
C8051F93x-C8051F92x devices include an on-chip dc-dc converter to allow operation from a single cell
battery with a supply voltage as low as 0.9 V. The dc-dc converter is a switching boost converter with an
input voltage range of 0.9 to 1.8 V and a programmable output voltage range of 1.8 to 3.3 V. The default
output voltage is 1.9 V. The dc-dc converter can supply the system with up to 65 mW of regulated power
(or up to 100 mW in some applications) and can be used for powering other devices in the system. This
allows the most flexibility when interfacing to sensors and other analog signals which typically require a
higher supply voltage than a single-cell battery can provide.
Figure 16.1 shows a block diagram of the dc-dc converter. During normal operation in the first half of the
switching cycle, the Duty Cycle Control switch is closed and the Diode Bypass switch is open. Since the
output voltage is higher than the voltage at the DCEN pin, no current flows through the diode and the load
is powered from the output capacitor. During this stage, the DCEN pin is connected to ground through the
Duty Cycle Control switch, generating a positive voltage across the inductor and forcing its current to ramp
up.
In the second half of the switching cycle, the Duty Cycle control switch is opened and the Diode Bypass
switch is closed. This connects DCEN directly to VDD/DC+ and forces the inductor current to charge the
output capacitor. Once the inductor transfers its stored energy to the output capacitor, the Duty Cycle Control switch is closed, the Diode Bypass switch is opened, and the cycle repeats.
The dc-dc converter has a built in voltage reference and oscillator, and will automatically limit or turn off the
switching activity in case the peak inductor current rises beyond a safe limit or the output voltage rises
above the programmed target value. This allows the dc-dc converter output to be safely overdriven by a
secondary power source (when available) in order to preserve battery life. The dc-dc converter’s settings
can be modified using SFR registers which provide the ability to change the target output voltage, oscillator
frequency or source, Diode Bypass switch resistance, peak inductor current, and minimum duty cycle.
DC/DC Converter
VBAT
VDD/DC+
0.68 uH
DCEN
Diode
Bypass
4.7 uF
Duty
Cycle
Control
GND
Control Logic
DC0CN
Voltage
Reference
DC0CF
DC/DC
Oscillator
Lparasitic
Lparasitic
1uF
Iload
Cload
GND/DC-
Figure 16.1. DC-DC Converter Block Diagram
Rev. 1.3
175
C8051F93x-C8051F92x
16.1. Startup Behavior
On initial power-on, the dc-dc converter outputs a constant 50% duty cycle until there is sufficient voltage
on the output capacitor to maintain regulation. The size of the output capacitor and the amount of load current present during startup will determine the length of time it takes to charge the output capacitor.
During initial power-on reset, the maximum peak inductor current threshold, which triggers the overcurrent
protection circuit, is set to approximately 125 mA. This generates a “soft-start” to limit the output voltage
slew rate and prevent excessive in-rush current at the output capacitor. In order to ensure reliable startup
of the dc-dc converter, the following restrictions have been imposed:
•
The maximum dc load current allowed during startup is given in Table 4.14 on page 66. If the dc-dc
converter is powering external sensors or devices through the VDD/DC+ pin or through GPIO pins,
then the current supplied to these sensors or devices is counted towards this limit. The in-rush current
into capacitors does not count towards this limit.
•
The maximum total output capacitance is given in Table 4.14 on page 66. This value includes the
required 1 µF ceramic output capacitor and any additional capacitance connected to the VDD/DC+ pin.

Once initial power-on is complete, the peak inductor current limit can be increased by software as shown in
Table 16.1. Limiting the peak inductor current can allow the device to start up near the battery’s end of life.
.
Table 16.1. IPeak Inductor Current Limit Settings
SWSEL
ILIMIT
Peak Current (mA)
1
0
100
0
0
125
1
1
250
0
1
500
The peak inductor current is dependent on several factors including the dc load current and can be estimated using following equation:
2 I LOAD  VDD/DC+ – VBAT 
I PK = --------------------------------------------------------------------------------------------------efficiency  inductance  frequency
efficiency = 0.80
inductance = 0.68 µH
frequency = 2.4 MHz
176
Rev. 1.3
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16.2. High Power Applications
The dc-dc converter is designed to provide the system with 65 mW of output power, however, it can safely
provide up to 100 mW of output power without any risk of damage to the device. For high power applications, the system should be carefully designed to prevent unwanted VBAT and VDD/DC+ Supply Monitor
resets, which are more likely to occur when the dc-dc converter output power exceeds 65mW. In addition,
output power above 65 mW causes the dc-dc converter to have relaxed output regulation, high output ripple and more analog noise. At high output power, an inductor with low DC resistance should be chosen in
order to minimize power loss and maximize efficiency.
The combination of high output power and low input voltage will result in very high peak and average
inductor currents. If the power supply has a high internal resistance, the transient voltage on the VBAT terminal could drop below 0.9 V and trigger a VBAT Supply Monitor Reset, even if the open-circuit voltage is
well above the 0.9 V threshold. While this problem is most often associated with operation from very small
batteries or batteries that are near the end of their useful life, it can also occur when using bench power
supplies that have a slow transient response; the supply’s display may indicate a voltage above 0.9 V, but
the minimum voltage on the VBAT pin may be lower. A similar problem can occur at the output of the dc-dc
converter: using the default low current limit setting (125 mA) can trigger VDD Supply Monitor resets if there
is a high transient load current, particularly if the programmed output voltage is at or near 1.8 V.
16.3. Pulse Skipping Mode
The dc-dc converter allows the user to set the minimum pulse width such that if the duty cycle needs to
decrease below a certain width in order to maintain regulation, an entire "clock pulse" will be skipped.
Pulse skipping can provide substantial power savings, particularly at low values of load current. The converter will continue to maintain a minimum output voltage at its programmed value when pulse skipping is
employed, though the output voltage ripple can be higher. Another consideration is that the dc-dc will operate with pulse-frequency modulation rather than pulse-width modulation, which makes the switching frequency spectrum less predictable; this could be an issue if the dc-dc converter is used to power a radio.
Figure 4.5 and Figure 4.6 on page 52 and 53 show the effect of pulse skipping on power consumption.
Rev. 1.3
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C8051F93x-C8051F92x
16.4. Enabling the DC-DC Converter
On power-on reset, the state of the DCEN pin is sampled to determine if the device will power up in onecell or two-cell mode. In two-cell mode, the dc-dc converter always remains disabled. In one-cell mode, the
dc-dc converter remains disabled in Sleep Mode, and enabled in all other power modes. See Section
“14. Power Management” on page 159 for complete details on available power modes.
The dc-dc converter is enabled (one-cell mode) in hardware by placing a 0.68 µH inductor between DCEN
and VBAT. The dc-dc converter is disabled (two-cell mode) by shorting DCEN directly to GND. The DCEN
pin should never be left floating. Note that the device can only switch between one-cell and two-cell mode
during a power-on reset. See Section “18. Reset Sources” on page 184 for more information regarding
reset behavior.
Figure 16.2 shows the two dc-dc converter configuration options.
0.68 uH
DC-DC Converter
Enabled
0.9 to 1.8 V 
Supply Voltage
1 uF
4.7 uF
VBAT
GND
DCEN VDD/DC+ GND/DC-
VBAT
GND
DCEN VDD/DC+ GND/DC-
(one-cell mode)
DC-DC Converter
Disabled
1.8 to 3.6 V 
Supply Voltage
(two-cell mode)
Figure 16.2. DC-DC Converter Configuration Options
When the dc-dc converter “Enabled” configuration (one-cell mode) is chosen, the following guidelines
apply:
•
•
•
•
•
178
In most cases, the GND/DC– pin should not be externally connected to GND.
The 0.68 µH inductor should be placed as close as possible to the DCEN pin for maximum efficiency.
The 4.7 µF capacitor should be placed as close as possible to the inductor.
The current loop including GND, the 4.7 µF capacitor, the 0.68 µH inductor and the DCEN pin should
be made as short as possible.
The PCB traces connecting VDD/DC+ to the output capacitor and the output capacitor to GND/DC–
should be as short and as thick as possible in order to minimize parasitic inductance.
Rev. 1.3
C8051F93x-C8051F92x
16.5. Minimizing Power Supply Noise
To minimize noise on the power supply lines, the GND and GND/DC- pins should be kept separate, as
shown in Figure 16.2; one or the other should be connected to the pc board ground plane. For applications
in which the dc-dc converter is used only to power internal circuits, the GND pin is normally connected to
the board ground.
The large decoupling capacitors in the input and output circuits ensure that each supply is relatively quiet
with respect to its own ground. However, connecting a circuit element "diagonally" (e.g. connecting an
external chip between VDD/DC+ and GND, or between VBAT and GND/DC-) can result in high supply
noise across that circuit element. For applications in which the dc-dc converter is used to power external
analog circuitry, it is recommended to connect the GND/DC– pin to the board ground and connect the battery’s negative terminal to the GND pin only, which is not connected to board ground.
To accommodate situations in which ADC0 is sampling a signal that is referenced to one of the external
grounds, we recommend using the Analog Ground Reference (P0.1/AGND) option described in Section
5.12. This option prevents any voltage differences between the internal chip ground and the external
grounds from modulating the ADC input signal. If this option is enabled, the P0.1 pin should be tied to the
ground reference of the external analog input signal. When using the ADC with the dc-dc converter, we
also recommend enabling the SYNC bit in the DC0CN register to minimize interference.
These general guidelines provide the best performance in most applications, though some situations may
benefit from experimentation to eliminate any residual noise issues. Examples might include tying the
grounds together, using additional low-inductance decoupling caps in parallel with the recommended ones,
investigating the effects of different dc-dc converter settings, etc.
16.6. Selecting the Optimum Switch Size
The dc-dc converter has two built-in switches (the diode bypass switch and duty cycle control switch). To
maximize efficiency, one of two switch sizes may be selected. The large switches are ideal for carrying
high currents and the small switches are ideal for low current applications. The ideal switchover point to
switch from the small switches to the large switches varies with the programmed output voltage. At an output voltage of 2 V, the ideal switchover point is at approximately 4 mA total output current. At an output
voltage of 3 V, the ideal switchover point is at approximately 8 mA total output current.
16.7. DC-DC Converter Clocking Options
The dc-dc converter may be clocked from its internal oscillator, or from any system clock source, selectable by the CLKSEL bit (DC0CF.0). The dc-dc converter internal oscillator frequency is approximately
2.4 MHz. For a more accurate clock source, the system clock, or a divided version of the system clock may
be used as the dc-dc clock source. The dc-dc converter has a built in clock divider (configured using
DC0CF[6:5]) which allows any system clock frequency over 1.6 MHz to generate a valid clock in the range
of 1.6 to 3.2 MHz.
When the precision internal oscillator is selected as the system clock source, the OSCICL register may be
used to fine tune the oscillator frequency and the dc-dc converter clock. The oscillator frequency should
only be decreased since it is factory calibrated at its maximum frequency. The minimum frequency which
can be reached by the oscillator after taking into account process variations is approximately 16 MHz. The
system clock routed to the dc-dc converter clock divider also may be inverted by setting the CLKINV bit
(DC0CF.3) to logic 1. These options can be used to minimize interference in noise sensitive applications.
Rev. 1.3
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C8051F93x-C8051F92x
16.8. DC-DC Converter Behavior in Sleep Mode
When the C8051F93x-C8051F92x devices are placed in Sleep mode, the dc-dc converter is disabled, and
the VDD/DC+ output is internally connected to VBAT by default. This behavior ensures that the GPIO pins
are powered from a low-impedance source during sleep mode. If the GPIO pins are not used as inputs or
outputs during sleep mode, then the VDD/DC+ output can be made to float during Sleep mode by setting
the VDDSLP bit in the DC0CF register to 1.
Setting this bit can provide power savings in two ways. First, if the sleep interval is relatively short and the
VDD/DC+ load current (include leakage currents) is negligible, then the capacitor on VDD/DC+ will maintain the output voltage near the programmed value, which means that the VDD/DC+ capacitor will not need
to be recharged upon every wake up event. The second power advantage is that internal or external lowpower circuits that require more than 1.8 V can continue to function during Sleep mode without operating
the dc-dc converter, powered by the energy stored in the 1 µF output decoupling capacitor. For example,
the C8051F93x-C8051F92x comparators require about 0.4 µA when operating in their lowest power mode.
If the dc-dc converter output were increased to 3.3 V just before putting the device into Sleep mode, then
the comparator could be powered for more than 3 seconds before the output voltage dropped to 1.8 V. In
this example, the overall energy consumption would be much lower than if the dc-dc converter were kept
running to power the comparator.
If the load current on VDD/DC+ is high enough to discharge the VDD/DC+ capacitance to a voltage lower
than VBAT during the sleep interval, an internal diode will prevent VDD/DC+ from dropping more than a
few hundred millivolts below VBAT. There may be some additional leakage current from VBAT to ground
when the VDD/DC+ level falls below VBAT, but this leakage current should be small compared to the current from VDD/DC+.
The amount of time that it takes for a device configured in one-cell mode to wake up from Sleep mode
depends on a number of factors, including the dc-dc converter clock speed, the settings of the SWSEL and
ILIMIT bits, the battery internal resistance, the load current, and the difference between the VBAT voltage
level and the programmed output voltage. The wake up time can be as short as 2 µs, though it is more
commonly in the range of 5 to 10 µs, and it can exceed 50 µs under extreme conditions.
See Section “14. Power Management” on page 159 for more information about sleep mode.
180
Rev. 1.3
C8051F93x-C8051F92x
16.9. DC-DC Converter Register Descriptions
The SFRs used to configure the dc-dc converter are described in the following register descriptions. The
reset values for these registers can be used as-is in most systems; therefore, no software intervention or
initialization is required.
SFR Definition 16.1. DC0CN: DC-DC Converter Control
Bit
7
6
5
4
3
2
1
Name
MINPW
SWSEL
Reserved
SYNC
VSEL
Type
R/W
R/W
R/W
R/W
R/W
1
0
0
Reset
0
0
SFR Page = 0x0; SFR Address = 0x97
Bit
Name
7:6
0
0
0
1
Function
MINPW[1:0] DC-DC Converter Minimum Pulse Width.
Specifies the minimum pulse width.
00: No minimum duty cycle.
01: Minimum pulse width is 20 ns.
10: Minimum pulse width is 40 ns.
11: Minimum pulse width is 80 ns.
5
SWSEL
DC-DC Converter Switch Select.
Selects one of two possible converter switch sizes to maximize efficiency.
0: The large switches are selected (best efficiency for high output currents).
1: The small switches are selected (best efficiency for low output currents).
4
Reserved
3
SYNC
Reserved. Always Write to 0.
ADC0 Synchronization Enable.
When synchronization is enabled, the ADC0SC[4:0] bits in the ADC0CF register
must be set to 00000b. Behavior as described is valid in REVC and later devices.
0: The ADC is not synchronized to the dc-dc converter.
1: The ADC is synchronized to the dc-dc converter. ADC0 tracking is performed
during the longest quiet time of the dc-dc converter switching cycle and ADC0 SAR
clock is also synchronized to the dc-dc converter switching cycle.
2:0
VSEL[2:0]
DC-DC Converter Output Voltage Select.
Specifies the target output voltage.
000: Target output voltage is 1.8 V.
001: Target output voltage is 1.9 V.
010: Target output voltage is 2.0 V.
011: Target output voltage is 2.1 V.
100: Target output voltage is 2.4 V.
101: Target output voltage is 2.7 V.
110: Target output voltage is 3.0 V.
111: Target output voltage is 3.3 V.
Rev. 1.3
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C8051F93x-C8051F92x
SFR Definition 16.2. DC0CF: DC-DC Converter Configuration
Bit
7
6
Name
Reserved
Type
R
R/W
Reset
0
0
5
4
3
2
1
0
AD0CKINV
CLKINV
ILIMIT
VDDSLP
CLKSEL
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
CLKDIV[1:0]
SFR Page = 0x0; SFR Address = 0x96
Bit
Name
7
Reserved Reserved.
6:5
4
3
Function
Read = 0b; Must write 0b.
CLKDIV[1:0] DC-DC Clock Divider.
Divides the dc-dc converter clock when the system clock is selected as the clock
source for dc-dc converter. These bits are ignored when the dc-dc converter is
clocked from its local oscillator.
00: The dc-dc converter clock is system clock divided by 1.
01: The dc-dc converter clock is system clock divided by 2.
10: The dc-dc converter clock is system clock divided by 4.
11: The dc-dc converter clock is system clock divided by 8.
AD0CKINV ADC0 Clock Inversion (Clock Invert During Sync).
Inverts the ADC0 SAR clock derived from the dc-dc converter clock when the SYNC
bit (DC0CN.3) is enabled. This bit is ignored when the SYNC bit is set to zero.
0: ADC0 SAR clock is inverted.
1: ADC0 SAR clock is not inverted.
CLKINV
DC-DC Converter Clock Invert.
Inverts the system clock used as the input to the dc-dc clock divider.
0: The dc-dc converter clock is not inverted.
1: The dc-dc converter clock is inverted.
2
ILIMIT
Peak Current Limit Threshold.
Sets the threshold for the maximum allowed peak inductor current. See Table 16.1
for peak inductor current levels.
0: Peak inductor current is set at a lower level.
1: Peak inductor current is set at a higher level.
1
0
VDDSLP
VDD-DC+ Sleep Mode Connection.
CLKSEL
Specifies the power source for VDD/DC+ in Sleep Mode when the dc-dc converter is
enabled.
0: VDD-DC+ connected to VBAT in Sleep Mode.
1: VDD-DC+ is floating in Sleep Mode.
DC-DC Converter Clock Source Select.
Specifies the dc-dc converter clock source.
0: The dc-dc converter is clocked from its local oscillator.
1: The dc-dc converter is clocked from the system clock.
16.10. DC-DC Converter Specifications
See Table 4.14 on page 66 for a detailed listing of dc-dc converter specifications.
182
Rev. 1.3
C8051F93x-C8051F92x
17. Voltage Regulator (VREG0)
C8051F93x-C8051F92x devices include an internal voltage regulator (VREG0) to regulate the internal
core supply to 1.8 V from a VDD/DC+ supply of 1.8 to 3.6 V. Electrical characteristics for the on-chip
regulator are specified in the Electrical Specifications chapter.
The REG0CN register allows the Precision Oscillator Bias to be disabled, reducing supply current in all
non-sleep power modes. This bias should only be disabled when the precision oscillator is not being used.
The internal regulator (VREG0) is disabled when the device enters sleep mode and remains enabled when
the device enters suspend mode. See Section “14. Power Management” on page 159 for complete details
about low power modes.
SFR Definition 17.1. REG0CN: Voltage Regulator Control
Bit
7
Name
6
5
4
Reserved
Reserved
OSCBIAS
3
2
1
0
Reserved
Type
R
R/W
R/W
R/W
R
R
R
R/W
Reset
0
0
0
1
0
0
0
0
SFR Page = 0x0; SFR Address = 0xC9
Bit
Name
7
Unused
Function
Unused.
Read = 0b. Write = Don’t care.
6
Reserved Reserved.
Read = 0b. Must Write 0b.
5
Reserved Reserved.
Read = 0b. Must Write 0b.
4
OSCBIAS Precision Oscillator Bias.
When set to 1, the bias used by the precision oscillator is forced on. If the precision
oscillator is not being used, this bit may be cleared to 0 to save approximately 80 µA
of supply current in all non-Sleep power modes. If disabled then re-enabled, the precision oscillator bias requires 4 µs of settling time.
3:1
Unused
Unused.
Read = 000b. Write = Don’t care.
0
Reserved Reserved.
Read = 0b. Must Write 0b.
17.1. Voltage Regulator Electrical Specifications
See Table 4.15 on page 66 for detailed Voltage Regulator Electrical Specifications.
Rev. 1.3
183
C8051F93x-C8051F92x
18. Reset Sources
Reset circuitry allows the controller to be easily placed in a predefined default condition. On entry to this
reset state, the following occur:
•
•
•
•
CIP-51 halts program execution
Special Function Registers (SFRs) are initialized to their defined reset values
External Port pins are forced to a known state
Interrupts and timers are disabled
All SFRs are reset to the predefined values noted in the SFR descriptions. The contents of RAM are
unaffected during a reset; any previously stored data is preserved as long as power is not lost. Since the
stack pointer SFR is reset, the stack is effectively lost, even though the data on the stack is not altered.
The Port I/O latches are reset to 0xFF (all logic ones) in open-drain mode. Weak pullups are enabled
during and after the reset. For VDD Monitor and power-on resets, the RST pin is driven low until the device
exits the reset state.
On exit from the reset state, the program counter (PC) is reset, and the system clock defaults to an internal
oscillator. Refer to Section “19. Clocking Sources” on page 191 for information on selecting and
configuring the system clock source. The Watchdog Timer is enabled with the system clock divided by 12
as its clock source (Section “26.4. Watchdog Timer Mode” on page 316 details the use of the Watchdog
Timer). Program execution begins at location 0x0000.
VDD/DC+
+
-
Px.x
SmaRTClock
Power On
Reset
Supply
Monitor
Comparator 0
Px.x
VBAT
+
-
C0RSEF
(wired-OR)
RST
'0'
Enable
RTC0RE
Missing
Clock
Detector
(oneshot)
EN
Reset
Funnel
PCA
WDT
(Software Reset)
SWRSF
System
Clock
Illegal Flash
Operation
WDT
Enable
MCD
Enable
EN
CIP-51
Microcontroller
Core
System Reset
System Reset
Power Management
Block (PMU0)
Reset
Extended Interrupt
Handler
Figure 18.1. Reset Sources
184
Rev. 1.3
Power-On Reset
C8051F93x-C8051F92x
18.1. Power-On (VBAT Supply Monitor) Reset
During power-up, the device is held in a reset state and the RST pin is driven low until VBAT settles above
VPOR. An additional delay occurs before the device is released from reset; the delay decreases as the
VBAT ramp time increases (VBAT ramp time is defined as how fast VBAT ramps from 0 V to VPOR).
Figure 18.3 plots the power-on and VDD monitor reset timing. For valid ramp times (less than 3 ms), the
power-on reset delay (TPORDelay) is typically 3 ms (VBAT = 0.9 V), 7 ms (VBAT = 1.8 V), or 15 ms (VBAT =
3.6 V).
Note: The maximum VDD ramp time is 3 ms; slower ramp times may cause the device to be released from reset
before VBAT reaches the VPOR level.
volts
On exit from a power-on reset, the PORSF flag (RSTSRC.1) is set by hardware to logic 1. When PORSF is
set, all of the other reset flags in the RSTSRC Register are indeterminate (PORSF is cleared by all other
resets). Since all resets cause program execution to begin at the same location (0x0000), software can
read the PORSF flag to determine if a power-up was the cause of reset. The contents of internal data
memory should be assumed to be undefined after a power-on reset.
VBAT
~0.8
VPOR
VB
AT
0.6
~0.5
See specification
table for min/max
voltages.
t
Logic HIGH
Logic LOW
RST
TPORDelay
Power-On
Reset
TPORDelay
Power-On
Reset
Figure 18.2. Power-Fail Reset Timing Diagram
Rev. 1.3
185
C8051F93x-C8051F92x
18.2. Power-Fail (VDD/DC+ Supply Monitor) Reset
C8051F93x-C8051F92x devices have a VDD/DC+ Supply Monitor that is enabled and selected as a reset
source after each power-on or power-fail reset. When enabled and selected as a reset source, any power
down transition or power irregularity that causes VDD/DC+ to drop below VRST will cause the RST pin to
be driven low and the CIP-51 will be held in a reset state (see Figure 18.3). When VDD/DC+ returns to a
level above VRST, the CIP-51 will be released from the reset state.
After a power-fail reset, the PORSF flag reads 1, the contents of RAM invalid, and the VDD/DC+ supply
monitor is enabled and selected as a reset source. The enable state of the VDD/DC+ supply monitor and
its selection as a reset source is only altered by power-on and power-fail resets. For example, if the
VDD/DC+ supply monitor is de-selected as a reset source and disabled by software, then a software reset
is performed, the VDD/DC+ supply monitor will remain disabled and de-selected after the reset.
In battery-operated systems, the contents of RAM can be preserved near the end of the battery’s usable
life if the device is placed in sleep mode prior to a power-fail reset occurring. When the device is in sleep
mode, the power-fail reset is automatically disabled and the contents of RAM are preserved as long as the
VBAT supply does not fall below VPOR. A large capacitor can be used to hold the power supply voltage
above VPOR while the user is replacing the battery. Upon waking from sleep mode, the enable and reset
source select state of the VDD/DC+ supply monitor are restored to the value last set by the user.
To allow software early notification that a power failure is about to occur, the VDDOK bit is cleared when
the VDD/DC+ supply falls below the VWARN threshold. The VDDOK bit can be configured to generate an
interrupt. See Section “12. Interrupt Handler” on page 136 for more details.
volts
Important Note: To protect the integrity of Flash contents, the VDD/DC+ supply monitor must be
enabled and selected as a reset source if software contains routines which erase or write Flash
memory. If the VDD/DC+ supply monitor is not enabled, any erase or write performed on Flash memory
will cause a Flash Error device reset.
VDD/DC+
V WARN
V RST
VBAT
V POR
t
VDDOK
SLEEP
RST
Active Mode
Power-Fail Reset
Sleep Mode
RAM Retained - No Reset
Note: W akeup signal
required after new
battery insertion
Figure 18.3. Power-Fail Reset Timing Diagram
186
Rev. 1.3
C8051F93x-C8051F92x
Important Notes:
•
The Power-on Reset (POR) delay is not incurred after a VDD/DC+ supply monitor reset. See Section
“4. Electrical Characteristics” on page 45 for complete electrical characteristics of the VDD/DC+ monitor.
Software should take care not to inadvertently disable the VDD Monitor as a reset source when writing
to RSTSRC to enable other reset sources or to trigger a software reset. All writes to RSTSRC should
explicitly set PORSF to '1' to keep the VDD Monitor enabled as a reset source.
The VDD/DC+ supply monitor must be enabled before selecting it as a reset source. Selecting the
VDD/DC+ supply monitor as a reset source before it has stabilized may generate a system reset. In
systems where this reset would be undesirable, a delay should be introduced between enabling the
VDD/DC+ supply monitor and selecting it as a reset source. See Section “4. Electrical Characteristics”
on page 45 for minimum VDD/DC+ Supply Monitor turn-on time. No delay should be introduced in
systems where software contains routines that erase or write Flash memory. The procedure for
enabling the VDD/DC+ supply monitor and selecting it as a reset source is shown below:
•
•
1. Enable the VDD/DC+ Supply Monitor (VDMEN bit in VDM0CN = 1).
2. Wait for the VDD/DC+ Supply Monitor to stabilize (optional).
3. Select the VDD/DC+ Supply Monitor as a reset source (PORSF bit in RSTSRC = 1).
SFR Definition 18.1. VDM0CN: VDD/DC+ Supply Monitor Control
Bit
7
6
5
4
3
2
Name
VDMEN
VDDSTAT
VDDOK
Reserved
Reserved
Reserved
Type
R/W
R
R
R/W
R/W
Reset
1
Varies
Varies
0
0
SFR Page = 0x0; SFR Address = 0xFF
Bit
Name
7
VDMEN
1
0
R/W
R/W
R/W
0
0
0
Function
VDD/DC+ Supply Monitor Enable.
This bit turns the VDD/DC+ supply monitor circuit on/off. The VDD/DC+ Supply
Monitor cannot generate system resets until it is also selected as a reset source in
register RSTSRC (SFR Definition 18.2).
0: VDD/DC+ Supply Monitor Disabled.
1: VDD/DC+ Supply Monitor Enabled.
6
VDDSTAT
VDD/DC+ Supply Status.
This bit indicates the current power supply status.
0: VDD/DC+ is at or below the VRST threshold.
1: VDD/DC+ is above the VRST threshold.
5
VDDOK
VDD/DC+ Supply Status (Early Warning).
This bit indicates the current power supply status.
0: VDD/DC+ is at or below the VWARN threshold.
1: VDD/DC+ is above the VWARN monitor threshold.
4:2
Reserved
Reserved.
Read = 000b. Must Write 000b.
1:0
Unused
Unused.
Read = 00b. Write = Don’t Care.
Rev. 1.3
187
C8051F93x-C8051F92x
18.3. External Reset
The external RST pin provides a means for external circuitry to force the device into a reset state. Asserting an active-low signal on the RST pin generates a reset; an external pullup and/or decoupling of the RST
pin may be necessary to avoid erroneous noise-induced resets. See Table 4.4 for complete RST pin specifications. The external reset remains functional even when the device is in the low power suspend and
sleep modes. The PINRSF flag (RSTSRC.0) is set on exit from an external reset.
18.4. Missing Clock Detector Reset
The Missing Clock Detector (MCD) is a one-shot circuit that is triggered by the system clock. If the system
clock remains high or low for more than 100 µs, the one-shot will time out and generate a reset. After a
MCD reset, the MCDRSF flag (RSTSRC.2) will read 1, signifying the MCD as the reset source; otherwise,
this bit reads 0. Writing a 1 to the MCDRSF bit enables the Missing Clock Detector; writing a 0 disables it.
The missing clock detector reset is automatically disabled when the device is in the low power Suspend or
Sleep mode. Upon exit from either low power state, the enabled/disabled state of this reset source is
restored to its previous value. The state of the RST pin is unaffected by this reset.
18.5. Comparator0 Reset
Comparator0 can be configured as a reset source by writing a 1 to the C0RSEF flag (RSTSRC.5).
Comparator0 should be enabled and allowed to settle prior to writing to C0RSEF to prevent any turn-on
chatter on the output from generating an unwanted reset. The Comparator0 reset is active-low: if the noninverting input voltage (on CP0+) is less than the inverting input voltage (on CP0-), the device is put into
the reset state. After a Comparator0 reset, the C0RSEF flag (RSTSRC.5) will read 1 signifying
Comparator0 as the reset source; otherwise, this bit reads 0. The Comparator0 reset source remains functional even when the device is in the low power suspend and sleep states as long as Comparator0 is also
enabled as a wake-up source. The state of the RST pin is unaffected by this reset.
18.6. PCA Watchdog Timer Reset
The programmable Watchdog Timer (WDT) function of the Programmable Counter Array (PCA) can be
used to prevent software from running out of control during a system malfunction. The PCA WDT function
can be enabled or disabled by software as described in Section “26.4. Watchdog Timer Mode” on
page 316; the WDT is enabled and clocked by SYSCLK / 12 following any reset. If a system malfunction
prevents user software from updating the WDT, a reset is generated and the WDTRSF bit (RSTSRC.5) is
set to 1. The PCA Watchdog Timer reset source is automatically disabled when the device is in the low
power Suspend or Sleep mode. Upon exit from either low power state, the enabled/disabled state of this
reset source is restored to its previous value.The state of the RST pin is unaffected by this reset.
188
Rev. 1.3
C8051F93x-C8051F92x
18.7. Flash Error Reset
If a Flash read/write/erase or program read targets an illegal address, a system reset is generated. This
may occur due to any of the following:
•
•
•
•
•
A Flash write or erase is attempted above user code space. This occurs when PSWE is set to 1 and a
MOVX write operation targets an address above the Lock Byte address.
A Flash read is attempted above user code space. This occurs when a MOVC operation targets an
address above the Lock Byte address.
A Program read is attempted above user code space. This occurs when user code attempts to branch
to an address above the Lock Byte address.
A Flash read, write or erase attempt is restricted due to a Flash security setting (see Section
“13.3. Security Options” on page 150).
A Flash write or erase is attempted while the VDD Monitor is disabled.
The FERROR bit (RSTSRC.6) is set following a Flash error reset. The state of the RST pin is unaffected by
this reset.
18.8. SmaRTClock (Real Time Clock) Reset
The SmaRTClock can generate a system reset on two events: SmaRTClock Oscillator Fail or SmaRTClock Alarm. The SmaRTClock Oscillator Fail event occurs when the SmaRTClock Missing Clock Detector
is enabled and the SmaRTClock clock is below approximately 20 kHz. A SmaRTClock alarm event occurs
when the SmaRTClock Alarm is enabled and the SmaRTClock timer value matches the ALARMn registers. The SmaRTClock can be configured as a reset source by writing a 1 to the RTC0RE flag (RSTSRC.7). The SmaRTClock reset remains functional even when the device is in the low power Suspend or
Sleep mode. The state of the RST pin is unaffected by this reset.
18.9. Software Reset
Software may force a reset by writing a 1 to the SWRSF bit (RSTSRC.4). The SWRSF bit will read 1 following a software forced reset. The state of the RST pin is unaffected by this reset.
Rev. 1.3
189
C8051F93x-C8051F92x
SFR Definition 18.2. RSTSRC: Reset Source
Bit
7
6
5
4
3
2
1
0
Name
RTC0RE
FERROR
C0RSEF
SWRSF
WDTRSF
MCDRSF
PORSF
PINRSF
Type
R/W
R
R/W
R/W
R
R/W
R/W
R
Reset
Varies
Varies
Varies
Varies
Varies
Varies
Varies
Varies
SFR Page = 0x0; SFR Address = 0xEF.
Bit
Name
Description
Write
Read
7
RTC0RE SmaRTClock Reset Enable
and Flag
0: Disable SmaRTClock
Set to 1 if SmaRTClock
as a reset source.
alarm or oscillator fail
1: Enable SmaRTClock as caused the last reset.
a reset source.
6
FERROR Flash Error Reset Flag.
N/A
5
C0RSEF Comparator0 Reset Enable
and Flag.
0: Disable Comparator0 as Set to 1 if Comparator0
a reset source.
caused the last reset.
1: Enable Comparator0 as
a reset source.
4
SWRSF
Writing a 1 forces a system reset.
Software Reset Force and
Flag.
3
WDTRSF Watchdog Timer Reset Flag. N/A
2
MCDRSF Missing Clock Detector
(MCD) Enable and Flag.
Set to 1 if Flash
read/write/erase error
caused the last reset.
Set to 1 if last reset was
caused by a write to
SWRSF.
Set to 1 if Watchdog Timer
overflow caused the last
reset.
0: Disable the MCD.
Set to 1 if Missing Clock
1: Enable the MCD.
Detector timeout caused
The MCD triggers a reset the last reset.
if a missing clock condition
is detected.
1
PORSF
Power-On / Power-Fail
Reset Flag, and Power-Fail
Reset Enable.
0: Disable the VDD/DC+
Supply Monitor as a reset
source.
1: Enable the VDD/DC+
Supply Monitor as a reset
source.3
Set to 1 anytime a poweron or VDD monitor reset
occurs.2
0
PINRSF
HW Pin Reset Flag.
N/A
Set to 1 if RST pin caused
the last reset.
Notes:
1. It is safe to use read-modify-write operations (ORL, ANL, etc.) to enable or disable specific interrupt sources.
2. If PORSF read back 1, the value read from all other bits in this register are indeterminate.
3. Writing a 1 to PORSF before the VDD/DC+ Supply Monitor is stabilized may generate a system reset.
190
Rev. 1.3
C8051F93x-C8051F92x
19. Clocking Sources
C8051F93x-C8051F92x devices include a programmable precision internal oscillator, an external oscillator
drive circuit, a low power internal oscillator, and a SmaRTClock real time clock oscillator. The precision
internal oscillator can be enabled/disabled and calibrated using the OSCICN and OSCICL registers, as
shown in Figure 19.1. The external oscillator can be configured using the OSCXCN register. The low
power internal oscillator is automatically enabled and disabled when selected and deselected as a clock
source. SmaRTClock operation is described in the SmaRTClock oscillator chapter.
The system clock (SYSCLK) can be derived from the precision internal oscillator, external oscillator, low
power internal oscillator, or SmaRTClock oscillator. The global clock divider can generate a system clock
that is 1, 2, 4, 8, 16, 32, 64, or 128 times slower that the selected input clock source. Oscillator electrical
specifications can be found in the Electrical Specifications Chapter.
OSCICL
OSCICN
CLKSEL
VDD
XTAL2
CLKSL1
CLKSL0
CLKRDY
CLKDIV2
CLKDIV1
CLKDIV0
Option 3
IOSCEN
IFRDY
Option 2
XTAL2
EN
Precision
Internal Oscillator
Option 1
Precision Internal Oscillator
XTAL1
External Oscillator
External
Oscillator
Drive Circuit
10M
CLKRDY
Low Power Internal Oscillator
XTAL2
n
SYSCLK
Clock Divider
smaRTClock Oscillator
Option 4
XFCN2
XFCN1
XFCN0
XTLVLD
XOSCMD2
XOSCMD1
XOSCMD0
XTAL2
Low Power
Internal Oscillator
SmaRTClock
Oscillator
OSCXCN
Figure 19.1. Clocking Sources Block Diagram
The proper way of changing the system clock when both the clock source and the clock divide value are
being changed is as follows:
If switching from a fast “undivided” clock to a slower “undivided” clock:
a. Change the clock divide value.
b. Poll for CLKRDY > 1.
c. Change the clock source.
If switching from a slow “undivided” clock to a faster “undivided” clock:
a. Change the clock source.
b. Change the clock divide value.
c. Poll for CLKRDY > 1.
Rev. 1.3
191
C8051F93x-C8051F92x
19.1. Programmable Precision Internal Oscillator
All C8051F93x-C8051F92x devices include a programmable precision internal oscillator that may be
selected as the system clock. OSCICL is factory calibrated to obtain a 24.5 MHz frequency. See Section
“4. Electrical Characteristics” on page 45 for complete oscillator specifications.
The precision oscillator supports a spread spectrum mode which modulates the output frequency in order
to reduce the EMI generated by the system. When enabled (SSE = 1), the oscillator output frequency is
modulated by a stepped triangle wave whose frequency is equal to the oscillator frequency divided by 384
(63.8 kHz using the factory calibration). The deviation from the nominal oscillator frequency is +0%, –1.6%,
and the step size is typically 0.26% of the nominal frequency. When using this mode, the typical average
oscillator frequency is lowered from 24.5 MHz to 24.3 MHz.
19.2. Low Power Internal Oscillator
All C8051F93x-C8051F92x devices include a low power internal oscillator that defaults as the system
clock after a system reset. The low power internal oscillator frequency is 20 MHz ± 10% and is
automatically enabled when selected as the system clock and disabled when not in use. See Section
“4. Electrical Characteristics” on page 45 for complete oscillator specifications.
19.3. External Oscillator Drive Circuit
All C8051F93x-C8051F92x devices include an external oscillator circuit that may drive an external crystal,
ceramic resonator, capacitor, or RC network. A CMOS clock may also provide a clock input. Figure 19.1
shows a block diagram of the four external oscillator options. The external oscillator is enabled and
configured using the OSCXCN register.
The external oscillator output may be selected as the system clock or used to clock some of the digital
peripherals (e.g., timers, PCA, etc.). See the data sheet chapters for each digital peripheral for details. See
Section “4. Electrical Characteristics” on page 45 for complete oscillator specifications.
19.3.1. External Crystal Mode
If a crystal or ceramic resonator is used as the external oscillator, the crystal/resonator and a 10 M
resistor must be wired across the XTAL1 and XTAL2 pins as shown in Figure 19.1, Option 1. Appropriate
loading capacitors should be added to XTAL1 and XTAL2, and both pins should be configured for analog
I/O with the digital output drivers disabled.
Figure 19.2 shows the external oscillator circuit for a 20 MHz quartz crystal with a manufacturer
recommended load capacitance of 12.5 pF. Loading capacitors are "in series" as seen by the crystal and
"in parallel" with the stray capacitance of the XTAL1 and XTAL2 pins. The total value of the each loading
capacitor and the stray capacitance of each XTAL pin should equal 12.5pF x 2 = 25 pF. With a stray
capacitance of 10 pF per pin, the 15 pF capacitors yield an equivalent series capacitance of 12.5 pF
across the crystal.
Note: The recommended load capacitance depends upon the crystal and the manufacturer. Refer to the crystal data
sheet when completing these calculations.
192
Rev. 1.3
C8051F93x-C8051F92x
15 pF
XTAL1
10 M

25 MHz
XTAL2
15 pF
Figure 19.2. 25 MHz External Crystal Example
Important Note on External Crystals: Crystal oscillator circuits are quite sensitive to PCB layout. The
crystal should be placed as close as possible to the XTAL pins on the device. The traces should be as
short as possible and shielded with ground plane from any other traces which could introduce noise or
interference.
When using an external crystal, the external oscillator drive circuit must be configured by software for
Crystal Oscillator Mode or Crystal Oscillator Mode with divide by 2 stage. The divide by 2 stage ensures
that the clock derived from the external oscillator has a duty cycle of 50%. The External Oscillator
Frequency Control value (XFCN) must also be specified based on the crystal frequency. The selection
should be based on Table 19.1. For example, a 25 MHz crystal requires an XFCN setting of 111b.
Table 19.1. Recommended XFCN Settings for Crystal Mode
XFCN
Crystal Frequency
Bias Current
Typical Supply Current
(VDD = 2.4 V)
000
f  20 kHz
0.5 µA
3.0 µA, f = 32.768 kHz
001
20 kHz f 58 kHz
1.5 µA
4.8 µA, f = 32.768 kHz
010
58 kHz  f 155 kHz
4.8 µA
9.6 µA, f = 32.768 kHz
011
155 kHz  f 415 kHz
14 µA
28 µA, f = 400 kHz
100
415 kHz  f 1.1 MHz
40 µA
71 µA, f = 400 kHz
101
1.1 MHz  f 3.1 MHz
120 µA
193 µA, f = 400 kHz
110
3.1 MHz  f 8.2 MHz
550 µA
940 µA, f = 8 MHz
111
8.2 MHz  f 25 MHz
2.6 mA
3.9 mA, f = 25 MHz
When the crystal oscillator is first enabled, the external oscillator valid detector allows software to
determine when the external system clock has stabilized. Switching to the external oscillator before the
crystal oscillator has stabilized can result in unpredictable behavior. The recommended procedure for
starting the crystal is:
1.
2.
3.
4.
Configure XTAL1 and XTAL2 for analog I/O and disable the digital output drivers.
Configure and enable the external oscillator.
Poll for XTLVLD > 1.
Switch the system clock to the external oscillator.
Rev. 1.3
193
C8051F93x-C8051F92x
19.3.2. External RC Mode
If an RC network is used as the external oscillator, the circuit should be configured as shown in
Figure 19.1, Option 2. The RC network should be added to XTAL2, and XTAL2 should be configured for
analog I/O with the digital output drivers disabled. XTAL1 is not affected in RC mode.
The capacitor should be no greater than 100 pF; however for very small capacitors, the total capacitance
may be dominated by parasitic capacitance in the PCB layout. The resistor should be no smaller than
10k. The oscillation frequency can be determined by the following equation:
3
1.23  10
f = ------------------------RC
where
f = frequency of clock in MHz
VDD = power supply voltage in Volts
R = pull-up resistor value in k
C = capacitor value on the XTAL2 pin in pF
To determine the required External Oscillator Frequency Control value (XFCN) in the OSCXCN Register,
first select the RC network value to produce the desired frequency of oscillation. For example, if the
frequency desired is 100 kHz, let R = 246 k and C = 50 pF:
3
3
1.23  10
1.23  10
f = ------------------------- = ------------------------- = 100 kHz
RC
246  50
where
f = frequency of clock in MHz
VDD = power supply voltage in Volts
R = pull-up resistor value in k
C = capacitor value on the XTAL2 pin in pF
Referencing Table 19.2, the recommended XFCN setting is 010.
Table 19.2. Recommended XFCN Settings for RC and C modes
194
XFCN
Approximate
Frequency Range (RC
and C Mode)
K Factor (C Mode)
Typical Supply Current/ Actual
Measured Frequency
(C Mode, VDD = 2.4 V)
000
f 25 kHz
K Factor = 0.87
3.0 µA, f = 11 kHz, C = 33 pF
001
25 kHz f 50 kHz
K Factor = 2.6
5.5 µA, f = 33 kHz, C = 33 pF
010
50 kHz f 100 kHz
K Factor = 7.7
13 µA, f = 98 kHz, C = 33 pF
011
100 kHz f 200 kHz
K Factor = 22
32 µA, f = 270 kHz, C = 33 pF
100
200 kHz f 400 kHz
K Factor = 65
82 µA, f = 310 kHz, C = 46 pF
101
400 kHz f 800 kHz
K Factor = 180
242 µA, f = 890 kHz, C = 46 pF
110
800 kHz f 1.6 MHz
K Factor = 664
1.0 mA, f = 2.0 MHz, C = 46 pF
111
1.6 MHz f 3.2 MHz
K Factor = 1590
4.6 mA, f = 6.8 MHz, C = 46 pF
Rev. 1.3
C8051F93x-C8051F92x
When the RC oscillator is first enabled, the external oscillator valid detector allows software to determine
when oscillation has stabilized. The recommended procedure for starting the RC oscillator is:
1.
2.
3.
4.
Configure XTAL2 for analog I/O and disable the digital output drivers.
Configure and enable the external oscillator.
Poll for XTLVLD > 1.
Switch the system clock to the external oscillator.
19.3.3. External Capacitor Mode
If a capacitor is used as the external oscillator, the circuit should be configured as shown in Figure 19.1,
Option 3. The capacitor should be added to XTAL2, and XTAL2 should be configured for analog I/O with
the digital output drivers disabled. XTAL1 is not affected in RC mode.
The capacitor should be no greater than 100 pF; however, for very small capacitors, the total capacitance
may be dominated by parasitic capacitance in the PCB layout. The oscillation frequency and the required
External Oscillator Frequency Control value (XFCN) in the OSCXCN Register can be determined by the
following equation:
KF
f = --------------------C  V DD
where
f = frequency of clock in MHz
VDD = power supply voltage in Volts
R = pull-up resistor value in k
C = capacitor value on the XTAL2 pin in pF
Below is an example of selecting the capacitor and finding the frequency of oscillation Assume VDD = 3.0 V
and f = 150 kHz:
KF
f = --------------------C  V DD
KF
0.150 MHz = ----------------C  3.0
Since a frequency of roughly 150 kHz is desired, select the K Factor from Table 19.2 as KF = 22:
22
0.150 MHz = ----------------------C  3.0 V
22
C = ----------------------------------------------0.150 MHz  3.0 V
C = 48.8 pF
Therefore, the XFCN value to use in this example is 011 and C is approximately 50 pF.
The recommended startup procedure for C mode is the same as RC mode.
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19.3.4. External CMOS Clock Mode
If an external CMOS clock is used as the external oscillator, the clock should be directly routed into XTAL2.
The XTAL2 pin should be configured as a digital input. XTAL1 is not used in external CMOS clock mode.
The external oscillator valid detector will always return zero when the external oscillator is configured to
External CMOS Clock mode.
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19.4. Special Function Registers for Selecting and Configuring the System Clock
The clocking sources on C8051F93x-C8051F92x devices are enabled and configured using the OSCICN,
OSCICL, OSCXCN and the SmaRTClock internal registers. See Section “20. SmaRTClock (Real Time
Clock)” on page 200 for SmaRTClock register descriptions. The system clock source for the MCU can be
selected using the CLKSEL register. To minimize active mode current, the oneshot timer which sets Flash
read time should by bypassed when the system clock is greater than 10 MHz. See the FLSCL register
description for details.
The clock selected as the system clock can be divided by 1, 2, 4, 8, 16, 32, 64, or 128. When switching
between two clock divide values, the transition may take up to 128 cycles of the undivided clock source.
The CLKRDY flag can be polled to determine when the new clock divide value has been applied. The clock
divider must be set to "divide by 1" when entering suspend or sleep mode.
The system clock source may also be switched on-the-fly. The switchover takes effect after one clock
period of the slower oscillator.
SFR Definition 19.1. CLKSEL: Clock Select
Bit
7
6
5
4
3
2
Name
CLKRDY
Type
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
1
1
0
1
0
0
CLKDIV[2:0]
1
0
CLKSEL[2:0]
SFR Page = All Pages; SFR Address = 0xA9
Bit
Name
7
CLKRDY
6:4
3
2:0
CLKDIV[2:0]
CLKSEL[2:0]
Function
System Clock Divider Clock Ready Flag.
0: The selected clock divide setting has not been applied to the system clock.
1: The selected clock divide setting has been applied to the system clock.
System Clock Divider Bits.
Selects the clock division to be applied to the undivided system clock source.
000: System clock is divided by 1.
001: System clock is divided by 2.
010: System clock is divided by 4.
011: System clock is divided by 8.
100: System clock is divided by 16.
101: System clock is divided by 32.
110: System clock is divided by 64.
111: System clock is divided by 128.
Unused. Read = 0b. Must Write 0b.
System Clock Select.
Selects the oscillator to be used as the undivided system clock source.
000: Precision Internal Oscillator.
001: External Oscillator.
011: SmaRTClock Oscillator.
100: Low Power Oscillator.
All other values reserved.
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SFR Definition 19.2. OSCICN: Internal Oscillator Control
Bit
7
6
5
4
3
Name
IOSCEN
IFRDY
Type
R/W
R
R/W
R/W
R/W
Reset
0
0
0
0
1
2
1
0
R/W
R/W
R/W
1
1
1
Reserved[5:0]
SFR Page = 0x0; SFR Address = 0xB2
Bit
Name
7
IOSCEN
Function
Internal Oscillator Enable.
0: Internal oscillator disabled.
1: Internal oscillator enabled.
6
IFRDY
Internal Oscillator Frequency Ready Flag.
0: Internal oscillator is not running at its programmed frequency.
1: Internal oscillator is running at its programmed frequency.
5:0
Reserved Reserved.
Read = 001111b. Must Write 001111b.
Note: It is recommended to use read-modify-write operations such as ORL and ANL to set or clear the enable bit of
this register.
SFR Definition 19.3. OSCICL: Internal Oscillator Calibration
Bit
7
6
5
4
Name
SSE
Type
R/W
R
R/W
R/W
Reset
0
Varies
Varies
Varies
3
2
1
0
R/W
R/W
R/W
R/W
Varies
Varies
Varies
Varies
OSCICL[6:0]
SFR Page = 0x0; SFR Address = 0xB3
Bit
Name
7
SSE
Function
Spread Spectrum Enable.
0: Spread Spectrum clock dithering disabled.
1: Spread Spectrum clock dithering enabled.
6:0
OSCICL
Internal Oscillator Calibration.
Factory calibrated to obtain a frequency of 24.5 MHz. Incrementing this register
decreases the oscillator frequency and decrementing this register increases the
oscillator frequency. The step size is approximately 1% of the calibrated frequency.
The recommended calibration frequency range is between 16 and 24.5 MHz.
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SFR Definition 19.4. OSCXCN: External Oscillator Control
Bit
7
6
Name XCLKVLD
5
4
XOSCMD[2:0]
3
2
Reserved
1
0
XFCN[2:0]
Type
R
R
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
SFR Page = 0x0; SFR Address = 0xB1
Bit
7
Name
Function
XCLKVLD External Oscillator Valid Flag.
Provides External Oscillator status and is valid at all times for all modes of operation
except External CMOS Clock Mode and External CMOS Clock Mode with divide by
2. In these modes, XCLKVLD always returns 0.
0: External Oscillator is unused or not yet stable.
1: External Oscillator is running and stable.
6:4
XOSCMD External Oscillator Mode Bits.
Configures the external oscillator circuit to the selected mode.
00x: External Oscillator circuit disabled.
010: External CMOS Clock Mode.
011: External CMOS Clock Mode with divide by 2 stage.
100: RC Oscillator Mode.
101: Capacitor Oscillator Mode.
110: Crystal Oscillator Mode.
111: Crystal Oscillator Mode with divide by 2 stage.
3
Reserved Reserved.
Read = 0b. Must Write 0b.
2:0
XFCN
External Oscillator Frequency Control Bits.
Controls the external oscillator bias current.
000-111: See Table 19.1 on page 193 (Crystal Mode) or Table 19.2 on page 194 (RC
or C Mode) for recommended settings.
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20. SmaRTClock (Real Time Clock)
C8051F93x-C8051F92x devices include an ultra low power 32-bit SmaRTClock Peripheral (Real Time
Clock) with alarm. The SmaRTClock has a dedicated 32 kHz oscillator that can be configured for use with
or without a crystal. No external resistor or loading capacitors are required. The on-chip loading capacitors
are programmable to 16 discrete levels allowing compatibility with a wide range of crystals. The SmaRTClock can operate directly from a 0.9–3.6 V battery voltage and remains operational even when the device
goes into its lowest power down mode.
The SmaRTClock allows a maximum of 36 hour 32-bit independent time-keeping when used with a
32.768 kHz Watch Crystal. The SmaRTClock provides an Alarm and Missing SmaRTClock events, which
could be used as reset or wakeup sources. See Section “18. Reset Sources” on page 184 and Section
“14. Power Management” on page 159 for details on reset sources and low power mode wake-up sources,
respectively.
XTAL3
XTAL4
SmaRTClock
Power/
Clock
Mgmt
Programmable Load Capacitors
SmaRTClock Oscillator
CIP-51 CPU
32-Bit
SmaRTClock
Timer
SmaRTClock State Machine
Wake-Up
Interrupt
Internal
Registers
CAPTUREn
RTC0CN
RTC0XCN
RTC0XCF
RTC0PIN
ALARMn
Interface
Registers
RTC0KEY
RTC0ADR
RTC0DAT
Figure 20.1. SmaRTClock Block Diagram
200
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C8051F93x-C8051F92x
20.1. SmaRTClock Interface
The SmaRTClock Interface consists of three registers: RTC0KEY, RTC0ADR, and RTC0DAT. These interface registers are located on the CIP-51’s SFR map and provide access to the SmaRTClock internal registers listed in Table 20.1. The SmaRTClock internal registers can only be accessed indirectly through the
SmaRTClock Interface.
Table 20.1. SmaRTClock Internal Registers
SmaRTClock SmaRTClock
Address
Register
Register Name
Description
0x00–0x03
CAPTUREn
SmaRTClock Capture
Registers
Four Registers used for setting the 32-bit
SmaRTClock timer or reading its current value.
0x04
RTC0CN
SmaRTClock Control
Register
Controls the operation of the SmaRTClock State
Machine.
0x05
RTC0XCN
SmaRTClock Oscillator
Control Register
Controls the operation of the SmaRTClock
Oscillator.
0x06
RTC0XCF
SmaRTClock Oscillator
Configuration Register
Controls the value of the programmable
oscillator load capacitance and
enables/disables AutoStep.
0x07
RTC0PIN
SmaRTClock Pin
Configuration Register
Forces XTAL3 and XTAL4 to be internally
shorted.
Note: This register also contains other reserved bits
which should not be modified.
0x08–0x0B
ALARMn
SmaRTClock Alarm
Registers
Four registers used for setting or reading the
32-bit SmaRTClock alarm value.
20.1.1. SmaRTClock Lock and Key Functions
The SmaRTClock Interface is protected with a lock and key function. The SmaRTClock Lock and Key Register (RTC0KEY) must be written with the correct key codes, in sequence, before writes and reads to
RTC0ADR and RTC0DAT may be performed. The key codes are: 0xA5, 0xF1. There are no timing restrictions, but the key codes must be written in order. If the key codes are written out of order, the wrong codes
are written, or an indirect register read or write is attempted while the interface is locked, the SmaRTClock
interface will be disabled, and the RTC0ADR and RTC0DAT registers will become inaccessible until the
next system reset. Once the SmaRTClock interface is unlocked, software may perform any number of
accesses to the SmaRTClock registers until the interface is re-locked or the device is reset. Any write to
RTC0KEY while the SmaRTClock interface is unlocked will re-lock the interface.
Reading the RTC0KEY register at any time will provide the SmaRTClock Interface status and will not interfere with the sequence that is being written. The RTC0KEY register description in SFR Definition 20.1 lists
the definition of each status code.
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20.1.2. Using RTC0ADR and RTC0DAT to Access SmaRTClock Internal Registers
The SmaRTClock internal registers can be read and written using RTC0ADR and RTC0DAT. The
RTC0ADR register selects the SmaRTClock internal register that will be targeted by subsequent reads or
writes. Recommended instruction timing is provided in this section. If the recommended instruction timing
is not followed, then BUSY (RTC0ADR.7) should be checked prior to each read or write operation to make
sure the SmaRTClock Interface is not busy performing the previous read or write operation. A
SmaRTClock Write operation is initiated by writing to the RTC0DAT register. Below is an example of
writing to a SmaRTClock internal register.
1. Poll BUSY (RTC0ADR.7) until it returns 0 or follow recommended instruction timing.
2. Write 0x05 to RTC0ADR. This selects the internal RTC0CN register at SmaRTClock Address
0x05.
3. Write 0x00 to RTC0DAT. This operation writes 0x00 to the internal RTC0CN register.
A SmaRTClock Read operation is initiated by setting the SmaRTClock Interface Busy bit. This transfers
the contents of the internal register selected by RTC0ADR to RTC0DAT. The transferred data will remain in
RTC0DAT until the next read or write operation. Below is an example of reading a SmaRTClock internal
register.
1. Poll BUSY (RTC0ADR.7) until it returns 0 or follow recommended instruction timing.
2. Write 0x05 to RTC0ADR. This selects the internal RTC0CN register at SmaRTClock Address
0x05.
3. Write 1 to BUSY. This initiates the transfer of data from RTC0CN to RTC0DAT.
4. Poll BUSY (RTC0ADR.7) until it returns 0 or follow recommend instruction timing.
5. Read data from RTC0DAT. This data is a copy of the RTC0CN register. 
Note: The RTC0ADR and RTC0DAT registers will retain their state upon a device reset.
20.1.3. RTC0ADR Short Strobe Feature
Reads and writes to indirect SmaRTClock registers normally take 7 system clock cycles. To minimize the
indirect register access time, the Short Strobe feature decreases the read and write access time to 6
system clocks. The Short Strobe feature is automatically enabled on reset and can be manually
enabled/disabled using the SHORT (RTC0ADR.4) control bit.
Recommended Instruction Timing for a single register read with short strobe enabled:
mov RTC0ADR, #095h
nop
nop
nop
mov A, RTC0DAT

Recommended Instruction Timing for a single register write with short strobe enabled:
mov RTC0ADR, #095h
mov RTC0DAT, #000h
nop
202
Rev. 1.3
C8051F93x-C8051F92x
20.1.4. SmaRTClock Interface Autoread Feature
When Autoread is enabled, each read from RTC0DAT initiates the next indirect read operation on the
SmaRTClock internal register selected by RTC0ADR. Software should set the BUSY bit once at the
beginning of each series of consecutive reads. Software should follow recommended instruction timing or
check if the SmaRTClock Interface is busy prior to reading RTC0DAT. Autoread is enabled by setting
AUTORD (RTC0ADR.6) to logic 1.
20.1.5. RTC0ADR Autoincrement Feature
For ease of reading and writing the 32-bit CAPTURE and ALARM values, RTC0ADR automatically
increments after each read or write to a CAPTUREn or ALARMn register. This speeds up the process of
setting an alarm or reading the current SmaRTClock timer value. Autoincrement is always enabled.
Recommended Instruction Timing for a multi-byte register read with short strobe and autoread enabled:
mov
nop
nop
nop
mov
nop
nop
mov
nop
nop
mov
nop
nop
mov
RTC0ADR, #0d0h
A, RTC0DAT
A, RTC0DAT
A, RTC0DAT
A, RTC0DAT
Recommended Instruction Timing for a multi-byte register write with short strobe enabled:
mov
mov
nop
mov
nop
mov
nop
mov
nop
RTC0ADR, #010h
RTC0DAT, #05h
RTC0DAT, #06h
RTC0DAT, #07h
RTC0DAT, #08h
Rev. 1.3
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SFR Definition 20.1. RTC0KEY: SmaRTClock Lock and Key
Bit
7
6
5
4
3
Name
RTC0ST[7:0]
Type
R/W
Reset
0
0
0
0
SFR Page = 0x0; SFR Address = 0xAE
Bit
Name
7:0
RTC0ST
0
2
1
0
0
0
0
Function
SmaRTClock Interface Lock/Key and Status.
Locks/unlocks the SmaRTClock interface when written. Provides lock status when
read.
Read:
0x00: SmaRTClock Interface is locked.
0x01: SmaRTClock Interface is locked.
First key code (0xA5) has been written, waiting for second key code.
0x02: SmaRTClock Interface is unlocked.
First and second key codes (0xA5, 0xF1) have been written.
0x03: SmaRTClock Interface is disabled until the next system reset.
Write:
When RTC0ST = 0x00 (locked), writing 0xA5 followed by 0xF1 unlocks the
SmaRTClock Interface.
When RTC0ST = 0x01 (waiting for second key code), writing any value other
than the second key code (0xF1) will change RTC0STATE to 0x03 and disable
the SmaRTClock Interface until the next system reset.
When RTC0ST = 0x02 (unlocked), any write to RTC0KEY will lock the SmaRTClock Interface.
When RTC0ST = 0x03 (disabled), writes to RTC0KEY have no effect.
204
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SFR Definition 20.2. RTC0ADR: SmaRTClock Address
Bit
7
6
Name
BUSY
AUTORD
Type
R/W
R/W
Reset
0
0
5
4
3
SHORT
ADDR[3:0]
R
R/W
R/W
0
0
0
SFR Page = 0x0; SFR Address = 0xAC
Bit
Name
7
BUSY
2
0
1
0
0
0
Function
SmaRTClock Interface Busy Indicator.
Indicates SmaRTClock interface status. Writing 1 to this bit initiates an indirect read.
6
AUTORD SmaRTClock Interface Autoread Enable.
Enables/disables Autoread.
0: Autoread Disabled.
1: Autoread Enabled.
5
Unused
Unused. Read = 0b; Write = Don’t Care.
4
SHORT
Short Strobe Enable.
Enables/disables the Short Strobe Feature.
0: Short Strobe disabled.
1: Short Strobe enabled.
3:0
ADDR[3:0] SmaRTClock Indirect Register Address.
Sets the currently selected SmaRTClock register.
See Table 20.1 for a listing of all SmaRTClock indirect registers.
Note: The ADDR bits increment after each indirect read/write operation that targets a CAPTUREn or ALARMn
internal SmaRTClock register.
SFR Definition 20.3. RTC0DAT: SmaRTClock Data
Bit
7
6
5
4
3
Name
RTC0DAT[7:0]
Type
R/W
Reset
0
0
0
0
SFR Page= 0x0; SFR Address = 0xAD
Bit
Name
7:0
0
2
1
0
0
0
0
Function
RTC0DAT SmaRTClock Data Bits.
Holds data transferred to/from the internal SmaRTClock register selected by
RTC0ADR.
Note: Read-modify-write instructions (orl, anl, etc.) should not be used on this register.
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C8051F93x-C8051F92x
20.2. SmaRTClock Clocking Sources
The SmaRTClock peripheral is clocked from its own timebase, independent of the system clock. The
SmaRTClock timebase is derived from the SmaRTClock oscillator circuit, which has two modes of operation: Crystal Mode, and Self-Oscillate Mode. The oscillation frequency is 32.768 kHz in Crystal Mode and
can be programmed in the range of 10 kHz to 40 kHz in Self-Oscillate Mode. The frequency of the SmaRTClock oscillator can be measured with respect to another oscillator using an on-chip timer. See Section
“25. Timers” on page 283 for more information on how this can be accomplished.
Note: The SmaRTClock timebase can be selected as the system clock and routed to a port pin. See Section “19. Clocking Sources” on page 191 for information on selecting the system clock source and Section
“21. Port Input/Output” on page 216 for information on how to route the system clock to a port pin.
20.2.1. Using the SmaRTClock Oscillator with a Crystal or External CMOS Clock
When using crystal mode, a 32.768 kHz crystal should be connected between XTAL3 and XTAL4. No other
external components are required. The following steps show how to start the SmaRTClock crystal oscillator in software:
1. Set SmaRTClock to Crystal Mode (XMODE = 1).
2. Disable Automatic Gain Control (AGCEN) and enable Bias Doubling (BIASX2) for fast crystal
startup.
3. Set the desired loading capacitance (RTC0XCF).
4. Enable power to the SmaRTClock oscillator circuit (RTC0EN = 1).
5. Wait 20 ms.
6. Poll the SmaRTClock Clock Valid Bit (CLKVLD) until the crystal oscillator stabilizes.
7. Poll the SmaRTClock Load Capacitance Ready Bit (LOADRDY) until the load capacitance
reaches its programmed value.
8. Enable Automatic Gain Control (AGCEN) and disable Bias Doubling (BIASX2) for maximum
power savings.
9. Enable the SmaRTClock missing clock detector.
10. Wait 2 ms.
11. Clear the PMU0CF wake-up source flags.
In crystal mode, the SmaRTClock oscillator may be driven by an external CMOS clock. The CMOS clock
should be applied to XTAL3. XTAL4 should be left floating. The input low voltage (VIL) and input high
voltage (VIH) for XTAL3 when used with an external CMOS clock are 0.1 and 0.8 V, respectively. The
SmaRTClock oscillator should be configured to its lowest bias setting with AGC disabled. The CLKVLD bit
is indeterminate when using a CMOS clock, however, the OSCFAIL bit may be checked 2 ms after
SmaRTClock oscillator is powered on to ensure that there is a valid clock on XTAL3.
20.2.2. Using the SmaRTClock Oscillator in Self-Oscillate Mode
When using Self-Oscillate Mode, the XTAL3 and XTAL4 pins should be shorted together. The RTC0PIN
register can be used to internally short XTAL3 and XTAL4. The following steps show how to configure
SmaRTClock for use in Self-Oscillate Mode:
1. Set SmaRTClock to Self-Oscillate Mode (XMODE = 0).
2. Set the desired oscillation frequency:
For oscillation at about 20 kHz, set BIASX2 = 0.
For oscillation at about 40 kHz, set BIASX2 = 1.
3. The oscillator starts oscillating instantaneously.
4. Fine tune the oscillation frequency by adjusting the load capacitance (RTC0XCF).
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20.2.3. Programmable Load Capacitance
The programmable load capacitance has 16 values to support crystal oscillators with a wide range of recommended load capacitance. If Automatic Load Capacitance Stepping is enabled, the crystal load capacitors start at the smallest setting to allow a fast startup time, then slowly increase the capacitance until the
final programmed value is reached. The final programmed loading capacitor value is specified using the
LOADCAP bits in the RTC0XCF register. The LOADCAP setting specifies the amount of on-chip load
capacitance and does not include any stray PCB capacitance. Once the final programmed loading capacitor value is reached, the LOADRDY flag will be set by hardware to logic 1.
When using the SmaRTClock oscillator in Self-Oscillate mode, the programmable load capacitance can be
used to fine tune the oscillation frequency. In most cases, increasing the load capacitor value will result in
a decrease in oscillation frequency. Table 20.2 shows the crystal load capacitance for various settings of
LOADCAP.
Table 20.2. SmaRTClock Load Capacitance Settings
LOADCAP
Crystal Load Capacitance
Equivalent Capacitance seen on
XTAL3 and XTAL4
0000
4.0 pF
8.0 pF
0001
4.5 pF
9.0 pF
0010
5.0 pF
10.0 pF
0011
5.5 pF
11.0 pF
0100
6.0 pF
12.0 pF
0101
6.5 pF
13.0 pF
0110
7.0 pF
14.0 pF
0111
7.5 pF
15.0 pF
1000
8.0 pF
16.0 pF
1001
8.5 pF
17.0 pF
1010
9.0 pF
18.0 pF
1011
9.5 pF
19.0 pF
1100
10.5 pF
21.0 pF
1101
11.5 pF
23.0 pF
1110
12.5 pF
25.0 pF
1111
13.5 pF
27.0 pF
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20.2.4. Automatic Gain Control (Crystal Mode Only) and SmaRTClock Bias Doubling
Automatic Gain Control allows the SmaRTClock oscillator to trim the oscillation amplitude of a crystal in
order to achieve the lowest possible power consumption. Automatic Gain Control automatically detects
when the oscillation amplitude has reached a point where it safe to reduce the drive current, therefore, it
may be enabled during crystal startup. It is recommended to enable Automatic Gain Control in most
systems which use the SmaRTClock oscillator in Crystal Mode. The following are recommended crystal
specifications and operating conditions when Automatic Gain Control is enabled:
•
•
•
•
ESR < 50 k
Load Capacitance < 10 pF
Supply Voltage < 3.0 V
Temperature > –20 °C
When using Automatic Gain Control, it is recommended to perform an oscillation robustness test to ensure
that the chosen crystal will oscillate under the worst case condition to which the system will be exposed.
The worst case condition that should result in the least robust oscillation is at the following system
conditions: lowest temperature, highest supply voltage, highest ESR, highest load capacitance, and lowest
bias current (AGC enabled, Bias Double Disabled).
To perform the oscillation robustness test, the SmaRTClock oscillator should be enabled and selected as
the system clock source. Next, the SYSCLK signal should be routed to a port pin configured as a push-pull
digital output. The positive duty cycle of the output clock can be used as an indicator of oscillation
robustness. As shown in Figure 20.2, duty cycles less than 55% indicate a robust oscillation. As the duty
cycle approaches 60%, oscillation becomes less reliable and the risk of clock failure increases. Increasing
the bias current (by disabling AGC) will always improve oscillation robustness and will reduce the output
clock’s duty cycle. This test should be performed at the worst case system conditions, as results at very
low temperatures or high supply voltage will vary from results taken at room temperature or low supply
voltage.
Safe Operating Zone
25%
Low Risk of Clock
Failure
55%
High Risk of Clock
Failure
60%
Duty Cycle
Figure 20.2. Interpreting Oscillation Robustness (Duty Cycle) Test Results
As an alternative to performing the oscillation robustness test, Automatic Gain Control may be disabled at
the cost of increased power consumption (approximately 200 nA). Disabling Automatic Gain Control will
provide the crystal oscillator with higher immunity against external factors which may lead to clock failure.
Automatic Gain Control must be disabled if using the SmaRTClock oscillator in self-oscillate mode.
208
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Table 20.3 shows a summary of the oscillator bias settings. The SmaRTClock Bias Doubling feature allows
the self-oscillation frequency to be increased (almost doubled) and allows a higher crystal drive strength in
crystal mode. High crystal drive strength is recommended when the crystal is exposed to poor
environmental conditions such as excessive moisture. SmaRTClock Bias Doubling is enabled by setting
BIASX2 (RTC0XCN.5) to 1.
.
Table 20.3. SmaRTClock Bias Settings
Mode
Setting
Power
Consumption
Crystal
Bias Double Off, AGC On
Lowest
600 nA
Bias Double Off, AGC Off
Low
800 nA
Bias Double On, AGC On
High
Bias Double On, AGC Off
Highest
Bias Double Off
Low
Bias Double On
High
Self-Oscillate
Rev. 1.3
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C8051F93x-C8051F92x
20.2.5. Missing SmaRTClock Detector
The missing SmaRTClock detector is a one-shot circuit enabled by setting MCLKEN (RTC0CN.6) to 1.
When the SmaRTClock Missing Clock Detector is enabled, OSCFAIL (RTC0CN.5) is set by hardware if
SmaRTClock oscillator remains high or low for more than 100 µs.
A SmaRTClock Missing Clock detector timeout can trigger an interrupt, wake the device from a low power
mode, or reset the device. See Section “12. Interrupt Handler” on page 136, Section “14. Power
Management” on page 159, and Section “18. Reset Sources” on page 184 for more information.
Note: The SmaRTClock Missing Clock Detector should be disabled when making changes to the oscillator settings in
RTC0XCN.
20.2.6. SmaRTClock Oscillator Crystal Valid Detector
The SmaRTClock oscillator crystal valid detector is an oscillation amplitude detector circuit used during
crystal startup to determine when oscillation has started and is nearly stable. The output of this detector
can be read from the CLKVLD bit (RTX0XCN.4).
Notes:
•
•
The CLKVLD bit has a blanking interval of 2 ms. During the first 2 ms after turning on the crystal oscillator, the output of CLKVLD is not valid.
This SmaRTClock crystal valid detector (CLKVLD) is not intended for detecting an oscillator failure.
The missing SmaRTClock detector (CLKFAIL) should be used for this purpose.
20.3. SmaRTClock Timer and Alarm Function
The SmaRTClock timer is a 32-bit counter that, when running (RTC0TR = 1), is incremented every
SmaRTClock oscillator cycle. The timer has an alarm function that can be set to generate an interrupt,
wake the device from a low power mode, or reset the device at a specific time. See Section “12. Interrupt
Handler” on page 136, Section “14. Power Management” on page 159, and Section “18. Reset Sources”
on page 184 for more information.
The SmaRTClock timer includes an Auto Reset feature, which automatically resets the timer to zero one
SmaRTClock cycle after an alarm occurs. When using Auto Reset, the Alarm match value should always
be set to 1 count less than the desired match value. Auto Reset can be enabled by writing a 1 to ALRM
(RTC0CN.2).
20.3.1. Setting and Reading the SmaRTClock Timer Value
The 32-bit SmaRTClock timer can be set or read using the six CAPTUREn internal registers. Note that the
timer does not need to be stopped before reading or setting its value. The following steps can be used to
set the timer value:
1. Write the desired 32-bit set value to the CAPTUREn registers.
2. Write 1 to RTC0SET. This will transfer the contents of the CAPTUREn registers to the SmaRTClock timer.
3. Operation is complete when RTC0SET is cleared to 0 by hardware.
The following steps can be used to read the current timer value:
1. Write 1 to RTC0CAP. This will transfer the contents of the timer to the CAPTUREn registers.
2. Poll RTC0CAP until it is cleared to 0 by hardware.
3. A snapshot of the timer value can be read from the CAPTUREn registers
210
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C8051F93x-C8051F92x
20.3.2. Setting a SmaRTClock Alarm
The SmaRTClock alarm function compares the 32-bit value of SmaRTClock Timer to the value of the
ALARMn registers. An alarm event is triggered if the SmaRTClock timer is equal to the ALARMn registers.
If Auto Reset is enabled, the 32-bit timer will be cleared to zero one SmaRTClock cycle after the alarm
event.
The SmaRTClock alarm event can be configured to reset the MCU, wake it up from a low power mode, or
generate an interrupt. See Section “12. Interrupt Handler” on page 136, Section “14. Power Management”
on page 159, and Section “18. Reset Sources” on page 184 for more information.
The following steps can be used to set up a SmaRTClock Alarm:
1. Disable SmaRTClock Alarm Events (RTC0AEN = 0).
2. Set the ALARMn registers to the desired value.
3. Enable SmaRTClock Alarm Events (RTC0AEN = 1).
Notes:
•
•
•
The ALRM bit, which is used as the SmaRTClock Alarm Event flag, is cleared by disabling SmaRTClock Alarm Events (RTC0AEN = 0).
If AutoReset is disabled, disabling (RTC0AEN = 0) then Re-enabling Alarm Events (RTC0AEN = 1)
after a SmaRTClock Alarm without modifying ALARMn registers will automatically schedule the next
alarm after 2^32 SmaRTClock cycles (approximately 36 hours using a 32.768 kHz crystal).
The SmaRTClock Alarm Event flag will remain asserted for a maximum of one SmaRTClock cycle.
See Section “14. Power Management” on page 159 for information on how to capture a SmaRTClock
Alarm event using a flag which is not automatically cleared by hardware.
20.3.3. Software Considerations for using the SmaRTClock Timer and Alarm
The SmaRTClock timer and alarm have two operating modes to suit varying applications. The two modes
are described below:
Mode 1:
The first mode uses the SmaRTClock timer as a perpetual timebase which is never reset to zero. Every 36
hours, the timer is allowed to overflow without being stopped or disrupted. The alarm interval is software
managed and is added to the ALRMn registers by software after each alarm. This allows the alarm match
value to always stay ahead of the timer by one software managed interval. If software uses 32-bit unsigned
addition to increment the alarm match value, then it does not need to handle overflows since both the timer
and the alarm match value will overflow in the same manner.
This mode is ideal for applications which have a long alarm interval (e.g. 24 or 36 hours) and/or have a
need for a perpetual timebase. An example of an application that needs a perpetual timebase is one
whose wake-up interval is constantly changing. For these applications, software can keep track of the
number of timer overflows in a 16-bit variable, extending the 32-bit (36 hour) timer to a 48-bit (272 year)
perpetual timebase.
Mode 2:
The second mode uses the SmaRTClock timer as a general purpose up counter which is auto reset to zero
by hardware after each alarm. The alarm interval is managed by hardware and stored in the ALRMn
registers. Software only needs to set the alarm interval once during device initialization. After each alarm,
software should keep a count of the number of alarms that have occurred in order to keep track of time.
This mode is ideal for applications that require minimal software intervention and/or have a fixed alarm
interval. This mode is the most power efficient since it requires less CPU time per alarm.
Rev. 1.3
211
C8051F93x-C8051F92x
Internal Register Definition 20.4. RTC0CN: SmaRTClock Control
Bit
7
6
5
4
3
2
Name
RTC0EN
MCLKEN
OSCFAIL
RTC0TR
RTC0AEN
ALRM
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
Varies
0
0
0
0
0
SmaRTClock Address = 0x04
Bit
Name
7
RTC0EN
1
0
RTC0SET RTC0CAP
Function
SmaRTClock Enable.
Enables/disables the SmaRTClock oscillator and associated bias currents.
0: SmaRTClock oscillator disabled.
1: SmaRTClock oscillator enabled.
6
MCLKEN Missing SmaRTClock Detector Enable.
Enables/disables the missing SmaRTClock detector.
0: Missing SmaRTClock detector disabled.
1: Missing SmaRTClock detector enabled.
5
OSCFAIL SmaRTClock Oscillator Fail Event Flag.
Set by hardware when a missing SmaRTClock detector timeout occurs. Must be
cleared by software. The value of this bit is not defined when the SmaRTClock 
oscillator is disabled.
4
RTC0TR
SmaRTClock Timer Run Control.
Controls if the SmaRTClock timer is running or stopped (holds current value).
0: SmaRTClock timer is stopped.
1: SmaRTClock timer is running.
3
RTC0AEN SmaRTClock Alarm Enable.
Enables/disables the SmaRTClock alarm function. Also clears the ALRM flag.
0: SmaRTClock alarm disabled.
1: SmaRTClock alarm enabled.
2
ALRM
Read:
0: SmaRTClock alarm
event flag is de-asserted.
Reads return the state of the 1: SmaRTClock alarm
event flag is asserted.
alarm event flag.
SmaRTClock Alarm Event
Flag and Auto Reset
Enable
Write:
0: Disable Auto Reset.
1: Enable Auto Reset.
Writes enable/disable the 
Auto Reset function.
1
RTC0SET SmaRTClock Timer Set.
Writing 1 initiates a SmaRTClock timer set operation. This bit is cleared to 0 by hardware to indicate that the timer set operation is complete.
0
RTC0CAP SmaRTClock Timer Capture.
Writing 1 initiates a SmaRTClock timer capture operation. This bit is cleared to 0 by
hardware to indicate that the timer capture operation is complete.
Note: The ALRM flag will remain asserted for a maximum of one SmaRTClock cycle. See Section “Power
Management” on page 159 for information on how to capture a SmaRTClock Alarm event using a flag which
is not automatically cleared by hardware.
212
Rev. 1.3
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Internal Register Definition 20.5. RTC0XCN: SmaRTClock Oscillator Control
Bit
7
6
5
4
3
2
1
0
Name
AGCEN
XMODE
BIASX2
CLKVLD
Type
R/W
R/W
R/W
R
R
R
R
R
Reset
0
0
0
0
0
0
0
0
SmaRTClock Address = 0x05
Bit
Name
7
AGCEN
Function
SmaRTClock Oscillator Automatic Gain Control (AGC) Enable.
0: AGC disabled.
1: AGC enabled.
6
XMODE
SmaRTClock Oscillator Mode.
Selects Crystal or Self Oscillate Mode.
0: Self-Oscillate Mode selected.
1: Crystal Mode selected.
5
BIASX2
SmaRTClock Oscillator Bias Double Enable.
Enables/disables the Bias Double feature.
0: Bias Double disabled.
1: Bias Double enabled.
4
CLKVLD
SmaRTClock Oscillator Crystal Valid Indicator.
Indicates if oscillation amplitude is sufficient for maintaining oscillation.
0: Oscillation has not started or oscillation amplitude is too low to maintain oscillation.
1: Sufficient oscillation amplitude detected.
3:0
Unused
Unused.
Read = 0000b; Write = Don’t Care.
Rev. 1.3
213
C8051F93x-C8051F92x
Internal Register Definition 20.6. RTC0XCF: SmaRTClock Oscillator Configuration
Bit
7
6
Name AUTOSTP
5
4
3
LOADRDY
R/W
R
R
R
Reset
0
0
0
0
0
R/W
Varies
SmaRTClock Address = 0x06
Bit
Name
AUTOSTP
1
LOADCAP
Type
7
2
Varies
Varies
Varies
Function
Automatic Load Capacitance Stepping Enable.
Enables/disables automatic load capacitance stepping.
0: Load capacitance stepping disabled.
1: Load capacitance stepping enabled.
6
LOADRDY
Load Capacitance Ready Indicator.
Set by hardware when the load capacitance matches the programmed value.
0: Load capacitance is currently stepping.
1: Load capacitance has reached it programmed value.
5:4
Unused
Unused.
Read = 00b; Write = Don’t Care.
3:0
LOADCAP
Load Capacitance Programmed Value.
Holds the user’s desired value of the load capacitance. See Table 20.2 on
page 207.
Internal Register Definition 20.7. RTC0PIN: SmaRTClock Pin Configuration
Bit
7
6
5
4
Name
RTC0PIN
Type
W
Reset
0
1
1
0
SmaRTClock Address = 0x07
Bit
Name
7:0
3
2
1
0
0
1
1
1
Function
RTC0PIN SmaRTClock Pin Configuration.
Writing 0xE7 to this register forces XTAL3 and XTAL4 to be internally shorted for use
with Self Oscillate Mode.
Writing 0x67 returns XTAL3 and XTAL4 to their normal configuration.
214
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C8051F93x-C8051F92x
Internal Register Definition 20.8. CAPTUREn: SmaRTClock Timer Capture
Bit
7
6
5
4
3
2
1
0
CAPTURE[31:0]
Name
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
SmaRTClock Addresses: CAPTURE0 = 0x00; CAPTURE1 = 0x01; CAPTURE2 =0x02; CAPTURE3: 0x03.
Bit
Name
Function
7:0
CAPTURE[31:0] SmaRTClock Timer Capture.
These 4 registers (CAPTURE3–CAPTURE0) are used to read or set the 32-bit
SmaRTClock timer. Data is transferred to or from the SmaRTClock timer when
the RTC0SET or RTC0CAP bits are set.
Note: The least significant bit of the timer capture value is in CAPTURE0.0.
Internal Register Definition 20.9. ALARMn: SmaRTClock Alarm Programmed Value
Bit
7
6
5
4
3
2
1
0
ALARM[31:0]
Name
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
SmaRTClock Addresses: ALARM0 = 0x08; ALARM1 = 0x09; ALARM2 = 0x0A; ALARM3 = 0x0B
Bit
Name
Function
7:0
ALARM[31:0] SmaRTClock Alarm Programmed Value.
These 4 registers (ALARM3–ALARM0) are used to set an alarm event for the
SmaRTClock timer. The SmaRTClock alarm should be disabled (RTC0AEN=0)
when updating these registers.
Note: The least significant bit of the alarm programmed value is in ALARM0.0.
Rev. 1.3
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C8051F93x-C8051F92x
21. Port Input/Output
Digital and analog resources are available through 24 I/O pins (C8051F930/20) or 16 I/O pins
(C8051F931/21). Port pins are organized as three byte-wide ports. Port pins P0.0–P2.6 can be defined as
digital or analog I/O. Digital I/O pins can be assigned to one of the internal digital resources or used as
general purpose I/O (GPIO). Analog I/O pins are used by the internal analog resources. P2.7 can be used
as GPIO and is shared with the C2 Interface Data signal (C2D). See Section “27. C2 Interface” on
page 324 for more details.
The designer has complete control over which digital and analog functions are assigned to individual port
pins, limited only by the number of physical I/O pins. This resource assignment flexibility is achieved
through the use of a Priority Crossbar Decoder. See Section 21.3 for more information on the Crossbar.
All Port I/Os are 5 V tolerant when used as digital inputs or open-drain outputs. For Port I/Os configured as
push-pull outputs, current is sourced from the VDD/DC+ supply. Port I/Os used for analog functions can
operate up to the VDD/DC+ supply voltage. See Section 21.1 for more information on Port I/O operating
modes and the electrical specifications chapter for detailed electrical specifications.
XBR0, XBR1,
XBR2, PnSKIP
Registers
Port Match
P0MASK, P0MAT
P1MASK, P1MAT
External Interrupts
EX0 and EX1
Priority
Decoder
Highest
Priority
UART
4
(Internal Digital Signals)
SPI0
SPI1
SMBus
CP0
CP1
Outputs
P0.0
2
Digital
Crossbar
8
4
8
7
T0, T1
P0
I/O
Cells
P0.7
SYSCLK
PCA
Lowest
Priority
PnMDOUT,
PnMDIN Registers
2
P1.0
P1
I/O
Cells
P1.7
2
8
(Port Latches)
P0
8
(P0.0-P0.7)
8
P1
P2.0
P2
I/O
Cell
To EMIF
(P1.0-P1.7)
8
P2
To Analog Peripherals
(ADC0, CP0, and CP1 inputs,
VREF, IREF0, AGND)
(P2.0-P2.7)
Figure 21.1. Port I/O Functional Block Diagram
216
P1.6
Rev. 1.3
P2.6
P2.7
P1.7–2.6 only available
on 32-pin devices
P2.7 is available on all
devices
C8051F93x-C8051F92x
21.1. Port I/O Modes of Operation
Port pins P0.0–P2.6 use the Port I/O cell shown in Figure 21.2. Each Port I/O cell can be configured by
software for analog I/O or digital I/O using the PnMDIN registers. On reset, all Port I/O cells default to a digital high impedance state with weak pull-ups enabled.
21.1.1. Port Pins Configured for Analog I/O
Any pins to be used as Comparator or ADC input, external oscillator input/output, or AGND, VREF, or Current Reference output should be configured for analog I/O (PnMDIN.n = 0). When a pin is configured for
analog I/O, its weak pullup and digital receiver are disabled. In most cases, software should also disable
the digital output drivers. Port pins configured for analog I/O will always read back a value of 0 regardless
of the actual voltage on the pin.
Configuring pins as analog I/O saves power and isolates the Port pin from digital interference. Port pins
configured as digital inputs may still be used by analog peripherals; however, this practice is not recommended and may result in measurement errors.
21.1.2. Port Pins Configured For Digital I/O
Any pins to be used by digital peripherals (UART, SPI, SMBus, etc.), external digital event capture functions, or as GPIO should be configured as digital I/O (PnMDIN.n = 1). For digital I/O pins, one of two output
modes (push-pull or open-drain) must be selected using the PnMDOUT registers.
Push-pull outputs (PnMDOUT.n = 1) drive the Port pad to the VDD/DC+ or GND supply rails based on the
output logic value of the Port pin. Open-drain outputs have the high side driver disabled; therefore, they
only drive the Port pad to GND when the output logic value is 0 and become high impedance inputs (both
high and low drivers turned off) when the output logic value is 1.
When a digital I/O cell is placed in the high impedance state, a weak pull-up transistor pulls the Port pad to
the VDD/DC+ supply voltage to ensure the digital input is at a defined logic state. Weak pull-ups are disabled when the I/O cell is driven to GND to minimize power consumption and may be globally disabled by
setting WEAKPUD to 1. The user must ensure that digital I/O are always internally or externally pulled or
driven to a valid logic state. Port pins configured for digital I/O always read back the logic state of the Port
pad, regardless of the output logic value of the Port pin.
WEAKPUD
(Weak Pull-Up Disable)
PnMDOUT.x
(1 for push-pull)
(0 for open-drain)
VDD/DC+
XBARE
(Crossbar
Enable)
VDD/DC+
(WEAK)
PORT
PAD
Pn.x – Output
Logic Value
(Port Latch or
Crossbar)
PnMDIN.x
(1 for digital)
(0 for analog)
To/From Analog
Peripheral
GND
Pn.x – Input Logic Value
(Reads 0 when pin is configured as an analog I/O)
Figure 21.2. Port I/O Cell Block Diagram
Rev. 1.3
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C8051F93x-C8051F92x
21.1.3. Interfacing Port I/O to 5 V and 3.3 V Logic
All Port I/O configured for digital, open-drain operation are capable of interfacing to digital logic operating
at a supply voltage higher than 4.5 V and less than 5.25 V. When the supply voltage is in the range of 1.8
to 2.2 V, the I/O may also interface to digital logic operating between 3.0 to 3.6 V if the input signal
frequency is less than 12.5 MHz or less than 25 MHz if the signal rise time (10% to 90%) is less than
1.2 ns. When operating at a supply voltage above 2.2 V, the device should not interface to 3.3 V logic;
however, interfacing to 5 V logic is permitted. An external pull-up resistor to the higher supply voltage is
typically required for most systems.
Important Notes:
•
•
•
When interfacing to a signal that is between 4.5 and 5.25 V, the maximum clock frequency that may be
input on a GPIO pin is 12.5 MHz. The exception to this rule is when routing an external CMOS clock to
P0.3, in which case, a signal up to 25 MHz is valid as long as the rise time (10% to 90%) is shorter
than 1.8 ns.
When the supply voltage is less than 2.2 V and interfacing to a signal that is between 3.0 and 3.6 V,
the maximum clock frequency that may be input on a GPIO pin is 3.125 MHz. The exception to this
rule is when routing an external CMOS clock to P0.3, in which case, a signal up to 25 MHz is valued as
long as the rise time (10% to 90%) is shorter than 1.2 ns.
In a multi-voltage interface, the external pull-up resistor should be sized to allow a current of at least
150 μA to flow into the Port pin when the supply voltage is between (VDD/DC+ plus 0.4 V) and
(VDD/DC+ plus 1.0 V). Once the Port pad voltage increases beyond this range, the current flowing into
the Port pin is minimal.
These guidelines only apply to multi-voltage interfaces. Port I/Os may always interface to digital logic
operating at the same supply voltage.
21.1.4. Increasing Port I/O Drive Strength
Port I/O output drivers support a high and low drive strength; the default is low drive strength. The drive
strength of a Port I/O can be configured using the PnDRV registers. See Section “4. Electrical
Characteristics” on page 45 for the difference in output drive strength between the two modes.
21.2. Assigning Port I/O Pins to Analog and Digital Functions
Port I/O pins P0.0–P2.6 can be assigned to various analog, digital, and external interrupt functions. The
Port pins assuaged to analog functions should be configured for analog I/O and Port pins assuaged to digital or external interrupt functions should be configured for digital I/O.
21.2.1. Assigning Port I/O Pins to Analog Functions
Table 21.1 shows all available analog functions that need Port I/O assignments. Port pins selected for
these analog functions should have their digital drivers disabled (PnMDOUT.n = 0 and Port Latch =
1) and their corresponding bit in PnSKIP set to 1. This reserves the pin for use by the analog function
and does not allow it to be claimed by the Crossbar. Table 21.1 shows the potential mapping of Port I/O to
each analog function.
Table 21.1. Port I/O Assignment for Analog Functions
Analog Function
218
Potentially
Assignable Port Pins
SFR(s) used for
Assignment
ADC Input
P0.0–P2.6
ADC0MX, PnSKIP
Comparator0 Input
P0.0–P2.6
CPT0MX, PnSKIP
Rev. 1.3
C8051F93x-C8051F92x
Table 21.1. Port I/O Assignment for Analog Functions
Analog Function
Potentially
Assignable Port Pins
SFR(s) used for
Assignment
Comparator1 Input
P0.0–P2.6
CPT1MX, PnSKIP
Voltage Reference (VREF0)
P0.0
REF0CN, PnSKIP
Analog Ground Reference (AGND)
P0.1
REF0CN, PnSKIP
Current Reference (IREF0)
P0.7
IREF0CN, PnSKIP
External Oscillator Input (XTAL1)
P0.2
OSCXCN, PnSKIP
External Oscillator Output (XTAL2)
P0.3
OSCXCN, PnSKIP
Rev. 1.3
219
C8051F93x-C8051F92x
21.2.2. Assigning Port I/O Pins to Digital Functions
Any Port pins not assigned to analog functions may be assigned to digital functions or used as GPIO. Most
digital functions rely on the Crossbar for pin assignment; however, some digital functions bypass the
Crossbar in a manner similar to the analog functions listed above. Port pins used by these digital functions and any Port pins selected for use as GPIO should have their corresponding bit in PnSKIP set
to 1. Table 21.2 shows all available digital functions and the potential mapping of Port I/O to each digital
function.
Table 21.2. Port I/O Assignment for Digital Functions
Digital Function
Potentially Assignable Port Pins
UART0, SPI1, SPI0, SMBus,
Any Port pin available for assignment by the
CP0 and CP1 Outputs, SysCrossbar. This includes P0.0–P2.6 pins which
tem Clock Output, PCA0,
have their PnSKIP bit set to 0.
Timer0 and Timer1 External Note: The Crossbar will always assign UART0 and
SPI1 pins to fixed locations.
Inputs.
SFR(s) used for
Assignment
XBR0, XBR1, XBR2
Any pin used for GPIO
P0.0–P2.6
P0SKIP, P1SKIP,
P2SKIP
External Memory Interface
P1.0–P2.6
P1SKIP, P2SKIP
EMI0CF
21.2.3. Assigning Port I/O Pins to External Digital Event Capture Functions
External digital event capture functions can be used to trigger an interrupt or wake the device from a low
power mode when a transition occurs on a digital I/O pin. The digital event capture functions do not require
dedicated pins and will function on both GPIO pins (PnSKIP = 1) and pins in use by the Crossbar (PnSKIP
= 0). External digital even capture functions cannot be used on pins configured for analog I/O. Table 21.3
shows all available external digital event capture functions.
Table 21.3. Port I/O Assignment for External Digital Event Capture Functions
Digital Function
Potentially Assignable Port Pins
SFR(s) used for
Assignment
External Interrupt 0
P0.0–P0.7
IT01CF
External Interrupt 1
P0.0–P0.7
IT01CF
P0.0–P1.7
P0MASK, P0MAT
P1MASK, P1MAT
Port Match
Note: On C8051F931/21 devices Port Match is not
available on P1.6 or P1.7.
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C8051F93x-C8051F92x
21.3. Priority Crossbar Decoder
The Priority Crossbar Decoder assigns a Port I/O pin to each software selected digital function using the
fixed peripheral priority order shown in Figure 21.3. The registers XBR0, XBR1, and XBR2 defined in SFR
Definition 21.1, SFR Definition 21.2, and SFR Definition 21.3 are used to select digital functions in the
Crossbar. The Port pins available for assignment by the Crossbar include all Port pins (P0.0–P2.6) which
have their corresponding bit in PnSKIP set to 0.
From Figure 21.3, the highest priority peripheral is UART0. If UART0 is selected in the Crossbar (using the
XBRn registers), then P0.4 and P0.5 will be assigned to UART0. The next highest priority peripheral is
SPI1. If SPI1 is selected in the Crossbar, then P1.0–P1.2 will be assigned to SPI1. P1.3 will be assigned if
SPI1 is configured for 4-wire mode. The user should ensure that the pins to be assigned by the Crossbar
have their PnSKIP bits set to 0.
For all remaining digital functions selected in the Crossbar, starting at the top of Figure 21.3 going down,
the least-significant unskipped, unassigned Port pin(s) are assigned to that function. If a Port pin is already
assigned (e.g., UART0 or SPI1 pins), or if its PnSKIP bit is set to 1, then the Crossbar will skip over the pin
and find next available unskipped, unassigned Port pin. All Port pins used for analog functions, GPIO, or
dedicated digital functions such as the EMIF should have their PnSKIP bit set to 1.
Figure 21.3 shows the Crossbar Decoder priority with no Port pins skipped (P0SKIP, P1SKIP, P2SKIP =
0x00); Figure 21.4 shows the Crossbar Decoder priority with the External Oscillator pins (XTAL1 and
XTAL2) skipped (P0SKIP = 0x0C).
Important Notes:
•
•
•
•
The Crossbar must be enabled (XBARE = 1) before any Port pin is used as a digital output. Port output
drivers are disabled while the Crossbar is disabled.
When SMBus is selected in the Crossbar, the pins associated with SDA and SCL will automatically be
forced into open-drain output mode regardless of the PnMDOUT setting.
SPI0 can be operated in either 3-wire or 4-wire modes, depending on the state of the NSSMD1NSSMD0 bits in register SPI0CN. The NSS signal is only routed to a Port pin when 4-wire mode is
selected. When SPI0 is selected in the Crossbar, the SPI0 mode (3-wire or 4-wire) will affect the pinout
of all digital functions lower in priority than SPI0.
For given XBRn, PnSKIP, and SPInCN register settings, one can determine the I/O pin-out of the
device using Figure 21.3 and Figure 21.4.
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AD4
AD5
AD6
AD7
A8
A9
A10
A11
ALE
/RD
/WR
C2D
5
AD3
4
AD2
3
AD1
2
AD0
1
P2
IREF0
XTAL2
0
P1
CNVSTR
XTAL1
PIN I/O
AGND
SF Signals
VREF
P0
6
7
0
1
2
3
4
5
6
7
0
1 2
3
4 5 6 7
TX0
RX0
SCK (SPI1)
MISO (SPI1)
MOSI (SPI1)
(*4-Wire SPI Only)
NSS* (SPI1)
SCK (SPI0)
MISO (SPI0)
MOSI (SPI0)
(*4-Wire SPI Only)
NSS* (SPI0)
SDA
SCL
CP0
CP0A
CP1
CP1A
/SYSCLK
CEX0
CEX1
CEX2
CEX3
CEX4
CEX5
ECI
T0
T1
0
0
0
0
0
0
P0SKIP[0:7]
0
0
0
0
0
0
0
0
P1SKIP[0:7]
0
0
0
0 0
0
P2SKIP[0:7]
Figure 21.3. Crossbar Priority Decoder with No Pins Skipped
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0 0 0 X
C8051F93x-C8051F92x
1
2
3
4
5
6
7
A11
AD7
0
ALE
/RD
/WR
C2D
AD6
7
0 1 2 3
4 5 6 7
A8
AD5
6
A9
A10
AD4
5
AD3
4
AD2
3
AD1
2
AD0
1
P2
IREF0
XTAL2
0
P1
CNVSTR
XTAL1
PIN I/O
AGND
SF Signals
VREF
P0
TX0
RX0
SCK (SPI1)
MISO (SPI1)
MOSI (SPI1)
(*4-Wire SPI Only)
NSS* (SPI1)
SCK (SPI0)
MISO (SPI0)
MOSI (SPI0)
(*4-Wire SPI Only)
NSS* (SPI0)
SDA
SCL
CP0
CP0A
CP1
CP1A
/SYSCLK
CEX0
CEX1
CEX2
CEX3
CEX4
CEX5
ECI
T0
T1
0
0
0
0
0
0
P0SKIP[0:7]
0
0
0
0
0
0
0
0
P1SKIP[0:7]
0
0
0 0 0 0
0 0 0 X
P2SKIP[0:7]
Figure 21.4. Crossbar Priority Decoder with Crystal Pins Skipped
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SFR Definition 21.1. XBR0: Port I/O Crossbar Register 0
Bit
7
6
5
4
3
2
1
0
Name
CP1AE
CP1E
CP0AE
CP0E
SYSCKE
SMB0E
SPI0E
URT0E
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
SFR Page = 0x0; SFR Address = 0xE1
Bit
Name
7
CP1AE
Function
Comparator1 Asynchronous Output Enable.
0: Asynchronous CP1 output unavailable at Port pin.
1: Asynchronous CP1 output routed to Port pin.
6
CP1E
Comparator1 Output Enable.
0: CP1 output unavailable at Port pin.
1: CP1 output routed to Port pin.
5
CP0AE
Comparator0 Asynchronous Output Enable.
0: Asynchronous CP0 output unavailable at Port pin.
1: Asynchronous CP0 output routed to Port pin.
4
CP0E
Comparator0 Output Enable.
0: CP1 output unavailable at Port pin.
1: CP1 output routed to Port pin.
3
SYSCKE SYSCLK Output Enable.
0: SYSCLK output unavailable at Port pin.
1: SYSCLK output routed to Port pin.
2
SMB0E
SMBus I/O Enable.
0: SMBus I/O unavailable at Port pin.
1: SDA and SCL routed to Port pins.
1
SPI0E
SPI0 I/O Enable
0: SPI0 I/O unavailable at Port pin.
1: SCK, MISO, and MOSI (for SPI0) routed to Port pins.
NSS (for SPI0) routed to Port pin only if SPI0 is configured to 4-wire mode.
0
URT0E
UART0 Output Enable.
0: UART I/O unavailable at Port pin.
1: TX0 and RX0 routed to Port pins P0.4 and P0.5.
Note: SPI0 can be assigned either 3 or 4 Port I/O pins.
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SFR Definition 21.2. XBR1: Port I/O Crossbar Register 1
Bit
7
Name
6
5
4
3
SPI1E
T1E
T0E
ECIE
2
1
0
PCA0ME[2:0]
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
SFR Page = 0x0; SFR Address = 0xE2
Bit
Name
7
Unused
Function
Unused.
Read = 0b; Write = Don’t Care.
6
SPI1E
SPI1 I/O Enable.
0: SPI0 I/O unavailable at Port pin.
1: SCK (for SPI1) routed to P1.0.
MISO (for SPI1) routed to P1.1.
MOSI (for SPI1) routed to P1.2.
NSS (for SPI1) routed to P1.3 only if SPI1 is configured to 4-wire mode.
5
T1E
Timer1 Input Enable.
0: T1 input unavailable at Port pin.
1: T1 input routed to Port pin.
4
T0E
Timer0 Input Enable.
0: T0 input unavailable at Port pin.
1: T0 input routed to Port pin.
3
ECIE
PCA0 External Counter Input (ECI) Enable.
0: PCA0 external counter input unavailable at Port pin.
1: PCA0 external counter input routed to Port pin.
2:0
PCA0ME PCA0 Module I/O Enable.
000: All PCA0 I/O unavailable at Port pin.
001: CEX0 routed to Port pin.
010: CEX0, CEX1 routed to Port pins.
011: CEX0, CEX1, CEX2 routed to Port pins.
100: CEX0, CEX1, CEX2 CEX3 routed to Port pins.
101: CEX0, CEX1, CEX2, CEX3, CEX4 routed to Port pins.
110: CEX0, CEX1, CEX2, CEX3, CEX4, CEX5 routed to Port pins.
111: Reserved.
Note: SPI1 can be assigned either 3 or 4 Port I/O pins.
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SFR Definition 21.3. XBR2: Port I/O Crossbar Register 2
Bit
7
6
5
4
3
2
1
0
Name
WEAKPUD
XBARE
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
SFR Page = 0x0; SFR Address = 0xE3
Bit
Name
7
6
WEAKPUD
XBARE
Function
Port I/O Weak Pullup Disable
0: Weak Pullups enabled (except for Port I/O pins configured for analog mode).
Crossbar Enable
0: Crossbar disabled.
1: Crossbar enabled.
5:0
Unused
Unused.
Read = 000000b; Write = Don’t Care.
Note: The Crossbar must be enabled (XBARE = 1) to use any Port pin as a digital output.
226
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21.4. Port Match
Port match functionality allows system events to be triggered by a logic value change on P0 or P1. A
software controlled value stored in the PnMAT registers specifies the expected or normal logic values of P0
and P1. A Port mismatch event occurs if the logic levels of the Port’s input pins no longer match the
software controlled value. This allows Software to be notified if a certain change or pattern occurs on P0 or
P1 input pins regardless of the XBRn settings. Note: On C8051F931/21 devices, Port Match is not
available on P1.6 or P1.7.
The PnMASK registers can be used to individually select which P0 and P1 pins should be compared
against the PnMAT registers. A Port mismatch event is generated if (P0 & P0MASK) does not equal
(PnMAT & P0MASK) or if (P1 & P1MASK) does not equal (PnMAT & P1MASK).
A Port mismatch event may be used to generate an interrupt or wake the device from a low power mode.
See Section “12. Interrupt Handler” on page 136 and Section “14. Power Management” on page 159 for
more details on interrupt and wake-up sources.
SFR Definition 21.4. P0MASK: Port0 Mask Register
Bit
7
6
5
4
3
Name
P0MASK[7:0]
Type
R/W
Reset
0
0
0
0
0
SFR Page= 0x0; SFR Address = 0xC7
Bit
Name
7:0
2
1
0
0
0
0
Function
P0MASK[7:0] Port0 Mask Value.
Selects the P0 pins to be compared with the corresponding bits in P0MAT.
0: P0.n pin pad logic value is ignored and cannot cause a Port Mismatch event.
1: P0.n pin pad logic value is compared to P0MAT.n.
SFR Definition 21.5. P0MAT: Port0 Match Register
Bit
7
6
5
4
3
Name
P0MAT[7:0]
Type
R/W
Reset
1
1
1
1
SFR Page= 0x0; SFR Address = 0xD7
Bit
Name
7 :0
1
2
1
0
1
1
1
Function
P0MAT[7:0] Port 0 Match Value.
Match comparison value used on Port 0 for bits in P0MASK which are set to 1.
0: P0.n pin logic value is compared with logic LOW.
1: P0.n pin logic value is compared with logic HIGH.
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SFR Definition 21.6. P1MASK: Port1 Mask Register
Bit
7
6
5
4
3
Name
P1MASK[7:0]
Type
R/W
Reset
0
0
0
0
0
SFR Page= 0x0; SFR Address = 0xBF
Bit
Name
7:0
2
1
0
0
0
0
Function
P1MASK[7:0] Port 1 Mask Value.
Selects P1 pins to be compared to the corresponding bits in P1MAT.
0: P1.n pin logic value is ignored and cannot cause a Port Mismatch event.
1: P1.n pin logic value is compared to P1MAT.n.
Note: On C8051F931/21 devices, port match is not available on P1.6 or P1.7. The corresponding P1MASK bits
must be set to 0b.
SFR Definition 21.7. P1MAT: Port1 Match Register
Bit
7
6
5
4
3
Name
P1MAT[7:0]
Type
R/W
Reset
1
1
1
1
SFR Page = 0x0; SFR Address = 0xCF
Bit
Name
7:0
1
2
1
0
1
1
1
Function
P1MAT[7:0] Port 1 Match Value.
Match comparison value used on Port 1 for bits in P1MASK which are set to 1.
0: P1.n pin logic value is compared with logic LOW.
1: P1.n pin logic value is compared with logic HIGH.
Note: On C8051F931/21 devices, port match is not available on P1.6 or P1.7.
228
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21.5. Special Function Registers for Accessing and Configuring Port I/O
All Port I/O are accessed through corresponding special function registers (SFRs) that are both byte
addressable and bit addressable. When writing to a Port, the value written to the SFR is latched to maintain the output data value at each pin. When reading, the logic levels of the Port's input pins are returned
regardless of the XBRn settings (i.e., even when the pin is assigned to another signal by the Crossbar, the
Port register can always read its corresponding Port I/O pin). The exception to this is the execution of the
read-modify-write instructions that target a Port Latch register as the destination. The read-modify-write
instructions when operating on a Port SFR are the following: ANL, ORL, XRL, JBC, CPL, INC, DEC, DJNZ
and MOV, CLR or SETB, when the destination is an individual bit in a Port SFR. For these instructions, the
value of the latch register (not the pin) is read, modified, and written back to the SFR.
Each Port has a corresponding PnSKIP register which allows its individual Port pins to be assigned to digital functions or skipped by the Crossbar. All Port pins used for analog functions, GPIO, or dedicated digital
functions such as the EMIF should have their PnSKIP bit set to 1.
The Port input mode of the I/O pins is defined using the Port Input Mode registers (PnMDIN). Each Port
cell can be configured for analog or digital I/O. This selection is required even for the digital resources
selected in the XBRn registers, and is not automatic. The only exception to this is P2.7, which can only be
used for digital I/O.
The output driver characteristics of the I/O pins are defined using the Port Output Mode registers (PnMDOUT). Each Port Output driver can be configured as either open drain or push-pull. This selection is
required even for the digital resources selected in the XBRn registers, and is not automatic. The only
exception to this is the SMBus (SDA, SCL) pins, which are configured as open-drain regardless of the
PnMDOUT settings.
The drive strength of the output drivers are controlled by the Port Drive Strength (PnDRV) registers. The
default is low drive strength. See Section “4. Electrical Characteristics” on page 45 for the difference in output drive strength between the two modes.
Rev. 1.3
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SFR Definition 21.8. P0: Port0
Bit
7
6
5
4
Name
P0[7:0]
Type
R/W
Reset
1
1
1
1
3
2
1
0
1
1
1
1
SFR Page = All Pages; SFR Address = 0x80; Bit-Addressable
Bit
Name
Description
Write
7:0
P0[7:0]
Read
0: Set output latch to logic
LOW.
Sets the Port latch logic
value or reads the Port pin 1: Set output latch to logic
logic state in Port cells con- HIGH.
figured for digital I/O.
Port 0 Data.
0: P0.n Port pin is logic
LOW.
1: P0.n Port pin is logic
HIGH.
SFR Definition 21.9. P0SKIP: Port0 Skip
Bit
7
6
5
4
3
Name
P0SKIP[7:0]
Type
R/W
Reset
0
0
0
0
SFR Page= 0x0; SFR Address = 0xD4
Bit
Name
7:0
0
2
1
0
0
0
0
Function
P0SKIP[7:0] Port 0 Crossbar Skip Enable Bits.
These bits select Port 0 pins to be skipped by the Crossbar Decoder. Port pins used
for analog, special functions or GPIO should be skipped by the Crossbar.
0: Corresponding P0.n pin is not skipped by the Crossbar.
1: Corresponding P0.n pin is skipped by the Crossbar.
230
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SFR Definition 21.10. P0MDIN: Port0 Input Mode
Bit
7
6
5
4
3
Name
P0MDIN[7:0]
Type
R/W
Reset
1
1
1
1
1
SFR Page= 0x0; SFR Address = 0xF1
Bit
Name
7:0
P0MDIN[7:0]
2
1
0
1
1
1
Function
Analog Configuration Bits for P0.7–P0.0 (respectively).
Port pins configured for analog mode have their weak pullup, and digital receiver
disabled. The digital driver is not explicitly disabled.
0: Corresponding P0.n pin is configured for analog mode.
1: Corresponding P0.n pin is not configured for analog mode.
SFR Definition 21.11. P0MDOUT: Port0 Output Mode
Bit
7
6
5
4
3
Name
P0MDOUT[7:0]
Type
R/W
Reset
0
0
0
0
SFR Page = 0x0; SFR Address = 0xA4
Bit
Name
7:0
0
2
1
0
0
0
0
Function
P0MDOUT[7:0] Output Configuration Bits for P0.7–P0.0 (respectively).
These bits control the digital driver even when the corresponding bit in register
P0MDIN is logic 0.
0: Corresponding P0.n Output is open-drain.
1: Corresponding P0.n Output is push-pull.
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SFR Definition 21.12. P0DRV: Port0 Drive Strength
Bit
7
6
5
4
3
Name
P0DRV[7:0]
Type
R/W
Reset
0
0
0
0
SFR Page = 0xF; SFR Address = 0xA4
Bit
Name
7:0
0
2
1
0
0
0
0
Function
P0DRV[7:0] Drive Strength Configuration Bits for P0.7–P0.0 (respectively).
Configures digital I/O Port cells to high or low output drive strength.
0: Corresponding P0.n Output has low output drive strength.
1: Corresponding P0.n Output has high output drive strength.
232
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SFR Definition 21.13. P1: Port1
Bit
7
6
5
4
Name
P1[7:0]
Type
R/W
Reset
1
1
1
1
3
2
1
0
1
1
1
1
SFR Page = All Pages; SFR Address = 0x90; Bit-Addressable
Bit
Name
Description
Write
7:0
P1[7:0]
Read
0: Set output latch to logic
LOW.
Sets the Port latch logic
value or reads the Port pin 1: Set output latch to logic
logic state in Port cells con- HIGH.
figured for digital I/O.
Port 1 Data.
0: P1.n Port pin is logic
LOW.
1: P1.n Port pin is logic
HIGH.
Note: Pin P1.7 is only available in 32-pin devices.
SFR Definition 21.14. P1SKIP: Port1 Skip
Bit
7
6
5
4
3
Name
P1SKIP[7:0]
Type
R/W
Reset
0
0
0
0
SFR Page = 0x0; SFR Address = 0xD5
Bit
Name
7:0
0
2
1
0
0
0
0
Function
P1SKIP[7:0] Port 1 Crossbar Skip Enable Bits.
These bits select Port 1 pins to be skipped by the Crossbar Decoder. Port pins used
for analog, special functions or GPIO should be skipped by the Crossbar.
0: Corresponding P1.n pin is not skipped by the Crossbar.
1: Corresponding P1.n pin is skipped by the Crossbar.
Note: Pin P1.7 is only available in 32-pin devices.
Rev. 1.3
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SFR Definition 21.15. P1MDIN: Port1 Input Mode
Bit
7
6
5
4
3
Name
P1MDIN[7:0]
Type
R/W
Reset
1
1
1
1
1
SFR Page = 0x0; SFR Address = 0xF2
Bit
Name
7:0
P1MDIN[7:0]
2
1
0
1
1
1
Function
Analog Configuration Bits for P1.7–P1.0 (respectively).
Port pins configured for analog mode have their weak pullup and digital receiver
disabled. The digital driver is not explicitly disabled.
0: Corresponding P1.n pin is configured for analog mode.
1: Corresponding P1.n pin is not configured for analog mode.
Note: Pin P1.7 is only available in 32-pin devices.
SFR Definition 21.16. P1MDOUT: Port1 Output Mode
Bit
7
6
5
4
3
Name
P1MDOUT[7:0]
Type
R/W
Reset
0
0
0
0
SFR Page = 0x0; SFR Address = 0xA5
Bit
Name
7:0
0
2
1
0
0
0
0
Function
P1MDOUT[7:0] Output Configuration Bits for P1.7–P1.0 (respectively).
These bits control the digital driver even when the corresponding bit in register
P1MDIN is logic 0.
0: Corresponding P1.n Output is open-drain.
1: Corresponding P1.n Output is push-pull.
Note: Pin P1.7 is only available in 32-pin devices.
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SFR Definition 21.17. P1DRV: Port1 Drive Strength
Bit
7
6
5
4
3
Name
P1DRV[7:0]
Type
R/W
Reset
0
0
0
0
0
SFR Page = 0xF; SFR Address = 0xA5
Bit
Name
7:0
2
1
0
0
0
0
Function
P1DRV[7:0] Drive Strength Configuration Bits for P1.7–P1.0 (respectively).
Configures digital I/O Port cells to high or low output drive strength.
0: Corresponding P1.n Output has low output drive strength.
1: Corresponding P1.n Output has high output drive strength.
Note: Pin P1.7 is only available in 32-pin devices.
SFR Definition 21.18. P2: Port2
Bit
7
6
5
4
Name
P2[7:0]
Type
R/W
Reset
1
1
1
1
3
2
1
0
1
1
1
1
SFR Page = All Pages; SFR Address = 0xA0; Bit-Addressable
Bit
Name
7:0
P2[7:0]
Description
Read
0: Set output latch to logic
LOW.
Sets the Port latch logic
value or reads the Port pin 1: Set output latch to logic
logic state in Port cells con- HIGH.
figured for digital I/O.
Port 2 Data.
Write
0: P2.n Port pin is logic
LOW.
1: P2.n Port pin is logic
HIGH.
Note: Pins P2.0-P2.6 are only available in 32-pin devices.
Rev. 1.3
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SFR Definition 21.19. P2SKIP: Port2 Skip
Bit
7
6
5
4
3
Name
P2SKIP[7:0]
Type
R/W
Reset
0
0
0
0
0
2
1
0
0
0
0
SFR Page = 0x0; SFR Address = 0xD6
Bit
Name
7:0
P2SKIP[7:0]
Description
Read
Write
Port 1 Crossbar Skip Enable Bits.
These bits select Port 2 pins to be skipped by the Crossbar Decoder. Port pins
used for analog, special functions or GPIO should be skipped by the Crossbar.
0: Corresponding P2.n pin is not skipped by the Crossbar.
1: Corresponding P2.n pin is skipped by the Crossbar.
Note: Pins P2.0-P2.6 are only available in 32-pin devices.
SFR Definition 21.20. P2MDIN: Port2 Input Mode
Bit
7
Name
Reserved
6
5
4
1
0
1
1
1
R/W
1
1
1
1
SFR Page = 0x0; SFR Address = 0xF3
Bit
Name
7
6:0
2
P2MDIN[6:0]
Type
Reset
3
1
Function
Reserved. Read = 1b; Must Write 1b.
P2MDIN[3:0]
Analog Configuration Bits for P2.6–P2.0 (respectively).
Port pins configured for analog mode have their weak pullup and digital receiver
disabled. The digital driver is not explicitly disabled.
0: Corresponding P2.n pin is configured for analog mode.
1: Corresponding P2.n pin is not configured for analog mode.
Note: Pins P2.0-P2.6 are only available in 32-pin devices.
236
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SFR Definition 21.21. P2MDOUT: Port2 Output Mode
Bit
7
6
5
4
3
Name
P2MDOUT[7:0]
Type
R/W
Reset
0
0
0
0
0
SFR Page = 0x0; SFR Address = 0xA6
Bit
Name
7:0
2
1
0
0
0
0
Function
P2MDOUT[7:0] Output Configuration Bits for P2.7–P2.0 (respectively).
These bits control the digital driver even when the corresponding bit in register
P2MDIN is logic 0.
0: Corresponding P2.n Output is open-drain.
1: Corresponding P2.n Output is push-pull.
Note: Pins P2.0-P2.6 are only available in 32-pin devices.
SFR Definition 21.22. P2DRV: Port2 Drive Strength
Bit
7
6
5
4
3
Name
P2DRV[7:0]
Type
R/W
Reset
0
0
0
0
SFR Page = 0x0F; SFR Address = 0xA6
Bit
Name
7:0
P2DRV[7:0]
0
2
1
0
0
0
0
Function
Drive Strength Configuration Bits for P2.7–P2.0 (respectively).
Configures digital I/O Port cells to high or low output drive strength.
0: Corresponding P2.n Output has low output drive strength.
1: Corresponding P2.n Output has high output drive strength.
Note: Pins P2.0-P2.6 are only available in 32-pin devices.
Rev. 1.3
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C8051F93x-C8051F92x
22. SMBus
The SMBus I/O interface is a two-wire, bi-directional serial bus. The SMBus is compliant with the System
Management Bus Specification, version 1.1, and compatible with the I2C serial bus. Reads and writes to
the interface by the system controller are byte oriented with the SMBus interface autonomously controlling
the serial transfer of the data. Data can be transferred at up to 1/20th of the system clock as a master or
slave (this can be faster than allowed by the SMBus specification, depending on the system clock used). A
method of extending the clock-low duration is available to accommodate devices with different speed
capabilities on the same bus.
The SMBus interface may operate as a master and/or slave, and may function on a bus with multiple
masters. The SMBus provides control of SDA (serial data), SCL (serial clock) generation and
synchronization, arbitration logic, and START/STOP control and generation. The SMBus peripheral can be
fully driven by software (i.e., software accepts/rejects slave addresses, and generates ACKs), or hardware
slave address recognition and automatic ACK generation can be enabled to minimize software overhead.
A block diagram of the SMBus peripheral and the associated SFRs is shown in Figure 22.1.
SMB0CN
M T S S A A A S
A X T T CR C I
SMAOK B K
T O
R L
E D
QO
R E
S
T
SMB0CF
E I B E S S S S
N N U XMMMM
S H S T B B B B
M Y H T F CC
B
OO T S S
L E E 1 0
D
SMBUS CONTROL LOGIC
Arbitration
SCL Synchronization
SCL Generation (Master Mode)
SDA Control
Hardware Slave Address Recognition
Hardware ACK Generation
Data Path
IRQ Generation
Control
Interrupt
Request
00
T0 Overflow
01
T1 Overflow
10
TMR2H Overflow
11
TMR2L Overflow
SCL
Control
S
L
V
5
S
L
V
4
S
L
V
3
S
L
V
2
S
L
V
1
SMB0ADR
SG
L C
V
0
S S S S S S S
L L L L L L L
V V V V V V V
MMMMMMM
6 5 4 3 2 1 0
SMB0ADM
SDA
FILTER
E
H
A
C
K
N
Figure 22.1. SMBus Block Diagram
238
C
R
O
S
S
B
A
R
N
SDA
Control
SMB0DAT
7 6 5 4 3 2 1 0
S
L
V
6
SCL
FILTER
Rev. 1.3
Port I/O
C8051F93x-C8051F92x
22.1. Supporting Documents
It is assumed the reader is familiar with or has access to the following supporting documents:
1. The I2C-Bus and How to Use It (including specifications), Philips Semiconductor.
2. The I2C-Bus Specification—Version 2.0, Philips Semiconductor.
3. System Management Bus Specification—Version 1.1, SBS Implementers Forum.
22.2. SMBus Configuration
Figure 22.2 shows a typical SMBus configuration. The SMBus specification allows any recessive voltage
between 3.0 V and 5.0 V; different devices on the bus may operate at different voltage levels. The bidirectional SCL (serial clock) and SDA (serial data) lines must be connected to a positive power supply
voltage through a pullup resistor or similar circuit. Every device connected to the bus must have an opendrain or open-collector output for both the SCL and SDA lines, so that both are pulled high (recessive
state) when the bus is free. The maximum number of devices on the bus is limited only by the requirement
that the rise and fall times on the bus not exceed 300 ns and 1000 ns, respectively.
VDD = 5 V
VDD = 3 V
VDD = 5 V
VDD = 3 V
Master
Device
Slave
Device 1
Slave
Device 2
SDA
SCL
Figure 22.2. Typical SMBus Configuration
Rev. 1.3
239
C8051F93x-C8051F92x
22.3. SMBus Operation
Two types of data transfers are possible: data transfers from a master transmitter to an addressed slave
receiver (WRITE), and data transfers from an addressed slave transmitter to a master receiver (READ).
The master device initiates both types of data transfers and provides the serial clock pulses on SCL. The
SMBus interface may operate as a master or a slave, and multiple master devices on the same bus are
supported. If two or more masters attempt to initiate a data transfer simultaneously, an arbitration scheme
is employed with a single master always winning the arbitration. Note that it is not necessary to specify one
device as the Master in a system; any device who transmits a START and a slave address becomes the
master for the duration of that transfer.
A typical SMBus transaction consists of a START condition followed by an address byte (Bits7–1: 7-bit
slave address; Bit0: R/W direction bit), one or more bytes of data, and a STOP condition. Bytes that are
received (by a master or slave) are acknowledged (ACK) with a low SDA during a high SCL (see
Figure 22.3). If the receiving device does not ACK, the transmitting device will read a NACK (not
acknowledge), which is a high SDA during a high SCL.
The direction bit (R/W) occupies the least-significant bit position of the address byte. The direction bit is set
to logic 1 to indicate a "READ" operation and cleared to logic 0 to indicate a "WRITE" operation.
All transactions are initiated by a master, with one or more addressed slave devices as the target. The
master generates the START condition and then transmits the slave address and direction bit. If the
transaction is a WRITE operation from the master to the slave, the master transmits the data a byte at a
time waiting for an ACK from the slave at the end of each byte. For READ operations, the slave transmits
the data waiting for an ACK from the master at the end of each byte. At the end of the data transfer, the
master generates a STOP condition to terminate the transaction and free the bus. Figure 22.3 illustrates a
typical SMBus transaction.
SCL
SDA
SLA6
START
SLA5-0
Slave Address + R/W
R/W
D7
ACK
D6-0
Data Byte
NACK
STOP
Figure 22.3. SMBus Transaction
22.3.1. Transmitter Vs. Receiver
On the SMBus communications interface, a device is the “transmitter” when it is sending an address or
data byte to another device on the bus. A device is a “receiver” when an address or data byte is being sent
to it from another device on the bus. The transmitter controls the SDA line during the address or data byte.
After each byte of address or data information is sent by the transmitter, the receiver sends an ACK or
NACK bit during the ACK phase of the transfer, during which time the receiver controls the SDA line.
240
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22.3.2. Arbitration
A master may start a transfer only if the bus is free. The bus is free after a STOP condition or after the SCL
and SDA lines remain high for a specified time (see Section “22.3.5. SCL High (SMBus Free) Timeout” on
page 241). In the event that two or more devices attempt to begin a transfer at the same time, an
arbitration scheme is employed to force one master to give up the bus. The master devices continue
transmitting until one attempts a HIGH while the other transmits a LOW. Since the bus is open-drain, the
bus will be pulled LOW. The master attempting the HIGH will detect a LOW SDA and lose the arbitration.
The winning master continues its transmission without interruption; the losing master becomes a slave and
receives the rest of the transfer if addressed. This arbitration scheme is non-destructive: one device
always wins, and no data is lost.
22.3.3. Clock Low Extension
SMBus provides a clock synchronization mechanism, similar to I2C, which allows devices with different
speed capabilities to coexist on the bus. A clock-low extension is used during a transfer in order to allow
slower slave devices to communicate with faster masters. The slave may temporarily hold the SCL line
LOW to extend the clock low period, effectively decreasing the serial clock frequency.
22.3.4. SCL Low Timeout
If the SCL line is held low by a slave device on the bus, no further communication is possible. Furthermore,
the master cannot force the SCL line high to correct the error condition. To solve this problem, the SMBus
protocol specifies that devices participating in a transfer must detect any clock cycle held low longer than
25 ms as a “timeout” condition. Devices that have detected the timeout condition must reset the
communication no later than 10 ms after detecting the timeout condition.
When the SMBTOE bit in SMB0CF is set, Timer 3 is used to detect SCL low timeouts. Timer 3 is forced to
reload when SCL is high, and allowed to count when SCL is low. With Timer 3 enabled and configured to
overflow after 25 ms (and SMBTOE set), the Timer 3 interrupt service routine can be used to reset (disable
and re-enable) the SMBus in the event of an SCL low timeout.
22.3.5. SCL High (SMBus Free) Timeout
The SMBus specification stipulates that if the SCL and SDA lines remain high for more that 50 µs, the bus
is designated as free. When the SMBFTE bit in SMB0CF is set, the bus will be considered free if SCL and
SDA remain high for more than 10 SMBus clock source periods (as defined by the timer configured for the
SMBus clock source). If the SMBus is waiting to generate a Master START, the START will be generated
following this timeout. A clock source is required for free timeout detection, even in a slave-only
implementation.
Rev. 1.3
241
C8051F93x-C8051F92x
22.4. Using the SMBus
The SMBus can operate in both Master and Slave modes. The interface provides timing and shifting control for serial transfers; higher level protocol is determined by user software. The SMBus interface provides
the following application-independent features:
•
•
•
•
•
•
•
•
Byte-wise serial data transfers
Clock signal generation on SCL (Master Mode only) and SDA data synchronization
Timeout/bus error recognition, as defined by the SMB0CF configuration register
START/STOP timing, detection, and generation
Bus arbitration
Interrupt generation
Status information
Optional hardware recognition of slave address and automatic acknowledgement of address/data
SMBus interrupts are generated for each data byte or slave address that is transferred. When hardware
acknowledgement is disabled, the point at which the interrupt is generated depends on whether the
hardware is acting as a data transmitter or receiver. When a transmitter (i.e., sending address/data,
receiving an ACK), this interrupt is generated after the ACK cycle so that software may read the received
ACK value; when receiving data (i.e., receiving address/data, sending an ACK), this interrupt is generated
before the ACK cycle so that software may define the outgoing ACK value. If hardware acknowledgement
is enabled, these interrupts are always generated after the ACK cycle. See Section 22.5 for more details
on transmission sequences.
Interrupts are also generated to indicate the beginning of a transfer when a master (START generated), or
the end of a transfer when a slave (STOP detected). Software should read the SMB0CN (SMBus Control
register) to find the cause of the SMBus interrupt. The SMB0CN register is described in Section 22.4.2;
Table 22.5 provides a quick SMB0CN decoding reference.
242
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C8051F93x-C8051F92x
22.4.1. SMBus Configuration Register
The SMBus Configuration register (SMB0CF) is used to enable the SMBus Master and/or Slave modes,
select the SMBus clock source, and select the SMBus timing and timeout options. When the ENSMB bit is
set, the SMBus is enabled for all master and slave events. Slave events may be disabled by setting the
INH bit. With slave events inhibited, the SMBus interface will still monitor the SCL and SDA pins; however,
the interface will NACK all received addresses and will not generate any slave interrupts. When the INH bit
is set, all slave events will be inhibited following the next START (interrupts will continue for the duration of
the current transfer).
Table 22.1. SMBus Clock Source Selection
SMBCS1
0
0
1
1
SMBCS0
0
1
0
1
SMBus Clock Source
Timer 0 Overflow
Timer 1 Overflow
Timer 2 High Byte Overflow
Timer 2 Low Byte Overflow
The SMBCS1–0 bits select the SMBus clock source, which is used only when operating as a master or
when the Free Timeout detection is enabled. When operating as a master, overflows from the selected
source determine the absolute minimum SCL low and high times as defined in Equation 22.1. The
selected clock source may be shared by other peripherals so long as the timer is left running at all times.
For example, Timer 1 overflows may generate the SMBus and UART baud rates simultaneously. Timer
configuration is covered in Section “25. Timers” on page 283.
1
T HighMin = T LowMin = ---------------------------------------------f ClockSourceOverflow
Equation 22.1. Minimum SCL High and Low Times
The selected clock source should be configured to establish the minimum SCL High and Low times as per
Equation 22.1. When the interface is operating as a master (and SCL is not driven or extended by any
other devices on the bus), the typical SMBus bit rate is approximated by Equation 22.2.
f ClockSourceOverflow
BitRate = ---------------------------------------------3
Equation 22.2. Typical SMBus Bit Rate
Figure 22.4 shows the typical SCL generation described by Equation 22.2. Notice that THIGH is typically
twice as large as TLOW. The actual SCL output may vary due to other devices on the bus (SCL may be
extended low by slower slave devices, or driven low by contending master devices). The bit rate when
operating as a master will never exceed the limits defined by equation Equation 22.1.
Timer Source
Overflows
SCL
TLow
THigh
SCL High Timeout
Figure 22.4. Typical SMBus SCL Generation
Rev. 1.3
243
C8051F93x-C8051F92x
Setting the EXTHOLD bit extends the minimum setup and hold times for the SDA line. The minimum SDA
setup time defines the absolute minimum time that SDA is stable before SCL transitions from low-to-high.
The minimum SDA hold time defines the absolute minimum time that the current SDA value remains stable
after SCL transitions from high-to-low. EXTHOLD should be set so that the minimum setup and hold times
meet the SMBus Specification requirements of 250 ns and 300 ns, respectively. Table 22.2 shows the
minimum setup and hold times for the two EXTHOLD settings. Setup and hold time extensions are
typically necessary when SYSCLK is above 10 MHz.
Table 22.2. Minimum SDA Setup and Hold Times
EXTHOLD
Minimum SDA Setup Time
Minimum SDA Hold Time
Tlow – 4 system clocks
0
3 system clocks
or
1 system clock + s/w delay*
1
11 system clocks
12 system clocks
*Note: Setup Time for ACK bit transmissions and the MSB of all data transfers. When
using software acknowledgement, the s/w delay occurs between the time SMB0DAT
or ACK is written and when SI is cleared. Note that if SI is cleared in the same write
that defines the outgoing ACK value, s/w delay is zero.
With the SMBTOE bit set, Timer 3 should be configured to overflow after 25 ms in order to detect SCL low
timeouts (see Section “22.3.4. SCL Low Timeout” on page 241). The SMBus interface will force Timer 3 to
reload while SCL is high, and allow Timer 3 to count when SCL is low. The Timer 3 interrupt service routine
should be used to reset SMBus communication by disabling and re-enabling the SMBus.
SMBus Free Timeout detection can be enabled by setting the SMBFTE bit. When this bit is set, the bus will
be considered free if SDA and SCL remain high for more than 10 SMBus clock source periods (see
Figure 22.4).
244
Rev. 1.3
C8051F93x-C8051F92x
SFR Definition 22.1. SMB0CF: SMBus Clock/Configuration
Bit
7
6
5
4
Name
ENSMB
INH
BUSY
Type
R/W
R/W
R
R/W
Reset
0
0
0
0
EXTHOLD SMBTOE
SFR Page = 0x0; SFR Address = 0xC1
Bit
Name
7
ENSMB
3
2
1
0
SMBFTE
SMBCS[1:0]
R/W
R/W
R/W
0
0
0
0
Function
SMBus Enable.
This bit enables the SMBus interface when set to 1. When enabled, the interface
constantly monitors the SDA and SCL pins.
6
INH
SMBus Slave Inhibit.
When this bit is set to logic 1, the SMBus does not generate an interrupt when slave
events occur. This effectively removes the SMBus slave from the bus. Master Mode
interrupts are not affected.
5
BUSY
SMBus Busy Indicator.
This bit is set to logic 1 by hardware when a transfer is in progress. It is cleared to
logic 0 when a STOP or free-timeout is sensed.
4
EXTHOLD
SMBus Setup and Hold Time Extension Enable.
This bit controls the SDA setup and hold times according to Table 22.2.
0: SDA Extended Setup and Hold Times disabled.
1: SDA Extended Setup and Hold Times enabled.
3
SMBTOE
SMBus SCL Timeout Detection Enable.
This bit enables SCL low timeout detection. If set to logic 1, the SMBus forces
Timer 3 to reload while SCL is high and allows Timer 3 to count when SCL goes low.
If Timer 3 is configured to Split Mode, only the High Byte of the timer is held in reload
while SCL is high. Timer 3 should be programmed to generate interrupts at 25 ms,
and the Timer 3 interrupt service routine should reset SMBus communication.
2
SMBFTE
SMBus Free Timeout Detection Enable.
When this bit is set to logic 1, the bus will be considered free if SCL and SDA remain
high for more than 10 SMBus clock source periods.
1 :0
SMBCS[1:0] SMBus Clock Source Selection.
These two bits select the SMBus clock source, which is used to generate the SMBus
bit rate. The selected device should be configured according to Equation 22.1.
00: Timer 0 Overflow
01: Timer 1 Overflow
10:Timer 2 High Byte Overflow
11: Timer 2 Low Byte Overflow
Rev. 1.3
245
C8051F93x-C8051F92x
22.4.2. SMB0CN Control Register
SMB0CN is used to control the interface and to provide status information (see SFR Definition 22.2). The
higher four bits of SMB0CN (MASTER, TXMODE, STA, and STO) form a status vector that can be used to
jump to service routines. MASTER indicates whether a device is the master or slave during the current
transfer. TXMODE indicates whether the device is transmitting or receiving data for the current byte.
STA and STO indicate that a START and/or STOP has been detected or generated since the last SMBus
interrupt. STA and STO are also used to generate START and STOP conditions when operating as a
master. Writing a 1 to STA will cause the SMBus interface to enter Master Mode and generate a START
when the bus becomes free (STA is not cleared by hardware after the START is generated). Writing a 1 to
STO while in Master Mode will cause the interface to generate a STOP and end the current transfer after
the next ACK cycle. If STO and STA are both set (while in Master Mode), a STOP followed by a START will
be generated.
The ARBLOST bit indicates that the interface has lost an arbitration. This may occur anytime the interface
is transmitting (master or slave). A lost arbitration while operating as a slave indicates a bus error
condition. ARBLOST is cleared by hardware each time SI is cleared.
The SI bit (SMBus Interrupt Flag) is set at the beginning and end of each transfer, after each byte frame, or
when an arbitration is lost; see Table 22.3 for more details.
Important Note About the SI Bit: The SMBus interface is stalled while SI is set; thus SCL is held low, and
the bus is stalled until software clears SI.
22.4.2.1.Software ACK Generation
When the EHACK bit in register SMB0ADM is cleared to 0, the firmware on the device must detect incoming slave addresses and ACK or NACK the slave address and incoming data bytes. As a receiver, writing
the ACK bit defines the outgoing ACK value; as a transmitter, reading the ACK bit indicates the value
received during the last ACK cycle. ACKRQ is set each time a byte is received, indicating that an outgoing
ACK value is needed. When ACKRQ is set, software should write the desired outgoing value to the ACK
bit before clearing SI. A NACK will be generated if software does not write the ACK bit before clearing SI.
SDA will reflect the defined ACK value immediately following a write to the ACK bit; however SCL will
remain low until SI is cleared. If a received slave address is not acknowledged, further slave events will be
ignored until the next START is detected.
22.4.2.2.Hardware ACK Generation
When the EHACK bit in register SMB0ADM is set to 1, automatic slave address recognition and ACK generation is enabled. More detail about automatic slave address recognition can be found in Section 22.4.3.
As a receiver, the value currently specified by the ACK bit will be automatically sent on the bus during the
ACK cycle of an incoming data byte. As a transmitter, reading the ACK bit indicates the value received on
the last ACK cycle. The ACKRQ bit is not used when hardware ACK generation is enabled. If a received
slave address is NACKed by hardware, further slave events will be ignored until the next START is
detected, and no interrupt will be generated.
Table 22.3 lists all sources for hardware changes to the SMB0CN bits. Refer to Table 22.5 for SMBus
status decoding using the SMB0CN register.
Refer to the C8051F930 errata when using hardware ACK generation on C8051F930/31/20/21 devices.
246
Rev. 1.3
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SFR Definition 22.2. SMB0CN: SMBus Control
Bit
7
6
5
4
3
2
1
0
Name
MASTER
TXMODE
STA
STO
ACKRQ
ARBLOST
ACK
SI
Type
R
R
R/W
R/W
R
R
R/W
R/W
Reset
0
0
0
0
0
0
0
0
SFR Page = 0x0; SFR Address = 0xC0; Bit-Addressable
Bit
Name
Description
Read
Write
7
MASTER SMBus Master/Slave
Indicator. This read-only bit
indicates when the SMBus is
operating as a master.
0: SMBus operating in
slave mode.
1: SMBus operating in
master mode.
N/A
6
TXMODE SMBus Transmit Mode
Indicator. This read-only bit
indicates when the SMBus is
operating as a transmitter.
0: SMBus in Receiver
Mode.
1: SMBus in Transmitter
Mode.
N/A
5
STA
SMBus Start Flag.
0: No Start or repeated
Start detected.
1: Start or repeated Start
detected.
0: No Start generated.
1: When Configured as a
Master, initiates a START
or repeated START.
4
STO
SMBus Stop Flag.
0: No Stop condition
detected.
1: Stop condition detected
(if in Slave Mode) or pending (if in Master Mode).
0: No STOP condition is
transmitted.
1: When configured as a
Master, causes a STOP
condition to be transmitted after the next ACK
cycle.
Cleared by Hardware.
3
ACKRQ
SMBus Acknowledge
Request.
0: No Ack requested
1: ACK requested
N/A
0: No arbitration error.
1: Arbitration Lost
N/A
2
ARBLOST SMBus Arbitration Lost
Indicator.
1
ACK
SMBus Acknowledge.
0: NACK received.
1: ACK received.
0: Send NACK
1: Send ACK
0
SI
SMBus Interrupt Flag.
0: No interrupt pending
0: Clear interrupt, and initiate next state machine
event.
1: Force interrupt.
This bit is set by hardware
1: Interrupt Pending
under the conditions listed in
Table 15.3. SI must be cleared
by software. While SI is set,
SCL is held low and the
SMBus is stalled.
Rev. 1.3
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C8051F93x-C8051F92x
Table 22.3. Sources for Hardware Changes to SMB0CN
Bit
Set by Hardware When:
MASTER
• A START is generated.
TXMODE
• START is generated.
• SMB0DAT is written before the start of an
SMBus frame.
STA
STO
ACKRQ
ARBLOST
ACK
SI
248
• A START followed by an address byte is
received.
• A STOP is detected while addressed as a
slave.
• Arbitration is lost due to a detected STOP.
• A byte has been received and an ACK
response value is needed (only when hardware ACK is not enabled).
• A repeated START is detected as a MASTER
when STA is low (unwanted repeated START).
• SCL is sensed low while attempting to generate a STOP or repeated START condition.
• SDA is sensed low while transmitting a 1
(excluding ACK bits).
• The incoming ACK value is low 
(ACKNOWLEDGE).
• A START has been generated.
• Lost arbitration.
• A byte has been transmitted and an
ACK/NACK received.
• A byte has been received.
• A START or repeated START followed by a
slave address + R/W has been received.
• A STOP has been received.
Rev. 1.3
Cleared by Hardware When:
• A STOP is generated.
• Arbitration is lost.
• A START is detected.
• Arbitration is lost.
• SMB0DAT is not written before the
start of an SMBus frame.
• Must be cleared by software.
• A pending STOP is generated.
• After each ACK cycle.
• Each time SI is cleared.
• The incoming ACK value is high (NOT
ACKNOWLEDGE).
• Must be cleared by software.
C8051F93x-C8051F92x
22.4.3. Hardware Slave Address Recognition
The SMBus hardware has the capability to automatically recognize incoming slave addresses and send an
ACK without software intervention. Automatic slave address recognition is enabled by setting the EHACK
bit in register SMB0ADM to 1. This will enable both automatic slave address recognition and automatic
hardware ACK generation for received bytes (as a master or slave). More detail on automatic hardware
ACK generation can be found in Section 22.4.2.2.
The registers used to define which address(es) are recognized by the hardware are the SMBus Slave
Address register (SFR Definition 22.3) and the SMBus Slave Address Mask register (SFR Definition 22.4).
A single address or range of addresses (including the General Call Address 0x00) can be specified using
these two registers. The most-significant seven bits of the two registers are used to define which
addresses will be ACKed. A 1 in bit positions of the slave address mask SLVM[6:0] enable a comparison
between the received slave address and the hardware’s slave address SLV[6:0] for those bits. A 0 in a bit
of the slave address mask means that bit will be treated as a “don’t care” for comparison purposes. In this
case, either a 1 or a 0 value are acceptable on the incoming slave address. Additionally, if the GC bit in
register SMB0ADR is set to 1, hardware will recognize the General Call Address (0x00). Table 22.4 shows
some example parameter settings and the slave addresses that will be recognized by hardware under
those conditions. Refer to the C8051F930 errata when using hardware ACK generation on
C8051F930/31/20/21 devices.
Table 22.4. Hardware Address Recognition Examples (EHACK = 1)
Hardware Slave Address
SLV[6:0]
Slave Address Mask
SLVM[6:0]
GC bit
Slave Addresses Recognized by
Hardware
0x34
0x7F
0
0x34
0x34
0x7F
1
0x34, 0x00 (General Call)
0x34
0x7E
0
0x34, 0x35
0x34
0x7E
1
0x34, 0x35, 0x00 (General Call)
0x70
0x73
0
0x70, 0x74, 0x78, 0x7C
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SFR Definition 22.3. SMB0ADR: SMBus Slave Address
Bit
7
6
5
4
3
2
1
0
Name
SLV[6:0]
GC
Type
R/W
R/W
Reset
0
0
0
0
SFR Page = 0x0; SFR Address = 0xF4
Bit
Name
7 :1
SLV[6:0]
0
0
0
0
Function
SMBus Hardware Slave Address.
Defines the SMBus Slave Address(es) for automatic hardware acknowledgement.
Only address bits which have a 1 in the corresponding bit position in SLVM[6:0]
are checked against the incoming address. This allows multiple addresses to be
recognized.
0
GC
General Call Address Enable.
When hardware address recognition is enabled (EHACK = 1), this bit will determine whether the General Call Address (0x00) is also recognized by hardware.
0: General Call Address is ignored.
1: General Call Address is recognized.
SFR Definition 22.4. SMB0ADM: SMBus Slave Address Mask
Bit
7
6
5
4
3
2
1
0
Name
SLVM[6:0]
EHACK
Type
R/W
R/W
Reset
1
1
1
1
SFR Page = 0x0; SFR Address = 0xF5
Bit
Name
7 :1
SLVM[6:0]
1
1
1
0
Function
SMBus Slave Address Mask.
Defines which bits of register SMB0ADR are compared with an incoming address
byte, and which bits are ignored. Any bit set to 1 in SLVM[6:0] enables comparisons with the corresponding bit in SLV[6:0]. Bits set to 0 are ignored (can be either
0 or 1 in the incoming address).
0
EHACK
Hardware Acknowledge Enable.
Enables hardware acknowledgement of slave address and received data bytes.
0: Firmware must manually acknowledge all incoming address and data bytes.
1: Automatic Slave Address Recognition and Hardware Acknowledge is Enabled.
250
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22.4.4. Data Register
The SMBus Data register SMB0DAT holds a byte of serial data to be transmitted or one that has just been
received. Software may safely read or write to the data register when the SI flag is set. Software should not
attempt to access the SMB0DAT register when the SMBus is enabled and the SI flag is cleared to logic 0,
as the interface may be in the process of shifting a byte of data into or out of the register.
Data in SMB0DAT is always shifted out MSB first. After a byte has been received, the first bit of received
data is located at the MSB of SMB0DAT. While data is being shifted out, data on the bus is simultaneously
being shifted in. SMB0DAT always contains the last data byte present on the bus. In the event of lost
arbitration, the transition from master transmitter to slave receiver is made with the correct data or address
in SMB0DAT.
SFR Definition 22.5. SMB0DAT: SMBus Data
Bit
7
6
5
4
3
Name
SMB0DAT[7:0]
Type
R/W
Reset
0
0
0
0
SFR Page = 0x0; SFR Address = 0xC2
Bit
Name
0
2
1
0
0
0
0
Function
7:0 SMB0DAT[7:0] SMBus Data.
The SMB0DAT register contains a byte of data to be transmitted on the SMBus
serial interface or a byte that has just been received on the SMBus serial interface.
The CPU can read from or write to this register whenever the SI serial interrupt flag
(SMB0CN.0) is set to logic 1. The serial data in the register remains stable as long
as the SI flag is set. When the SI flag is not set, the system may be in the process
of shifting data in/out and the CPU should not attempt to access this register.
Rev. 1.3
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22.5. SMBus Transfer Modes
The SMBus interface may be configured to operate as master and/or slave. At any particular time, it will be
operating in one of the following four modes: Master Transmitter, Master Receiver, Slave Transmitter, or
Slave Receiver. The SMBus interface enters Master Mode any time a START is generated, and remains in
Master Mode until it loses an arbitration or generates a STOP. An SMBus interrupt is generated at the end
of all SMBus byte frames. Note that the position of the ACK interrupt when operating as a receiver
depends on whether hardware ACK generation is enabled. As a receiver, the interrupt for an ACK occurs
before the ACK with hardware ACK generation disabled, and after the ACK when hardware ACK
generation is enabled. As a transmitter, interrupts occur after the ACK, regardless of whether hardware
ACK generation is enabled or not.
22.5.1. Write Sequence (Master)
During a write sequence, an SMBus master writes data to a slave device. The master in this transfer will be
a transmitter during the address byte, and a transmitter during all data bytes. The SMBus interface
generates the START condition and transmits the first byte containing the address of the target slave and
the data direction bit. In this case the data direction bit (R/W) will be logic 0 (WRITE). The master then
transmits one or more bytes of serial data. After each byte is transmitted, an acknowledge bit is generated
by the slave. The transfer is ended when the STO bit is set and a STOP is generated. Note that the
interface will switch to Master Receiver Mode if SMB0DAT is not written following a Master Transmitter
interrupt. Figure 22.5 shows a typical master write sequence. Two transmit data bytes are shown, though
any number of bytes may be transmitted. All “data byte transferred” interrupts occur after the ACK cycle in
this mode, regardless of whether hardware ACK generation is enabled.
Interrupts with Hardware ACK Enabled (EHACK = 1)
S
SLA
W
A
Data Byte
A
Data Byte
A
Interrupts with Hardware ACK Disabled (EHACK = 0)
S = START
P = STOP
A = ACK
W = WRITE
SLA = Slave Address
Received by SMBus
Interface
Transmitted by
SMBus Interface
Figure 22.5. Typical Master Write Sequence
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C8051F93x-C8051F92x
22.5.2. Read Sequence (Master)
During a read sequence, an SMBus master reads data from a slave device. The master in this transfer will
be a transmitter during the address byte, and a receiver during all data bytes. The SMBus interface
generates the START condition and transmits the first byte containing the address of the target slave and
the data direction bit. In this case the data direction bit (R/W) will be logic 1 (READ). Serial data is then
received from the slave on SDA while the SMBus outputs the serial clock. The slave transmits one or more
bytes of serial data.
If hardware ACK generation is disabled, the ACKRQ is set to 1 and an interrupt is generated after each
received byte. Software must write the ACK bit at that time to ACK or NACK the received byte.
With hardware ACK generation enabled, the SMBus hardware will automatically generate the ACK/NACK,
and then post the interrupt. It is important to note that the appropriate ACK or NACK value should be
set up by the software prior to receiving the byte when hardware ACK generation is enabled.
Writing a 1 to the ACK bit generates an ACK; writing a 0 generates a NACK. Software should write a 0 to
the ACK bit for the last data transfer, to transmit a NACK. The interface exits Master Receiver Mode after
the STO bit is set and a STOP is generated. The interface will switch to Master Transmitter Mode if
SMB0DAT is written while an active Master Receiver. Figure 22.6 shows a typical master read sequence.
Two received data bytes are shown, though any number of bytes may be received. The “data byte
transferred” interrupts occur at different places in the sequence, depending on whether hardware ACK
generation is enabled. The interrupt occurs before the ACK with hardware ACK generation disabled, and
after the ACK when hardware ACK generation is enabled.
Interrupts with Hardware ACK Enabled (EHACK = 1)
S
SLA
R
A
Data Byte
A
Data Byte
N
P
Interrupts with Hardware ACK Disabled (EHACK = 0)
S = START
P = STOP
A = ACK
N = NACK
R = READ
SLA = Slave Address
Received by SMBus
Interface
Transmitted by
SMBus Interface
Figure 22.6. Typical Master Read Sequence
Rev. 1.3
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C8051F93x-C8051F92x
22.5.3. Write Sequence (Slave)
During a write sequence, an SMBus master writes data to a slave device. The slave in this transfer will be
a receiver during the address byte, and a receiver during all data bytes. When slave events are enabled
(INH = 0), the interface enters Slave Receiver Mode when a START followed by a slave address and
direction bit (WRITE in this case) is received. If hardware ACK generation is disabled, upon entering Slave
Receiver Mode, an interrupt is generated and the ACKRQ bit is set. The software must respond to the
received slave address with an ACK, or ignore the received slave address with a NACK. If hardware ACK
generation is enabled, the hardware will apply the ACK for a slave address which matches the criteria set
up by SMB0ADR and SMB0ADM. The interrupt will occur after the ACK cycle.
If the received slave address is ignored (by software or hardware), slave interrupts will be inhibited until the
next START is detected. If the received slave address is acknowledged, zero or more data bytes are
received.
If hardware ACK generation is disabled, the ACKRQ is set to 1 and an interrupt is generated after each
received byte. Software must write the ACK bit at that time to ACK or NACK the received byte.
With hardware ACK generation enabled, the SMBus hardware will automatically generate the ACK/NACK,
and then post the interrupt. The appropriate ACK or NACK value should be set up by the software
prior to receiving the byte when hardware ACK generation is enabled.
The interface exits Slave Receiver Mode after receiving a STOP. Note that the interface will switch to Slave
Transmitter Mode if SMB0DAT is written while an active Slave Receiver. Figure 22.7 shows a typical slave
write sequence. Two received data bytes are shown, though any number of bytes may be received. Notice
that the ‘data byte transferred’ interrupts occur at different places in the sequence, depending on whether
hardware ACK generation is enabled. The interrupt occurs before the ACK with hardware ACK generation
disabled, and after the ACK when hardware ACK generation is enabled.
Interrupts with Hardware ACK Enabled (EHACK = 1)
S
SLA
W
A
Data Byte
A
Data Byte
A
P
Interrupts with Hardware ACK Disabled (EHACK = 0)
S = START
P = STOP
A = ACK
W = WRITE
SLA = Slave Address
Received by SMBus
Interface
Transmitted by
SMBus Interface
Figure 22.7. Typical Slave Write Sequence
254
Rev. 1.3
C8051F93x-C8051F92x
22.5.4. Read Sequence (Slave)
During a read sequence, an SMBus master reads data from a slave device. The slave in this transfer will
be a receiver during the address byte, and a transmitter during all data bytes. When slave events are
enabled (INH = 0), the interface enters Slave Receiver Mode (to receive the slave address) when a START
followed by a slave address and direction bit (READ in this case) is received. If hardware ACK generation
is disabled, upon entering Slave Receiver Mode, an interrupt is generated and the ACKRQ bit is set. The
software must respond to the received slave address with an ACK, or ignore the received slave address
with a NACK. If hardware ACK generation is enabled, the hardware will apply the ACK for a slave address
which matches the criteria set up by SMB0ADR and SMB0ADM. The interrupt will occur after the ACK
cycle.
If the received slave address is ignored (by software or hardware), slave interrupts will be inhibited until the
next START is detected. If the received slave address is acknowledged, zero or more data bytes are
transmitted. If the received slave address is acknowledged, data should be written to SMB0DAT to be
transmitted. The interface enters Slave Transmitter Mode, and transmits one or more bytes of data. After
each byte is transmitted, the master sends an acknowledge bit; if the acknowledge bit is an ACK,
SMB0DAT should be written with the next data byte. If the acknowledge bit is a NACK, SMB0DAT should
not be written to before SI is cleared (an error condition may be generated if SMB0DAT is written following
a received NACK while in Slave Transmitter Mode). The interface exits Slave Transmitter Mode after
receiving a STOP. Note that the interface will switch to Slave Receiver Mode if SMB0DAT is not written
following a Slave Transmitter interrupt. Figure 22.8 shows a typical slave read sequence. Two transmitted
data bytes are shown, though any number of bytes may be transmitted. All of the “data byte transferred”
interrupts occur after the ACK cycle in this mode, regardless of whether hardware ACK generation is
enabled.
Interrupts with Hardware ACK Enabled (EHACK = 1)
S
SLA
R
A
Data Byte
A
Data Byte
N
P
Interrupts with Hardware ACK Disabled (EHACK = 0)
S = START
P = STOP
N = NACK
R = READ
SLA = Slave Address
Received by SMBus
Interface
Transmitted by
SMBus Interface
Figure 22.8. Typical Slave Read Sequence
22.6. SMBus Status Decoding
The current SMBus status can be easily decoded using the SMB0CN register. The appropriate actions to
take in response to an SMBus event depend on whether hardware slave address recognition and ACK
generation is enabled or disabled. Table 22.5 describes the typical actions when hardware slave address
recognition and ACK generation is disabled. Table 22.6 describes the typical actions when hardware slave
address recognition and ACK generation is enabled. In the tables, STATUS VECTOR refers to the four
upper bits of SMB0CN: MASTER, TXMODE, STA, and STO. The shown response options are only the
typical responses; application-specific procedures are allowed as long as they conform to the SMBus
specification. Highlighted responses are allowed by hardware but do not conform to the SMBus
specification.
Rev. 1.3
255
C8051F93x-C8051F92x
0
0
1100
0
1000
1
0
A master START was generated.
Load slave address + R/W into
SMB0DAT.
STO
ARBLOST
0 X
Typical Response Options
STA
ACKRQ
0
ACK
Status
Vector
Mode
Master Transmitter
Master Receiver
256
1110
Current SMbus State
0
0 X
1100
1
0 X
1110
0
1 X
-
Load next data byte into
SMB0DAT.
0
0 X
1100
End transfer with STOP.
0
1 X
-
1 X
-
0 X
1110
Switch to Master Receiver Mode
(clear SI without writing new data 0
to SMB0DAT).
0 X
1000
Acknowledge received byte;
Read SMB0DAT.
0
0
1
1000
Send NACK to indicate last byte,
0
and send STOP.
1
0
-
Send NACK to indicate last byte,
and send STOP followed by
1
START.
1
0
1110
Send ACK followed by repeated
START.
1
0
1
1110
Send NACK to indicate last byte,
1
and send repeated START.
0
0
1110
Send ACK and switch to Master
Transmitter Mode (write to
SMB0DAT before clearing SI).
0
0
1
1100
Send NACK and switch to Master Transmitter Mode (write to
SMB0DAT before clearing SI).
0
0
0
1100
A master data or address byte Set STA to restart transfer.
0 was transmitted; NACK
Abort transfer.
received.
A master data or address byte End transfer with STOP and start
1
another transfer.
1 was transmitted; ACK
received.
Send repeated START.
1
0 X
A master data byte was
received; ACK requested.
ACK
Values to
Write
Values Read
Next Status
Vector Expected
Table 22.5. SMBus Status Decoding With Hardware ACK Generation Disabled (EHACK = 0)
Rev. 1.3
C8051F93x-C8051F92x
Values to
Write
STA
STO
0
0
0
A slave byte was transmitted; No action required (expecting
NACK received.
STOP condition).
0
0 X
0001
0
0
1
A slave byte was transmitted; Load SMB0DAT with next data
ACK received.
byte to transmit.
0
0 X
0100
0
1 X
A Slave byte was transmitted; No action required (expecting
error detected.
Master to end transfer).
0
0 X
0001
0
0 X
-
0
0
1
0000
If Read, Load SMB0DAT with
0
data byte; ACK received address
0
1
0100
NACK received address.
0
0
0
-
If Write, Acknowledge received
address
0
0
1
0000
0
1
0100
0
0
-
0
1110
Current SMbus State
Typical Response Options
An illegal STOP or bus error
Clear STO.
0 X X was detected while a Slave
Transmission was in progress.
1
0 X
A slave address + R/W was
received; ACK requested.
Slave Receiver
0010
1
Bus Error Condition
0000
If Read, Load SMB0DAT with
Lost arbitration as master;
0
1 X slave address + R/W received; data byte; ACK received address
ACK requested.
NACK received address.
0
Reschedule failed transfer;
NACK received address.
1
0
Clear STO.
0
0 X
-
Lost arbitration while attempt- No action required (transfer
complete/aborted).
ing a STOP.
0
0
0
-
Acknowledge received byte;
Read SMB0DAT.
0
0
1
0000
NACK received byte.
0
0
0
-
0
0 X
-
1
0 X
1110
Abort failed transfer.
0
0 X
1110
0
A STOP was detected while
0 X addressed as a Slave Transmitter or Slave Receiver.
1
1 X
1
A slave byte was received;
0 X
ACK requested.
0001
If Write, Acknowledge received
address
ACK
ACK
0101
ARBLOST
Status
Vector
0100
ACKRQ
Slave Transmitter
Mode
Values Read
Next Status
Vector Expected
Table 22.5. SMBus Status Decoding With Hardware ACK Generation Disabled (EHACK = 0)
0010
0
1 X
Lost arbitration while attempt- Abort failed transfer.
ing a repeated START.
Reschedule failed transfer.
0001
0
1 X
Lost arbitration due to a
detected STOP.
Reschedule failed transfer.
1
0 X
0000
1
1 X
Lost arbitration while transmit- Abort failed transfer.
ting a data byte as master.
Reschedule failed transfer.
0
0
0
-
1
0
0
1110
Rev. 1.3
257
C8051F93x-C8051F92x
0
0
1100
0
Master Receiver
0
0
Load slave address + R/W into
SMB0DAT.
0
0
0 X
1100
1
0 X
1110
0
1 X
-
Load next data byte into
SMB0DAT.
0
0 X
1100
End transfer with STOP.
0
1 X
-
1 X
-
0 X
1110
0
1
1000
A master data or address byte Set STA to restart transfer.
0 was transmitted; NACK
Abort transfer.
received.
End transfer with STOP and start
A master data or address byte
1
another transfer.
1 was transmitted; ACK
Send repeated START.
1
received.
Switch to Master Receiver Mode
(clear SI without writing new data
0
to SMB0DAT). Set ACK for initial
data byte.
1
A master data byte was
received; ACK sent.
1000
0
258
0
A master START was generated.
STO
ARBLOST
0 X
Typical Response Options
STA
ACKRQ
0
ACK
Status
Vector
Mode
Master Transmitter
1110
Current SMbus State
A master data byte was
0 received; NACK sent (last
byte).
ACK
Values to
Write
Values Read
Next Status
Vector Expected
Table 22.6. SMBus Status Decoding With Hardware ACK Generation Enabled (EHACK = 1)
Set ACK for next data byte;
Read SMB0DAT.
0
0
1
1000
Set NACK to indicate next data
byte as the last data byte;
Read SMB0DAT.
0
0
0
1000
Initiate repeated START.
1
0
0
1110
Switch to Master Transmitter
Mode (write to SMB0DAT before 0
clearing SI).
0 X
1100
Read SMB0DAT; send STOP.
0
1
0
-
Read SMB0DAT; Send STOP
followed by START.
1
1
0
1110
Initiate repeated START.
1
0
0
1110
0 X
1100
Switch to Master Transmitter
Mode (write to SMB0DAT before 0
clearing SI).
Rev. 1.3
C8051F93x-C8051F92x
Values to
Write
STA
STO
0
0
0
A slave byte was transmitted; No action required (expecting
NACK received.
STOP condition).
0
0 X
0001
0
0
1
A slave byte was transmitted; Load SMB0DAT with next data
ACK received.
byte to transmit.
0
0 X
0100
0
1 X
A Slave byte was transmitted; No action required (expecting
error detected.
Master to end transfer).
0
0 X
0001
0
0 X
—
If Write, Set ACK for first data
byte.
0
0
1
0000
If Read, Load SMB0DAT with
data byte
0
0 X
0100
If Write, Set ACK for first data
byte.
0
0
1
0000
0
0 X
0100
Reschedule failed transfer
1
0 X
1110
Clear STO.
0
0 X
—
Lost arbitration while attempt- No action required (transfer
complete/aborted).
ing a STOP.
0
0
0
—
Set ACK for next data byte;
Read SMB0DAT.
0
0
1
0000
Set NACK for next data byte;
Read SMB0DAT.
0
0
0
0000
0
0 X
—
1
0 X
1110
Abort failed transfer.
0
0 X
—
Current SMbus State
Typical Response Options
An illegal STOP or bus error
Clear STO.
0 X X was detected while a Slave
Transmission was in progress.
0
0 X
A slave address + R/W was
received; ACK sent.
Slave Receiver
0010
0
Bus Error Condition
0
A STOP was detected while
0 X addressed as a Slave Transmitter or Slave Receiver.
0
1 X
0001
0000
Lost arbitration as master;
1 X slave address + R/W received; If Read, Load SMB0DAT with
data byte
ACK sent.
0
0 X A slave byte was received.
ACK
ACK
0101
ARBLOST
Status
Vector
0100
ACKRQ
Slave Transmitter
Mode
Values Read
Next Status
Vector Expected
Table 22.6. SMBus Status Decoding With Hardware ACK Generation Enabled (EHACK = 1)
0010
0
1 X
Lost arbitration while attempt- Abort failed transfer.
ing a repeated START.
Reschedule failed transfer.
0001
0
1 X
Lost arbitration due to a
detected STOP.
Reschedule failed transfer.
1
0 X
1110
0000
0
1 X
Lost arbitration while transmit- Abort failed transfer.
ting a data byte as master.
Reschedule failed transfer.
0
0 X
—
1
0 X
1110
Rev. 1.3
259
C8051F93x-C8051F92x
23. UART0
UART0 is an asynchronous, full duplex serial port offering modes 1 and 3 of the standard 8051 UART.
Enhanced baud rate support allows a wide range of clock sources to generate standard baud rates (details
in Section “23.1. Enhanced Baud Rate Generation” on page 261). Received data buffering allows UART0
to start reception of a second incoming data byte before software has finished reading the previous data
byte.
UART0 has two associated SFRs: Serial Control Register 0 (SCON0) and Serial Data Buffer 0 (SBUF0).
The single SBUF0 location provides access to both transmit and receive registers. Writes to SBUF0
always access the Transmit register. Reads of SBUF0 always access the buffered Receive register;
it is not possible to read data from the Transmit register.
With UART0 interrupts enabled, an interrupt is generated each time a transmit is completed (TI0 is set in
SCON0), or a data byte has been received (RI0 is set in SCON0). The UART0 interrupt flags are not
cleared by hardware when the CPU vectors to the interrupt service routine. They must be cleared manually
by software, allowing software to determine the cause of the UART0 interrupt (transmit complete or receive
complete).
SFR Bus
Write to
SBUF
TB8
SBUF
(TX Shift)
SET
D
Q
TX
CLR
Crossbar
Zero Detector
Stop Bit
Shift
Start
Data
Tx Control
Tx Clock
Send
Tx IRQ
TI
MCE
REN
TB8
RB8
TI
RI
SMODE
SCON
UART Baud
Rate Generator
RI
Serial
Port
Interrupt
Port I/O
Rx IRQ
Rx Clock
Rx Control
Start
Shift
0x1FF
RB8
Load
SBUF
Input Shift Register
(9 bits)
Load SBUF
SBUF
(RX Latch)
Read
SBUF
SFR Bus
RX
Crossbar
Figure 23.1. UART0 Block Diagram
260
Rev. 1.3
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23.1. Enhanced Baud Rate Generation
The UART0 baud rate is generated by Timer 1 in 8-bit auto-reload mode. The TX clock is generated by
TL1; the RX clock is generated by a copy of TL1 (shown as RX Timer in Figure 23.2), which is not useraccessible. Both TX and RX Timer overflows are divided by two to generate the TX and RX baud rates.
The RX Timer runs when Timer 1 is enabled, and uses the same reload value (TH1). However, an
RX Timer reload is forced when a START condition is detected on the RX pin. This allows a receive to
begin any time a START is detected, independent of the TX Timer state.
Timer 1
TL1
UART
Overflow
2
TX Clock
Overflow
2
RX Clock
TH1
Start
Detected
RX Timer
Figure 23.2. UART0 Baud Rate Logic
Timer 1 should be configured for Mode 2, 8-bit auto-reload (see Section “25.1.3. Mode 2: 8-bit Counter/Timer with Auto-Reload” on page 287). The Timer 1 reload value should be set so that overflows will
occur at two times the desired UART baud rate frequency. Note that Timer 1 may be clocked by one of six
sources: SYSCLK, SYSCLK / 4, SYSCLK / 12, SYSCLK / 48, the external oscillator clock / 8, or an external input T1. For any given Timer 1 clock source, the UART0 baud rate is determined by Equation 23.1-A
and Equation 23.1-B.
A)
1
UartBaudRate = ---  T1_Overflow_Rate
2
B)
T1 CLK
T1_Overflow_Rate = -------------------------256 – TH1
Equation 23.1. UART0 Baud Rate
Where T1CLK is the frequency of the clock supplied to Timer 1, and T1H is the high byte of Timer 1 (reload
value). Timer 1 clock frequency is selected as described in Section “25.1. Timer 0 and Timer 1” on
page 285. A quick reference for typical baud rates and system clock frequencies is given in Table 23.1
through Table 23.2. Note that the internal oscillator may still generate the system clock when the external
oscillator is driving Timer 1.
Rev. 1.3
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C8051F93x-C8051F92x
23.2. Operational Modes
UART0 provides standard asynchronous, full duplex communication. The UART mode (8-bit or 9-bit) is
selected by the S0MODE bit (SCON0.7). Typical UART connection options are shown below.
TX
RS-232
LEVEL
XLTR
RS-232
RX
C8051Fxxx
OR
TX
TX
RX
RX
MCU
C8051Fxxx
Figure 23.3. UART Interconnect Diagram
23.2.1. 8-Bit UART
8-Bit UART mode uses a total of 10 bits per data byte: one start bit, eight data bits (LSB first), and one stop
bit. Data are transmitted LSB first from the TX0 pin and received at the RX0 pin. On receive, the eight data
bits are stored in SBUF0 and the stop bit goes into RB80 (SCON0.2).
Data transmission begins when software writes a data byte to the SBUF0 register. The TI0 Transmit Interrupt Flag (SCON0.1) is set at the end of the transmission (the beginning of the stop-bit time). Data reception can begin any time after the REN0 Receive Enable bit (SCON0.4) is set to logic 1. After the stop bit is
received, the data byte will be loaded into the SBUF0 receive register if the following conditions are met:
RI0 must be logic 0, and if MCE0 is logic 1, the stop bit must be logic 1. In the event of a receive data overrun, the first received 8 bits are latched into the SBUF0 receive register and the following overrun data bits
are lost.
If these conditions are met, the eight bits of data is stored in SBUF0, the stop bit is stored in RB80 and the
RI0 flag is set. If these conditions are not met, SBUF0 and RB80 will not be loaded and the RI0 flag will not
be set. An interrupt will occur if enabled when either TI0 or RI0 is set.
MARK
SPACE
START
BIT
D0
D1
D2
D3
D4
D5
D6
BIT TIMES
BIT SAMPLING
Figure 23.4. 8-Bit UART Timing Diagram
262
Rev. 1.3
D7
STOP
BIT
C8051F93x-C8051F92x
23.2.2. 9-Bit UART
9-bit UART mode uses a total of eleven bits per data byte: a start bit, 8 data bits (LSB first), a programmable ninth data bit, and a stop bit. The state of the ninth transmit data bit is determined by the value in TB80
(SCON0.3), which is assigned by user software. It can be assigned the value of the parity flag (bit P in register PSW) for error detection, or used in multiprocessor communications. On receive, the ninth data bit
goes into RB80 (SCON0.2) and the stop bit is ignored.
Data transmission begins when an instruction writes a data byte to the SBUF0 register. The TI0 Transmit
Interrupt Flag (SCON0.1) is set at the end of the transmission (the beginning of the stop-bit time). Data
reception can begin any time after the REN0 Receive Enable bit (SCON0.4) is set to 1. After the stop bit is
received, the data byte will be loaded into the SBUF0 receive register if the following conditions are met:
(1) RI0 must be logic 0, and (2) if MCE0 is logic 1, the 9th bit must be logic 1 (when MCE0 is logic 0, the
state of the ninth data bit is unimportant). If these conditions are met, the eight bits of data are stored in
SBUF0, the ninth bit is stored in RB80, and the RI0 flag is set to 1. If the above conditions are not met,
SBUF0 and RB80 will not be loaded and the RI0 flag will not be set to 1. A UART0 interrupt will occur if
enabled when either TI0 or RI0 is set to 1.
MARK
SPACE
START
BIT
D0
D1
D2
D3
D4
D5
D6
D7
D8
STOP
BIT
BIT TIMES
BIT SAMPLING
Figure 23.5. 9-Bit UART Timing Diagram
23.3. Multiprocessor Communications
9-Bit UART mode supports multiprocessor communication between a master processor and one or more
slave processors by special use of the ninth data bit. When a master processor wants to transmit to one or
more slaves, it first sends an address byte to select the target(s). An address byte differs from a data byte
in that its ninth bit is logic 1; in a data byte, the ninth bit is always set to logic 0.
Setting the MCE0 bit (SCON0.5) of a slave processor configures its UART such that when a stop bit is
received, the UART will generate an interrupt only if the ninth bit is logic 1 (RB80 = 1) signifying an address
byte has been received. In the UART interrupt handler, software will compare the received address with
the slave's own assigned 8-bit address. If the addresses match, the slave will clear its MCE0 bit to enable
interrupts on the reception of the following data byte(s). Slaves that weren't addressed leave their MCE0
bits set and do not generate interrupts on the reception of the following data bytes, thereby ignoring the
data. Once the entire message is received, the addressed slave resets its MCE0 bit to ignore all transmissions until it receives the next address byte.
Multiple addresses can be assigned to a single slave and/or a single address can be assigned to multiple
slaves, thereby enabling "broadcast" transmissions to more than one slave simultaneously. The master
processor can be configured to receive all transmissions or a protocol can be implemented such that the
master/slave role is temporarily reversed to enable half-duplex transmission between the original master
and slave(s).
Rev. 1.3
263
C8051F93x-C8051F92x
Master
Device
RX
TX
Slave
Device
RX
TX
Slave
Device
RX
TX
Slave
Device
RX
TX
Figure 23.6. UART Multi-Processor Mode Interconnect Diagram
264
Rev. 1.3
V+
C8051F93x-C8051F92x
SFR Definition 23.1. SCON0: Serial Port 0 Control
Bit
7
6
Name
S0MODE
Type
R/W
Reset
0
5
4
3
2
1
0
MCE0
REN0
TB80
RB80
TI0
RI0
R
R/W
R/W
R/W
R/W
R/W
R/W
1
0
0
0
0
0
0
SFR Page = 0x0; SFR Address = 0x98; Bit-Addressable
Bit
7
6
5
Name
Function
S0MODE Serial Port 0 Operation Mode.
Selects the UART0 Operation Mode.
0: 8-bit UART with Variable Baud Rate.
1: 9-bit UART with Variable Baud Rate.
Unused Unused.
MCE0
Read = 1b. Write = Don’t Care.
Multiprocessor Communication Enable.
For Mode 0 (8-bit UART): Checks for valid stop bit.
0: Logic level of stop bit is ignored.
1: RI0 will only be activated if stop bit is logic level 1.
For Mode 1 (9-bit UART): Multiprocessor Communications Enable.
4
3
2
1
0
REN0
0: Logic level of ninth bit is ignored.
1: RI0 is set and an interrupt is generated only when the ninth bit is logic 1.
Receive Enable.
TB80
0: UART0 reception disabled.
1: UART0 reception enabled.
Ninth Transmission Bit.
RB80
The logic level of this bit will be sent as the ninth transmission bit in 9-bit UART Mode
(Mode 1). Unused in 8-bit mode (Mode 0).
Ninth Receive Bit.
TI0
RB80 is assigned the value of the STOP bit in Mode 0; it is assigned the value of the
9th data bit in Mode 1.
Transmit Interrupt Flag.
RI0
Set by hardware when a byte of data has been transmitted by UART0 (after the 8th bit
in 8-bit UART Mode, or at the beginning of the STOP bit in 9-bit UART Mode). When
the UART0 interrupt is enabled, setting this bit causes the CPU to vector to the UART0
interrupt service routine. This bit must be cleared manually by software.
Receive Interrupt Flag.
Set to 1 by hardware when a byte of data has been received by UART0 (set at the
STOP bit sampling time). When the UART0 interrupt is enabled, setting this bit to 1
causes the CPU to vector to the UART0 interrupt service routine. This bit must be
cleared manually by software.
Rev. 1.3
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C8051F93x-C8051F92x
SFR Definition 23.2. SBUF0: Serial (UART0) Port Data Buffer
Bit
7
6
5
4
3
2
1
0
SBUF0[7:0]
Name
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
SFR Page = 0x0; SFR Address = 0x99
Bit
Name
7:0
SBUF0
Function
Serial Data Buffer Bits 7:0 (MSB–LSB).
This SFR accesses two registers; a transmit shift register and a receive latch register.
When data is written to SBUF0, it goes to the transmit shift register and is held for
serial transmission. Writing a byte to SBUF0 initiates the transmission. A read of
SBUF0 returns the contents of the receive latch.
266
Rev. 1.3
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Table 23.1. Timer Settings for Standard Baud Rates
Using The Internal 24.5 MHz Oscillator
SYSCLK from
Internal Osc.
Frequency: 24.5 MHz
Target
Baud Rate
(bps)
Baud Rate
% Error
Oscillator Divide
Factor
Timer Clock
Source
SCA1–SCA0
(pre-scale
select)1
T1M1
Timer 1
Reload
Value (hex)
230400
–0.32%
106
SYSCLK
XX2
1
0xCB
115200
–0.32%
212
SYSCLK
XX
1
0x96
57600
0.15%
426
SYSCLK
XX
1
0x2B
28800
–0.32%
848
SYSCLK/4
01
0
0x96
14400
0.15%
1704
SYSCLK/12
00
0
0xB9
9600
–0.32%
2544
SYSCLK/12
00
0
0x96
2400
–0.32%
10176
SYSCLK/48
10
0
0x96
1200
0.15%
20448
SYSCLK/48
10
0
0x2B
SCA1–SCA0
(pre-scale
select)1
T1M1
Timer 1
Reload
Value (hex)
Notes:
1. SCA1–SCA0 and T1M bit definitions can be found in Section 25.1.
2. X = Don’t care.
Table 23.2. Timer Settings for Standard Baud Rates
Using an External 22.1184 MHz Oscillator
SYSCLK from
Internal Osc.
SYSCLK from
External Osc.
Frequency: 22.1184 MHz
Target
Baud Rate
(bps)
Baud Rate
% Error
Oscilla- Timer Clock
tor Divide
Source
Factor
230400
0.00%
96
SYSCLK
XX2
1
0xD0
115200
0.00%
192
SYSCLK
XX
1
0xA0
57600
0.00%
384
SYSCLK
XX
1
0x40
28800
0.00%
768
SYSCLK / 12
00
0
0xE0
14400
0.00%
1536
SYSCLK / 12
00
0
0xC0
9600
0.00%
2304
SYSCLK / 12
00
0
0xA0
2400
0.00%
9216
SYSCLK / 48
10
0
0xA0
1200
0.00%
18432
SYSCLK / 48
10
0
0x40
230400
0.00%
96
EXTCLK / 8
11
0
0xFA
115200
0.00%
192
EXTCLK / 8
11
0
0xF4
57600
0.00%
384
EXTCLK / 8
11
0
0xE8
28800
0.00%
768
EXTCLK / 8
11
0
0xD0
14400
0.00%
1536
EXTCLK / 8
11
0
0xA0
9600
0.00%
2304
EXTCLK / 8
11
0
0x70
Notes:
1. SCA1–SCA0 and T1M bit definitions can be found in Section 25.1.
2. X = Don’t care.
Rev. 1.3
267
C8051F93x-C8051F92x
24. Enhanced Serial Peripheral Interface (SPI0 and SPI1)
The Enhanced Serial Peripheral Interfaces (SPI0 and SPI1) provide access to two identical, flexible, fullduplex synchronous serial busses. Both SPI0 and SPI1 will be referred to collectively as SPIn. SPIn can
operate as a master or slave device in both 3-wire or 4-wire modes, and supports multiple masters and
slaves on a single SPI bus. The slave-select (NSS) signal can be configured as an input to select SPIn in
slave mode, or to disable Master Mode operation in a multi-master environment, avoiding contention on
the SPI bus when more than one master attempts simultaneous data transfers. NSS can also be
configured as a chip-select output in master mode, or disabled for 3-wire operation. Additional general
purpose port I/O pins can be used to select multiple slave devices in master mode.
SFR Bus
SYSCLK
SPInCN
SPIBSY
MSTEN
CKPHA
CKPOL
SLVSEL
NSSIN
SRMT
RXBMT
SPIFn
WCOLn
MODFn
RXOVRNn
NSSnMD1
NSSnMD0
TXBMTn
SPInEN
SPInCFG
SCR7
SCR6
SCR5
SCR4
SCR3
SCR2
SCR1
SCR0
SPInCKR
Clock Divide
Logic
SPI CONTROL LOGIC
Data Path
Control
SPIn IRQ
Pin Interface
Control
MOSI
Tx Data
SPInDAT
SCK
Transmit Data Buffer
Shift Register
Rx Data
7 6 5 4 3 2 1 0
Receive Data Buffer
Pin
Control
Logic
MISO
NSS
Read
SPI0DAT
Write
SPI0DAT
SFR Bus
Figure 24.1. SPI Block Diagram
268
Rev. 1.3
C
R
O
S
S
B
A
R
Port I/O
C8051F93x-C8051F92x
24.1. Signal Descriptions
The four signals used by each SPIn (MOSI, MISO, SCK, NSS) are described below.
24.1.1. Master Out, Slave In (MOSI)
The master-out, slave-in (MOSI) signal is an output from a master device and an input to slave devices. It
is used to serially transfer data from the master to the slave. This signal is an output when SPIn is operating as a master anSPInd an input when SPIn is operating as a slave. Data is transferred most-significant
bit first. When configured as a master, MOSI is driven by the MSB of the shift register in both 3- and 4-wire
mode.
24.1.2. Master In, Slave Out (MISO)
The master-in, slave-out (MISO) signal is an output from a slave device and an input to the master device.
It is used to serially transfer data from the slave to the master. This signal is an input when SPIn is operating as a master and an output when SPIn is operating as a slave. Data is transferred most-significant bit
first. The MISO pin is placed in a high-impedance state when the SPI module is disabled and when the SPI
operates in 4-wire mode as a slave that is not selected. When acting as a slave in 3-wire mode, MISO is
always driven by the MSB of the shift register.
24.1.3. Serial Clock (SCK)
The serial clock (SCK) signal is an output from the master device and an input to slave devices. It is used
to synchronize the transfer of data between the master and slave on the MOSI and MISO lines. SPIn generates this signal when operating as a master. The SCK signal is ignored by a SPI slave when the slave is
not selected (NSS = 1) in 4-wire slave mode.
24.1.4. Slave Select (NSS)
The function of the slave-select (NSS) signal is dependent on the setting of the NSSnMD1 and NSSnMD0
bits in the SPInCN register. There are three possible modes that can be selected with these bits:
1. NSSMD[1:0] = 00: 3-Wire Master or 3-Wire Slave Mode: SPIn operates in 3-wire mode, and
NSS is disabled. When operating as a slave device, SPIn is always selected in 3-wire mode.
Since no select signal is present, SPIn must be the only slave on the bus in 3-wire mode. This
is intended for point-to-point communication between a master and one slave.
2. NSSMD[1:0] = 01: 4-Wire Slave or Multi-Master Mode: SPIn operates in 4-wire mode, and
NSS is enabled as an input. When operating as a slave, NSS selects the SPIn device. When
operating as a master, a 1-to-0 transition of the NSS signal disables the master function of
SPIn so that multiple master devices can be used on the same SPI bus.
3. NSSMD[1:0] = 1x: 4-Wire Master Mode: SPIn operates in 4-wire mode, and NSS is enabled as
an output. The setting of NSSMD0 determines what logic level the NSS pin will output. This
configuration should only be used when operating SPIn as a master device.
See Figure 24.2, Figure 24.3, and Figure 24.4 for typical connection diagrams of the various operational
modes. Note that the setting of NSSMD bits affects the pinout of the device. When in 3-wire master or
3-wire slave mode, the NSS pin will not be mapped by the crossbar. In all other modes, the NSS signal will
be mapped to a pin on the device. See Section “21. Port Input/Output” on page 216 for general purpose
port I/O and crossbar information.
Rev. 1.3
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C8051F93x-C8051F92x
24.2. SPI Master Mode Operation
A SPI master device initiates all data transfers on a SPI bus. SPIn is placed in master mode by setting the
Master Enable flag (MSTENn, SPInCN.6). Writing a byte of data to the SPIn data register (SPInDAT) when
in master mode writes to the transmit buffer. If the SPI shift register is empty, the byte in the transmit buffer
is moved to the shift register, and a data transfer begins. The SPIn master immediately shifts out the data
serially on the MOSI line while providing the serial clock on SCK. The SPIFn (SPInCN.7) flag is set to logic
1 at the end of the transfer. If interrupts are enabled, an interrupt request is generated when the SPIF flag
is set. While the SPIn master transfers data to a slave on the MOSI line, the addressed SPI slave device
simultaneously transfers the contents of its shift register to the SPI master on the MISO line in a full-duplex
operation. Therefore, the SPIF flag serves as both a transmit-complete and receive-data-ready flag. The
data byte received from the slave is transferred MSB-first into the master's shift register. When a byte is
fully shifted into the register, it is moved to the receive buffer where it can be read by the processor by
reading SPInDAT.
When configured as a master, SPIn can operate in one of three different modes: multi-master mode, 3-wire
single-master mode, and 4-wire single-master mode. The default, multi-master mode is active when
NSSnMD1 (SPInCN.3) = 0 and NSSnMD0 (SPInCN.2) = 1. In this mode, NSS is an input to the device,
and is used to disable the master SPIn when another master is accessing the bus. When NSS is pulled low
in this mode, MSTENn (SPInCN.6) and SPIENn (SPInCN.0) are set to 0 to disable the SPI master device,
and a Mode Fault is generated (MODFn, SPInCN.5 = 1). Mode Fault will generate an interrupt if enabled.
SPIn must be manually re-enabled in software under these circumstances. In multi-master systems,
devices will typically default to being slave devices while they are not acting as the system master device.
In multi-master mode, slave devices can be addressed individually (if needed) using general-purpose I/O
pins. Figure 24.2 shows a connection diagram between two master devices in multiple-master mode.
3-wire single-master mode is active when NSSnMD1 (SPInCN.3) = 0 and NSSnMD0 (SPInCN.2) = 0. In
this mode, NSS is not used, and is not mapped to an external port pin through the crossbar. Any slave
devices that must be addressed in this mode should be selected using general-purpose I/O pins.
Figure 24.3 shows a connection diagram between a master device in 3-wire master mode and a slave
device.
4-wire single-master mode is active when NSSnMD1 (SPInCN.3) = 1. In this mode, NSS is configured as
an output pin, and can be used as a slave-select signal for a single SPI device. In this mode, the output
value of NSS is controlled (in software) with the bit NSSnMD0 (SPInCN.2). Additional slave devices can be
addressed using general-purpose I/O pins. Figure 24.4 shows a connection diagram for a master device in
4-wire master mode and two slave devices.
270
Rev. 1.3
C8051F93x-C8051F92x
Master
Device 1
NSS
GPIO
MISO
MISO
MOSI
MOSI
SCK
SCK
GPIO
NSS
Master
Device 2
Figure 24.2. Multiple-Master Mode Connection Diagram
Master
Device
MISO
MISO
MOSI
MOSI
SCK
SCK
Slave
Device
Figure 24.3. 3-Wire Single Master and 3-Wire Single Slave Mode Connection Diagram
Master
Device
GPIO
MISO
MISO
MOSI
MOSI
SCK
SCK
NSS
NSS
MISO
MOSI
Slave
Device
Slave
Device
SCK
NSS
Figure 24.4. 4-Wire Single Master Mode and 4-Wire Slave Mode Connection Diagram
Rev. 1.3
271
C8051F93x-C8051F92x
24.3. SPI Slave Mode Operation
When SPIn is enabled and not configured as a master, it will operate as a SPI slave. As a slave, bytes are
shifted in through the MOSI pin and out through the MISO pin by a master device controlling the SCK signal. A bit counter in the SPIn logic counts SCK edges. When 8 bits have been shifted through the shift register, the SPIF flag is set to logic 1, and the byte is copied into the receive buffer. Data is read from the
receive buffer by reading SPInDAT. A slave device cannot initiate transfers. Data to be transferred to the
master device is pre-loaded into the shift register by writing to SPInDAT. Writes to SPInDAT are doublebuffered, and are placed in the transmit buffer first. If the shift register is empty, the contents of the transmit
buffer will immediately be transferred into the shift register. When the shift register already contains data,
the SPI will load the shift register with the transmit buffer’s contents after the last SCK edge of the next (or
current) SPI transfer.
When configured as a slave, SPIn can be configured for 4-wire or 3-wire operation. The default, 4-wire
slave mode, is active when NSSnMD1 (SPInCN.3) = 0 and NSSnMD0 (SPInCN.2) = 1. In 4-wire mode, the
NSS signal is routed to a port pin and configured as a digital input. SPIn is enabled when NSS is logic 0,
and disabled when NSS is logic 1. The bit counter is reset on a falling edge of NSS. Note that the NSS signal must be driven low at least 2 system clocks before the first active edge of SCK for each byte transfer.
Figure 24.4 shows a connection diagram between two slave devices in 4-wire slave mode and a master
device.
3-wire slave mode is active when NSSnMD1 (SPInCN.3) = 0 and NSSnMD0 (SPInCN.2) = 0. NSS is not
used in this mode, and is not mapped to an external port pin through the crossbar. Since there is no way of
uniquely addressing the device in 3-wire slave mode, SPIn must be the only slave device present on the
bus. It is important to note that in 3-wire slave mode there is no external means of resetting the bit counter
that determines when a full byte has been received. The bit counter can only be reset by disabling and reenabling SPIn with the SPIEN bit. Figure 24.3 shows a connection diagram between a slave device in 3wire slave mode and a master device.
24.4. SPI Interrupt Sources
When SPIn interrupts are enabled, the following four flags will generate an interrupt when they are set to
logic 1:
All of the following bits must be cleared by software.
1. The SPI Interrupt Flag, SPIFn (SPInCN.7) is set to logic 1 at the end of each byte transfer.
This flag can occur in all SPIn modes.
2. The Write Collision Flag, WCOLn (SPInCN.6) is set to logic 1 if a write to SPInDAT is
attempted when the transmit buffer has not been emptied to the SPI shift register. When this
occurs, the write to SPInDAT will be ignored, and the transmit buffer will not be written.This
flag can occur in all SPIn modes.
3. The Mode Fault Flag MODFn (SPInCN.5) is set to logic 1 when SPIn is configured as a
master, and for multi-master mode and the NSS pin is pulled low. When a Mode Fault occurs,
the MSTENn and SPIENn bits in SPI0CN are set to logic 0 to disable SPIn and allow another
master device to access the bus.
4. The Receive Overrun Flag RXOVRNn (SPInCN.4) is set to logic 1 when configured as a slave,
and a transfer is completed and the receive buffer still holds an unread byte from a previous
transfer. The new byte is not transferred to the receive buffer, allowing the previously received
data byte to be read. The data byte which caused the overrun is lost.
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24.5. Serial Clock Phase and Polarity
Four combinations of serial clock phase and polarity can be selected using the clock control bits in the SPI
Configuration Register (SPInCFG). The CKPHA bit (SPInCFG.5) selects one of two clock phases (edge
used to latch the data). The CKPOL bit (SPInCFG.4) selects between an active-high or active-low clock.
Both master and slave devices must be configured to use the same clock phase and polarity. SPI0 should
be disabled (by clearing the SPIENn bit, SPInCN.0) when changing the clock phase or polarity. The clock
and data line relationships for master mode are shown in Figure 24.5. For slave mode, the clock and data
relationships are shown in Figure 24.6 and Figure 24.7. Note that CKPHA must be set to 0 on both the
master and slave SPI when communicating between two of the following devices: C8051F04x,
C8051F06x, C8051F12x, C8051F31x, C8051F32x, and C8051F33x.
The SPIn Clock Rate Register (SPInCKR) as shown in SFR Definition 24.3 controls the master mode
serial clock frequency. This register is ignored when operating in slave mode. When the SPI is configured
as a master, the maximum data transfer rate (bits/sec) is one-half the system clock frequency or 12.5 MHz,
whichever is slower. When the SPI is configured as a slave, the maximum data transfer rate (bits/sec) for
full-duplex operation is 1/10 the system clock frequency, provided that the master issues SCK, NSS (in 4wire slave mode), and the serial input data synchronously with the slave’s system clock. If the master
issues SCK, NSS, and the serial input data asynchronously, the maximum data transfer rate (bits/sec)
must be less than 1/10 the system clock frequency. In the special case where the master only wants to
transmit data to the slave and does not need to receive data from the slave (i.e. half-duplex operation), the
SPI slave can receive data at a maximum data transfer rate (bits/sec) of 1/4 the system clock frequency.
This is provided that the master issues SCK, NSS, and the serial input data synchronously with the slave’s
system clock.
SCK
(CKPOL=0, CKPHA=0)
SCK
(CKPOL=0, CKPHA=1)
SCK
(CKPOL=1, CKPHA=0)
SCK
(CKPOL=1, CKPHA=1)
MISO/MOSI
MSB
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
NSS (Must Remain High
in Multi-Master Mode)
Figure 24.5. Master Mode Data/Clock Timing
Rev. 1.3
273
C8051F93x-C8051F92x
SCK
(CKPOL=0, CKPHA=0)
SCK
(CKPOL=1, CKPHA=0)
MOSI
MSB
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
MISO
MSB
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
NSS (4-Wire Mode)
Figure 24.6. Slave Mode Data/Clock Timing (CKPHA = 0)
SCK
(CKPOL=0, CKPHA=1)
SCK
(CKPOL=1, CKPHA=1)
MOSI
MSB
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
MISO
MSB
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
NSS (4-Wire Mode)
Figure 24.7. Slave Mode Data/Clock Timing (CKPHA = 1)
274
Rev. 1.3
Bit 0
Bit 0
C8051F93x-C8051F92x
24.6. SPI Special Function Registers
SPI0 and SPI1 are accessed and controlled through four special function registers (8 registers total) in the
system controller: SPInCN Control Register, SPInDAT Data Register, SPInCFG Configuration Register,
and SPInCKR Clock Rate Register. The special function registers related to the operation of the SPI0 and
SPI1 Bus are described in the following figures.
Rev. 1.3
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SFR Definition 24.1. SPInCFG: SPI Configuration
Bit
7
6
5
4
3
2
1
0
Name
SPIBSY
MSTEN
CKPHA
CKPOL
SLVSEL
NSSIN
SRMT
RXBMT
Type
R
R/W
R/W
R/W
R
R
R
R
Reset
0
0
0
0
0
1
1
1
SFR Addresses: SPI0CFG = 0xA1, SPI1CFG = 0x84 
SFR Pages: SPI0CFG = 0x0, SPI1CFG = 0x0
Bit
Name
7
SPIBSY
Function
SPI Busy.
This bit is set to logic 1 when a SPI transfer is in progress (master or slave mode).
6
MSTEN
Master Mode Enable.
0: Disable master mode. Operate in slave mode.
1: Enable master mode. Operate as a master.
5
CKPHA
SPI Clock Phase.
0: Data centered on first edge of SCK period.*
1: Data centered on second edge of SCK period.*
4
CKPOL
SPI Clock Polarity.
0: SCK line low in idle state.
1: SCK line high in idle state.
3
SLVSEL
Slave Selected Flag.
Set to logic 1 whenever the NSS pin is low indicating SPI0 is the selected slave. It
is cleared to logic 0 when NSS is high (slave not selected). This bit does not indicate the instantaneous value at the NSS pin, but rather a de-glitched version of the
pin input.
2
NSSIN
NSS Instantaneous Pin Input.
This bit mimics the instantaneous value that is present on the NSS port pin at the
time that the register is read. This input is not de-glitched.
1
SRMT
Shift Register Empty (valid in slave mode only).
Set to logic 1 when data has been transferred in/out of the shift register, and there
is no data is available to read from the transmit buffer or write to the receive buffer.
Set to logic 0 when a data byte is transferred to the shift register from the transmit
buffer or by a transition on SCK. Note: SRMT = 1 in Master Mode.
0
RXBMT
Receive Buffer Empty (valid in slave mode only).
Set to logic 1 when the receive buffer has been read and contains no new information. If there is new information available in the receive buffer that has not been
read, this bit will return to logic 0. Note: RXBMT = 1 in Master Mode.
*Note: In slave mode, data on MOSI is sampled in the center of each data bit. In master mode, data on MISO is
sampled one SYSCLK before the end of each data bit, to provide maximum settling time for the slave device.
See Table 24.1 for timing parameters.
276
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SFR Definition 24.2. SPInCN: SPI Control
Bit
7
6
Name
SPIFn
Type
R/W
R/W
Reset
0
0
5
4
3
2
1
0
RXOVRNn
NSSnMD1
NSSnMD0
TXBMTn
SPInEN
R/W
R/W
R/W
R/W
R
R/W
0
0
0
1
1
0
WCOLn MODFn
SFR Addresses: SPI0CN = 0xF8, Bit-Addressable; SPI1CN = 0xB0, Bit-Addressable
SFR Pages: SPI0CN = 0x0, SPI1CN = 0x0
Bit
Name
Function
7
SPIFn
SPIn Interrupt Flag.
This bit is set to logic 1 by hardware at the end of a data transfer. If interrupts are
enabled, setting this bit causes the CPU to vector to the SPIn interrupt service
routine. This bit is not automatically cleared by hardware. It must be cleared by
software.
6
WCOLn
Write Collision Flag.
This bit is set to logic 1 by hardware (and generates a SPI0 interrupt) to indicate a
write to the SPI0 data register was attempted while a data transfer was in progress.
It must be cleared by software.
5
MODFn
Mode Fault Flag.
This bit is set to logic 1 by hardware (and generates a SPI0 interrupt) when a master mode collision is detected (NSS is low, MSTEN = 1, and NSSMD[1:0] = 01).
This bit is not automatically cleared by hardware. It must be cleared by software.
4
RXOVRNn
Receive Overrun Flag (valid in slave mode only).
This bit is set to logic 1 by hardware (and generates a SPIn interrupt) when the
receive buffer still holds unread data from a previous transfer and the last bit of the
current transfer is shifted into the SPI shift register. This bit is not automatically
cleared by hardware. It must be cleared by software.
3:2
NSSnMD[1:0] Slave Select Mode.
Selects between the following NSS operation modes:
(See Section 24.2 and Section 24.3).
00: 3-Wire Slave or 3-Wire Master Mode. NSS signal is not routed to a port pin.
01: 4-Wire Slave or Multi-Master Mode (Default). NSS is an input to the device.
1x: 4-Wire Single-Master Mode. NSS signal is mapped as an output from the
device and will assume the value of NSSMD0.
1
TXBMTn
Transmit Buffer Empty.
This bit will be set to logic 0 when new data has been written to the transmit buffer.
When data in the transmit buffer is transferred to the SPI shift register, this bit will
be set to logic 1, indicating that it is safe to write a new byte to the transmit buffer.
0
SPInEN
SPIn Enable.
0: SPIn disabled.
1: SPIn enabled.
Rev. 1.3
277
C8051F93x-C8051F92x
SFR Definition 24.3. SPInCKR: SPI Clock Rate
Bit
7
6
5
4
3
Name
SCRn[7:0]
Type
R/W
Reset
0
0
0
0
SFR Addresses: SPI0CKR = 0xA2, SPI1CKR = 0x85 
SFR Pages: SPI0CKR = 0x0, SPI1CKR = 0x0
Bit
Name
7:0
SCRn
0
2
1
0
0
0
0
Function
SPI Clock Rate.
These bits determine the frequency of the SCK output when the SPI module is
configured for master mode operation. The SCK clock frequency is a divided
version of the system clock, and is given in the following equation, where SYSCLK
is the system clock frequency and SPInCKR is the 8-bit value held in the SPInCKR
register.
SYSCLK
f SCK = ----------------------------------------------------------2   SPInCKR[7:0] + 1 
for 0 <= SPI0CKR <= 255
Example: If SYSCLK = 2 MHz and SPInCKR = 0x04,
2000000
f SCK = -------------------------2  4 + 1
f SCK = 200kHz
278
Rev. 1.3
C8051F93x-C8051F92x
SFR Definition 24.4. SPInDAT: SPI Data
Bit
7
6
5
4
3
Name
SPInDAT[7:0]
Type
R/W
Reset
0
0
0
0
SFR Addresses: SPI0DAT = 0xA3, SPI1DAT = 0x86 
SFR Pages: SPI0DAT = 0x0, SPI1DAT = 0x0
Bit
Name
7:0
SPInDAT
0
2
1
0
0
0
0
Function
SPIn Transmit and Receive Data.
The SPInDAT register is used to transmit and receive SPIn data. Writing data to
SPInDAT places the data into the transmit buffer and initiates a transfer when in
Master Mode. A read of SPInDAT returns the contents of the receive buffer.
Rev. 1.3
279
C8051F93x-C8051F92x
SCK*
T
T
MCKH
MCKL
T
T
MIS
MIH
MISO
MOSI
* SCK is shown for CKPOL = 0. SCK is the opposite polarity for CKPOL = 1.
Figure 24.8. SPI Master Timing (CKPHA = 0)
SCK*
T
T
MCKH
MCKL
T
T
MIS
MIH
MISO
MOSI
* SCK is shown for CKPOL = 0. SCK is the opposite polarity for CKPOL = 1.
Figure 24.9. SPI Master Timing (CKPHA = 1)
280
Rev. 1.3
C8051F93x-C8051F92x
NSS
T
T
SE
T
CKL
SD
SCK*
T
CKH
T
SIS
T
SIH
MOSI
T
T
SEZ
T
SOH
SDZ
MISO
* SCK is shown for CKPOL = 0. SCK is the opposite polarity for CKPOL = 1.
Figure 24.10. SPI Slave Timing (CKPHA = 0)
NSS
T
T
SE
T
CKL
SD
SCK*
T
CKH
T
SIS
T
SIH
MOSI
T
SEZ
T
T
SOH
SLH
T
SDZ
MISO
* SCK is shown for CKPOL = 0. SCK is the opposite polarity for CKPOL = 1.
Figure 24.11. SPI Slave Timing (CKPHA = 1)
Rev. 1.3
281
C8051F93x-C8051F92x
Table 24.1. SPI Slave Timing Parameters
Parameter
Description
Min
Max
Units
Master Mode Timing* (See Figure 24.8 and Figure 24.9)
TMCKH
SCK High Time
1 x TSYSCLK
—
ns
TMCKL
SCK Low Time
1 x TSYSCLK
—
ns
TMIS
MISO Valid to SCK Shift Edge
1 x TSYSCLK + 20
—
ns
TMIH
SCK Shift Edge to MISO Change
0
—
ns
Slave Mode Timing* (See Figure 24.10 and Figure 24.11)
TSE
NSS Falling to First SCK Edge
2 x TSYSCLK
—
ns
TSD
Last SCK Edge to NSS Rising
2 x TSYSCLK
—
ns
TSEZ
NSS Falling to MISO Valid
—
4 x TSYSCLK
ns
TSDZ
NSS Rising to MISO High-Z
—
4 x TSYSCLK
ns
TCKH
SCK High Time
5 x TSYSCLK
—
ns
TCKL
SCK Low Time
5 x TSYSCLK
—
ns
TSIS
MOSI Valid to SCK Sample Edge
2 x TSYSCLK
—
ns
TSIH
SCK Sample Edge to MOSI Change
2 x TSYSCLK
—
ns
TSOH
SCK Shift Edge to MISO Change
—
4 x TSYSCLK
ns
TSLH
Last SCK Edge to MISO Change 
(CKPHA = 1 ONLY)
6 x TSYSCLK
8 x TSYSCLK
ns
*Note: TSYSCLK is equal to one period of the device system clock (SYSCLK).
282
Rev. 1.3
C8051F93x-C8051F92x
25. Timers
Each MCU includes four counter/timers: two are 16-bit counter/timers compatible with those found in the
standard 8051, and two are 16-bit auto-reload timer for use with the ADC, SMBus, or for general purpose
use. These timers can be used to measure time intervals, count external events and generate periodic
interrupt requests. Timer 0 and Timer 1 are nearly identical and have four primary modes of operation.
Timer 2 and Timer 3 offer 16-bit and split 8-bit timer functionality with auto-reload. Additionally, Timer 2 and
Timer 3 have a Capture Mode that can be used to measure the SmaRTClock or a Comparator period with
respect to another oscillator. This is particularly useful when using Capacitive Touch Switches.
Timer 0 and Timer 1 Modes:
13-bit counter/timer
16-bit counter/timer
8-bit counter/timer with autoreload
Two 8-bit counter/timers (Timer 0
only)
Timer 2 Modes:
Timer 3 Modes:
16-bit timer with auto-reload
16-bit timer with auto-reload
Two 8-bit timers with auto-reload
Two 8-bit timers with auto-reload
Timers 0 and 1 may be clocked by one of five sources, determined by the Timer Mode Select bits (T1M–
T0M) and the Clock Scale bits (SCA1–SCA0). The Clock Scale bits define a pre-scaled clock from which
Timer 0 and/or Timer 1 may be clocked (See SFR Definition 25.1 for pre-scaled clock selection).
Timer 0/1 may then be configured to use this pre-scaled clock signal or the system clock. Timer 2 and
Timer 3 may be clocked by the system clock, the system clock divided by 12. Timer 2 may additionally be
clocked by the SmaRTClock divided by 8 or the Comparator0 output. Timer 3 may additionally be clocked
by the external oscillator clock source divided by 8 or the Comparator1 output.
Timer 0 and Timer 1 may also be operated as counters. When functioning as a counter, a counter/timer
register is incremented on each high-to-low transition at the selected input pin (T0 or T1). Events with a frequency of up to one-fourth the system clock frequency can be counted. The input signal need not be periodic, but it should be held at a given level for at least two full system clock cycles to ensure the level is
properly sampled.
Rev. 1.3
283
C8051F93x-C8051F92x
SFR Definition 25.1. CKCON: Clock Control
Bit
7
6
5
4
3
2
Name
T3MH
T3ML
T2MH
T2ML
T1M
T0M
SCA[1:0]
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
SFR Page = 0x0; SFR Address = 0x8E
Bit
Name
7
T3MH
1
0
0
0
Function
Timer 3 High Byte Clock Select.
Selects the clock supplied to the Timer 3 high byte (split 8-bit timer mode only).
0: Timer 3 high byte uses the clock defined by the T3XCLK bit in TMR3CN.
1: Timer 3 high byte uses the system clock.
6
T3ML
Timer 3 Low Byte Clock Select.
Selects the clock supplied to Timer 3. Selects the clock supplied to the lower 8-bit timer
in split 8-bit timer mode.
0: Timer 3 low byte uses the clock defined by the T3XCLK bit in TMR3CN.
1: Timer 3 low byte uses the system clock.
5
T2MH
Timer 2 High Byte Clock Select.
Selects the clock supplied to the Timer 2 high byte (split 8-bit timer mode only).
0: Timer 2 high byte uses the clock defined by the T2XCLK bit in TMR2CN.
1: Timer 2 high byte uses the system clock.
4
T2ML
Timer 2 Low Byte Clock Select.
Selects the clock supplied to Timer 2. If Timer 2 is configured in split 8-bit timer mode,
this bit selects the clock supplied to the lower 8-bit timer.
0: Timer 2 low byte uses the clock defined by the T2XCLK bit in TMR2CN.
1: Timer 2 low byte uses the system clock.
3
T1M
Timer 1 Clock Select.
Selects the clock source supplied to Timer 1. Ignored when C/T1 is set to 1.
0: Timer 1 uses the clock defined by the prescale bits SCA[1:0].
1: Timer 1 uses the system clock.
2
T0M
Timer 0 Clock Select.
Selects the clock source supplied to Timer 0. Ignored when C/T0 is set to 1.
0: Counter/Timer 0 uses the clock defined by the prescale bits SCA[1:0].
1: Counter/Timer 0 uses the system clock.
1:0
SCA[1:0] Timer 0/1 Prescale Bits.
These bits control the Timer 0/1 Clock Prescaler:
00: System clock divided by 12
01: System clock divided by 4
10: System clock divided by 48
11: External clock divided by 8 (synchronized with the system clock)
284
Rev. 1.3
C8051F93x-C8051F92x
25.1. Timer 0 and Timer 1
Each timer is implemented as a 16-bit register accessed as two separate bytes: a low byte (TL0 or TL1)
and a high byte (TH0 or TH1). The Counter/Timer Control register (TCON) is used to enable Timer 0 and
Timer 1 as well as indicate status. Timer 0 interrupts can be enabled by setting the ET0 bit in the IE
register (Section “12.5. Interrupt Register Descriptions” on page 139); Timer 1 interrupts can be enabled
by setting the ET1 bit in the IE register (Section “12.5. Interrupt Register Descriptions” on page 139). Both
counter/timers operate in one of four primary modes selected by setting the Mode Select bits T1M1–T0M0
in the Counter/Timer Mode register (TMOD). Each timer can be configured independently. Each operating
mode is described below.
25.1.1. Mode 0: 13-bit Counter/Timer
Timer 0 and Timer 1 operate as 13-bit counter/timers in Mode 0. The following describes the configuration
and operation of Timer 0. However, both timers operate identically, and Timer 1 is configured in the same
manner as described for Timer 0.
The TH0 register holds the eight MSBs of the 13-bit counter/timer. TL0 holds the five LSBs in bit positions
TL0.4–TL0.0. The three upper bits of TL0 (TL0.7–TL0.5) are indeterminate and should be masked out or
ignored when reading. As the 13-bit timer register increments and overflows from 0x1FFF (all ones) to
0x0000, the timer overflow flag TF0 (TCON.5) is set and an interrupt will occur if Timer 0 interrupts are
enabled.
The C/T0 bit (TMOD.2) selects the counter/timer's clock source. When C/T0 is set to logic 1, high-to-low
transitions at the selected Timer 0 input pin (T0) increment the timer register (Refer to Section
“21.3. Priority Crossbar Decoder” on page 221 for information on selecting and configuring external I/O
pins). Clearing C/T selects the clock defined by the T0M bit (CKCON.3). When T0M is set, Timer 0 is
clocked by the system clock. When T0M is cleared, Timer 0 is clocked by the source selected by the Clock
Scale bits in CKCON (see SFR Definition 25.1).
Setting the TR0 bit (TCON.4) enables the timer when either GATE0 (TMOD.3) is logic 0 or the input signal
INT0 is active as defined by bit IN0PL in register IT01CF (see SFR Definition 12.7). Setting GATE0 to 1
allows the timer to be controlled by the external input signal INT0 (see Section “12.5. Interrupt Register
Descriptions” on page 139), facilitating pulse width measurements
Table 25.1. Timer 0 Running Modes
TR0
GATE0
INT0
Counter/Timer
0
X
X
Disabled
1
0
X
Enabled
1
1
0
Disabled
1
1
1
Enabled
Note: X = Don't Care
Setting TR0 does not force the timer to reset. The timer registers should be loaded with the desired initial
value before the timer is enabled.
TL1 and TH1 form the 13-bit register for Timer 1 in the same manner as described above for TL0 and TH0.
Timer 1 is configured and controlled using the relevant TCON and TMOD bits just as with Timer 0. The
input signal INT1 is used with Timer 1; the INT1 polarity is defined by bit IN1PL in register IT01CF (see
SFR Definition 12.7).
Rev. 1.3
285
C8051F93x-C8051F92x
CKCON
T
3
M
H
P re -s ca le d C lo c k
0
SYSCLK
1
T
3
M
L
T
2
M
H
TM OD
T T T S S
2 1 0 C C
MMM A A
1 0
L
G
A
T
E
1
C
/
T
1
T
1
M
1
T
1
M
0
G
A
T
E
0
C
/
T
0
IT 0 1 C F
T
0
M
1
T
0
M
0
I
N
1
P
L
I
N
1
S
L
2
I
N
1
S
L
1
I
N
1
S
L
0
I
N
0
P
L
I
N
0
S
L
2
I
N
0
S
L
1
I
N
0
S
L
0
0
1
TCLK
TR0
C ro ss b a r
IN T 0
TL0
(5 b its )
TH0
(8 b its)
G ATE0
IN 0 P L
TCON
T0
TF1
TR1
TF0
TR0
IE 1
IT 1
IE 0
IT 0
Inte rru pt
XOR
Figure 25.1. T0 Mode 0 Block Diagram
25.1.2. Mode 1: 16-bit Counter/Timer
Mode 1 operation is the same as Mode 0, except that the counter/timer registers use all 16 bits. The
counter/timers are enabled and configured in Mode 1 in the same manner as for Mode 0.
286
Rev. 1.3
C8051F93x-C8051F92x
25.1.3. Mode 2: 8-bit Counter/Timer with Auto-Reload
Mode 2 configures Timer 0 and Timer 1 to operate as 8-bit counter/timers with automatic reload of the start
value. TL0 holds the count and TH0 holds the reload value. When the counter in TL0 overflows from all
ones to 0x00, the timer overflow flag TF0 (TCON.5) is set and the counter in TL0 is reloaded from TH0. If
Timer 0 interrupts are enabled, an interrupt will occur when the TF0 flag is set. The reload value in TH0 is
not changed. TL0 must be initialized to the desired value before enabling the timer for the first count to be
correct. When in Mode 2, Timer 1 operates identically to Timer 0.
Both counter/timers are enabled and configured in Mode 2 in the same manner as Mode 0. Setting the
TR0 bit (TCON.4) enables the timer when either GATE0 (TMOD.3) is logic 0 or when the input signal INT0
is active as defined by bit IN0PL in register IT01CF (see Section “12.6. External Interrupts INT0 and INT1”
on page 146 for details on the external input signals INT0 and INT1).
CKCON
T T T T T T S
3 3 2 2 1 0 C
MMMMMMA
H L H L
1
Pre-scaled Clock
TMOD
S
C
A
0
G
A
T
E
1
C
/
T
1
T
1
M
1
T
1
M
0
G
A
T
E
0
C
/
T
0
IT01CF
T
0
M
1
T
0
M
0
I
N
1
P
L
I
N
1
S
L
2
I
N
1
S
L
1
I
N
1
S
L
0
I
N
0
P
L
I
N
0
S
L
2
I
N
0
S
L
1
I
N
0
S
L
0
0
0
SYSCLK
1
1
T0
TL0
(8 bits)
TCON
TCLK
TR0
Crossbar
GATE0
TH0
(8 bits)
INT0
IN0PL
TF1
TR1
TF0
TR0
IE1
IT1
IE0
IT0
Interrupt
Reload
XOR
Figure 25.2. T0 Mode 2 Block Diagram
Rev. 1.3
287
C8051F93x-C8051F92x
25.1.4. Mode 3: Two 8-bit Counter/Timers (Timer 0 Only)
In Mode 3, Timer 0 is configured as two separate 8-bit counter/timers held in TL0 and TH0. The
counter/timer in TL0 is controlled using the Timer 0 control/status bits in TCON and TMOD: TR0, C/T0,
GATE0 and TF0. TL0 can use either the system clock or an external input signal as its timebase. The TH0
register is restricted to a timer function sourced by the system clock or prescaled clock. TH0 is enabled
using the Timer 1 run control bit TR1. TH0 sets the Timer 1 overflow flag TF1 on overflow and thus controls
the Timer 1 interrupt.
Timer 1 is inactive in Mode 3. When Timer 0 is operating in Mode 3, Timer 1 can be operated in Modes 0,
1 or 2, but cannot be clocked by external signals nor set the TF1 flag and generate an interrupt. However,
the Timer 1 overflow can be used to generate baud rates for the SMBus and/or UART, and/or initiate ADC
conversions. While Timer 0 is operating in Mode 3, Timer 1 run control is handled through its mode
settings. To run Timer 1 while Timer 0 is in Mode 3, set the Timer 1 Mode as 0, 1, or 2. To disable Timer 1,
configure it for Mode 3.
CKCO N
T T T T T T
3 3 2 2 1 0
MMMMMM
H L H L
Pre-scaled Clock
TM O D
S
C
A
1
S
C
A
0
G
A
T
E
1
C
/
T
1
T
1
M
1
T
1
M
0
G
A
T
E
0
C
/
T
0
T
0
M
1
T
0
M
0
0
TR1
1
0
TCON
SYSCLK
TH0
(8 bits)
1
T0
TL0
(8 bits)
TR0
Crossbar
INT0
G ATE0
IN0PL
XOR
Figure 25.3. T0 Mode 3 Block Diagram
288
Rev. 1.3
TF1
TR1
TF0
TR0
IE1
IT1
IE0
IT0
Interrupt
Interrupt
C8051F93x-C8051F92x
SFR Definition 25.2. TCON: Timer Control
Bit
7
6
5
4
3
2
1
0
Name
TF1
TR1
TF0
TR0
IE1
IT1
IE0
IT0
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
SFR Page = 0x0; SFR Address = 0x88; Bit-Addressable
Bit
Name
Function
7
TF1
Timer 1 Overflow Flag.
Set to 1 by hardware when Timer 1 overflows. This flag can be cleared by software
but is automatically cleared when the CPU vectors to the Timer 1 interrupt service
routine.
6
TR1
Timer 1 Run Control.
Timer 1 is enabled by setting this bit to 1.
5
TF0
Timer 0 Overflow Flag.
Set to 1 by hardware when Timer 0 overflows. This flag can be cleared by software
but is automatically cleared when the CPU vectors to the Timer 0 interrupt service
routine.
4
TR0
Timer 0 Run Control.
Timer 0 is enabled by setting this bit to 1.
3
IE1
External Interrupt 1.
This flag is set by hardware when an edge/level of type defined by IT1 is detected. It
can be cleared by software but is automatically cleared when the CPU vectors to the
External Interrupt 1 service routine in edge-triggered mode.
2
IT1
Interrupt 1 Type Select.
This bit selects whether the configured INT1 interrupt will be edge or level sensitive.
INT1 is configured active low or high by the IN1PL bit in the IT01CF register (see
SFR Definition 12.7).
0: INT1 is level triggered.
1: INT1 is edge triggered.
1
IE0
External Interrupt 0.
This flag is set by hardware when an edge/level of type defined by IT1 is detected. It
can be cleared by software but is automatically cleared when the CPU vectors to the
External Interrupt 0 service routine in edge-triggered mode.
0
IT0
Interrupt 0 Type Select.
This bit selects whether the configured INT0 interrupt will be edge or level sensitive.
INT0 is configured active low or high by the IN0PL bit in register IT01CF (see SFR
Definition 12.7).
0: INT0 is level triggered.
1: INT0 is edge triggered.
Rev. 1.3
289
C8051F93x-C8051F92x
SFR Definition 25.3. TMOD: Timer Mode
Bit
7
6
Name
GATE1
C/T1
Type
R/W
R/W
Reset
0
0
5
4
3
2
T1M[1:0]
GATE0
C/T0
T0M[1:0]
R/W
R/W
R/W
R/W
0
0
0
0
SFR Page = 0x0; SFR Address = 0x89
Bit
Name
7
GATE1
1
0
0
0
Function
Timer 1 Gate Control.
0: Timer 1 enabled when TR1 = 1 irrespective of INT1 logic level.
1: Timer 1 enabled only when TR1 = 1 AND INT1 is active as defined by bit IN1PL in
register IT01CF (see SFR Definition 12.7).
6
C/T1
Counter/Timer 1 Select.
0: Timer: Timer 1 incremented by clock defined by T1M bit in register CKCON.
1: Counter: Timer 1 incremented by high-to-low transitions on external pin (T1).
5:4
T1M[1:0]
Timer 1 Mode Select.
These bits select the Timer 1 operation mode.
00: Mode 0, 13-bit Counter/Timer
01: Mode 1, 16-bit Counter/Timer
10: Mode 2, 8-bit Counter/Timer with Auto-Reload
11: Mode 3, Timer 1 Inactive
3
GATE0
Timer 0 Gate Control.
0: Timer 0 enabled when TR0 = 1 irrespective of INT0 logic level.
1: Timer 0 enabled only when TR0 = 1 AND INT0 is active as defined by bit IN0PL in
register IT01CF (see SFR Definition 12.7).
2
C/T0
Counter/Timer 0 Select.
0: Timer: Timer 0 incremented by clock defined by T0M bit in register CKCON.
1: Counter: Timer 0 incremented by high-to-low transitions on external pin (T0).
1:0
T0M[1:0]
Timer 0 Mode Select.
These bits select the Timer 0 operation mode.
00: Mode 0, 13-bit Counter/Timer
01: Mode 1, 16-bit Counter/Timer
10: Mode 2, 8-bit Counter/Timer with Auto-Reload
11: Mode 3, Two 8-bit Counter/Timers
290
Rev. 1.3
C8051F93x-C8051F92x
SFR Definition 25.4. TL0: Timer 0 Low Byte
Bit
7
6
5
4
Name
TL0[7:0]
Type
R/W
Reset
0
0
0
0
SFR Page = 0x0; SFR Address = 0x8A
Bit
Name
7:0
TL0[7:0]
3
2
1
0
0
0
0
0
3
2
1
0
0
0
0
0
Function
Timer 0 Low Byte.
The TL0 register is the low byte of the 16-bit Timer 0.
SFR Definition 25.5. TL1: Timer 1 Low Byte
Bit
7
6
5
4
Name
TL1[7:0]
Type
R/W
Reset
0
0
0
0
SFR Page = 0x0; SFR Address = 0x8B
Bit
Name
7:0
TL1[7:0]
Function
Timer 1 Low Byte.
The TL1 register is the low byte of the 16-bit Timer 1.
Rev. 1.3
291
C8051F93x-C8051F92x
SFR Definition 25.6. TH0: Timer 0 High Byte
Bit
7
6
5
4
Name
TH0[7:0]
Type
R/W
Reset
0
0
0
0
SFR Page = 0x0; SFR Address = 0x8C
Bit
Name
7:0
TH0[7:0]
3
2
1
0
0
0
0
0
Function
Timer 0 High Byte.
The TH0 register is the high byte of the 16-bit Timer 0.
SFR Definition 25.7. TH1: Timer 1 High Byte
Bit
7
6
5
4
Name
TH1[7:0]
Type
R/W
Reset
0
0
0
0
SFR Page = 0x0; SFR Address = 0x8D
Bit
Name
7:0
TH1[7:0]
3
2
1
0
0
0
0
0
Function
Timer 1 High Byte.
The TH1 register is the high byte of the 16-bit Timer 1.
292
Rev. 1.3
C8051F93x-C8051F92x
25.2. Timer 2
Timer 2 is a 16-bit timer formed by two 8-bit SFRs: TMR2L (low byte) and TMR2H (high byte). Timer 2 may
operate in 16-bit auto-reload mode or (split) 8-bit auto-reload mode. The T2SPLIT bit (TMR2CN.3) defines
the Timer 2 operation mode. Timer 2 can also be used in Capture Mode to measure the SmaRTClock or
the Comparator 0 period with respect to another oscillator. The ability to measure the Comparator 0 period
with respect to the system clock is makes using Touch Sense Switches very easy.
Timer 2 may be clocked by the system clock, the system clock divided by 12, SmaRTClock divided by 8, or
Comparator 0 output. Note that the SmaRTClock divided by 8 and Comparator 0 output is synchronized
with the system clock.
25.2.1. 16-bit Timer with Auto-Reload
When T2SPLIT (TMR2CN.3) is zero, Timer 2 operates as a 16-bit timer with auto-reload. Timer 2 can be
clocked by SYSCLK, SYSCLK divided by 12, SmaRTClock divided by 8, or Comparator 0 output. As the
16-bit timer register increments and overflows from 0xFFFF to 0x0000, the 16-bit value in the Timer 2
reload registers (TMR2RLH and TMR2RLL) is loaded into the Timer 2 register as shown in Figure 25.4,
and the Timer 2 High Byte Overflow Flag (TMR2CN.7) is set. If Timer 2 interrupts are enabled (if IE.5 is
set), an interrupt will be generated on each Timer 2 overflow. Additionally, if Timer 2 interrupts are enabled
and the TF2LEN bit is set (TMR2CN.5), an interrupt will be generated each time the lower 8 bits (TMR2L)
overflow from 0xFF to 0x00.
CKCON
T2XCLK[1:0]
SmaRTClock / 8
Comparator 0
00
TL2
Overflow
0
01
TR2
TCLK
TMR2L
To ADC,
SMBus
To SMBus
TMR2H
TMR2CN
SYSCLK / 12
TTTTTTSS
3 3 2 2 1 0 CC
MMMMMM A A
HLHL
10
11
1
SYSCLK
TF2H
TF2L
TF2LEN
TF2CEN
T2SPLIT
TR2
Interrupt
T2XCLK
TMR2RLL TMR2RLH
Reload
Figure 25.4. Timer 2 16-Bit Mode Block Diagram
Rev. 1.3
293
C8051F93x-C8051F92x
25.2.2. 8-bit Timers with Auto-Reload
When T2SPLIT is set, Timer 2 operates as two 8-bit timers (TMR2H and TMR2L). Both 8-bit timers operate in auto-reload mode as shown in Figure 25.5. TMR2RLL holds the reload value for TMR2L; TMR2RLH
holds the reload value for TMR2H. The TR2 bit in TMR2CN handles the run control for TMR2H. TMR2L is
always running when configured for 8-bit Mode.
Each 8-bit timer may be configured to use SYSCLK, SYSCLK divided by 12, SmaRTClock divided by 8 or
Comparator 0 output. The Timer 2 Clock Select bits (T2MH and T2ML in CKCON) select either SYSCLK or
the clock defined by the Timer 2 External Clock Select bits (T2XCLK[1:0] in TMR2CN), as follows:
T2MH
T2XCLK[1:0]
0
0
0
0
1
00
01
10
11
X
TMR2H Clock
Source
SYSCLK / 12
SmaRTClock / 8
Reserved
Comparator 0
SYSCLK
T2ML
T2XCLK[1:0]
0
0
0
0
1
00
01
10
11
X
TMR2L Clock
Source
SYSCLK / 12
SmaRTClock / 8
Reserved
Comparator 0
SYSCLK
The TF2H bit is set when TMR2H overflows from 0xFF to 0x00; the TF2L bit is set when TMR2L overflows
from 0xFF to 0x00. When Timer 2 interrupts are enabled (IE.5), an interrupt is generated each time
TMR2H overflows. If Timer 2 interrupts are enabled and TF2LEN (TMR2CN.5) is set, an interrupt is
generated each time either TMR2L or TMR2H overflows. When TF2LEN is enabled, software must check
the TF2H and TF2L flags to determine the source of the Timer 2 interrupt. The TF2H and TF2L interrupt
flags are not cleared by hardware and must be manually cleared by software.
CKCON
TTTTTTSS
3 3 2 2 1 0 CC
MMMMMM A A
HLHL
1 0
T2XCLK[1:0]
SYSCLK / 12
00
SmaRTClock / 8
01
TMR2RLH
Reload
To SMBus
0
TCLK
TR2
11
TMR2RLL
SYSCLK
Reload
TMR2CN
Comparator 0
TMR2H
1
TF2H
TF2L
TF2LEN
TF2CEN
T2SPLIT
TR2
T2XCLK
1
TCLK
TMR2L
To ADC,
SMBus
0
Figure 25.5. Timer 2 8-Bit Mode Block Diagram
294
Rev. 1.3
Interrupt
C8051F93x-C8051F92x
25.2.3. Comparator 0/SmaRTClock Capture Mode
The Capture Mode in Timer 2 allows either Comparator 0 or the SmaRTClock period to be measured
against the system clock or the system clock divided by 12. Comparator 0 and the SmaRTClock period can
also be compared against each other. Timer 2 Capture Mode is enabled by setting TF2CEN to 1. Timer 2
should be in 16-bit auto-reload mode when using Capture Mode.
When Capture Mode is enabled, a capture event will be generated either every Comparator 0 rising edge
or every 8 SmaRTClock clock cycles, depending on the T2XCLK1 setting. When the capture event occurs,
the contents of Timer 2 (TMR2H:TMR2L) are loaded into the Timer 2 reload registers
(TMR2RLH:TMR2RLL) and the TF2H flag is set (triggering an interrupt if Timer 2 interrupts are enabled).
By recording the difference between two successive timer capture values, the Comparator 0 or SmaRTClock period can be determined with respect to the Timer 2 clock. The Timer 2 clock should be much faster
than the capture clock to achieve an accurate reading.
For example, if T2ML = 1b, T2XCLK1 = 0b, and TF2CEN = 1b, Timer 2 will clock every SYSCLK and capture every SmaRTClock clock divided by 8. If the SYSCLK is 24.5 MHz and the difference between two
successive captures is 5984, then the SmaRTClock clock is:
24.5 MHz/(5984/8) = 0.032754 MHz or 32.754 kHz.
This mode allows software to determine the exact SmaRTClock frequency in self-oscillate mode and the
time between consecutive Comparator 0 rising edges, which is useful for detecting changes in the
capacitance of a Touch Sense Switch.
T2XCLK[1:0]
CKCON
X0
Comparator 0
01
SmaRTClock / 8
11
0
TR2
T2XCLK1
SmaRTClock / 8
0
Comparator 0
1
TMR2L
TMR2H
Capture
1
SYSCLK
TCLK
TF2CEN
TMR2RLL TMR2RLH
TMR2CN
SYSCLK / 12
TTTTTTSS
3 3 2 2 1 0CC
MMMMMM A A
HLHL
1 0
TF2H
TF2L
TF2LEN
TF2CEN
T2SPLIT
TR2
T2XCLK1
T2XCLK0
Interrupt
Figure 25.6. Timer 2 Capture Mode Block Diagram
Rev. 1.3
295
C8051F93x-C8051F92x
SFR Definition 25.8. TMR2CN: Timer 2 Control
Bit
7
6
5
4
3
2
Name
TF2H
TF2L
TF2LEN
TF2CEN
T2SPLIT
TR2
T2XCLK[1:0]
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
SFR Page = 0x0; SFR Address = 0xC8; Bit-Addressable
Bit
Name
7
TF2H
1
0
0
0
Function
Timer 2 High Byte Overflow Flag.
Set by hardware when the Timer 2 high byte overflows from 0xFF to 0x00. In 16 bit
mode, this will occur when Timer 2 overflows from 0xFFFF to 0x0000. When the
Timer 2 interrupt is enabled, setting this bit causes the CPU to vector to the
Timer 2 interrupt service routine. This bit is not automatically cleared by hardware.
6
TF2L
Timer 2 Low Byte Overflow Flag.
Set by hardware when the Timer 2 low byte overflows from 0xFF to 0x00. TF2L will
be set when the low byte overflows regardless of the Timer 2 mode. This bit is not
automatically cleared by hardware.
5
TF2LEN
Timer 2 Low Byte Interrupt Enable.
When set to 1, this bit enables Timer 2 Low Byte interrupts. If Timer 2 interrupts
are also enabled, an interrupt will be generated when the low byte of Timer 2 overflows.
4
TF2CEN
Timer 2 Capture Enable.
When set to 1, this bit enables Timer 2 Capture Mode.
3
T2SPLIT
Timer 2 Split Mode Enable.
When set to 1, Timer 2 operates as two 8-bit timers with auto-reload. Otherwise,
Timer 2 operates in 16-bit auto-reload mode.
2
TR2
Timer 2 Run Control.
Timer 2 is enabled by setting this bit to 1. In 8-bit mode, this bit enables/disables
TMR2H only; TMR2L is always enabled in split mode.
1:0
T2XCLK[1:0]
Timer 2 External Clock Select.
This bit selects the “external” and “capture trigger” clock sources for Timer 2. If
Timer 2 is in 8-bit mode, this bit selects the “external” clock source for both timer
bytes. Timer 2 Clock Select bits (T2MH and T2ML in register CKCON) may still be
used to select between the “external” clock and the system clock for either timer.
Note: External clock sources are synchronized with the system clock.
00: External Clock is SYSCLK/12. Capture trigger is SmaRTClock/8.
01: External Clock is Comparator 0. Capture trigger is SmaRTClock/8.
10: External Clock is SYSCLK/12. Capture trigger is Comparator 0.
11: External Clock is SmaRTClock/8. Capture trigger is Comparator 0.
296
Rev. 1.3
C8051F93x-C8051F92x
SFR Definition 25.9. TMR2RLL: Timer 2 Reload Register Low Byte
Bit
7
6
5
4
3
Name
TMR2RLL[7:0]
Type
R/W
Reset
0
0
0
0
0
SFR Page = 0x0; SFR Address = 0xCA
Bit
Name
7:0
2
1
0
0
0
0
2
1
0
0
0
0
Function
TMR2RLL[7:0] Timer 2 Reload Register Low Byte.
TMR2RLL holds the low byte of the reload value for Timer 2.
SFR Definition 25.10. TMR2RLH: Timer 2 Reload Register High Byte
Bit
7
6
5
4
3
Name
TMR2RLH[7:0]
Type
R/W
Reset
0
0
0
0
SFR Page = 0x0; SFR Address = 0xCB
Bit
Name
0
Function
7:0 TMR2RLH[7:0] Timer 2 Reload Register High Byte.
TMR2RLH holds the high byte of the reload value for Timer 2.
Rev. 1.3
297
C8051F93x-C8051F92x
SFR Definition 25.11. TMR2L: Timer 2 Low Byte
Bit
7
6
5
4
3
Name
TMR2L[7:0]
Type
R/W
Reset
0
0
0
0
0
SFR Page = 0x0; SFR Address = 0xCC
Bit
Name
7:0
2
1
0
0
0
0
Function
TMR2L[7:0] Timer 2 Low Byte.
In 16-bit mode, the TMR2L register contains the low byte of the 16-bit Timer 2. In 8bit mode, TMR2L contains the 8-bit low byte timer value.
SFR Definition 25.12. TMR2H Timer 2 High Byte
Bit
7
6
5
4
3
Name
TMR2H[7:0]
Type
R/W
Reset
0
0
0
0
SFR Page = 0x0; SFR Address = 0xCD
Bit
Name
7:0
0
2
1
0
0
0
0
Function
TMR2H[7:0] Timer 2 Low Byte.
In 16-bit mode, the TMR2H register contains the high byte of the 16-bit Timer 2. In 8bit mode, TMR2H contains the 8-bit high byte timer value.
298
Rev. 1.3
C8051F93x-C8051F92x
25.3. Timer 3
Timer 3 is a 16-bit timer formed by two 8-bit SFRs: TMR3L (low byte) and TMR3H (high byte). Timer 3 may
operate in 16-bit auto-reload mode or (split) 8-bit auto-reload mode. The T3SPLIT bit (TMR2CN.3) defines
the Timer 3 operation mode. Timer 3 can also be used in Capture Mode to measure the external oscillator
source or the Comparator 1 period with respect to another oscillator. The ability to measure the
Comparator 1 period with respect to the system clock is makes using Touch Sense Switches very easy.
Timer 3 may be clocked by the system clock, the system clock divided by 12, external oscillator source
divided by 8, or Comparator 1 output. The external oscillator source divided by 8 and Comparator 1 output
is synchronized with the system clock.
25.3.1. 16-bit Timer with Auto-Reload
When T3SPLIT (TMR3CN.3) is zero, Timer 3 operates as a 16-bit timer with auto-reload. Timer 3 can be
clocked by SYSCLK, SYSCLK divided by 12, external oscillator clock source divided by 8, or Comparator 1
output. As the 16-bit timer register increments and overflows from 0xFFFF to 0x0000, the 16-bit value in
the Timer 3 reload registers (TMR3RLH and TMR3RLL) is loaded into the Timer 3 register as shown in
Figure 25.7, and the Timer 3 High Byte Overflow Flag (TMR3CN.7) is set. If Timer 3 interrupts are enabled
(if EIE1.7 is set), an interrupt will be generated on each Timer 3 overflow. Additionally, if Timer 3 interrupts
are enabled and the TF3LEN bit is set (TMR3CN.5), an interrupt will be generated each time the lower 8
bits (TMR3L) overflow from 0xFF to 0x00.
T3XCLK[1:0]
SYSCLK / 12
00
External Clock / 8
01
SYSCLK / 12
10
Comparator 1
11
CKCON
TTTTTTSS
3 3 2 2 1 0 CC
MMMMMM A A
HLHL
1 0
To ADC
0
TCLK
TMR3L
TMR3H
TMR3CN
TR3
1
SYSCLK
TMR3RLL TMR3RLH
TF3H
TF3L
TF3LEN
TF3CEN
T3SPLIT
TR3
T3XCLK1
T3XCLK0
Interrupt
Reload
Figure 25.7. Timer 3 16-Bit Mode Block Diagram
Rev. 1.3
299
C8051F93x-C8051F92x
25.3.2. 8-bit Timers with Auto-Reload
When T3SPLIT is set, Timer 3 operates as two 8-bit timers (TMR3H and TMR3L). Both 8-bit timers operate in auto-reload mode as shown in Figure 25.8. TMR3RLL holds the reload value for TMR3L; TMR3RLH
holds the reload value for TMR3H. The TR3 bit in TMR3CN handles the run control for TMR3H. TMR3L is
always running when configured for 8-bit Mode.
Each 8-bit timer may be configured to use SYSCLK, SYSCLK divided by 12, the external oscillator clock
source divided by 8, or Comparator 1. The Timer 3 Clock Select bits (T3MH and T3ML in CKCON) select
either SYSCLK or the clock defined by the Timer 3 External Clock Select bits (T3XCLK[1:0] in TMR3CN),
as follows:
T3MH
T3XCLK[1:0]
0
0
0
0
1
00
01
10
11
X
TMR3H Clock
Source
SYSCLK / 12
External Clock / 8
SYSCLK / 12
Comparator 1
SYSCLK
T3ML
T3XCLK[1:0]
0
0
0
0
1
00
01
10
11
X
TMR3L Clock
Source
SYSCLK / 12
External Clock / 8
SYSCLK / 12
Comparator 1
SYSCLK
The TF3H bit is set when TMR3H overflows from 0xFF to 0x00; the TF3L bit is set when TMR3L overflows
from 0xFF to 0x00. When Timer 3 interrupts are enabled, an interrupt is generated each time TMR3H overflows. If Timer 3 interrupts are enabled and TF3LEN (TMR3CN.5) is set, an interrupt is generated each
time either TMR3L or TMR3H overflows. When TF3LEN is enabled, software must check the TF3H and
TF3L flags to determine the source of the Timer 3 interrupt. The TF3H and TF3L interrupt flags are not
cleared by hardware and must be manually cleared by software.
T3XCLK[1:0]
CKCON
SYSCLK / 12
00
TTTTTTSS
3 3 2 2 1 0 CC
MMMMMM A A
HLHL
1 0
External Clock / 8
01
SYSCLK / 12
10
TMR3RLH
Reload
0
TMR3H
1
Comparator 1
11
TMR3RLL
SYSCLK
Reload
TMR3CN
TCLK
TR3
TF3H
TF3L
TF3LEN
TF3CEN
T3SPLIT
TR3
T3XCLK1
T3XCLK0
1
TCLK
TMR3L
To ADC
0
Figure 25.8. Timer 3 8-Bit Mode Block Diagram.
300
Rev. 1.3
Interrupt
C8051F93x-C8051F92x
25.3.3. Comparator 1/External Oscillator Capture Mode
The Capture Mode in Timer 3 allows either Comparator 1 or the external oscillator period to be measured
against the system clock or the system clock divided by 12. Comparator 1 and the external oscillator
period can also be compared against each other.
Setting TF3CEN to 1 enables the Comparator 1/External Oscillator Capture Mode for Timer 3. In this
mode, T3SPLIT should be set to 0, as the full 16-bit timer is used.
When Capture Mode is enabled, a capture event will be generated either every Comparator 1 rising edge
or every 8 external clock cycles, depending on the T3XCLK1 setting. When the capture event occurs, the
contents of Timer 3 (TMR3H:TMR3L) are loaded into the Timer 3 reload registers (TMR3RLH:TMR3RLL)
and the TF3H flag is set (triggering an interrupt if Timer 3 interrupts are enabled). By recording the difference between two successive timer capture values, the Comparator 1 or external clock period can be
determined with respect to the Timer 3 clock. The Timer 3 clock should be much faster than the capture
clock to achieve an accurate reading.
For example, if T3ML = 1b, T3XCLK1 = 0b, and TF3CEN = 1b, Timer 3 will clock every SYSCLK and capture every Comparator 1 rising edge. If SYSCLK is 24.5 MHz and the difference between two successive
captures is 350 counts, then the Comparator 1 period is:
350 x (1 / 24.5 MHz) = 14.2 µs.
This mode allows software to determine the exact frequency of the external oscillator in C and RC mode or
the time between consecutive Comparator 0 rising edges, which is useful for detecting changes in the
capacitance of a Touch Sense Switch.
T 3 X C L K [1 :0 ]
CKCON
00
E x te rn a l C lo c k / 8
01
SYSC LK / 12
10
C o m p a ra to r 1
11
T
3
M
H
T
3
M
L
T
2
M
H
T T T S S
2 1 0 C C
M M M A A
1 0
L
0
TR3
T3XC LK1
C o m p a ra to r 1
0
E x te rn a l C lo c k / 8
1
TM R 3L
TM R 3H
TM R 3R LL
TM R 3R LH
C a p tu re
1
SYSC LK
TC LK
TF3C EN
TMR3CN
SYSC LK / 12
TF3H
TF3L
TF3LEN
TF3CEN
T 3 S P L IT
TR3
T3XCLK1
T3XCLK0
In te rru p t
Figure 25.9. Timer 3 Capture Mode Block Diagram
Rev. 1.3
301
C8051F93x-C8051F92x
SFR Definition 25.13. TMR3CN: Timer 3 Control
Bit
7
6
5
4
3
2
Name
TF3H
TF3L
TF3LEN
TF3CEN
T3SPLIT
TR3
T3XCLK[1:0]
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
SFR Page = 0x0; SFR Address = 0x91
Bit
Name
7
TF3H
1
0
0
0
Function
Timer 3 High Byte Overflow Flag.
Set by hardware when the Timer 3 high byte overflows from 0xFF to 0x00. In 16 bit
mode, this will occur when Timer 3 overflows from 0xFFFF to 0x0000. When the
Timer 3 interrupt is enabled, setting this bit causes the CPU to vector to the Timer 3
interrupt service routine. This bit is not automatically cleared by hardware.
6
TF3L
Timer 3 Low Byte Overflow Flag.
Set by hardware when the Timer 3 low byte overflows from 0xFF to 0x00. TF3L will
be set when the low byte overflows regardless of the Timer 3 mode. This bit is not
automatically cleared by hardware.
5
TF3LEN
Timer 3 Low Byte Interrupt Enable.
When set to 1, this bit enables Timer 3 Low Byte interrupts. If Timer 3 interrupts are
also enabled, an interrupt will be generated when the low byte of Timer 3 overflows.
4
TF3CEN
Timer 3 Comparator 1/External Oscillator Capture Enable.
When set to 1, this bit enables Timer 3 Capture Mode.
3
T3SPLIT
Timer 3 Split Mode Enable.
When this bit is set, Timer 3 operates as two 8-bit timers with auto-reload.
0: Timer 3 operates in 16-bit auto-reload mode.
1: Timer 3 operates as two 8-bit auto-reload timers.
2
TR3
Timer 3 Run Control.
Timer 3 is enabled by setting this bit to 1. In 8-bit mode, this bit enables/disables
TMR3H only; TMR3L is always enabled in split mode.
1:0
T3XCLK[1:0] Timer 3 External Clock Select.
This bit selects the “external” and “capture trigger” clock sources for Timer 3. If
Timer 3 is in 8-bit mode, this bit selects the “external” clock source for both timer
bytes. Timer 3 Clock Select bits (T3MH and T3ML in register CKCON) may still be
used to select between the “external” clock and the system clock for either timer.
Note: External clock sources are synchronized with the system clock.
00: External Clock is SYSCLK /12. Capture trigger is Comparator 1.
01: External Clock is External Oscillator/8. Capture trigger is Comparator 1.
10: External Clock is SYSCLK/12. Capture trigger is External Oscillator/8.
11: External Clock is Comparator 1. Capture trigger is External Oscillator/8.
302
Rev. 1.3
C8051F93x-C8051F92x
SFR Definition 25.14. TMR3RLL: Timer 3 Reload Register Low Byte
Bit
7
6
5
4
3
Name
TMR3RLL[7:0]
Type
R/W
Reset
0
0
0
0
0
SFR Page = 0x0; SFR Address = 0x92
Bit
Name
7:0
2
1
0
0
0
0
2
1
0
0
0
0
Function
TMR3RLL[7:0] Timer 3 Reload Register Low Byte.
TMR3RLL holds the low byte of the reload value for Timer 3.
SFR Definition 25.15. TMR3RLH: Timer 3 Reload Register High Byte
Bit
7
6
5
4
3
Name
TMR3RLH[7:0]
Type
R/W
Reset
0
0
0
0
SFR Page = 0x0; SFR Address = 0x93
Bit
Name
0
Function
7:0 TMR3RLH[7:0] Timer 3 Reload Register High Byte.
TMR3RLH holds the high byte of the reload value for Timer 3.
Rev. 1.3
303
C8051F93x-C8051F92x
SFR Definition 25.16. TMR3L: Timer 3 Low Byte
Bit
7
6
5
4
3
Name
TMR3L[7:0]
Type
R/W
Reset
0
0
0
0
0
SFR Page = 0x0; SFR Address = 0x94
Bit
Name
7:0
TMR3L[7:0]
2
1
0
0
0
0
Function
Timer 3 Low Byte.
In 16-bit mode, the TMR3L register contains the low byte of the 16-bit Timer 3. In
8-bit mode, TMR3L contains the 8-bit low byte timer value.
SFR Definition 25.17. TMR3H Timer 3 High Byte
Bit
7
6
5
4
3
Name
TMR3H[7:0]
Type
R/W
Reset
0
0
0
0
SFR Page = 0x0; SFR Address = 0x95
Bit
Name
7:0
TMR3H[7:0]
0
2
1
0
0
0
0
Function
Timer 3 High Byte.
In 16-bit mode, the TMR3H register contains the high byte of the 16-bit Timer 3. In
8-bit mode, TMR3H contains the 8-bit high byte timer value.
304
Rev. 1.3
C8051F93x-C8051F92x
26. Programmable Counter Array
The Programmable Counter Array (PCA0) provides enhanced timer functionality while requiring less CPU
intervention than the standard 8051 counter/timers. The PCA consists of a dedicated 16-bit counter/timer
and six 16-bit capture/compare modules. Each capture/compare module has its own associated I/O line
(CEXn) which is routed through the Crossbar to Port I/O when enabled. The counter/timer is driven by a
programmable timebase that can select between seven sources: system clock, system clock divided by
four, system clock divided by twelve, the external oscillator clock source divided by 8, Timer 0 overflows, or
an external clock signal on the ECI input pin. Each capture/compare module may be configured to operate
independently in one of six modes: Edge-Triggered Capture, Software Timer, High-Speed Output,
Frequency Output, 8 to 11-Bit PWM, or 16-Bit PWM (each mode is described in Section
“26.3. Capture/Compare Modules” on page 308). The external oscillator clock option is ideal for real-time
clock (RTC) functionality, allowing the PCA to be clocked by a precision external oscillator while the
internal oscillator drives the system clock. The PCA is configured and controlled through the system
controller's Special Function Registers. The PCA block diagram is shown in Figure 26.1
Important Note: The PCA Module 5 may be used as a watchdog timer (WDT), and is enabled in this mode
following a system reset. Access to certain PCA registers is restricted while WDT mode is enabled.
See Section 26.4 for details.
SYSCLK/12
SYSCLK/4
Timer 0 Overflow
ECI
SYSCLK
PCA
CLOCK
MUX
16-Bit Counter/Timer
External Clock/8
Capture/Compare
Module 0
Capture/Compare
Module 1
Capture/Compare
Module 2
Capture/Compare
Module 3
Capture/Compare
Module 4
Capture/Compare
Module 5 / WDT
CEX5
CEX4
CEX3
CEX2
CEX1
CEX0
ECI
Crossbar
Port I/O
Figure 26.1. PCA Block Diagram
Rev. 1.3
305
C8051F93x-C8051F92x
26.1. PCA Counter/Timer
The 16-bit PCA counter/timer consists of two 8-bit SFRs: PCA0L and PCA0H. PCA0H is the high byte
(MSB) of the 16-bit counter/timer and PCA0L is the low byte (LSB). Reading PCA0L automatically latches
the value of PCA0H into a “snapshot” register; the following PCA0H read accesses this “snapshot” register.
Reading the PCA0L Register first guarantees an accurate reading of the entire 16-bit PCA0 counter.
Reading PCA0H or PCA0L does not disturb the counter operation. The CPS2–CPS0 bits in the PCA0MD
register select the timebase for the counter/timer as shown in Table 26.1.
When the counter/timer overflows from 0xFFFF to 0x0000, the Counter Overflow Flag (CF) in PCA0MD is
set to logic 1 and an interrupt request is generated if CF interrupts are enabled. Setting the ECF bit in
PCA0MD to logic 1 enables the CF flag to generate an interrupt request. The CF bit is not automatically
cleared by hardware when the CPU vectors to the interrupt service routine, and must be cleared by
software. Clearing the CIDL bit in the PCA0MD register allows the PCA to continue normal operation while
the CPU is in Idle mode.
Table 26.1. PCA Timebase Input Options
CPS2
0
0
0
CPS1
0
0
1
CPS0
0
1
0
0
1
1
1
1
1
1
0
0
1
1
0
1
0
1
Timebase
System clock divided by 12
System clock divided by 4
Timer 0 overflow
High-to-low transitions on ECI (max rate = system clock divided
by 4)
System clock
External oscillator source divided by 8*
Reserved
Reserved
*Note: External oscillator source divided by 8 is synchronized with the system clock.
IDLE
PCA0MD
C
I
D
L
WW
D D
T L
E C
K
C
P
S
2
C
P
S
1
CE
PC
S F
0
PCA0CN
CCC
FRC
F
5
C
C
F
4
C
C
F
3
C
C
F
2
C
C
F
1
C
C
F
0
To SFR Bus
PCA0L
read
Snapshot
Register
SYSCLK/12
SYSCLK/4
Timer 0 Overflow
ECI
SYSCLK
External Clock/8
000
001
010
0
1
PCA0H
PCA0L
Overflow
011
CF
100
To PCA Modules
101
Figure 26.2. PCA Counter/Timer Block Diagram
306
To PCA Interrupt System
Rev. 1.3
C8051F93x-C8051F92x
26.2. PCA0 Interrupt Sources
Figure 26.3 shows a diagram of the PCA interrupt tree. There are eight independent event flags that can
be used to generate a PCA0 interrupt. They are: the main PCA counter overflow flag (CF), which is set
upon a 16-bit overflow of the PCA0 counter, an intermediate overflow flag (COVF), which can be set on an
overflow from the 8th, 9th, 10th, or 11th bit of the PCA0 counter, and the individual flags for each PCA
channel (CCF0, CCF1, CCF2, CCF3, CCF4, and CCF5), which are set according to the operation mode of
that module. These event flags are always set when the trigger condition occurs. Each of these flags can
be individually selected to generate a PCA0 interrupt, using the corresponding interrupt enable flag (ECF
for CF, ECOV for COVF, and ECCFn for each CCFn). PCA0 interrupts must be globally enabled before any
individual interrupt sources are recognized by the processor. PCA0 interrupts are globally enabled by
setting the EA bit and the EPCA0 bit to logic 1.
(for n = 0 to 5)
PCA0CPMn
PCA0CN
P ECCMT P E
WC A A AOWC
MOPP TGMC
1 MP N n n n F
6 n n n
n
n
CCCCCCCC
FRCCCCCC
FFFFFF
5 4 3 2 1 0
PCA0MD
C WW
I DD
DT L
LEC
K
PCA0PWM
A CE
ROC
S VO
EFV
L
CCCE
PPPC
SSSF
2 1 0
C
L
S
E
L
1
PCA Counter/Timer 8, 9,
10 or 11-bit Overflow
C
L
S
E
L
0
Set 8, 9, 10, or 11 bit Operation
0
PCA Counter/Timer 16bit Overflow
0
1
1
ECCF0
PCA Module 0
(CCF0)
EPCA0
EA
0
0
0
1
1
1
Interrupt
Priority
Decoder
ECCF1
0
PCA Module 1
(CCF1)
1
ECCF2
0
PCA Module 2
(CCF2)
1
ECCF3
0
PCA Module 3
(CCF3)
1
ECCF4
0
PCA Module 4
(CCF4)
1
ECCF5
PCA Module 5
(CCF5)
0
1
Figure 26.3. PCA Interrupt Block Diagram
Rev. 1.3
307
C8051F93x-C8051F92x
26.3. Capture/Compare Modules
Each module can be configured to operate independently in one of six operation modes: edge-triggered
capture, software timer, high speed output, frequency output, 8 to 11-bit pulse width modulator, or 16-bit
pulse width modulator. Each module has Special Function Registers (SFRs) associated with it in the CIP51 system controller. These registers are used to exchange data with a module and configure the module's
mode of operation. Table 26.2 summarizes the bit settings in the PCA0CPMn and PCA0PWM registers
used to select the PCA capture/compare module’s operating mode. Note that all modules set to use 8, 9,
10, or 11-bit PWM mode must use the same cycle length (8-11 bits). Setting the ECCFn bit in a
PCA0CPMn register enables the module's CCFn interrupt.
Table 26.2. PCA0CPM and PCA0PWM Bit Settings for PCA Capture/Compare Modules
Operational Mode
PCA0CPMn
PCA0PWM
Bit Number 7 6 5 4 3 2 1 0 7 6 5
4–2
1–0
Capture triggered by positive edge on CEXn
X X 1 0 0 0 0 A 0 X B XXX
XX
Capture triggered by negative edge on CEXn
X X 0 1 0 0 0 A 0 X B XXX
XX
Capture triggered by any transition on CEXn
X X 1 1 0 0 0 A 0 X B XXX
XX
Software Timer
X C 0 0 1 0 0 A 0 X B XXX
XX
High Speed Output
X C 0 0 1 1 0 A 0 X B XXX
XX
Frequency Output
X C 0 0 0 1 1 A 0 X B XXX
XX
8-Bit Pulse Width Modulator (Note 7)
0 C 0 0 E 0 1 A 0 X B XXX
00
9-Bit Pulse Width Modulator (Note 7)
0 C 0 0 E 0 1 A D X B XXX
01
10-Bit Pulse Width Modulator (Note 7)
0 C 0 0 E 0 1 A D X B XXX
10
11-Bit Pulse Width Modulator (Note 7)
0 C 0 0 E 0 1 A D X B XXX
11
16-Bit Pulse Width Modulator
1 C 0 0 E 0 1 A 0 X B XXX
XX
Notes:
1. X = Don’t Care (no functional difference for individual module if 1 or 0).
2. A = Enable interrupts for this module (PCA interrupt triggered on CCFn set to 1).
3. B = Enable 8th, 9th, 10th or 11th bit overflow interrupt (Depends on setting of CLSEL[1:0]).
4. C = When set to 0, the digital comparator is off. For high speed and frequency output modes, the
associated pin will not toggle. In any of the PWM modes, this generates a 0% duty cycle (output = 0).
5. D = Selects whether the Capture/Compare register (0) or the Auto-Reload register (1) for the associated
channel is accessed via addresses PCA0CPHn and PCA0CPLn.
6. E = When set, a match event will cause the CCFn flag for the associated channel to be set.
7. All modules set to 8, 9, 10 or 11-bit PWM mode use the same cycle length setting.
308
Rev. 1.3
C8051F93x-C8051F92x
26.3.1. Edge-triggered Capture Mode
In this mode, a valid transition on the CEXn pin causes the PCA to capture the value of the PCA
counter/timer and load it into the corresponding module's 16-bit capture/compare register (PCA0CPLn and
PCA0CPHn). The CAPPn and CAPNn bits in the PCA0CPMn register are used to select the type of
transition that triggers the capture: low-to-high transition (positive edge), high-to-low transition (negative
edge), or either transition (positive or negative edge). When a capture occurs, the Capture/Compare Flag
(CCFn) in PCA0CN is set to logic 1. An interrupt request is generated if the CCFn interrupt for that module
is enabled. The CCFn bit is not automatically cleared by hardware when the CPU vectors to the interrupt
service routine, and must be cleared by software. If both CAPPn and CAPNn bits are set to logic 1, then
the state of the Port pin associated with CEXn can be read directly to determine whether a rising-edge or
falling-edge caused the capture.
PCA Interrupt
PCA0CPMn
P ECCMT P E
WC A A AOWC
MOPP TGMC
1 MP N n n n F
6 n n n
n
n
0 0 0 x
0
Port I/O
Crossbar
CEXn
CCC
CCC
FFF
2 1 0
(to CCFn)
x x
PCA0CN
CC
FR
1
PCA0CPLn
PCA0CPHn
Capture
0
1
PCA
Timebase
PCA0L
PCA0H
Figure 26.4. PCA Capture Mode Diagram
Note: The CEXn input signal must remain high or low for at least 2 system clock cycles to be recognized by the
hardware.
Rev. 1.3
309
C8051F93x-C8051F92x
26.3.2. Software Timer (Compare) Mode
In Software Timer mode, the PCA counter/timer value is compared to the module's 16-bit capture/compare
register (PCA0CPHn and PCA0CPLn). When a match occurs, the Capture/Compare Flag (CCFn) in
PCA0CN is set to logic 1. An interrupt request is generated if the CCFn interrupt for that module is
enabled. The CCFn bit is not automatically cleared by hardware when the CPU vectors to the interrupt
service routine, and must be cleared by software. Setting the ECOMn and MATn bits in the PCA0CPMn
register enables Software Timer mode.
Important Note About Capture/Compare Registers: When writing a 16-bit value to the PCA0
Capture/Compare registers, the low byte should always be written first. Writing to PCA0CPLn clears the
ECOMn bit to 0; writing to PCA0CPHn sets ECOMn to 1.
Write to
PCA0CPLn
0
ENB
Reset
Write to
PCA0CPHn
PCA Interrupt
ENB
1
PCA0CPMn
P ECCMT P E
WC A A AOWC
MOPP TGMC
1 MP N n n n F
6 n n n
n
n
x
0 0
PCA0CN
PCA0CPLn
CC
FR
PCA0CPHn
0 0 x
Enable
16-bit Comparator
PCA
Timebase
PCA0L
Match
PCA0H
Figure 26.5. PCA Software Timer Mode Diagram
310
CCC
CCC
FFF
2 1 0
Rev. 1.3
0
1
C8051F93x-C8051F92x
26.3.3. High-Speed Output Mode
In High-Speed Output mode, a module’s associated CEXn pin is toggled each time a match occurs
between the PCA Counter and the module's 16-bit capture/compare register (PCA0CPHn and
PCA0CPLn). When a match occurs, the Capture/Compare Flag (CCFn) in PCA0CN is set to logic 1. An
interrupt request is generated if the CCFn interrupt for that module is enabled. The CCFn bit is not
automatically cleared by hardware when the CPU vectors to the interrupt service routine, and must be
cleared by software. Setting the TOGn, MATn, and ECOMn bits in the PCA0CPMn register enables the
High-Speed Output mode. If ECOMn is cleared, the associated pin will retain its state, and not toggle on
the next match event.
Important Note About Capture/Compare Registers: When writing a 16-bit value to the PCA0
Capture/Compare registers, the low byte should always be written first. Writing to PCA0CPLn clears the
ECOMn bit to 0; writing to PCA0CPHn sets ECOMn to 1.
Write to
PCA0CPLn
0
ENB
Reset
Write to
PCA0CPHn
PCA0CPMn
P ECCMT P E
WC A A AOWC
MOPP TGMC
1 MPN n n n F
6 n n n
n
n
ENB
1
x
0 0
0 x
PCA Interrupt
PCA0CN
PCA0CPLn
Enable
CC
FR
PCA0CPHn
16-bit Comparator
Match
0
1
Toggle
PCA
Timebase
CCC
CCC
FFF
2 1 0
TOGn
0 CEXn
1
PCA0L
Crossbar
Port I/O
PCA0H
Figure 26.6. PCA High-Speed Output Mode Diagram
Rev. 1.3
311
C8051F93x-C8051F92x
26.3.4. Frequency Output Mode
Frequency Output Mode produces a programmable-frequency square wave on the module’s associated
CEXn pin. The capture/compare module high byte holds the number of PCA clocks to count before the
output is toggled. The frequency of the square wave is then defined by Equation 26.1.
F PCA
F CEXn = ----------------------------------------2  PCA0CPHn
Note: A value of 0x00 in the PCA0CPHn register is equal to 256 for this equation.
Equation 26.1. Square Wave Frequency Output
Where FPCA is the frequency of the clock selected by the CPS2–0 bits in the PCA mode register,
PCA0MD. The lower byte of the capture/compare module is compared to the PCA counter low byte; on a
match, CEXn is toggled and the offset held in the high byte is added to the matched value in PCA0CPLn.
Frequency Output Mode is enabled by setting the ECOMn, TOGn, and PWMn bits in the PCA0CPMn
register. The MATn bit should normally be set to 0 in this mode. If the MATn bit is set to 1, the CCFn flag for
the channel will be set when the 16-bit PCA0 counter and the 16-bit capture/compare register for the
channel are equal.
Write to
PCA0CPLn
0
ENB
Reset
PCA0CPMn
Write to
PCA0CPHn
ENB
1
P ECCMT P E
WC A A AOWC
MOPP TGMC
1 MP N n n n F
6 n n n
n
n
x
0 0 0
PCA0CPLn
8-bit Adder
Adder
Enable
Toggle
x
Enable
PCA Timebase
8-bit
Comparator
PCA0CPHn
TOGn
match
PCA0L
Figure 26.7. PCA Frequency Output Mode
312
Rev. 1.3
0 CEXn
1
Crossbar
Port I/O
C8051F93x-C8051F92x
26.3.5. 8-Bit, 9-Bit, 10-Bit and 11-Bit Pulse Width Modulator Modes
Each module can be used independently to generate a pulse width modulated (PWM) output on its
associated CEXn pin. The frequency of the output is dependent on the timebase for the PCA counter/timer,
and the setting of the PWM cycle length (8, 9, 10 or 11-bits). For backwards-compatibility with the 8-bit
PWM mode available on other devices, the 8-bit PWM mode operates slightly different than 9, 10 and 11bit PWM modes. It is important to note that all channels configured for 8/9/10/11-bit PWM mode will
use the same cycle length. It is not possible to configure one channel for 8-bit PWM mode and another
for 11-bit mode (for example). However, other PCA channels can be configured to Pin Capture, HighSpeed Output, Software Timer, Frequency Output, or 16-bit PWM mode independently.
26.3.5.1. 8-Bit Pulse Width Modulator Mode
The duty cycle of the PWM output signal in 8-bit PWM mode is varied using the module's PCA0CPLn
capture/compare register. When the value in the low byte of the PCA counter/timer (PCA0L) is equal to the
value in PCA0CPLn, the output on the CEXn pin will be set. When the count value in PCA0L overflows, the
CEXn output will be reset (see Figure 26.8). Also, when the counter/timer low byte (PCA0L) overflows from
0xFF to 0x00, PCA0CPLn is reloaded automatically with the value stored in the module’s capture/compare
high byte (PCA0CPHn) without software intervention. Setting the ECOMn and PWMn bits in the
PCA0CPMn register, and setting the CLSEL bits in register PCA0PWM to 00b enables 8-Bit Pulse Width
Modulator mode. If the MATn bit is set to 1, the CCFn flag for the module will be set each time an 8-bit
comparator match (rising edge) occurs. The COVF flag in PCA0PWM can be used to detect the overflow
(falling edge), which will occur every 256 PCA clock cycles. The duty cycle for 8-Bit PWM Mode is given in
Equation 26.2.
Important Note About Capture/Compare Registers: When writing a 16-bit value to the PCA0
Capture/Compare registers, the low byte should always be written first. Writing to PCA0CPLn clears the
ECOMn bit to 0; writing to PCA0CPHn sets ECOMn to 1.
 256 – PCA0CPHn 
Duty Cycle = --------------------------------------------------256
Equation 26.2. 8-Bit PWM Duty Cycle
Using Equation 26.2, the largest duty cycle is 100% (PCA0CPHn = 0), and the smallest duty cycle is
0.39% (PCA0CPHn = 0xFF). A 0% duty cycle may be generated by clearing the ECOMn bit to 0.
Write to
PCA0CPLn
0
ENB
Reset
PCA0CPHn
Write to
PCA0CPHn
ENB
COVF
1
PCA0PWM
A
R
S
E
L
EC
CO
OV
VF
0 x
C
L
S
E
L
1
PCA0CPMn
C
L
S
E
L
0
0 0
P ECCMT P E
WC A A AOWC
MOPP TGMC
1 MP N n n n F
6 n n n
n
n
0
0 0 x 0
PCA0CPLn
x
Enable
8-bit
Comparator
match
S
R
PCA Timebase
PCA0L
SET
CLR
Q
CEXn
Crossbar
Port I/O
Q
Overflow
Figure 26.8. PCA 8-Bit PWM Mode Diagram
Rev. 1.3
313
C8051F93x-C8051F92x
26.3.5.2. 9/10/11-bit Pulse Width Modulator Mode
The duty cycle of the PWM output signal in 9/10/11-bit PWM mode should be varied by writing to an “AutoReload” Register, which is dual-mapped into the PCA0CPHn and PCA0CPLn register locations. The data
written to define the duty cycle should be right-justified in the registers. The auto-reload registers are
accessed (read or written) when the bit ARSEL in PCA0PWM is set to 1. The capture/compare registers
are accessed when ARSEL is set to 0.
When the least-significant N bits of the PCA0 counter match the value in the associated module’s
capture/compare register (PCA0CPn), the output on CEXn is asserted high. When the counter overflows
from the Nth bit, CEXn is asserted low (see Figure 26.9). Upon an overflow from the Nth bit, the COVF flag
is set, and the value stored in the module’s auto-reload register is loaded into the capture/compare
register. The value of N is determined by the CLSEL bits in register PCA0PWM.
The 9, 10 or 11-bit PWM mode is selected by setting the ECOMn and PWMn bits in the PCA0CPMn
register, and setting the CLSEL bits in register PCA0PWM to the desired cycle length (other than 8-bits). If
the MATn bit is set to 1, the CCFn flag for the module will be set each time a comparator match (rising
edge) occurs. The COVF flag in PCA0PWM can be used to detect the overflow (falling edge), which will
occur every 512 (9-bit), 1024 (10-bit) or 2048 (11-bit) PCA clock cycles. The duty cycle for 9/10/11-Bit
PWM Mode is given in Equation 26.2, where N is the number of bits in the PWM cycle.
Important Note About PCA0CPHn and PCA0CPLn Registers: When writing a 16-bit value to the
PCA0CPn registers, the low byte should always be written first. Writing to PCA0CPLn clears the ECOMn
bit to 0; writing to PCA0CPHn sets ECOMn to 1.
 2 N – PCA0CPn Duty Cycle = ------------------------------------------2N
Equation 26.3. 9, 10, and 11-Bit PWM Duty Cycle
A 0% duty cycle may be generated by clearing the ECOMn bit to 0.
Write to
PCA0CPLn
0
R/W when
ARSEL = 1
ENB
Reset
Write to
PCA0CPHn
(Auto-Reload)
PCA0PWM
PCA0CPH:Ln
A
R
S
E
L
(right-justified)
ENB
1
C
L
S
E
L
1
EC
CO
OV
VF
PCA0CPMn
P ECCMT P E
WC A A AOWC
MOPP TGMC
1 MP N n n n F
6 n n n
n
n
0
0 0 x 0
R/W when
ARSEL = 0
C
L
S
E
L
0
x
(Capture/Compare)
Set “N” bits:
01 = 9 bits
10 = 10 bits
11 = 11 bits
PCA0CPH:Ln
(right-justified)
x
Enable
N-bit Comparator
match
S
R
PCA Timebase
SET
CLR
Q
CEXn
Crossbar
Q
PCA0H:L
Overflow of Nth Bit
Figure 26.9. PCA 9, 10 and 11-Bit PWM Mode Diagram
314
Rev. 1.3
Port I/O
C8051F93x-C8051F92x
26.3.6. 16-Bit Pulse Width Modulator Mode
A PCA module may also be operated in 16-Bit PWM mode. 16-bit PWM mode is independent of the other
(8/9/10/11-bit) PWM modes. In this mode, the 16-bit capture/compare module defines the number of PCA
clocks for the low time of the PWM signal. When the PCA counter matches the module contents, the
output on CEXn is asserted high; when the 16-bit counter overflows, CEXn is asserted low. To output a
varying duty cycle, new value writes should be synchronized with PCA CCFn match interrupts. 16-Bit
PWM Mode is enabled by setting the ECOMn, PWMn, and PWM16n bits in the PCA0CPMn register. For a
varying duty cycle, match interrupts should be enabled (ECCFn = 1 AND MATn = 1) to help synchronize
the capture/compare register writes. If the MATn bit is set to 1, the CCFn flag for the module will be set
each time a 16-bit comparator match (rising edge) occurs. The CF flag in PCA0CN can be used to detect
the overflow (falling edge). The duty cycle for 16-Bit PWM Mode is given by Equation 26.4.
Important Note About Capture/Compare Registers: When writing a 16-bit value to the PCA0
Capture/Compare registers, the low byte should always be written first. Writing to PCA0CPLn clears the
ECOMn bit to 0; writing to PCA0CPHn sets ECOMn to 1.
 65536 – PCA0CPn 
Duty Cycle = ----------------------------------------------------65536
Equation 26.4. 16-Bit PWM Duty Cycle
Using Equation 26.4, the largest duty cycle is 100% (PCA0CPn = 0), and the smallest duty cycle is
0.0015% (PCA0CPn = 0xFFFF). A 0% duty cycle may be generated by clearing the ECOMn bit to 0.
Write to
PCA0CPLn
0
ENB
Reset
Write to
PCA0CPHn
ENB
1
PCA0CPMn
P EC
WCA
MOP
1 MP
6 n n
n
1
C
A
P
N
n
MT P
AOW
TGM
n n n
0 0 x 0
E
C
C
F
n
PCA0CPHn
PCA0CPLn
x
Enable
16-bit Comparator
match
S
R
PCA Timebase
PCA0H
PCA0L
SET
CLR
Q
CEXn
Crossbar
Port I/O
Q
Overflow
Figure 26.10. PCA 16-Bit PWM Mode
Rev. 1.3
315
C8051F93x-C8051F92x
26.4. Watchdog Timer Mode
A programmable watchdog timer (WDT) function is available through the PCA Module 5. The WDT is used
to generate a reset if the time between writes to the WDT update register (PCA0CPH5) exceed a specified
limit. The WDT can be configured and enabled/disabled as needed by software.
With the WDTE bit set in the PCA0MD register, Module 5 operates as a watchdog timer (WDT). The
Module 5 high byte is compared to the PCA counter high byte; the Module 5 low byte holds the offset to be
used when WDT updates are performed. The Watchdog Timer is enabled on reset. Writes to some
PCA registers are restricted while the Watchdog Timer is enabled. The WDT will generate a reset
shortly after code begins execution. To avoid this reset, the WDT should be explicitly disabled (and
optionally re-configured and re-enabled if it is used in the system).
26.4.1. Watchdog Timer Operation
While the WDT is enabled:
•
•
•
•
•
•
PCA counter is forced on.
Writes to PCA0L and PCA0H are not allowed.
PCA clock source bits (CPS2–CPS0) are frozen.
PCA Idle control bit (CIDL) is frozen.
Module 5 is forced into software timer mode.
Writes to the Module 5 mode register (PCA0CPM5) are disabled.
While the WDT is enabled, writes to the CR bit will not change the PCA counter state; the counter will run
until the WDT is disabled. The PCA counter run control bit (CR) will read zero if the WDT is enabled but
user software has not enabled the PCA counter. If a match occurs between PCA0CPH5 and PCA0H while
the WDT is enabled, a reset will be generated. To prevent a WDT reset, the WDT may be updated with a
write of any value to PCA0CPH5. Upon a PCA0CPH5 write, PCA0H plus the offset held in PCA0CPL5 is
loaded into PCA0CPH5 (See Figure 26.11).
PCA0M D
C
I
D
L
W
D
T
E
W
D
L
C
K
C
P
S
2
C
P
S
1
C E
P C
S F
0
PCA0CPH5
Enable
PCA0CPL5
W rite to
PC A0C PH5
8-bit Adder
8-bit
C om parator
PCA0H
M atch
R eset
PC A0L O verflow
Adder
Enable
Figure 26.11. PCA Module 5 with Watchdog Timer Enabled
316
Rev. 1.3
C8051F93x-C8051F92x
Note that the 8-bit offset held in PCA0CPH5 is compared to the upper byte of the 16-bit PCA counter. This
offset value is the number of PCA0L overflows before a reset. Up to 256 PCA clocks may pass before the
first PCA0L overflow occurs, depending on the value of the PCA0L when the update is performed. The
total offset is then given (in PCA clocks) by Equation 26.5, where PCA0L is the value of the PCA0L register
at the time of the update.
Offset =  256  PCA0CPL5  +  256 – PCA0L 
Equation 26.5. Watchdog Timer Offset in PCA Clocks
The WDT reset is generated when PCA0L overflows while there is a match between PCA0CPH5 and
PCA0H. Software may force a WDT reset by writing a 1 to the CCF5 flag (PCA0CN.5) while the WDT is
enabled.
26.4.2. Watchdog Timer Usage
To configure the WDT, perform the following tasks:
•
•
•
•
•
•
Disable the WDT by writing a 0 to the WDTE bit.
Select the desired PCA clock source (with the CPS2–CPS0 bits).
Load PCA0CPL5 with the desired WDT update offset value.
Configure the PCA Idle mode (set CIDL if the WDT should be suspended while the CPU is in Idle
mode).
Enable the WDT by setting the WDTE bit to 1.
Reset the WDT timer by writing to PCA0CPH5.
The PCA clock source and idle mode select cannot be changed while the WDT is enabled. The watchdog
timer is enabled by setting the WDTE or WDLCK bits in the PCA0MD register. When WDLCK is set, the
WDT cannot be disabled until the next system reset. If WDLCK is not set, the WDT is disabled by clearing
the WDTE bit.
The WDT is enabled following any reset. The PCA0 counter clock defaults to the system clock divided by
12, PCA0L defaults to 0x00, and PCA0CPL5 defaults to 0x00. Using Equation 26.5, this results in a WDT
timeout interval of 256 PCA clock cycles, or 3072 system clock cycles. Table 26.3 lists some example
timeout intervals for typical system clocks.
Table 26.3. Watchdog Timer Timeout Intervals1
System Clock (Hz)
PCA0CPL5
Timeout Interval (ms)
24,500,000
255
32.1
24,500,000
128
16.2
24,500,000
32
4.1
3,062,5002
255
257
3,062,5002
128
129.5
3,062,5002
32
33.1
32,000
255
24576
32,000
128
12384
32,000
32
3168
Notes:
1. Assumes SYSCLK/12 as the PCA clock source, and a PCA0L value
of 0x00 at the update time.
2. Internal SYSCLK reset frequency = Internal Oscillator divided by 8.
Rev. 1.3
317
C8051F93x-C8051F92x
26.5. Register Descriptions for PCA0
Following are detailed descriptions of the special function registers related to the operation of the PCA.
SFR Definition 26.1. PCA0CN: PCA Control
Bit
7
6
5
4
3
2
1
0
Name
CF
CR
CCF5
CCF4
CCF3
CCF2
CCF1
CCF0
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
SFR Page = 0x0; SFR Address = 0xD8; Bit-Addressable
Bit
Name
Function
7
CF
PCA Counter/Timer Overflow Flag.
Set by hardware when the PCA Counter/Timer overflows from 0xFFFF to 0x0000.
When the Counter/Timer Overflow (CF) interrupt is enabled, setting this bit causes the
CPU to vector to the PCA interrupt service routine. This bit is not automatically cleared
by hardware and must be cleared by software.
6
CR
PCA Counter/Timer Run Control.
This bit enables/disables the PCA Counter/Timer.
0: PCA Counter/Timer disabled.
1: PCA Counter/Timer enabled.
5:0
CCF[5:0] PCA Module n Capture/Compare Flag.
These bits are set by hardware when a match or capture occurs in the associated PCA
Module n. When the CCFn interrupt is enabled, setting this bit causes the CPU to
vector to the PCA interrupt service routine. This bit is not automatically cleared by
hardware and must be cleared by software.
318
Rev. 1.3
C8051F93x-C8051F92x
SFR Definition 26.2. PCA0MD: PCA Mode
Bit
7
6
5
Name
CIDL
WDTE
WDLCK
Type
R/W
R/W
R/W
Reset
0
1
0
4
3
2
1
0
CPS2
CPS1
CPS0
ECF
R
R/W
R/W
R/W
R/W
0
0
0
0
0
SFR Page = 0x0; SFR Address = 0xD9
Bit
Name
7
CIDL
Function
PCA Counter/Timer Idle Control.
Specifies PCA behavior when CPU is in Idle Mode.
0: PCA continues to function normally while the system controller is in Idle Mode.
1: PCA operation is suspended while the system controller is in Idle Mode.
6
WDTE
Watchdog Timer Enable.
If this bit is set, PCA Module 2 is used as the watchdog timer.
0: Watchdog Timer disabled.
1: PCA Module 2 enabled as Watchdog Timer.
5
WDLCK
Watchdog Timer Lock.
This bit locks/unlocks the Watchdog Timer Enable. When WDLCK is set, the Watchdog
Timer may not be disabled until the next system reset.
0: Watchdog Timer Enable unlocked.
1: Watchdog Timer Enable locked.
4
3:1
Unused
Unused.
Read = 0b, Write = don't care.
CPS[2:0] PCA Counter/Timer Pulse Select.
These bits select the timebase source for the PCA counter
000: System clock divided by 12
001: System clock divided by 4
010: Timer 0 overflow
011: High-to-low transitions on ECI (max rate = system clock divided by 4)
100: System clock
101: External clock divided by 8 (synchronized with the system clock)
110: Reserved
111: Reserved
0
ECF
PCA Counter/Timer Overflow Interrupt Enable.
This bit sets the masking of the PCA Counter/Timer Overflow (CF) interrupt.
0: Disable the CF interrupt.
1: Enable a PCA Counter/Timer Overflow interrupt request when CF (PCA0CN.7) is
set.
Note: When the WDTE bit is set to 1, the other bits in the PCA0MD register cannot be modified. To change the
contents of the PCA0MD register, the Watchdog Timer must first be disabled.
Rev. 1.3
319
C8051F93x-C8051F92x
SFR Definition 26.3. PCA0PWM: PCA PWM Configuration
Bit
7
6
5
4
Name
ARSEL
ECOV
COVF
Type
R/W
R/W
R/W
R
R
R
Reset
0
0
0
0
0
0
ARSEL
2
1
0
CLSEL[1:0]
SFR Page = 0x0; SFR Address = 0xDF
Bit
Name
7
3
R/W
0
0
Function
Auto-Reload Register Select.
This bit selects whether to read and write the normal PCA capture/compare registers
(PCA0CPn), or the Auto-Reload registers at the same SFR addresses. This function
is used to define the reload value for 9, 10, and 11-bit PWM modes. In all other
modes, the Auto-Reload registers have no function.
0: Read/Write Capture/Compare Registers at PCA0CPHn and PCA0CPLn.
1: Read/Write Auto-Reload Registers at PCA0CPHn and PCA0CPLn.
6
ECOV
Cycle Overflow Interrupt Enable.
This bit sets the masking of the Cycle Overflow Flag (COVF) interrupt.
0: COVF will not generate PCA interrupts.
1: A PCA interrupt will be generated when COVF is set.
5
COVF
Cycle Overflow Flag.
This bit indicates an overflow of the 8th, 9th, 10th, or 11th bit of the main PCA counter
(PCA0). The specific bit used for this flag depends on the setting of the Cycle Length
Select bits. The bit can be set by hardware or software, but must be cleared by software.
0: No overflow has occurred since the last time this bit was cleared.
1: An overflow has occurred since the last time this bit was cleared.
4:2
Unused
Unused.
Read = 000b; Write = don’t care.
1:0 CLSEL[1:0] Cycle Length Select.
When 16-bit PWM mode is not selected, these bits select the length of the PWM
cycle, between 8, 9, 10, or 11 bits. This affects all channels configured for PWM which
are not using 16-bit PWM mode. These bits are ignored for individual channels configured to16-bit PWM mode.
00: 8 bits.
01: 9 bits.
10: 10 bits.
11: 11 bits.
320
Rev. 1.3
C8051F93x-C8051F92x
SFR Definition 26.4. PCA0CPMn: PCA Capture/Compare Mode
Bit
7
6
5
4
3
2
1
0
Name
PWM16n
ECOMn
CAPPn
CAPNn
MATn
TOGn
PWMn
ECCFn
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
SFR Address, Page: PCA0CPM0 = 0xDA, 0x0; PCA0CPM1 = 0xDB, 0x0; PCA0CPM2 = 0xDC, 0x0
PCA0CPM3 = 0xDD, 0x0; PCA0CPM4 = 0xDE, 0x0; PCA0CPM5 = 0xCE, 0x0
Bit
Name
Function
7
PWM16n 16-bit Pulse Width Modulation Enable.
This bit enables 16-bit mode when Pulse Width Modulation mode is enabled.
0: 8 to 11-bit PWM selected.
1: 16-bit PWM selected.
6
ECOMn
Comparator Function Enable.
This bit enables the comparator function for PCA module n when set to 1.
5
CAPPn
Capture Positive Function Enable.
This bit enables the positive edge capture for PCA module n when set to 1.
4
CAPNn
Capture Negative Function Enable.
This bit enables the negative edge capture for PCA module n when set to 1.
3
MATn
Match Function Enable.
This bit enables the match function for PCA module n when set to 1. When enabled,
matches of the PCA counter with a module's capture/compare register cause the CCFn
bit in PCA0MD register to be set to logic 1.
2
TOGn
Toggle Function Enable.
This bit enables the toggle function for PCA module n when set to 1. When enabled,
matches of the PCA counter with a module's capture/compare register cause the logic
level on the CEXn pin to toggle. If the PWMn bit is also set to logic 1, the module operates in Frequency Output Mode.
1
PWMn
Pulse Width Modulation Mode Enable.
This bit enables the PWM function for PCA module n when set to 1. When enabled, a
pulse width modulated signal is output on the CEXn pin. 8 to 11-bit PWM is used if
PWM16n is cleared; 16-bit mode is used if PWM16n is set to logic 1. If the TOGn bit is
also set, the module operates in Frequency Output Mode.
0
ECCFn
Capture/Compare Flag Interrupt Enable.
This bit sets the masking of the Capture/Compare Flag (CCFn) interrupt.
0: Disable CCFn interrupts.
1: Enable a Capture/Compare Flag interrupt request when CCFn is set.
Note: When the WDTE bit is set to 1, the PCA0CPM5 register cannot be modified, and module 5 acts as the
watchdog timer. To change the contents of the PCA0CPM5 register or the function of module 5, the Watchdog
Timer must be disabled.
Rev. 1.3
321
C8051F93x-C8051F92x
SFR Definition 26.5. PCA0L: PCA Counter/Timer Low Byte
Bit
7
6
5
4
3
2
1
0
PCA0[7:0]
Name
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
SFR Page = 0x0; SFR Address = 0xF9
Bit
Name
7:0
Function
PCA0[7:0] PCA Counter/Timer Low Byte.
The PCA0L register holds the low byte (LSB) of the 16-bit PCA Counter/Timer.
Note: When the WDTE bit is set to 1, the PCA0L register cannot be modified by software. To change the contents of
the PCA0L register, the Watchdog Timer must first be disabled.
SFR Definition 26.6. PCA0H: PCA Counter/Timer High Byte
Bit
7
6
5
4
3
2
1
0
PCA0[15:8]
Name
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
SFR Page = 0x0; SFR Address = 0xFA
Bit
Name
7:0
Function
PCA0[15:8] PCA Counter/Timer High Byte.
The PCA0H register holds the high byte (MSB) of the 16-bit PCA Counter/Timer.
Reads of this register will read the contents of a “snapshot” register, whose contents
are updated only when the contents of PCA0L are read (see Section 26.1).
Note: When the WDTE bit is set to 1, the PCA0H register cannot be modified by software. To change the contents of
the PCA0H register, the Watchdog Timer must first be disabled.
322
Rev. 1.3
C8051F93x-C8051F92x
SFR Definition 26.7. PCA0CPLn: PCA Capture Module Low Byte
Bit
7
6
5
4
3
2
1
0
PCA0CPn[7:0]
Name
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
SFR Addresses: PCA0CPL0 = 0xFB, PCA0CPL1 = 0xE9, PCA0CPL2 = 0xEB,
PCA0CPL3 = 0xED, PCA0CPL4 = 0xFD, PCA0CPL5 = 0xD2
PCA0CPL0 = 0x0, PCA0CPL1 = 0x0, PCA0CPL2 = 0x0,
PCA0CPL3 = 0x0, PCA0CPL4 = 0x0, PCA0CPL5 = 0x0
Name
Function
SFR Pages:
Bit
7:0
PCA0CPn[7:0] PCA Capture Module Low Byte.
The PCA0CPLn register holds the low byte (LSB) of the 16-bit capture module n.
This register address also allows access to the low byte of the corresponding
PCA channel’s auto-reload value for 9, 10, or 11-bit PWM mode. The ARSEL bit
in register PCA0PWM controls which register is accessed.
Note: A write to this register will clear the module’s ECOMn bit to a 0.
SFR Definition 26.8. PCA0CPHn: PCA Capture Module High Byte
Bit
7
6
5
4
3
2
1
0
PCA0CPn[15:8]
Name
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
SFR Addresses: PCA0CPH0 = 0xFC, PCA0CPH1 = 0xEA, PCA0CPH2 = 0xEC,
PCA0CPH3 = 0xEE, PCA0CPH4 = 0xFE, PCA0CPH5 = 0xD3
PCA0CPH0 = 0x0, PCA0CPH1 = 0x0, PCA0CPH2 = 0x0,
PCA0CPH3 = 0x0, PCA0CPH4 = 0x0, PCA0CPH5 = 0x0
Name
Function
SFR Pages:
Bit
7:0 PCA0CPn[15:8] PCA Capture Module High Byte.
The PCA0CPHn register holds the high byte (MSB) of the 16-bit capture module n.
This register address also allows access to the high byte of the corresponding
PCA channel’s auto-reload value for 9, 10, or 11-bit PWM mode. The ARSEL bit in
register PCA0PWM controls which register is accessed.
Note: A write to this register will set the module’s ECOMn bit to a 1.
Rev. 1.3
323
C8051F93x-C8051F92x
27. C2 Interface
C8051F93x-C8051F92x devices include an on-chip Silicon Labs 2-Wire (C2) debug interface to allow
Flash programming and in-system debugging with the production part installed in the end application. The
C2 interface uses a clock signal (C2CK) and a bi-directional C2 data signal (C2D) to transfer information
between the device and a host system. See the C2 Interface Specification for details on the C2 protocol.
27.1. C2 Interface Registers
The following describes the C2 registers necessary to perform Flash programming through the C2 interface. All C2 registers are accessed through the C2 interface as described in the C2 Interface Specification.
C2 Register Definition 27.1. C2ADD: C2 Address
Bit
7
6
5
4
3
Name
C2ADD[7:0]
Type
R/W
Reset
Bit
0
0
0
0
Name
0
2
1
0
0
0
0
Function
7:0 C2ADD[7:0] C2 Address.
The C2ADD register is accessed via the C2 interface to select the target Data register
for C2 Data Read and Data Write commands.
324
Address
Description
0x00
Selects the Device ID register for Data Read instructions
0x01
Selects the Revision ID register for Data Read instructions
0x02
Selects the C2 Flash Programming Control register for Data
Read/Write instructions
0xB4
Selects the C2 Flash Programming Data register for Data
Read/Write instructions
Rev. 1.3
C8051F93x-C8051F92x
C2 Register Definition 27.2. DEVICEID: C2 Device ID
Bit
7
6
5
4
3
Name
DEVICEID[7:0]
Type
R/W
Reset
0
0
0
1
0
C2 Address: 0x00
Bit
Name
7:0
2
1
0
1
0
0
Function
DEVICEID[7:0] Device ID.
This read-only register returns the 8-bit device ID: 0x16 (C8051F93x-C8051F92x).
C2 Register Definition 27.3. REVID: C2 Revision ID
Bit
7
6
5
4
3
Name
REVID[7:0]
Type
R/W
Reset
Varies
Varies
Varies
Varies
C2 Address: 0x01
Bit
Name
7:0
Varies
2
1
0
Varies
Varies
Varies
Function
REVID[7:0] Revision ID.
This read-only register returns the 8-bit revision ID. For example: 0x00 = Revision A.
Rev. 1.3
325
C8051F93x-C8051F92x
C2 Register Definition 27.4. FPCTL: C2 Flash Programming Control
Bit
7
6
5
4
3
Name
FPCTL[7:0]
Type
R/W
Reset
0
0
0
0
0
C2 Address: 0x02
Bit
Name
7:0
2
1
0
0
0
0
Function
FPCTL[7:0] Flash Programming Control Register.
This register is used to enable Flash programming via the C2 interface. To enable C2
Flash programming, the following codes must be written in order: 0x02, 0x01. Note
that once C2 Flash programming is enabled, a system reset must be issued to
resume normal operation.
C2 Register Definition 27.5. FPDAT: C2 Flash Programming Data
Bit
7
6
5
4
3
Name
FPDAT[7:0]
Type
R/W
Reset
0
0
0
0
C2 Address: 0xB4
Bit
Name
7:0
0
2
1
0
0
0
0
Function
FPDAT[7:0] C2 Flash Programming Data Register.
This register is used to pass Flash commands, addresses, and data during C2 Flash
accesses. Valid commands are listed below.
326
Code
Command
0x06
Flash Block Read
0x07
Flash Block Write
0x08
Flash Page Erase
0x03
Device Erase
Rev. 1.3
C8051F93x-C8051F92x
27.2. C2 Pin Sharing
The C2 protocol allows the C2 pins to be shared with user functions so that in-system debugging and
Flash programming may be performed. This is possible because C2 communication is typically performed
when the device is in the halt state, where all on-chip peripherals and user software are stalled. In this
halted state, the C2 interface can safely ‘borrow’ the C2CK (RST) and C2D pins. In most applications,
external resistors are required to isolate C2 interface traffic from the user application. A typical isolation
configuration is shown in Figure 27.1.
C8051Fxxx
RST (a)
C2CK
Input (b)
C2D
Output (c)
C2 Interface Master
Figure 27.1. Typical C2 Pin Sharing
The configuration in Figure 27.1 assumes the following:
1. The user input (b) cannot change state while the target device is halted.
2. The RST pin on the target device is used as an input only.
Additional resistors may be necessary depending on the specific application.
Rev. 1.3
327
C8051F93x-C8051F92x
DOCUMENT CHANGE LIST
Revision 1.0 to Revision 1.1
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

On front page, clarified that the SmaRTClock oscillator has an internal self-oscillate mode.
Updated block diagrams in system overview.
Updated mechanical package drawings for all three packages.
Added a new Absolute Maximum Rating specification for maximum total current through all Port pins.
Added additional data points for Sleep Mode current.
ADC0 Maximum SAR Clock frequency and Minimum Settling Time specifications updated. Also update
the turn-on time specification for the internal high speed VREF.
Updated Port I/O, Reset, IREF0, Comparator, and dc-dc converter specification tables.
Expanded note in ADC Data Register indicating that ADC0H:ADC0L should not be written when the
SYNC bit is set to 1.
Updated Figure 5.8 to correct order of operations in the temperature sensor transfer function equation.
Updated text which referred to the address as A[15:0]. The 12-bit address should be A[11:0].
Added a note to the FLSCL register description describing the need for a dummy 3-byte MOV
instruction following any operation that clears the BYPASS bit. Also updated the FLWR register
description indicating that writes to FLWR have no effect on system operation.
In the Flash chapter, added a note which says that 8-bit MOVX instructions cannot be used to erase or write
to Flash memory at addresses higher than 0x00FF.
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Updated chapter text and figures in the power management chapter.
Added a note to the CRC0CN register description describing the need for a dummy 3-byte MOV
instruction following any operation that initiates an automatic CRC operation.
Updated dc-dc converter diagram to properly show parasitic inductance.
Removed the requirement that the output voltage has to be at least 0.2 V higher than the input voltage.
Added several clarifications to the dc-dc converter chapter text.
Updated the CLKSEL register description.
In Table 19.1, changed the high end of the crystal frequency range to 25 MHz.
Globally changed “smaRTClock” to “SmaRTClock”.
Updated the RTC0PIN register description.
Updated recommend instruction timing for accessing indirect SmaRTClock registers. Polling ‘BUSY’ to
wait for data transfer is no longer required as long as the recommended instruction timing is followed.
Updated recommended crystal characteristics / operating conditions.
Added information on how to perform SmaRTClock oscillation robustness test.
Updated Port I/O Cell Diagram.
Corrected description of XBR0, bit 0. Also made minor updates to Port I/O chapter text.
Emphasized that port match is not available on P1.6 and P1.7 for ‘F931/’F921 devices.
Added a note to refer to the C8051F930 Errata when using the SMBus Hardware Acknowledge
Feature.
Updated text which refers to Timer 3, but references bits in the Timer 2 control register.
Updated text in PCA0 chapter related to the watchdog timer. The watchdog timer uses PCA module 5.
Re-formatted the PCA0CPMn register description to fit on a single page.
Revision 1.1 to Revision 1.2
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Removed references to AN338.
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Revision 1.2 to Revision 1.3
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Added labels to indicate center pad as “GND (optional)” to pinout diagrams in Figure 3.1 and
Figure 3.2.
Added package marking diagrams as Figure 3.4, Figure 3.5, and Figure 3.6 to help identify the silicon
revision.
Clarified conditions that apply to ‘VBAT Ramp Time for Power On’ for one-cell mode vs two-cell mode in
Table 4.4, “Reset Electrical Characteristics,” on page 59.
Updated Section “5.2.3. Burst Mode” on page 71 and Figure 5.3 to show difference in behavior
between internal convert start signals and external CNVSTR signal.
Added note about the need to ground the ADC mux before switching to the temperature sensor in
Section “5.6. Temperature Sensor” on page 86 and in SFR Definition 5.12 “ADC0MX”.
Updated Figure 7.4, “CPn Multiplexer Block Diagram,” to show CPnOUT pull-up voltage (inverted)and
to correct the locations of VDD/DC+, VBAT, Digital Supply, and GND multiplexer inputs.
Updated Table 8.1 to correct number of clock cycles for ‘CJNE A, direct, rel’.
Corrected VDD ramp time reference in item 2 of Section “13.5.1. VDD Maintenance and the VDD
Monitor” on page 153.
Updated CPT0WK bit description in SFR Definition 14.1, “PMU0CF”.
Added Section “15.2. 32-bit CRC Algorithm” on page 169 to illustrate the 32-bit CRC algorithm.
Updated Section “21.1.3. Interfacing Port I/O to 5 V and 3.3 V Logic” on page 218 to include notes
about sizing external pull-up resistors and other related information when using multi-voltage
interfaces.
Corrected clock sources associated with T3XCLK settings in Section “25.3.2. 8-bit Timers with AutoReload” on page 300, Figure 25.7, Figure 25.8, and Figure 25.9 to match the description in SFR
Definition 25.13.
Removed ‘SmaRTClock divided by 8’ from list of possible clock sources in text description in Section
“26. Programmable Counter Array” on page 305.
Replaced incorrect PCA channel references from PCA0CPH2 to PCA0CPH5 in Section
“26.4. Watchdog Timer Mode” on page 316 and Figure 26.11.
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