DRV8809 DRV8810 www.ti.com ............................................................................................................................................................... SLVS854A – JULY 2008 – REVISED JULY 2008 COMBINATION MOTOR DRIVERS WITH DC-DC CONVERTERS • FEATURES 1 • Configurable to Eight Modes of Combination Motor Driver – Bipolar Stepper Motor Driver – 16-Step Current-Mode Control – 800-mA Average Output Current as Stepper Motor Drive – DC Motor Driver – 800-mA Maximum Continuous Current and 8-A/500-ns or 3-A/100-ms Peak Current for Each DC Motor Drive – Low ON resistance Rds(ON) = 0.55 Ω at TJ = 25°C (Typ) 2 • • • • • • Three Integrated DC-DC Converters – On/Off Selectable Using C_SELECT Pin and Serial Interface – Outputs Programmable With External Resistor Network From 1.5 V to VDIN × 0.8 – 1.5-A Output Capability for All Three Channels 7-V to 40-V Operating Voltage Range for DC-DC Converters Two Serial Interfaces for Communications Thermally-Enhanced Surface-Mount 64-Pin QFP PowerPAD™ Package (Eco-Friendly – RoHS and No Sb/Br) Power-Down Function (Deep-Sleep Mode) Reset Signal Output (Active Low) Reset (All Clear) Control Input DESCRIPTION/ORDERING INFORMATION The DRV8809/DRV8810 provides an integrated motor driver solution. The chip has four H-bridges internally and is configurable to eight different modes of combination motor driver control. The output driver block for each H-bridge consists of N-channel power MOSFETs configured as full H-bridges to drive the motor windings. The stepper motor control has a 16-step mode programmable through the three-wire serial interface (SPI). The SPI input pins are 3.3-V compatible and 5-V tolerant. The DRV8809/DRV8810 has three DC-DC switch-mode buck converters to generate a programmable output voltage from 1.5 V to 80% of VDIN (Channel A) or up to 10 V (for Channel B and Channel C), with up to 1.5-A load current capability. The outputs are selected using the C_SELECT terminal at start-up or using serial interface during operation. An internal shutdown function is provided for overcurrent protection (OCP), short-circuit protection, overvoltage/undervoltage lockout (UVLO), and thermal shutdown (TSD). Also, the device has a reset function that operates at power on and at input to the In-Reset pin. ORDERING INFORMATION TA –20°C to 80°C (1) (2) PACKAGE (1) (2) Plastic QFP 64 (S-PQFP-G64) ORDERABLE PART NUMBER TOP-SIDE MARKING DRV8809A0PAP DRV8809A0PAP DRV8810A0PAP DRV8810A0PAP For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com. Package drawings, thermal data, and symbolization are available at www.ti.com/packaging. 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PowerPAD is a trademark of Texas Instruments Inc. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2008, Texas Instruments Incorporated DRV8809 DRV8810 SLVS854A – JULY 2008 – REVISED JULY 2008 ............................................................................................................................................................... www.ti.com BLOCK DIAGRAM (One Stepper Motor and Two DC Motor Drives) VM Cstorage 0.01uF VDIN Cbkt VM 0.1uF TH_OUT DCDC_MODE C_SELECT Vout 1 VCP Temperature Sens : Pre-TSD or Tsens (analog) OD_A DC/DC convertor Ch-A Voltage charge pump CP1 CP2 To To To Highside DC/DC H-bridges gate drive OUTA+ VM Motor Drive Output Control A Thermal Shut down RSA FBA OUTAMGND Vout 2 OD_B OUTB+ DC/DC convertor Ch-B VM FBB OD_C OUTB- OUTC+ Pre-Drive, Latch Registers & control circuitry DC/DC convertor Ch-C Stepper Motor RSB Regulator Internal supply Voltage Supervisory Vout 3 VM Motor Drive Output Control B VM Motor Drive Output Control C RSC DC Motor FBC OUTCMGND Freq divider for DC/DC In-Reset OSCD_mon OUTD+ OSCi 6.4MHz OSCM_mon LOGIC_OUT VM Motor Drive Output Control D Freq divider Motor PWM RSD nORT DC Motor OUTD- nSLEEP VREF_AB Setup / ex-setup registers LGND ENABLE_SD MTR Config ; Stepper x 2 Stepper + LDC Step + SDCx2 LDC + SDCx2 LDC x 2 SDC x 4 Large Stepper Ultra Large DC 2 Pin # 50 (NC) (NC) ENABLE_SD ENABLE_SD (NC) ENABLE_SD (NC) (NC) NC Serial Interface A-B STROBE_AB DATA_AB Pin # 54 (NC) (NC) (NC) (NC) (NC) ENABLE_SB (NC) (NC) Pin # 55 STROBE_AB STROBE_AB STROBE_AB ENABLE_LAB ENABLE_LAB ENABLE_SA STROBE_AB ENABLE_UL Pin # 61 Data_AB Data_AB Data_AB (NC) (NC) PHASE_SB Data_AB (NC) CLK_AB Pin # 62 CLK_AB CLK_AB CLK_AB PHASE_LAB PHASE_LAB PHASE_SA CLK_AB PHASE_UL VREF_CD Serial Interface C-D ENABLE_SC PHASE_SD PHASE_SC Pin # 51 STROBE_CD ENABLE_LCD ENABLE_SC ENABLE_SC ENABLE_LCD ENABLE_SC STROBE_CD (NC) Submit Documentation Feedback Pin # 59 Data_CD (NC) PHASE_SD PHASE_SD (NC) PHASE_SD Data_CD (NC) Pin # 60 CLK_CD PHASE_LCD PHASE_SC PHASE_SC PHASE_LCD PHASE_SC CLK_CD (NC) Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): DRV8809 DRV8810 DRV8809 DRV8810 www.ti.com ............................................................................................................................................................... SLVS854A – JULY 2008 – REVISED JULY 2008 PAP PACKAGE (TOP VIEW) 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 In-Reset nSLEEP CLK_AB DATA_AB CLK_CD DATA_CD OSCM_mon LGND nORT STROBE_AB (nc) LOGIC_OUT TH_OUT STROBE_CD (nc) C_SELECT PAP PACKAGE (TOP VIEW) Test-LGND MGND OUTA– RSA RSA OUTA+ MGND MGND OUTB+ RSB RSB OUTB– MGND LGND DCDC_MODE FBC 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 GND MGND OUTD– RSD RSD OUTD+ MGND MGND OUTC+ RSC RSC OUTC– MGND LGND OD_A OD_A OD_C OD_C OD_B OD_B FBB VCP OSCD_mon CP2 CP1 VDIN VDIN VDIN VM VREF_AB VREF_CD FBA 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 TERMINAL FUNCTIONS TERMINAL PULLUP/ PULLDOWN SHUNT RESISTOR NO. NAME IN SETUP MODE NAME IN OPERATION I/O DESCRIPTION 1 Test-LGND Test-LGND - Low power or analog ground 2 MGND MGND - Power ground for motor 3 OUTA- OUTA- O Motor-drive output for winding A– 4 RSA RSA I Channel A current-sense resistor 5 RSA RSA I Channel A current-sense resistor 6 OUTA+ OUTA+ O Motor-drive output for winding A+ 7 MGND MGND - Power ground for motor 8 MGND MGND - Power ground for motor 9 OUTB+ OUTB+ O Motor-drive output for winding B+ 10 RSB RSB I Channel B current-sense resistor 11 RSB RSB I Channel B current-sense resistor 12 OUTB- OUTB- O Motor-drive output for winding B– 13 MGND MGND - Power ground for motor 14 LGND LGND - 15 DCDC_MODE DCDC_MODE I Low-power or analog ground Up 200 kΩ DC-DC Ch-B/Ch-C operation mode select 16 FBC FBC I Feedback signal for DC-DC converter C 17 OD_C OD_C O Output for DC-DC switch mode regulator C 18 OD_C OD_C O Output for DC-DC switch mode regulator C 19 OD_B OD_B O Output for DC-DC switch mode regulator B 20 OD_B OD_B O Output for DC-DC switch mode regulator B 21 FBB FBB I Feedback signal for DC-DC converter B 22 VCP VCP - Charge pump capacitor Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): DRV8809 DRV8810 3 DRV8809 DRV8810 SLVS854A – JULY 2008 – REVISED JULY 2008 ............................................................................................................................................................... www.ti.com TERMINAL FUNCTIONS (continued) TERMINAL 4 PULLUP/ PULLDOWN SHUNT RESISTOR NO. NAME IN SETUP MODE NAME IN OPERATION I/O DESCRIPTION 23 OSCD_mon OSCD_mon O OSCD clock monitoring 24 CP2 CP2 - Charge-pump bucket capacitor (high side) 25 CP1 CP1 - Charge-pump bucket capacitor (low side) 26 VDIN VDIN Voltage supply for DC-DC converter 27 VDIN VDIN Voltage supply for DC-DC converter 28 VDIN VDIN 29 VM VM - Voltage supply for motors 30 VREF_AB VREF_AB I Voltage reference for maximum stepper motor current through A and B bridges 31 VREF_CD VREF_CD I Voltage reference for maximum stepper motor current through C and D bridges Voltage supply for DC-DC converter 32 FBA FBA I Feedback signal for DC-DC converter A 33 OD_A OD_A O Output for DC-DC switch mode regulator A 34 OD_A OD_A O Output for DC-DC switch mode regulator A 35 LGND LGND - Low-power or analog ground 36 MGND MGND - Power ground for motor 37 OUTC– OUTC– O Motor-drive output for winding C– 38 RSC RSC I Channel C current-sense resistor 39 RSC RSC I Channel C current-sense resistor 40 OUTC+ OUTC+ O Motor-drive output for winding C+ 41 MGND MGND - Power ground for motor 42 MGND MGND - Power ground for motor 43 OUTD+ OUTD+ O Motor-drive output for winding D+ 44 RSD RSD I Channel D current-sense resistor 45 RSD RSD I Channel D current-sense resistor 46 OUTD– OUTD– O Motor drive output for winding D– 47 MGND MGND - Power ground for motor 48 GND GND - Must be grounded 49 C_SELECT C_SELECT I Up 200 kΩ DC-DC converter selector 50 - ENABLE_SD I Down 100 kΩ Enable input for DC motor D control 50 - Reserved I Down 100 kΩ Reserved for DC motor operation 51 STROBE_CD ENABLE_SC I Down 100 kΩ Enable for DC motor C control 51 STROBE_CD ENABLE_LCD I Down 100 kΩ Enable for large DC motor CD control 51 STROBE_CD STROBE_CD I Down 100 kΩ Serial interface data strobe for H-bridge C, D stepper motor drive (latch on rising edge) 52 TH_OUT TH_OUT O Open drain 53 LOGIC OUT LOGIC OUT O Open drain Temperature-sensing output 54 - Reserved I Down 100 kΩ Reserved for four DC motor operation 54 - ENABLE_SB I Down 100 kΩ Enable for DC motor B control 55 STROBE_ AB STROBE_ AB I Down 100 kΩ Serial interface data strobe for H-bridge A, B stepper motor drive (latch on rising edge) 55 STROBE_AB ENABLE_LAB I Down 100 kΩ Enable for large DC motor AB control 55 STROBE_AB ENABLE_SA I Down 100 kΩ Enable for DC motor A control 56 nORT nORT O Open drain 57 LGND LGND - 58 OSCM_mon OSCM_mon O Open drain 59 DATA_CD PHASE_SD I Down Protection-monitoring output Reset output (open drain) Low power or analog ground OSCM clock monitoring 100 kΩ Serial input data for H-bridge C and D control Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): DRV8809 DRV8810 DRV8809 DRV8810 www.ti.com ............................................................................................................................................................... SLVS854A – JULY 2008 – REVISED JULY 2008 TERMINAL FUNCTIONS (continued) TERMINAL NO. NAME IN SETUP MODE NAME IN OPERATION I/O PULLUP/ PULLDOWN SHUNT RESISTOR 59 DATA_CD DATA_CD I Down 100 kΩ Serial input data for H-bridge C and D control 60 CLK_CD PHASE_SC I Down 100 kΩ Phase input for DC motor C control 60 CLK_CD CLK_CD I Down 100 kΩ Clock input synchronization for serial data CD 60 CLK_CD PHASE_LCD I Down 100 kΩ Phase input for large DC motor CD control 61 DATA_AB DATA_AB I Down 100 kΩ Serial input data for H-bridge A and B control 61 DATA_AB PHASE_SB I Down 100 kΩ Phase input for DC motor B control 62 CLK_AB CLK_AB I Down 100 kΩ Clock input synchronization for serial data AB 62 CLK_AB PHASE_LAB I Down 100 kΩ Phase input for large DC motor AB control 62 CLK_AB PHASE_SA I Down 100 kΩ Phase input for DC motor A control 63 nSLEEP=L nSLEEP I Down 100 kΩ Enable/disable (part can be in sleep state) 64 In-Reset In-Reset I Up 200 kΩ Reset (L: Reset, H/open: Normal operation) DESCRIPTION Table 1. Alternate Functions of Select Pins By Operation Mode CONFIG PIN 50 51 54 55 59 60 61 62 Default Name ENABLE_SD ENABLE_SC ENABLE_SB STROBE_AB PHASE_ SD PHASE_SC DATA_AB CLK_AB Dual Stepper - STROBE_CD - STROBE_AB DATA_CD CLK_CD DATA_AB CLK_AB Stepper + Large DC - ENABLE_LCD - STROBE_AB - PHASE_LCD DATA_AB CLK_AB Stepper + Dual Small DC ENABLE_SD ENABLE_SC - STROBE_AB PHASE_SD PHASE_SC DATA_AB CLK_AB Large DC + Dual Small DC ENABLE_SD ENABLE_SC - ENABLE_LAB PHASE _SD PHASE_SC - PHASE_LAB Dual Large DC - ENABLE_LCD - ENABLE_LAB - PHASE_LCD - PHASE_LAB Quad Small DC ENABLE_SD ENABLE_SC ENABLE_SB ENABLE_SA PHASE_SD PHASE_SC PHASE_SB PHASE_SA Large Stepper - STROBE_CD - STROBE_AB DATA_CD CLK_CD DATA_AB CLK_AB Ultra-Large DC - - - ENABLE_UL - - - PHASE_UL Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): DRV8809 DRV8810 5 DRV8809 DRV8810 SLVS854A – JULY 2008 – REVISED JULY 2008 ............................................................................................................................................................... www.ti.com Internal 3.3v supply 200k ohm (+/- 40%) 1) Pin open ; 3.0 to 3.3v ; A /ON, B /ON, C /ON 2) External R to GND ( 200kO +/-10% ); 1.3 to 2.0v ; DC_MODE Dependant # C_SELECT Soft start Control 3) GND; 0.0 to 0.3v ; All off GND Internal 3.3v supply 200k ohm (+/- 40%) # DCDC_MODE # In-Reset Hysteresis Deglitch Reset Control Deglitch is for In-Reset only GND # nSLEEP # ENABLE_x # STROBE_CD/ENABLE # STROBE_AB/ENABLE # DATA_CD/PHASE # CLK_CD/PHASE # DATA_AB/ENABLE # CLK_AB/ENABLE Hysteresis Serial Interface 100k ohm (+/- 30%) GND GND External 3.3v supply 1k ohm ( external ) # Th_OUT # LOGIC_OUT # nORT # OSCM_mon # OSCD_mon GND Figure 1. Input Pin Configurations External 3.3 V supply # Th_out # Logic_out # nORT 1 kW (external) # OSCM_mon # OSCD_mon GND Figure 2. Open-Drain Output Pin Configurations 6 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): DRV8809 DRV8810 DRV8809 DRV8810 www.ti.com ............................................................................................................................................................... SLVS854A – JULY 2008 – REVISED JULY 2008 ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) Supply voltage (1) VM 50 V Logic input voltage range, serial I/F inputs, and reset (2) –0.3 V to 5.5 V Continuous total power dissipation (θJA = 20°C/W) 4W Continuous motor-drive output current for each H-bridge (100 ms) 3A Peak motor-drive output current for each H-bridge (500 ns) 8A Continuous DC-DC converter output current 1.5 A Continuous DC-DC converter output current ODB, C in parallel mode TJ Operating junction temperature range (1 h) Tstg Storage temperature range 3.0 A 0°C to 150°C –65°C to 150°C Lead temperature 1.6 mm (1/16 in) from case for 10 s 260°C ESD levels on every pin, Human-Body Model (HBM) (1) (2) 2 kV Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The negative spike less than –5 V and narrower than 50-ns duration should not cause any problem. RECOMMENDED OPERATING CONDITIONS MIN NOM MAX 18 27 40 7 27 40 V Average output current for motor driver for each H-bridge 800 mA DC output current for DC-DC converter 1.2 A DC output current for DC-DC in Ch-B/C parallel mode 2.4 A Supply voltage, VM for motor control Supply voltage for DC-DC converter (VDIN) UNIT V Operating ambient temperature –10 50 °C Operating junction temperature 0 120 °C ELECTRICAL CHARACTERISTICS TJ = 0°C to 120°C, VM = 40 V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Supply (Sleep) Current ISLEEP1 Supply (sleep) current 1 nSLEEP = L, DC-DC all off 4 5 mA ISLEEP2 Supply (sleep) current 2 nSLEEP = L, VM = 8 V, Full duty cycle 7 10 mA ISLEEP3 Supply (sleep) current 3 nSLEEP = L, VM = 40 V, Full duty cycle 8 10 mA MAX UNIT ELECTRICAL CHARACTERISTICS TJ = 0°C to 120°C, VM = 7 V to 40 V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP Digital Interface Circuit VIH Digital high-level input voltage Digital inputs (1) IIH Digital high-level input current Digital inputs VIL Digital low-level input voltage Digital inputs 0.8 V IIL Digital low-level input current Digital inputs 100 µA Vhys Digital input hysteresis Digital inputs 0.3 0.6 V Tdegl Digital input deglitch time In-Reset 2.5 7.5 µs (1) 2 0.45 5 V 100 µA Absolute maximum rating for charge-pump circuit is 60 V. Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): DRV8809 DRV8810 7 DRV8809 DRV8810 SLVS854A – JULY 2008 – REVISED JULY 2008 ............................................................................................................................................................... www.ti.com ELECTRICAL CHARACTERISTICS (continued) TJ = 0°C to 120°C, VM = 7 V to 40 V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Charge-Pump VCP (＝P = 0.1 µF to 0.47 µF, Cbk = 0.01 µF ± 10%) VO(CP) Output voltage f(CP) Switching frequency tstart Start-up time ILOAD = 0 mA, VM > VthVM2 CStorage = 0.1 µF, VM ≥ 16 V VM + 10 VM + 13 1.6 V MHz 0.5 2 ms Internal Clock OSCi fOSCi System clock frequency 5.76 6.4 7.04 MHz VREF Reference voltage input 0.8 2.5 3.6 V Ileak-vr Input leak current 1 µA VREF Input C_SELECT for DC-DC Start-Up Selection (DCDC_MODE = L) Vcs0 DC-DC all off Vcs1 Turn on ODB then ODA Pull down by external 200-kΩ resistor Vcs2 Turn on ODB then ODC As pin open 0 0.3 V 1.3 2 V 3 3.3 V 0 0.3 V 1.3 2 V 3 3.6 V C_SELECT for DC-DC Start-Up Selection (DCDC_MODE = H or Open, Ch-B/C Parallel Mode) Vcs0 DC-DC all off Vcs1 Turn on ODB/C then ODA Pull down by external 200-kΩ resistor Vcs2 Turn on ODA then ODB/C As pin open Three DC-DC Converters (2) 1.25 = VO VDINOPE Operating supply voltage Ratio to VOUT(DC) VoutA = 1.5 V – 30 V, VoutB/C = 1.5 V – 10 V, Programmable with external reference on FBX × VDIN > 1.25 × Vout (largest) 20 V ≤ VDIN < 40 V –3 VO 3 ODA ODB ODC 6.5 V ≤ VDIN < 20 V –3 VO 5 –3 VO 5 VFB FBX feedback voltage For ODA/B/C IO ODx ODx output current (dc) With external L and C IO ODBC ODBC output current (DC) in Ch-B/Ch-C parallel mode With external L and C DCDC_MODE = H IO ODx2 Output current (dc) at low VDIN VDIN = 7 V, IO ODx3 Output current (dc) at low VDIN VDIN = 7 V, fOSCD Switching (chopping frequency) fOSCD = (0,0) Rds(ON) FET ON resistance at 0.8 A for OD_x TJ = 25°C VthVM– < VDIN < 6.5 V, VO ≤ 3.3 V 1.50 VO voltage to 5.5 V Vo_min6 (2) (3) (4) 8 V A 3 A VO = 5 V 0.8 A VO = 3.3 V 1.5 A 110 kHz 90 100 0.35 TJ = 120°C 0.50 VDIN = VthV_, VthV_ = 5-V load (dc) = 0.5 A (3) 4 V % 1 VthVM+ = 6-V load (DC) = 0.5 A (4) Ω –30 VO voltage drop from VDIN VO setting without kick UVP when VDIN = VthVM+ (VO setting at VDIN = 10 V) % 1.5 5.5-V VO at VDIN = VthV_ 5 V-Low V 6 V V DCDC_MODE = H, Ch-B and Ch-C are in parallel driving mode. Lower VDIN decrease gate drive and the voltage drop is increased. Specified by bench characterization only. VOUT (at VDIN = VthVM+) is lower than VO setting. When VDIN is down to VthVM+, undervoltage protection (UVP) shuts down the device, in case the VO is set as VO > 7 V. Specified by design. Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): DRV8809 DRV8810 DRV8809 DRV8810 www.ti.com ............................................................................................................................................................... SLVS854A – JULY 2008 – REVISED JULY 2008 ELECTRICAL CHARACTERISTICS (continued) TJ = 0°C to 120°C, VM = 7 V to 40 V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Three DC-DC Converter Protection IO DD ODx Overcurrent detect for OD_x source Peak current in each ON cycle tFILTOCP OCP filtering time By OSCi cycles 2 cycles tODSD DC-DC shutdown filter Number of subsequent chopping cycles with OCP detection 4 chop cycles Vovpx Overvoltage protection (OVP) Percentage of nominal Voutx detected at VFB 25 30 35 % Vuvpx Undervoltage protection (UVP) Percentage of nominal Voutx detected at VFB (VFB decreasing) -25 -30 -35 % tVfilter OVP/UVP filtering time 3 8 13 us tsst Start-up time with soft start 56 ms Vstover Start-up overshoot Ratio to VO 3 % VthVM– nORT for VM low threshold VM decreasing 4.5 5 6 V VthVM+ nORT for VM high threshold VM increasing 5.5 6 7 V VthVMh nORT for VM detect hysteresis (VthVM+) - (VthV—) 0.5 1 VthVM2 For motor driver off tVM filt VM monitor filtering time 1.8 3 A VM Supervisory (5) For VM threshold detect 10 V 15 V 30 µs Thermal Shutdown (TSD) TTSD Thermal shutdown set points 150 170 190 °C Temperature Sense, Pre TSD (See Extended Setup Register Definition) TTSD0 Temperature sense point 0 Register selectable, Assert logic H at TH_OUT 130 150 170 °C TTSD1 Temperature sense point 1 Register selectable, Assert logic H at TH_OUT 120 140 160 °C Tc_sens TH_OUT (analog out) temperature coefficient Specified by design 6 mV/°C RESET/nORT: Open-Drain Outputs (nORT, LOGIC_OUT, TH_OUT) VOH High-state voltage RL = 1 kΩ to 3.3 V 3 V VOL Low-state voltage RL = 1 kΩ to 3.3 V IOL Low-state sink current VO = 0.4 V tr Rise time 10% to 90% 1 µs tf Fall time 90% to 10% 50 ns 390 ms 0.3 3 V mA RESET/nORT Delay: Start-Up Sequence tord1 nORT delay 1 Reset deassertion from VthVM+ < VDIN for DC-DC wake up falling 300 tord3 DC-DC turnon delay From one DC-DC wake up to following DC-DC to go soft-start sequence 1.7 tord4 nORT delay 4 Reset deassertion from 2nd DC-DC wake up 120 180 ms In-Reset assertion to nORT assertion delay In-Reset falling to nORT failing 5 10 µs ms In-Reset treset (5) No nORT assertion to VthVM2 detection Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): DRV8809 DRV8810 9 DRV8809 DRV8810 SLVS854A – JULY 2008 – REVISED JULY 2008 ............................................................................................................................................................... www.ti.com ELECTRICAL CHARACTERISTICS (continued) TJ = 0°C to 120°C, VM = 7 V to 40 V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT H-Bridge Drivers (OUTx+ and OUTx–) IOUT1(max) Peak output current 1 Less than 500-ns period 8 A IOUT2(max) Peak output current 2 Less than 100-ms period 3 A IOUT(max) Average continuous output current 0.8 A Rds(ON) FET ON resistance at 0.8 A ICEX Output leakage current VOUTX = 0 V or 10 V 10 µA IRS Sense resistor supply current nORT = Low 15 µA IOC Motor Motor overcurrent threshold for each H-bridge (6) 5 A tfilterM Motor overcurrent filter time fOSCM Motor oscillator frequency fchop Motor chopping frequency = fOSCM/8 TJ = 25°C 0.55 TJ = 120°C 1 3 Ω 2.5 5 8.5 µs F_OSCM = (0,0) 720 800 880 kHz F_OSCM = (0,0) 90 100 110 kHz Stepper Motor Drive (Parameters Are Tested Without Motor Loading) ISTEPMOTORAVG Average stepper motor current for H-bridge VM = 40 V 800 mA ISTEPMOTORPeak Peak stepper motor current for H-bridge VM = 40 V 1.3 A Stepper motor current limit threshold (internal reference) (7) VL16 , Phase angle = 90° 100 VL15 , Phase angle = 84° 100 VL14 , Phase angle = 79° 98 VL13 , Phase angle = 73° 96 VL12 , Phase angle = 68° 92 VL11 , Phase angle = 62° 88 VL10 , Phase angle = 56° 83 VL9 , Phase angle = 51° 77 VL8 , Phase angle = 45° 71 VL7 , Phase angle = 40° 63 VL6 , Phase angle = 34° 56 VL5 , Phase angle = 28° 47 VL4 , Phase angle = 23° 38 VL3 , Phase angle = 17° 29 VL2 , Phase angle = 11° 20 VL1 , Phase angle = 6° 10 VL0 , Phase angle = 0° 0 IOUT Output current accuracy at 100% Excludes VREF and RSENS errors, setting (7) IOUT > 1 A (7) (8) IswLeakage Switch (driver MOSFET) leakage Outputs off current tab Stepper motor blanking time (6) (7) (8) 10 By OSCi cycles % –5 5 % –10 10 µA 8 9 cycles When the overcurrent is detected, all H-bridges are shut down and assert nORT pulse (40 ms). This is not measured directly, checked by Itrip amplifier gain without motor loading This device may show current setting error when motor current is less than 1 A, due to noise filter delay at the Itrip comparator. Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): DRV8809 DRV8810 DRV8809 DRV8810 www.ti.com ............................................................................................................................................................... SLVS854A – JULY 2008 – REVISED JULY 2008 ELECTRICAL CHARACTERISTICS (continued) TJ = 0°C to 120°C, VM = 7 V to 40 V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Stepper and DC Motor Drivers tr Rise time VM = 27 V 100 300 ns tf Fall time 20% to 80% 100 300 ns tPDOFF Enable or strobe detection to sink or source gate off delay tCOD Crossover delay time, to prevent shoot through tPDON Enable or strobe detection to sink or source gate on delay 50 150 400 ns 100 600 1000 ns 750 ns DC Motor Drivers TBLNK = (0,0) for Min, (1,1) for Max, fCHOP = 100 kHz 5.65 µs Minimum pulse duration (phase) 1 µs Minimum pulse duration (enable) 1 µs 25 MHz tblank Blanking time twPminp twPmine 1.6 Serial Interface f(CLK) Clock frequency 1 twh(CLK) Minimum high-level pulse width 10 ns twl(CLK) Minimum low-level pulse width 10 ns tsu Setup time, data to CLK↓ 10 ns th Hold time, CLK↓ to data 10 ns tcs CLK↓ to STROBE↑ 10 ns tsc STROBE↓ to CLK↑ 10 ns tw(STRB) Minimum strobe pulse duration 20 tss_min Strobe mask time from nSLEEP 1.5 ns 4 µs Serial Interface: ID Monitor Function at LOGIC_OUT, Extended Setup Mode tODL 0 data output delay bit 3 to bit 0 (ext-setup) = (1100) From strobe rise to LOGIC_OUT, 1 kΩ to external 3.3 V 4000 ns tODH 1 data output delay bit 3 to bit 0 (ext-setup) = (1111) From strobe rise to LOGIC_OUT, 1 kΩ to external 3.3 V 4000 ns Serial Interface The device has two serial interface circuit blocks for stepper motor driving control. These two serial interfaces provide controls to each motor driver independently. CLKAB Serial clock for H-bridge A, B DATAAB Serial data for H-bridge A, B STROBEAB Strobe input for H-bridge A, B CLKCD Serial clock for H-bridge C, D DATACD Serial data for H-bridge C, D STROBECD Strobe signal for H-bridge C, D Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): DRV8809 DRV8810 11 DRV8809 DRV8810 SLVS854A – JULY 2008 – REVISED JULY 2008 ............................................................................................................................................................... www.ti.com Sixteen bits serial data is shifted into the least significant bit (LSB) of the serial data input (DATA) shift register on the falling edge of the serial clock (CLK). After 16 bits of data transfer, the strobe signal (Strobe) rising edge latches all the shifted data. During data transfer, Strobe voltage level is acceptable high or low. DATA 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 CLK Strobe Figure 3. Serial Interface Setup Mode/Power-Down Mode The motor output mode is configured through serial interface (DATA AB, CLK AB and STROBEAB) when nSLEEP = L. After setup, the nSLEEP pin must be pulled high for normal motor drive control. The condition that the device requires for setup (initialization) is after the nORT (Reset) output goes to high from the low level (power on, recovery from VM < 7 V). While nSLEEP is low, all the motor drive functions are shut down and their outputs are high-impedance state. Also the stepper parameters in the register are all reset to 0. This device forces motor driver functions to shut down for the power-down mode, and it is not damaged even if nSLEEP is asserted during motor driving. At the Strobe pulse rising edge, the DATA signal level must be low for normal setup mode (see Extended Setup Mode for another option). Extended Setup Mode While nSLEEP = L, if the DATA signal level is set high when the Strobe pulse is set, the serial interface recognizes the input data to set the extended setup mode. This extended setup register enables monitoring and controlling the fault condition of this chip. One of the internal protection control signals is selected and provided to LOGIC OUT pin. Also, this enables the application to ignore the protection control and/or suppress the reset signal generation. This device has device ID (3-bit ROM) and vendor ID (1-bit ROM), which can be read out from LOGIC OUT. Four bits are assigned to select the LOGIC OUT signal, including the ID ROM bit readout. 12 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): DRV8809 DRV8810 DRV8809 DRV8810 www.ti.com ............................................................................................................................................................... SLVS854A – JULY 2008 – REVISED JULY 2008 Serial Interface A-B: Set A-B motor operating parameters and access to setup/extended setup register 16-bit shift register 16-bit latch (A-B drivers) Latch select 16-bit latch (setup) 16-bit latch (extended setup) Protection detect signal selector or Device ID/Vendor ID (ROM) A. A-B register at EXT-setup mode has device/vendor ID ROM. The ID must be read out at LOGIC OUT pin. Figure 4. Serial Interface A-B Serial interface C-D: Set C-D motor operating parameters Data 16-bit shift register Clock Strobe 16-bit latch (C-D drivers) Figure 5. Serial Interface C-D Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): DRV8809 DRV8810 13 DRV8809 DRV8810 SLVS854A – JULY 2008 – REVISED JULY 2008 ............................................................................................................................................................... www.ti.com Serial Interface Timing Bit 0 Data tsu Bit 1 Bit 14 Bit 15 th Clock twl(clk) tcs twh(clk) Strobe tw(strb) nSleep Figure 6. nSLEEP = H: Set Stepper Motor Operating Parameters Data Bit 0 Bit 1 tsu Bit 15 Bit 16 = L th Clock twl(clk) twh(clk) tcs Strobe tw(strb) tss_min nSleep ( Don't care ) Figure 7. nSLEEP = L (Bit 16 = L): Setup Mode Data Bit 0 Bit 1 tsu Bit 15 Bit 16 = H th Clock twl(clk) twh(clk) tcs Strobe tw(strb) tss_min nSleep A. ( Don't care ) For initial setup, nSLEEP state can be don’t care before the tss_min timing prior to the strobe. Figure 8. nSLEEP = L (Bit 16 = H): Extended Setup Mode 14 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): DRV8809 DRV8810 DRV8809 DRV8810 www.ti.com ............................................................................................................................................................... SLVS854A – JULY 2008 – REVISED JULY 2008 Setup Register Bit Assignment Setup register bits are assigned for motor configuration, blanking time, gain, and DC-DC switches. This register can be accessed only in Setup mode (nSLEEP = L and bit 16 data = L) . Table 2. Setup Register BIT NO. NAME DEFAULT 0 Motor select 0 0 DESCRIPTION 1 Motor select 1 0 2 Motor select 2 0 3 TBLNK AB0 0 4 TBLNK AB1 0 5 TBLNK CD0 0 6 TBLNK CD1 0 7 DC/DC_A SW 0 DC-DC ODA control, 0: ON (default), 1: OFF 8 DC/DC_B SW 0 DC-DC ODB control, 0: ON (default), 1: OFF 9 DC/DC_C SW 0 DC-DC ODC control, 0: ON (default), 1: OFF This bit is ignored when DCDC_MODE = H or open 10 Motor_AB gain 0 0: 1/10 (default), 1: 0 11 Motor_CD gain 0 0: 1/10 (default), 1: 0 12 OSCD frequency 0 0 13 OSCD frequency 1 0 <1,0> = (0,0) 100 kHz (default) (0,1) 50 kHz (1,0) 200 kHz (1,1) 132.5 kHz These setup bits can be changed when the DC-DC regulators are in operation. 14 OSCM frequency 0 0 15 OSCM frequency 1 0 Motor configuration, < 2,1,0 > (0,0,0): Stepper × 2 (default) (0,0,1): Stepper + LDC, (0,1,0): Stepper + 2 × sDCs (0,1,1): DCL + 2 × sDC, (1,0,0): DCL × 2 (1,0,1): 4 × sDC (1,1,0): Large stepper (1,1,1): Ultra-large DC Tblank for DC motor driving, Tblank is inserted at any phase change and beginning of each chopping cycle. AB1 AB0: Blanking time for A/B side drivers, CD1 CD0: Blanking time for C/D side drivers, 00: (1 ÷ fCHOP) ÷ 8 × 5 (= 6.25 µs) (default) 01: (1 ÷ fCHOP) ÷ 8 × 6 (= 7.50 µs) 10: (1 ÷ fCHOP) ÷ 8 × 3 (= 3.75 µs) 11: (1 ÷ fCHOP) ÷ 8 × 4 (= 5.00 µs) For stepper motor driving, only the fixed blanking time is applied. <1,0> = (0,0) 800 kHz (default) (0,1) 400 kHz (1,0) 1.06 MHz (1,1) 1.6 MHz The device can be configured to one out of eight different motor control combination modes. When the device is powered on or is recovering from reset, the mode can be selected by writing to the setup register through the serial interface AB, during Setup mode (nSLEEP = L). Table 3. DC and Stepper Motor Configuration SETUP REGISTER H-BRIDGE AND MOTOR CONFIGURATION BIT 2 BIT 1 BIT 0 0 0 0 OUTA+, OUTA– Stepper motor drive Stepper motor drive 0 0 1 Stepper motor drive Large DC motor drive 0 1 0 Stepper motor drive DC motor drive DC motor drive 0 1 1 Large DC motor drive DC motor drive DC motor drive 1 0 0 Large DC motor drive 1 0 1 1 1 0 Large stepper motor drive: A + B for first winding, C + D for second winding 1 1 1 Ultra-large DC motor drive DC motor drive OUTB+, OUTB– OUTC+, OUTC– OUTD+, OUTD– Large DC motor drive DC motor drive DC motor drive DC motor drive Default setting is (M0, M1, M2) = (0, 0, 0) Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): DRV8809 DRV8810 15 DRV8809 DRV8810 SLVS854A – JULY 2008 – REVISED JULY 2008 ............................................................................................................................................................... www.ti.com Extended setup (EX-setup) register bits are assigned for protection control, pre TSD, and multiplexer test mode selection. This register can be accessed only in Setup mode (nSLEEP = L and bit 16 data = H). Table 4. Extended Setup Register (EX-setup) Bit Assignment BIT NO. NAME DEFAULT 0 Signal select 0 0 1 Signal select 1 0 2 Signal select 2 0 3 Signal select 3 0 Signal selector monitored on LOGIC_OUT DC-DC OCP detection, DC-DC voltage supervisor (OVP or UVP), Motor overcurrent (four H-bridges), TSD, etc. [shutdown (protection) signals must be latched] 4 Ignore SD 0 0 0 = Normal operation, 1 = Ignore DC-DC OCP 5 Ignore SD 1 0 0 = Normal operation, 1 = Ignore DC-DC voltage supervisor 6 Ignore SD 2 0 0 = Normal operation, 1 = Ignore motor OCP 7 Ignore SD 3 0 0 = Normal operation, 1 = Ignore thermal shutdown 8 Disable nORT 0 (selective shutdown for DC-DC Ch-C) 0 0 = Normal operation 1 = Disable nORT assertion but shut down DC-DC Ch-C, in case of DC-DC Ch-C fault condition Ch-C shutdown is released by nSLEEP rise edge. If fault condition is on the other channels (with bit = 0), assert nORT and shut down all three DC-DC channels. This bit is ignored when DCDC_MODE = H or open 9 Disable nORT 1 (Selective shutdown for DC-DC Ch-B) 0 0 = Normal operation 1 = Disable nORT assertion but shut down DC-DC channel B, in case of DC-DC Ch-B fault condition Ch-B shutdown is released by nSLEEP rise edge. If fault condition on the other channels (with bit = 0), assert nORT and shut down all three DC-DC channels. 10 Disable nORT 2 (Selective shutdown for DC-DC Ch-A) 0 0 = Normal operation, 1 = Disable nORT assertion but shutdown the DC-DC Ch-A, in case of DC-DC Ch-A fault condition. Ch-A shutdown is released by nSLEEP rise edge. If fault condition on the other channels (with bit is 0), assert nORT and shut down all three DC-DC channels . 11 Pre TSD 0 0 0 = Ttsd0 = Ttsd - 20°C, 1 = Ttsd1= Ttsd - 30°C 12 Pre TSD 1 0 0 = Pre-TSD (logic) output, 1 = TH_OUT Analog output 13 Test mux 0 0 14 Test mux 1 0 15 Test mux 2 0 16 DESCRIPTION Test mode selection, < 2,1,0 > = (0,0,0) Normal operation (0,0,1) TSD control – 1, (0,1,0) TSD control – 2, (0,1,1) OSC monitor enable, Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): DRV8809 DRV8810 DRV8809 DRV8810 www.ti.com ............................................................................................................................................................... SLVS854A – JULY 2008 – REVISED JULY 2008 Table 5. LOGIC OUT Selection NO. EX-setup REGISTER (BITS 3–0) 0 0000 (default) DC-DC OCP_A DC-DC OVP_A DC-DC UVP_A Latched out 1 0001 DC-DC OCP_B DC-DC OVP_B DC-DC UVP_B Latched out 2 0010 DC-DC OCP_C DC-DC OVP_C DC-DC UVP_C Latched out 3 0011 DC-DC OCP_A DC-DC OCP_B DC-DC OCP_C Latched out 4 0100 DC-DC OVP_A DC-DC OVP_B DC-DC OVP_C Latched out 5 0101 DC-DC UVP_A DC-DC UVP_B DC-DC UVP_C Latched out 6 0110 Motor OCP Latched out 7 0111 TSD Latched out 8 1000 Revision <0> = 1: For this device <2,1,0> = (1,0,1) = 5 ROM 9 1001 Revision <1> = 0: For this device ROM 10 1010 Revision <2> = 1: For this device ROM 11 1011 Vendor <0> = 0: For TI <1,0> = TI (0,0), NG (1,0) ROM 12 1100 Vendor <1> = 0: For TI <1,0> = Reserve (0,1), (1,1) ROM 13 1101 Internal oscillator clock (as divided by 32 = 200 kHz) 14 1110 Fixed value as 1 (open-drain output buffer off) 15 1111 Fixed value as 1 (open-drain output buffer off) SIGNAL SELECTION MONITORED ON LOGIC OUT (LISTED SIGNALS TO BE MUXED BY OR) SIGNAL POINT This bit is ignored when DCDC_MODE pin = H or open. Table 6. Test Mux Selection NO. BITS 15, 14, 13 0 0, 0, 0 Normal operation DESCRIPTION 1 0, 0, 1 TSD control 1 At TSD event, shut down only motor driver part, DC-DC keep ON, keep setup register values, motor shutdown released by nSLEEP = L, no nORT assertion 2 0, 1, 0 TSD control 2 At TSD event, shut down only motor driver part, DC-DC keep ON, keep setup register values, motor shutdown released by nSLEEP = L, nORT assertion: 40-ms single pulse 3 0, 1, 1 OSC monitor enable Provide clock to OSCD_mon and OSCM_mon pins The serial interfaces communicate to the stepper parameter registers during nSLEEP = H . When nSLEEP = L, all register values are cleared. (1) (2) Table 7. Register Settings for Stepper Motor Driving Parameter (1) (2) (1) BIT NO. NAME DEFAULT VALUE 0 Torque 0 0 1 Torque 1 0 2 Decay B(D)0 0 3 Decay B(D)1 0 DESCRIPTION Torque control, b1 b0 00 equates to 50% 01 equates to 70 % 10 equates to 85% 11 equates to 100% Specified by design Decay mode control (1) B(D)1, B(D)0: 00 equates to 12.5 % (do not use) 01 equates to 37.5 % (do not use) 10 equates to 75% 11 equates to fast decay Specified by design This device has issues with stepper motor current setting accuracy. Decay mode should be 75% or fast decay (do not use mode 00 and 01) in this device. Decay mode should be 75% or fast decay (do not use mode 00 and 01) in this device. Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): DRV8809 DRV8810 17 DRV8809 DRV8810 SLVS854A – JULY 2008 – REVISED JULY 2008 ............................................................................................................................................................... www.ti.com Table 7. Register Settings for Stepper Motor Driving Parameter (continued) BIT NO. NAME DEFAULT VALUE 4 Current B(D)0 0 5 Current B(D)1 0 6 Current B(D)2 0 7 Current B(D)3 0 8 Phase B(D) 0 9 Decay A(C)0 0 10 Decay A(C)1 0 11 Current A(C)0 0 12 Current A(C)1 0 13 Current A(C)2 0 14 Current A(C)3 0 15 Phase A(C) 0 DESCRIPTION Phase B(D) current level setting (1) Control direction of current flow through winding B(D). A logic 1 allows conventional current flow from OUTB(D)+ to OUTB(D)–. Decay mode control (1) A(C)1, A(C)0: 00 equates to 12.5 % (do not use) 01 equates to 37.5 % (do not use) 10 equates to 75% 11 equates to fast decay Phase A current level setting (1) Control direction of current flow through winding A(C). A logic 1 allows conventional current flow from OUTA(C)+ to OUTA(C)–. Table 8. Torque Control Bit VREF INPUT CONTROL MOTOR TORQUE BIT VALUE ROUGH OUTPUT CURRENT SETTING Torque 0, 1 = 0, 0 50% high power consumption, I(max) = VREF * gain/RSense Torque 0, 1 = 0, 1 70% power Torque 0, 1 = 1, 0 85% power Torque 0, 1 = 1, 1 100% power Table 9. Decay Mode Control Bit BIT VALUE DECAY MODE SETTING Decay x0, x1 = 0, 0 12.5% decay mode (do not use) Decay x0, x1 = 0, 1 37.5% decay mode (do not use) Decay x0, x1 = 1, 0 75% decay mode Decay x0, x1 = 1, 1 100% fast decay mode Table 10. Current Flow Direction Bit BIT VALUE CURRENT DIRECTION Phase X = 0 OUTx+ = L, OUTx– = H Phase X = 1 OUTx+ = H, OUTx– = L Table 11. Revision Code/Vendor Code ROM Readout at LOGIC OUT 18 NO. EX-setup REGISTER (BITS 3–0) 8 1000 Revision <0> = 1: For this device * <2,1,0> = (1,0,1) = 5 SIGNAL SELECTION MONITORED ON LOGIC OUT 9 1001 Revision <1> = 0: For this device 10 1010 Revision <2> = 1: For this device 11 1011 Vendor <0> = 0: For TI <1,0> = TI (0,0), NG(1,0) 12 1100 Vendor <1> = 0: For TI <1,0> = Reserve (0,1), (1,1) Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): DRV8809 DRV8810 DRV8809 DRV8810 www.ti.com ............................................................................................................................................................... SLVS854A – JULY 2008 – REVISED JULY 2008 Table 12. Different Motor Drive Configuration Pinouts (Selected By Setup Register Bits 0 to 3) <setup> SETUP 0 (0,0,0) 1 (0,0,1) 2 (0,1,0) 3 (0,1,1) 4 (1,0,0) 5 (1,0,1) 6 (1,1,0) 7 (1,1,1) STEPPER MTR ×2 STEPPER MTR AND DC (LARGE) STEPPER MTR AND DC (SMALL) ×2 DC (LARGE) AND DC (SMALL) ×2 DC (LARGE) ×2 DC (SMALL) ×4 LARGE STEPPER ULTRALARGE DC 1 Test-LGND 2 MGND 3 OUTA– OUTA– OUTA– OUTA– OUTLAB– OUTLAB– OUTSA– OUTLAB– OUTULABCD– 4 RSA1 RSA1 RSA1 RSA1 RSLAB1 RSLAB1 RSA1 RSLAB1 RSULABCD1 5 RSA2 RSA2 RSA2 RSA2 RSLAB2 RSLAB2 RSA2 RSLAB2 RSULABCD1 6 OUTA+ OUTA+ OUTA+ OUTA+ OUTLAB+ OUTLAB+ OUTSA+ OUTLAB+ OUTULABCD+ 7 MGND 8 MGND 9 OUTB+ OUTB+ OUTB+ OUTB+ OUTLAB+ OUTLAB+ OUTSB+ OUTLAB+ OUTULABCD+ 10 RSB2 RSB2 RSB2 RSB2 RSLAB2 RSLAB2 RSB2 RSLAB2 RSULABCD1 11 RSB1 RSB1 RSB1 RSB1 RSLAB1 RSLAB1 RSB1 RSLAB1 RSULABCD1 12 OUTB– OUTB– OUTB– OUTB– OUTLAB– OUTLAB– OUTSB– OUTLAB– OUTULABCD– 13 MGND 14 LGND 15 DCDC_MODE 16 FBC 17 OD_C 18 OD_C 19 OD_B 20 OD_B 21 FBB 22 VCP 23 OSCD_mon 24 CP2 25 CP1 26 VDIN 27 VDIN 28 VDIN 29 VM 30 VREF_AB 31 VREF_CD 32 FBA 33 ODA 34 ODA 35 LGND 36 MGND 37 OUTC– OUTC– OUTLCD– OUTSC– OUTSC– OUTLCD– OUTSC– OUTLCD– OUTULABCD– 38 RSC1 RSC1 RSLCD1 RSC1 RSC1 RSLCD1 RSC1 RSLCD1 RSULABCD1 39 RSC2 RSC2 RSLCD2 RSC2 RSC2 RSLCD2 RSC2 RSLCD2 RSULABCD1 40 OUTC+ OUTC+ OUTLCD+ OUTSC+ OUTSC+ OUTLCD+ OUTSC+ OUTLCD+ OUTLABCD+ 41 MGND 42 MGND 43 OUTD+ OUTD+ OUTLCD+ OUTSD+ OUTSD+ OUTLCD+ OUTSD+ OUTSD+ OUTULABCD+ 44 RSD2 RSD2 RSLCD2 RSD2 RSD2 RSLCD2 RSD2 RSD2 RSULABCD1 45 RSD1 RSD1 RSLCD1 RSD1 RSD1 RSLCD1 RSD1 RSD1 RSULABCD1 46 OUTD– OUTD– OUTLCD– OUTSD– OUTSD– OUTLCD– OUTSD– OUTSD– OUTULABCD– 47 MGND 48 GND Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): DRV8809 DRV8810 19 DRV8809 DRV8810 SLVS854A – JULY 2008 – REVISED JULY 2008 ............................................................................................................................................................... www.ti.com Table 12. Different Motor Drive Configuration Pinouts (Selected By Setup Register Bits 0 to 3) (continued) <setup> SETUP 0 (0,0,0) 1 (0,0,1) 2 (0,1,0) 3 (0,1,1) 4 (1,0,0) 5 (1,0,1) 6 (1,1,0) 7 (1,1,1) STEPPER MTR ×2 STEPPER MTR AND DC (LARGE) STEPPER MTR AND DC (SMALL) ×2 DC (LARGE) AND DC (SMALL) ×2 DC (LARGE) ×2 DC (SMALL) ×4 LARGE STEPPER ULTRALARGE DC - - ENABLE_SD ENABLE_SD - ENABLE_SD - ENABLE_SC ENABLE_LC D ENABLE_SC ENABLE_LC D - - ENABLE_SB - ENABLE_LAB ENABLE_LA B ENABLE_SA ENABLE_LA B 49 50 51 C_SELECT STROBE_CD STROBE_CD ENABLE_LCD ENABLE_SC 52 TH_OUT 53 54 55 LOGIC OUT STROBE AB - - STROBE AB STROBE AB STROBE AB 56 nORT 57 LGND 58 OSCM_mon 59 DATA_CD DATA_CD - PHASE SD PHASE SD - PHASE SD - 60 CLK_CD CLK_CD PHASE_LCD PHASE SC PHASE SC PHASE_LCD PHASE SC PHASE_LCD 61 DATA_AB DATA_AB DATA_AB DATA_AB - - PHASE SB - 62 CLK_AB CLK_AB CLK_AB CLK_AB PHASE_LAB PHASE_LAB PHASE SA PHASE_LAB 63 nSLEEP=L nSLEEP=H 64 ENABLE_ABC D PHASE_ABCD In-Reset Motor Driver Configuration OUTAVREF_AB Motor Drive Output Control A NC DATA_AB RSA OUTA+ Pre Drive and Control STROBE_AB VM OUTB+ Motor Drive Output Control B Stepper Motor VM RSB CLK_AB OUTB- OUTCVREF_CD Motor Drive Output Control C NC OUTC+ Pre Drive and Control STROBE_CD VM RSC OUTD+ DATA_CD Motor Drive Output Control D CLK_CD Stepper Motor VM RSD OUTD- Figure 9. Motor Configuration 0, Two Stepper 20 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): DRV8809 DRV8810 DRV8809 DRV8810 www.ti.com ............................................................................................................................................................... SLVS854A – JULY 2008 – REVISED JULY 2008 OUTAVREF_AB Motor Drive Output Control A NC STROBE_AB RSA OUTA+ Pre Drive and Control DATA_AB VM OUTB+ Motor Drive Output Control B VM Stepper Motor RSB CLK_AB OUTB- OUTLCDVREF_CD Motor Drive Output Control C NC ENABLE_LCD VM RSLB OUTLCD+ Pre Drive and Control OUTLCD+ NC Motor Drive Output Control D PHASE_LCD Large DC Motor RSLB OUTLCD- Figure 10. Motor Configuration 1, One Stepper and One Large DC OUTAVREF_AB Motor Drive Output Control A NC STROBE_AB RSA OUTA+ Pre Drive and Control DATA_AB VM OUTB+ Motor Drive Output Control B VM Stepper Motor RSB CLK_AB OUTB- OUTSCVREF_CD Motor Drive Output Control C ENABLE_SD ENABLE_SC VM OUTSC+ Pre Drive and Control OUTSD+ PHASE_SD PHASE_SC DC Motor RSC Motor Drive Output Control D VM DC Motor RSD OUTSD- Figure 11. Motor Configuration 2, One Stepper and Two Small DCs Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): DRV8809 DRV8810 21 DRV8809 DRV8810 SLVS854A – JULY 2008 – REVISED JULY 2008 ............................................................................................................................................................... www.ti.com OUTLABVREF_AB Motor Drive Output Control A NC NC RSLAB OUTLAB+ Pre Drive and Control ENABLE_LAB VM OUTLAB+ Motor Drive Output Control B Large DC Motor RSLAB PHASE_LAB OUTLAB- OUTSCVREF_CD Motor Drive Output Control C ENABLE_SD DC Motor RSC OUTSC+ Pre Drive and Control ENABLE_SC VM OUTSD+ PHASE_SD Motor Drive Output Control D PHASE_SC VM DC Motor RSD OUTSD- Figure 12. Motor Configuration 3, One Large DC and Two Small DCs OUTLABVREF_AB Motor Drive Output Control A NC ENABLE_LAB OUTLAB+ Pre Drive and Control NC VM RSLAB OUTLAB+ Motor Drive Output Control B Large DC Motor RSLAB PHASE_LAB OUTLAB- OUTLCDVREF_CD Motor Drive Output Control C NC ENABLE_LCD VM RSLCD OUTLCD+ Pre Drive and Control OUTLCD+ NC PHASE_LCD Motor Drive Output Control D Large DC Motor RSLCD OUTLCD- Figure 13. Motor Configuration 4, Two Large DCs 22 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): DRV8809 DRV8810 DRV8809 DRV8810 www.ti.com ............................................................................................................................................................... SLVS854A – JULY 2008 – REVISED JULY 2008 OUTSAVREF_AB VM Motor Drive Output Control A ENABLE_SB OUTSA+ Pre Drive and Control ENABLE_SA PHASE_SB DC Motor RSA OUTSB+ VM Motor Drive Output Control B DC Motor RSB PHASE_SA OUTSB- OUTSCVREF_CD VM Motor Drive Output Control C ENABLE_SD OUTSC+ Pre Drive and Control ENABLE_SC OUTSD+ PHASE_SD VM Motor Drive Output Control D PHASE_SC DC Motor RSC DC Motor RSD OUTSD- Figure 14. Motor Configuration 5, Four Small DCs OUTAVREF_AB Motor Drive Output Control A NC STROBE_AB RSA OUTA+ Pre Drive and Control DATA_AB VM OUTB+ Motor Drive Output Control B RSB CLK_AB OUTB- OUTCVREF_CD VM Motor Drive Output Control C NC STROBE_CD RSC Stepper Motor OUTC+ Pre Drive and Control OUTD+ DATA_CD Motor Drive Output Control D CLK_CD RSD OUTD- Figure 15. Motor Configuration 6, Single Large Stepper Motor Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): DRV8809 DRV8810 23 DRV8809 DRV8810 SLVS854A – JULY 2008 – REVISED JULY 2008 ............................................................................................................................................................... www.ti.com OUTSAVREF_AB Motor Drive Output Control A ENABLE_SB ENABLE_SA RSA OUTSA+ Pre Drive and Control PHASE_SB VM OUTSB+ Motor Drive Output Control B PHASE_SA OUTSB- DC Motor OUTSCVREF_CD Motor Drive Output Control C ENABLE_SD ENABLE_SC OUTSC+ Pre Drive and Control OUTSD+ PHASE_SD Motor Drive Output Control D PHASE_SC OUTSD- Figure 16. Motor Configuration 7, Ultra-Large DC 24 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): DRV8809 DRV8810 DRV8809 DRV8810 www.ti.com ............................................................................................................................................................... SLVS854A – JULY 2008 – REVISED JULY 2008 Bipolar Current Regulated Stepper Motor Drive The following functionality is common to all the H-bridge drives. A crossover delay is inherent to the control circuitry to prevent cross conduction of the upper and lower switches on the same side of the H-bridge. A blanking (deglitch) time is incorporated to prevent false triggering due to initial current spikes at turnon with a discharged capacitive load. The stepper motor current can be programmed to 16 different current levels using a 4-bit register. The average current level for a particular angular rotation is shown in Table 14. Enable or Phase reversal or Itrip detection tPDON Sink or source gate off to on tPDOFF tCOD Sink or source gate on to off Current sense blanking time tBLANK – DC motor blanking time tab Stepper blanking time Figure 17. Crossover and Blanking Timing for H-Bridge For stepper motor configured H-bridges, only tab (stepper blanking time) is set for current sensing. For DC motor-configured H-bridges, tBLANK is included to ignore huge current spike due to rush current to varistor capacitance. Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): DRV8809 DRV8810 25 DRV8809 DRV8810 SLVS854A – JULY 2008 – REVISED JULY 2008 ............................................................................................................................................................... www.ti.com Short/Open for Motor Outputs When a short/open situation happens, the protection circuit prevents device damage under certain conditions (short at start up, etc). VM Charge pump RSA VM Rsens OSCM_mon OSCM ( 800kHz ) OUTA OSCi ( 6.4MHz ) OUTA/ DATA_AB CLK_AB Strobe_AB Stepper parameter register Torque, Decay, Current, & Phase Control logic & Pre-driver Current Sens MGND RSB Current limit VM Rsens OUTB VM supervisor (15v) Stepper Motor turn on/off OUTB/ over current detect Protect disable Setup/ex-setup register Protection control & nORT assertion Figure 18. Stepper Motor Driver 26 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): DRV8809 DRV8810 DRV8809 DRV8810 www.ti.com ............................................................................................................................................................... SLVS854A – JULY 2008 – REVISED JULY 2008 Table 13. Angular Rotation Setting for Stepping Motor Driver (Parameter Bit in Stepper Register) BIT 14 BIT 13 BIT 12 BIT 11 BIT 7 BIT 6 BIT 5 BIT 4 CURRENT A (C) 3 CURRENT A (C) 2 CURRENT A (C) 1 CURRENT A (C) 0 CURRENT B (D) 3 CURRENT B (D) 2 CURRENT B (D) 1 CURRENT B (D) 0 L L H STEP SET ANGLE (deg) 16 90 H H H H L L 15 84.4 H H H H L L L 14 78.8 H H H L L L H L 13 73.1 H H L H L L H H 12 67.5 H H L L L H L L 11 61.2 H L H H L H L H 10 56.3 H L H L L H H L 9 50.6 H L L H L H H H 8 45 H L L L H L L L 7 39.4 L H H H H L L H 6 33.8 L H H L H L H L 5 28.1 L H L H H L H H 4 22.5 L H L L H H L L 3 16.9 L L H H H H L H 2 11.3 L L H L H H H L 1 5.6 L L L H H H H H 0 0 L L L L H H H H RdsON vs Idrain 1.0 TJ = 120°C 0.9 RdsON (W) 0.8 0.7 TJ = 70°C 0.6 0.5 TJ = 25°C 0.4 0.5 1 1.5 2 2.5 3 3.5 Idrain (A) A. This plot includes both actual device characterization data and extrapolated data. B. Actual device has self-heating effect to increase the junction temperature, with continuous loading current more than 1 A. C. The device temperature is set to 70°C for the Rds(ON) test. Figure 19. Typical Rds(ON) Value vs Drain Current (DMOS FET in H-Bridge) Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): DRV8809 DRV8810 27 DRV8809 DRV8810 SLVS854A – JULY 2008 – REVISED JULY 2008 ............................................................................................................................................................... www.ti.com VM Charge pump VM Rssx Rsens OSCM_mon OSCM ( 800kHz ) Control logic & Pre-driver OSCi ( 6.4MHz ) OUTx DC Motor Current Sens Enable_x Phase_x OUTx/ Current limit VM supervisor (15v) turn on/off over current detect MGND Protect disable Protection control & nORT assertion Figure 20. DC Motor Drive The motor configuration setup bits in the setup register can select three types of DC motor driving: utilizing a single H-bridge, utilizing two (A and B, or C and D) H-bridges in parallel, or utilizing four H-bridges in parallel. For the setup register value (bit 2,1,0) = (1,0,1), the device configuration is 4× DC motor, which enables each H-bridge to drive a DC motor independently. The ENABLEx and PHASEx input terminals are reassigned from the serial interface pins and some reserved pins, after nSLEEP pin is set to H. For the setup register value (bit 2,1,0) = (0,1,1), the device configuration is 1× large DC + 2× DC motor mode. The large DC driving utilizes two H-bridges in parallel and controlled by ENABLE_AB and PHASE_AB pins. Two Rsens pins should be connected together. The VREF inputs are used for the Rsense comparator reference voltage. VREF_AB provides the voltage to both H-bridge A and B, and VREF_CD provides the voltage for H-bridge C and D. Table 14. DC Motor Drive Truth Table 28 FAULT CONDITION nSLEEP ENABLEX PHASEX + HIGH SIDE + LOW SIDE - HIGH SIDE - LOW SIDE 0 0 X X OFF OFF OFF OFF 0 1 0 X OFF OFF OFF OFF 0 1 1 0 OFF ON ON OFF 0 1 1 1 ON OFF OFF ON Motor OCP 1 X X OFF OFF OFF OFF TSD X X X OFF OFF OFF OFF Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): DRV8809 DRV8810 DRV8809 DRV8810 www.ti.com ............................................................................................................................................................... SLVS854A – JULY 2008 – REVISED JULY 2008 Charge Pump The charge-pump voltage-generator circuit utilizes external storage and bucket capacitors. It provides the necessary voltage to drive the high-side switches for both DC-DC regulators and motor drivers. The charge-pump circuit is driven at a frequency of 1.6 MHz (nom). Recommended bucket capacitance is 10 nF, 16 V (min), and storage capacitance is 0.1 µF, 60 V (min). The charge-pump storage capacitor, Cstage, should be connected from the VCP output, pin 22, to VM. For power-saving purposes in sleep mode, the charge pump is stopped when n_sleep = L and all three regulators are turned OFF. When the part is powered up, the charge pump is started first after the C_select capture, and 10 ms after the CP startup, the first regulator is started up. Table 15. Charge Pump FAULT CONDITION DC-DC Ch-A DC-DC Ch-B DC-DC Ch-C nSLEEP CHARGE PUMP 0 OFF OFF OFF 0 OFF 0 ON X X X ON 0 X ON X X ON 0 X X ON X ON 0 X X X 1 ON Motor OCP X X X 1 ON TSD X X X X OFF VM Charge pump OSCD (100 kHz) OSCi (6.4 MHz) Vref 1.5 V Overcurrent sense OD_x Control logic and predriver Current limit Output voltage supervisor Disable (mask) FBx Over current detect Protect disable UVP OVP (-30%) (+30%) C_SELECT Soft start, Protection control, and nORT assertion Setup/ Extended Setup register Figure 21. DC-DC Converter This is a switch-mode regulator with integrated switches, to provide a programmed output set by the feedback terminal. The DC-DC converter has a fixed frequency variable duty cycle topology with a switching frequency of 100 kHz (nom). External filtering (inductor and capacitor) and external catch diode are required. The output voltage is short-circuit protected. If the system has a high input voltage and a very light load on the output, the converter may not provide energy to the inductor (skip) until the load line or the minimum voltage threshold is reached. Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): DRV8809 DRV8810 29 DRV8809 DRV8810 SLVS854A – JULY 2008 – REVISED JULY 2008 ............................................................................................................................................................... www.ti.com The regulator has a soft-start function to limit the rush current during start up. It is achieved by using VFB ramp during soft start. For unused DC-DC converter channels, the external components can be removed if the channel is set to inactive by the C_SELECT pin and register bits. Also, the VFB pin can be left open or connected to ground. DCDC_MODE selector can operate channel B and C in parallel mode to handle 2× output driving capability. VFB_B pin is active for feedback, and VFB_C pin must be pulled down internally. DCDC_MODE for Parallel-Mode Control The DCDC_MODE pin selects the DC-DC converter parallel driving for Ch-B and Ch-C. The input is pulled up to internal 3.3 V by a 200-kΩ resistor. When the pin is H or left open, Ch-B and Ch-C are driven in parallel. Table 16. C_SELECT for Start-Up C_SELECT PIN VOLTAGE DC-DC Vout1, ODA DC-DC Vout2, ODB DC-DC Vout3, ODC OFF OFF OFF Gnd 0 V to 0.3 V Pull Down (by external 200 kW) 1.3 V to 2 V OPEN 3 V to 3.3 V See Table 17 ON ON ON DCDC_MODE and C_SELECT Timing Delay and Start-Up Order DCDC_MODE and C_SELECT play a role in the order of regulator enablement, as well as the time when the first regulator is enabled to when the second is enabled. Regulators B and C are always enabled together, whether they are working in parallel mode or not. Table 17. DCDC_MODE and C_SELECT Timing Delay (DRV8809) DCDC_MODE C_SELECT TIMING DELAY L GND None No regulator is enabled. DESCRIPTION L Pull down None No regulator is enabled. L 3 V to 3.3 V 1.6 ms H GND None Ch-A followed by Ch-B and Ch-C H Pull down 1.6 ms Ch-B and Ch-C followed by Ch-A H 3 V to 3.3 V 1.6 ms Ch-A followed by Ch-B and Ch-C No regulator is enabled. Table 18. DCDC_MODE and C_SELECT Timing Delay (DRV8810) DCDC_MODE C_SELECT TIMING DELAY DESCRIPTION L GND None No regulator is enabled. L Pull down None No regulator is enabled. L 3 V to 3.3 V 1.6 ms Ch-A followed by Ch-B and Ch-C H GND None H Pull down 20 ms to 40 ms No regulator is enabled. Ch-B and Ch-C followed by Ch-A H 3 V to 3.3 V 20 ms to 40 ms Ch-A followed by Ch-B and Ch-C In-Reset: Input for System Reset In-Reset pin assertion stops all the DC-DC converters and H-bridges. It also reset all the register contents to default value. After deassertion of the input, the device follows the initial start-up sequence. The C_SELECT state is captured after the In-Reset deassertion. The input is pulled up to internal 3.3 V by 200-kΩ resistor. When the pin = H or left open, reset function is asserted. Also it has deglitch filter of 2.5 µs to 7.5 µs. 30 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): DRV8809 DRV8810 DRV8809 DRV8810 www.ti.com ............................................................................................................................................................... SLVS854A – JULY 2008 – REVISED JULY 2008 Tsens output voltage ( V ) 2.60 2.40 2.20 2.00 1.80 1.60 0 30 60 90 120 150 180 Temperature ( deg C ) Figure 22. Tsens (Analog Out) Temperature Coefficient: Voltage Plot Example (Typical) Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): DRV8809 DRV8810 31 DRV8809 DRV8810 SLVS854A – JULY 2008 – REVISED JULY 2008 ............................................................................................................................................................... www.ti.com VM (CSELECT = Open) VthVM + VM=6.0v Capture C_select then start Charge Pump VthVM VM=5.0v VCP C P s tart to D C/ D C d el a y 10 ms (Note A) DC/DC_A DC/DC_B DC/DC_C Delay (Note B) nORT (= L ) Protection mask: OCP/OVP/UVP for CH-A/B/C (= H ) 120 ms (20 ms + 100 ms) A. Charge-pump wake-up delay, from 10 ms to 20 ms, due to asynchronous event capture B. For the DRV8809, delay is 1.6 ms for both DC_MODE high and low. For the DRV8810, delay is 20 ms to 40 ms for DC_MODE high and 1.6 ms for DC_MODE low. Figure 23. Power-Up Timing (Power Up With DC-DC Turn-On By C_SELECT) NOTE: When VM crosses VthVM+ (about 6 V), the C_select state is captured. If C_SELECT is open (pulled up to internal 3.3 V), all DC-DC regulator channels (A, B, and C) are turned on. The time of channels B and C to be turned on, with regards to channel A, depends on the state of DC_MODE. 32 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): DRV8809 DRV8810 DRV8809 DRV8810 www.ti.com ............................................................................................................................................................... SLVS854A – JULY 2008 – REVISED JULY 2008 Figure 24. Power-Up Timing (Power Up Without DC-DC Turn-On: C_SELECT = GND) NOTE: When VM crosses VthVM+ (about 6 V) with C_SELECT = GND, none of the three regulators are turned on. The nORT output is released to H after 300 ms from the VthVM+ crossing. See Note B 120 ms (See Note A) A. 120 ms to 140 ms due to asynchronous event capture B. After VM power up, DC-DC starts at the setup register strobe. Figure 25. Power-Up Timing (DC-DC Regulator Wake Up by Setup Register) NOTE: Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): DRV8809 DRV8810 33 DRV8809 DRV8810 SLVS854A – JULY 2008 – REVISED JULY 2008 ............................................................................................................................................................... www.ti.com The regulator is started from the strobe input, same as charge pump. There is no 10-ms waiting period, because VCP pin already reached VM – 0.7 V. VM ( CSELECT = GND ) VthVM+ VM=6.0v DC/DC_B ( off -> on ) DC/DC_C (off -> on ) Delay (Note B) DC/DC_A ( off -> on ) See Note A Setup register strobe [ Setup (9,8,7) =(0,0,0) ] nORT (= H) protection mask (=L) 120 ms A. After VM power up, DC-DC starts at the setup register strobe. B. For the DRV8809, delay is 1.6 ms for both DC_MODE high and low. For the DRV8810, delay is 20 ms to 40 ms for DC_MODE high and 1.6 ms for DC_MODE low. Figure 26. Power-Up Timing (DC-DC Regulator Wake Up by Setup Register, All Three Channels On) 34 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): DRV8809 DRV8810 DRV8809 DRV8810 www.ti.com ............................................................................................................................................................... SLVS854A – JULY 2008 – REVISED JULY 2008 10 ms (Note A) A. Charge-pump wake-up delay, from 10 ms to 20 ms, due to asynchronous event capture B. Start-up with VM glitch (not below VthV—). Only channels B and C are shown. Same applies to Channel A. Figure 27. VM Start-Up/Power-Down and Glitch Condition Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): DRV8809 DRV8810 35 DRV8809 DRV8810 SLVS854A – JULY 2008 – REVISED JULY 2008 ............................................................................................................................................................... www.ti.com 10 ms (Note A) 10 ms (Note A) A. Charge-pump wake-up delay, from 10 ms to 20 ms, due to asynchronous event capture B. Start-up with VM glitch (below VthV_). Only channels B and C are shown. Same applies to Channel A. Figure 28. VM Startup/Power-Down and Glitch Condition VthVM+ VM=6.0v VM VthVMVM=5.0v Mask Shutdown DC/DC_B DC/DC_C nORT protection mask A. Only channels B and C are shown. Same applies to Channel A. Figure 29. Power Down (Normal) 36 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): DRV8809 DRV8810 DRV8809 DRV8810 www.ti.com ............................................................................................................................................................... SLVS854A – JULY 2008 – REVISED JULY 2008 VthVM+ VM=6.0v VM VthVM- Mask VM=5.0v DC/DC_B DC/DC_C nORT protection mask A. Only channels B and C are shown. Same applies to Channel A. Figure 30. Power Down (Glitch on VM) VthVM+ VM=6.0v VthVM+ VM VM=5.0v VthVM- Restart ( CSELECT = OPEN ) Shutdown DC/DC_B 10 ms (Note A) 10 ms (Note A) DC/DC_ C t 40 ms 120 ms in case t <120 ms nORT =L protection mask =H A. Charge-pump wake-up delay, from 10 ms to 20 ms, due to asynchronous event capture B. Only channels B and C are shown. Same applies to Channel A. Figure 31. Power Down (Glitch on VM Below VthV_) Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): DRV8809 DRV8810 37 DRV8809 DRV8810 SLVS854A – JULY 2008 – REVISED JULY 2008 ............................................................................................................................................................... www.ti.com InReset nORT 10 us Figure 32. Shutdown by In-Reset Blanking Time Insertion Timing for DC Motor Driving For the DC motor driving H-bridge, tBlank is inserted at each phase reversal and also following each chopping cycle (once every eight OSCM clocks). For a large n number (5 or 6) tBlank setup may decrease the itrip detect window. The user must be careful to optimize in the system. Case A: Phase duty = 25% Case A*1 for setup bit = (1,0) Case A*2 for setup bit = (0,1) OSCM Phase Resync Resync Resync Resync fChop 8 x OSCM clocks tBlank (1,0) *1 tBlank (0,1) *2 n=3 n=3 (n=6) n=3 n=6 n=3 n=6 n=3 (n=6) n=6 *1 : Setup register bit <4,3> = ( 1,0 ) : tBlank = OSCM clock x 3 (or bit <5,6> for H-bridge C,D channel ) *2 : Setup register bit <4,3> = ( 0,1 ) : tBlank = OSCM clock x 6 (or bit <5,6> for H-bridge C,D channel ) Figure 33. Blanking Time Insertion Timing, Case A Case B: Phase duty = 40% Case B*1 for setup bit =(1,0) Case B*2 for setup bit =(0,1) 38 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): DRV8809 DRV8810 DRV8809 DRV8810 www.ti.com ............................................................................................................................................................... SLVS854A – JULY 2008 – REVISED JULY 2008 OSCM Phase Resync Resync Resync Resync fChop 8 x OSCM clocks tBlank (1,0) *1 tBlank (0,1) *2 8 x OSCM clocks n=3 n=3 n=6 n=3 (n=3) n=6 n=3 (n=6) (n=6) n=6 *1 : Setup register bit <4,3> = ( 1,0 ) : tBlank = OSCM clock x 3 (or bit <5,6> for H-bridge C,D channel ) *2 : Setup register bit <4,3> = ( 0,1 ) : tBlank = OSCM clock x 6 (or bit <5,6> for H-bridge C,D channel ) Figure 34. Blanking Time Insertion Timing, Case B Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): DRV8809 DRV8810 39 DRV8809 DRV8810 SLVS854A – JULY 2008 – REVISED JULY 2008 ............................................................................................................................................................... www.ti.com Table 19. Function Table nORT, Power Down, VM < 4.5 V Conditions DEVICE STATUS CHARGE PUMP OSCD OSCM nORT (RESET) OUTPUT nSLEEP Active Active Active Inactive Available MODE SETTING nORT Inactive Active Active Active Depend on power down VM < 6 V during power down Active Active Active See timing chart Depend on power down 4.5 V < VM Inactive Inactive Inactive Active Unavailable Table 20. Shutdown Functions CASE OF SUPPLY SHUTDOWN DC-DC Vout1 DC-DC Vout2 DC-DC Vout3 MOTOR nORT (RESET) DC-DC Vout1 OCP, OVP Shut down Shut down Shut down Shut down Reset ON (L out) DC-DC Vout2 OCP, OVP Shut down Shut down Shut down Shut down Reset ON (L out) DC-DC Vout3 OCP, OVP Shut down Shut down Shut down Shut down Reset ON (L out) Motor OCP NA NA NA OFF Reset one pulse (tlow = 40 ms) TSD Shut down Shut down Shut down Shut down Reset ON (L out) • Shutdown of DC-DCs is released at VM > VthVM+ when VM is increasing. In case VM decreases, DC-DCs are shut down when VM <VthV_. When VM decreases and VthVM+ > VM > VthV_, the DC-DC output voltage supervisor is ignored. Motor shutdown is released by VM < 4.5 V or nSLEEP rising edge. nORT (reset) ON/OFF time is 40 ms. The data in Table 21 is valid if the protection control bits in the EX-setup register are all 0. • • • Table 21. Modes of Operation (1) (2) POR M OFF VM VM (1) (2) 40 ISD Vout 1 Vout2 OVP Vout3 MOTO R Vout1 Vout 2 TSD Vout 3 EXTERNAL PIN MOTOR nSL EEP IC CSEL BLOCK FUNCTIONS MOT OR Vout 1 Vout2 Vout3 nORT H 0 0 0 0 0 0 0 0 0 0 H N On On On On 1 X X X X X X X X X X X Off Off Off Off Off L 0 1 X X X X X X X X X X O On Off On/Off On/Off H 0 1 X X X X X X X X X p S/D S/D S/D S/D L 0 1 X X X X X X X X e S/D S/D S/D S/D L 0 1 X X X X X X X r S/D S/D S/D S/D L 0 1 X X X X X X a Off On On On L/P 0 1 X X X X X t S/D S/D S/D S/D L 0 1 X X X X I S/D S/D S/D S/D L 0 1 X X X o S/D S/D S/D S/D L 0 1 X X n S/D S/D S/D S/D L 0 Low X S Off On On On H Hig h All off X Off Off Off L 200 k X On On Off H Open X Off On On H Valid only if the protection control bits (in EX-setup register) are all 0. N = Normal operation, S = Sleep mode, 0 = Off, 1 = On, X = Don’t care, S/D = Shutdown, P = Pulse after fault occurs (retry), OFF = Must toggle sleep terminal or power-on reset (nORT), S/D = Must do a power-on reset (nORT) Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): DRV8809 DRV8810 DRV8809 DRV8810 www.ti.com ............................................................................................................................................................... SLVS854A – JULY 2008 – REVISED JULY 2008 APPLICATION INFORMATION Application Schematic For one stepper and two DC motor configuration: • DC-DC Ch-A = 5 V (12 V) • DC-DC Ch-B = 1.5 V • DC-DC Ch-C = 3.3 V If start-up from Ch-B (1.5 V) ≥ Ch-A (5 V), Ch-C 3.3 V should be turned on by the setup register (200 kΩ between C_SELECT pin and GND). 0.1uF Cstrage DCDC_MODE 0.01uF Cbkt C_SELECT VM 100uF TH_OUT VCP CP1 VDIN CP2 VM 200 k Vout 1 Temperature Sens : Pre-TSD or Tsens (analog) 330uH OD_A 5.0v (12.0v) 0.1uF 220uF FBA 5.6k (9.1k) DC/DC convertor Ch-A Voltage charge pump To Highside gate drive To DC/DC To Hbridges OUTA+ Motor Drive Output Control A Thermal Shut down 1.48v 2.4k (1.3k) VM 0.2 ohm RSA OUTAMGND Vout 2 330uH OD_B OUTB+ 1.5v DC/DC convertor Ch-B 220uF 0.1uF Vout 3 FBB 1.50v 3.0k 330uH 0.1uF Regulator Internal supply Voltage Supervisory DC/DC convertor Ch-C 220uF 1.50v 0.2 ohm VM OUTC+ Motor Drive Output Control C 1.2k 1.0k Stepper Motor RSB OUTB- Pre-Drive, Latch Registers & control circuitry OD_C 3.3v Motor Drive Output Control B VM 0.2 ohm RSC DC Motor FBC OUTCFreq divider for DC/DC In-Reset MGND OSCD_Mon OUTD+ OSCi 6.4MHz OSCM_Mon Motor Drive Output Control D Freq divider Motor PWM LOGIC_OUT nORT 0.2 ohm RSD DC Motor OUTDVREF_AB nSLEEP Setup / ex-setup registers LGND ENABLE_SD (reserved) STROBE_AB 2.5v VREF_SCD Serial Interface A-B DATA_AB Serial Interface C-D CLK_AB ENABLE_SC PHASE_SD PHASE_SC Figure 35. Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): DRV8809 DRV8810 41 PACKAGE OPTION ADDENDUM www.ti.com 4-Aug-2008 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty DRV8809PAP ACTIVE HTQFP PAP 64 160 Green (RoHS & no Sb/Br) CU NIPDAU DRV8810PAP PREVIEW HTQFP PAP 64 160 TBD Call TI Lead/Ball Finish MSL Peak Temp (3) Level-3-260C-168 HR Call TI (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. 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