Keysight M3102A Pxie arbitrary waveform generator and digitizer with optional real-time sequencing and fpga programming Datasheet

Keysight M3302A
PXIe Arbitrary Waveform Generator and
Digitizer with Optional Real-Time
Sequencing and FPGA Programming
500 MSa/s, 16 Bits, 2 Channel Arbitrary Waveform Generator
500 MSa/s, 14 Bits, 2 Channel Digitizer
Data Sheet
02 | Keysight | M3302A PXIe Arbitrary Waveform Generator and Digitizer Combo with Optional Real-Time Sequencing and FPGA Programming - Data Sheet
Fast, Flexible, High-Performance Control, Testing
and Prototyping
The M3302A combines high-performance arbitrary waveform generator channels and
digitizer channels in the same module providing the ideal tool for testing and prototyping
in control or communications applications. Performance meets simplicity thanks to
easy-to-use programming libraries, real-time sequencing technology (Hard Virtual
Instrumentation or HVI), and graphical FPGA programming technology.
Features
Outputs (AWG)
–– 500 MSa/s, 16 Bits, 2 Channels
Inputs (digitizer)
–– 500 MSa/s, 14 Bits, 2 Channels
Output features
–– AWGs, function generators, AM/FM/PM modulators
–– Advanced triggering and marking functionalities
Input features
–– Powerful data acquisition system (DAQ)
–– Advanced triggering and marking functionalities
Less than 400 ns input to output latency
Optional HW programming for high-performance applications
–– Real-time sequencing (HVI technology)
–– FPGA programming
–– Xilinx Kintex-7 325T or 410T FPGA
Up to 2 GB of onboard RAM (~ 1 Gsamples)
Mechanical/interface
–– 2 slots 3U (PXIe)
–– Up to 200 MB/s transfer BW with P2P capabilities
–– Independent DMA channels for fast and efficient data transfer
Applications
General purpose AWGs & digitizers
High-performance control
Communications: BB/IF SDR, channel emulation, transceiver testing
Aerospace & defense (A/D): RADAR, electronic warfare (EW)
Hardware-in-the-loop (HIL), automated test equipment (ATE)
Scientific research
Quantum computing
03 | Keysight | M3302A PXIe Arbitrary Waveform Generator and Digitizer Combo with Optional Real-Time Sequencing and FPGA Programming - Data Sheet
Functional Block Diagram
Output - Arbitrary Waveform Generator
Channel 1
Channel x
Function
generator
(FGx)
Channel 1
output
Frequency Phase
Amplitude Offset
Angle
modulator
FM
Dual
arbitrary
waveform
generator
(AWGx)
Amplitude
modulator
AM
DAC
LPF
Channel x
output
Quadrature
modulator
IQ
Channel n
Odd channels only
Even channels only
Channel n
output
Dual modulation option only
Figure 1. M3302A output functional block diagram, all channels have identical output structure
Input - Digitizer
Channel 1
Channel 1
output
Channel x
Input settings
Channel x
output
Full scale, Z,
coupling (as
available)
Prescaler
÷
Data
acquisition
(DAQx)
Analog
trigger
Channel n
Channel n
output
Figure 2. M3302A input functional block diagram, all channels have identical input structure
04 | Keysight | M3302A PXIe Arbitrary Waveform Generator and Digitizer Combo with Optional Real-Time Sequencing and FPGA Programming - Data Sheet
Programming Technology and Software Tools
Software programming
–– Easy-to-use native programming libraries for most common languages: C, C++, Visual Studio,
LabVIEW, MATLAB, Python, and more
Hardware programming (optional)
–– Real-time sequencing (Hard Virtual Instrumentation or HVI technology)
–– Graphical flowchart-style M3601A design environment (-HV1 option required on HW)
–– Ultra-fast, fully-parallelized, hard real-time execution
–– Ultra-fast, time-deterministic decision-making
–– Off-the-shelf inter-module synchronization & data exchange
–– FPGA programming
–– Graphical M3602A FPGA design environment (-FP1 option required on HW)
–– No FPGA know-how required
–– Include high-level to low-level design elements: off-the-shelf DSP blocks, MATLAB/
Simulink designs, Xilinx CORE Generator IP cores, Xilinx VIVADO/ISE projects, VHDL or
Verilog code
–– Ultra-fast, one-click compiling and on-the-fly programming
No programming
–– Ready-to-use SD1 SPF (software front panels)
PXIe Arbitrary Waveform Generators, Digitizers and Combination Modules
Outputs (AWGs)
Inputs (Digitizers)
Product
Type
Speed
(MSa/s)
Bits
Ch
BW
(MHz)
M3202A
AWG
1000
14
2/4
400
M3201A
AWG
500
16
2/4
200
M3102A
Speed
(MSa/s)
Bits
Ch
BW
(MHz)
Digitizer
500
14
2/4
DC-200
M3100A
Digitizer
100
14
4/8
DC-100
M3302A
Combo
500
16
2
200
500
14
2
DC-200
M3300A
Combo
500
16
2/4
200
100
14
4/8
DC-100
05 | Keysight | M3302A PXIe Arbitrary Waveform Generator and Digitizer Combo with Optional Real-Time Sequencing and FPGA Programming - Data Sheet
AWG Technical Specifications and Characteristics
General characteristics
M3302A-C22
Parameter
Min
Typ
Max
Units
Comments
Inputs and outputs
Channels (single-ended mode)
2
Out
Channels (differential mode)
1
Out
clock 1
1
Out
Reference clock 2
1
In
Triggers/markers 1, 3
1
In/out
Reconfigurable
Triggers/markers 2, 3
8
In/out
Reconfigurable
Reference
Differential uses 2 channels
Output channels overview
Sampling rate 4
0.005
Voltage resolution
Output frequency
500
16
DC
Real-time BW
Output voltage
–1.5
MSa/s
Bits
200
MHz
200
MHz
1.5
Volts
Built-in functionalities
Function generators
2
1 per channel
Dual AWGs
2
1 per channel
IQ modulators
2
1 per channel
Frequency modulators
2
1 per channel
Phase modulators
2
1 per channel
Amplitude modulators
2
1 per channel
DC offset modulators
2
1 per channel
Onboard memory
RAM memory
1.
2.
3.
4.
16
2048
MBytes
At front panel
At backplane
Markers available from firmware version v3.0 or later
(-CLV) option: DC to 500 MSa/s; (-CLF) option: fixed 500 MSa/s
06 | Keysight | M3302A PXIe Arbitrary Waveform Generator and Digitizer Combo with Optional Real-Time Sequencing and FPGA Programming - Data Sheet
I/O specifications
M3302A-C22
Parameter
Min
Typ
Max
Units
Comments
100
500
MSa/s
0
200
MHz
Limited by a reconstruction filter
–1.5
1.5
Volts
On a 50 Ω load
Output channels
Sampling rate 1
Output frequency
Output voltage
Source impedance
50
Ω
Reference clock output
10 to 12.52
Frequency
MHz
Generated from the internal clock, user selectable
800
mVpp
On a 50 Ω load
Power
2
dBm
On a 50 Ω load
Source impedance
50
Ω
AC coupled
Voltage
External I/O trigger/marker
VIH
2
5
V
VIL
0
0.8
V
VOH
2.4
3.3
V
On a high Z load
VOL
0
0.25 V
On a high Z load
Input impedance
10
KΩ
Source impedance
TTL
–
Speed
100
MHz
1. (-CLV) option: 100 to 500 MSa/s; (-CLF) option: fixed 500 MSa/s
2. CLF option is set to 10 MHz while with CLV option varies from 12.5 MHz to 10 MHz
07 | Keysight | M3302A PXIe Arbitrary Waveform Generator and Digitizer Combo with Optional Real-Time Sequencing and FPGA Programming - Data Sheet
Function generators (FGs) specifications
M3302A-C22
Parameter
Min
Typ
Max
Units
Comments
General specifications
Function generators
2
–
1 per channel
Waveform types
4
–
Sinusoidal, triangular, square and DC
Frequency range
0
200
MHz
Frequency resolution
45
Bits
Frequency resolution
5.7
µHz
Phase range
0
360
Deg
Phase resolution
24
Bits
Phase resolution
21.5
µdeg
Frequency change rate
100
MChanges/s
With HVI technology
Frequency modulation rate
500
MSamples/s
With AWGs and angle modulators
Phase change rate
100
MChanges/s
With HVI technology
Phase modulation rate
500
MSamples/s
With AWGs and angle modulators
Max
Units
Comments
1.5
Volts
Amplitude + offset values
Speed performance
Amplitude and offset specifications
M3302A-C22
Parameter
Min
Typ
General specifications
Amplitude/offset range
–1.5
Amplitude/offset resolution
16
Bits
Amplitude/offset resolution
45.8
µV
Amplitude/offset change rate
500
MChanges/s
With HVI technology
Amplitude/offset modulation rate
500
MSamples/s
With AWGs and amplitude modulators
Speed performance
08 | Keysight | M3302A PXIe Arbitrary Waveform Generator and Digitizer Combo with Optional Real-Time Sequencing and FPGA Programming - Data Sheet
Arbitrary waveform generators (AWGs) specifications
M3302A-C22
Parameter
Min
Typ
Max
Units
Comments
General specifications
Dual AWGs
2
Aggregated speed (16 bits)
Aggregated speed (32 bits)
Waveform multiple
1 Dual AWG per output channel
2000
MSa/s
For all onboard waveforms combined
1000
MSa/s
For all onboard waveforms combined
Samples
Waveform length must be a multiple of this value
957M
Samples
Maximum depends on onboard RAM
478M
Samples
Maximum depends on onboard RAM
%
Effic. = waveform size/waveform size in RAM
5
16-bit waveform length
15
32-bit waveform length
10
Waveform length efficiency
Trigger
93.5
Selec.
External Trigger (input connector, backplane triggers), software trigger
AWG specifications (16-bit single waveform)
Speed
500
Resolution
AWG destination
16
MSa/s
Per AWG
Bits
Selec.
Amplitude, offset, frequency or phase
AWG specifications (16-bit dual waveform)
Speed (waveform A)
500
MSa/s
Per AWG
Speed (waveform B)
500
MSa/s
Per AWG
Resolution (waveform A)
Resolution (waveform B)
16
Bits
16
Bits
AWG destination (waveform A)
Selec.
Amplitude, offset or I
AWG destination (waveform B)
Selec.
Frequency, phase or Q
AWG specifications (32-bit single waveform)
Speed
Resolution
AWG destination
100
32
MSa/s
Per AWG, minimum prescaler: 1
Bits
Selec.
Amplitude, offset, frequency or phase
AWG specifications (32-bit dual waveform)
Speed (waveform A)
Speed (waveform B)
100
MSa/s
Per AWG, minimum prescaler: 1
100
MSa/s
Per AWG, minimum prescaler: 1
Resolution (waveform A)
32
Bits
Resolution (waveform B)
32
Bits
AWG destination (waveform A)
Selec.
Amplitude or offset
AWG destination (waveform B)
Selec.
Frequency or phase
09 | Keysight | M3302A PXIe Arbitrary Waveform Generator and Digitizer Combo with Optional Real-Time Sequencing and FPGA Programming - Data Sheet
Angle modulators specifications
M3302A-C22
Parameter
Min
Typ
Max
Units
Comments
General specifications
Frequency modulators
2
1 per output channel
Phase modulators
2
1 per output channel
Carrier signal source
FGs
Modulating signal source
Table 3 on page 8
AWGs
Table 5 on the 9
Frequency modulators (16-bit modulating waveform)
Deviation
–Dev. gain
Modulating signal resolution
+Dev. gain
16
Modulating signal BW
0
Deviation gain
0
Deviation gain resolution
MHz
Bits
AWG waveform
250
MHz
AWG Nyquist limit
200
MHz
16
Bits
Frequency modulators (32-bit modulating waveform)
Deviation
–Dev. gain
Modulating signal resolution
+Dev. gain
32
MHz
Bits
AWG waveform
AWG Nyquist limit
Modulating signal BW
0
50
MHz
Deviation gain
0
200
MHz
Deviation gain resolution
16
Bits
Phase modulators (16-bit modulating waveform)
Deviation
–Dev. gain
Modulating signal resolution
+Dev. gain
16
Deg
Bits
AWG waveform
AWG Nyquist limit
Modulating signal BW
0
250
MHz
Deviation gain
0
180
Deg
Deviation gain resolution
16
Bits
~ 5.5 mdeg
Phase modulators (32-bit modulating waveform)
Deviation
–Dev. gin
Modulating signal resolution
+Dev. gain
16
Deg
Bits
AWG waveform is truncated
AWG Nyquist limit
Modulating signal BW
0
50
MHz
Deviation gain
0
180
Deg
Deviation gain resolution
16
Bits
~ 5.5 mdeg
10 | Keysight | M3302A PXIe Arbitrary Waveform Generator and Digitizer Combo with Optional Real-Time Sequencing and FPGA Programming - Data Sheet
Amplitude modulators specifications
M3302A-C22
Parameter
Min
Typ
Max
Units
Comments
General specifications
Amplitude modulators
2
1 per output channel
Offset modulators
2
1 per output channel
Carrier signal source
Modulating signal source
FGs
Table 3 on page 8
AWGs
Table 5 on page 9
Amplitude & offset modulators (16-bit modulating waveform)
Deviation
–Dev. gain
Modulating signal resolution
+Dev. gain
16
Modulating signal BW
0
Deviation gain
0
Deviation gain resolution
Vp
Bits
AWG waveform
250
MHz
AWG Nyquist limit
1.5
Vp
16
Bits
Limited by the output DAC
Amplitude & offset modulators (32-bit modulating waveform)
Deviation
–Dev. gain
Modulating signal resolution
+Dev. gain
16
Vp
Bits
AWG waveform is truncated
AWG Nyquist limit
Modulating signal BW
0
50
MHz
Deviation gain
0
1.5
Vp
Deviation gain resolution
16
Bits
Limited by the output DAC
11 | Keysight | M3302A PXIe Arbitrary Waveform Generator and Digitizer Combo with Optional Real-Time Sequencing and FPGA Programming - Data Sheet
IQ modulators specifications
M3302A-C22
Parameter
Min
Typ
Max
Units
Comments
General specifications
IQ modulators
2
Carrier signal source
Modulating signal source
1 per output channel
FGs
Table 3 on page 8
AWGs
Table 5 on page 9
External I/O trigger/marker
Amplitude deviation
−1.5
Phase deviation
−180
I modulating signal resolution
I modulating signal BW
Vp
180
Deg
16
0
Q modulating signal resolution
Q modulating signal BW
1.5
250
16
0
Bits
AWG waveform
MHz
AWG Nyquist limit
Bits
AWG waveform
250
MHz
AWG Nyquist limit
Max
Units
Comments
500
MHz
Clock system specifications
M3302A-C22
Parameter
Min
Typ
General specifications
Clock frequency 1
1.
> 100
(-CLV) option: 100 to 500 MSa/s; (-CLF) option: fixed 500 MSa/s
12 | Keysight | M3302A PXIe Arbitrary Waveform Generator and Digitizer Combo with Optional Real-Time Sequencing and FPGA Programming - Data Sheet
AC performance
M3302A-C22
Parameter
Min
Typ
Max
Units
Comments
General characteristics
Analog output jitter
<2
ps
RMS (cycle-to-cycle)
AWG trigger to output jitter
<2
ps
RMS (cycle-to-cycle) for any trigger referenced to the chassis clock;
independent of input trigger jitter if input jitter < 4nS peak-to-peak
Trigger resolution
10
ns
< 20
ps
Between ch 0 & ch 1, and ch 2 & ch 3
< 50
ps
Between any channel
< 150
ps
Between modules, chassis dependant 2
Clock output jitter
<2
ps
RMS (cycle-to-cycle)
Clock accuracy and stability
100
ppm
PXIe, cPCIe versions; chassis dependent 1.
Channel-to-channel skew
AC characteristics
Spurious-free dynamic range (SFDR)
Pout = 4 dBm, measured from DC to max frequency
fout = 10 MHz
68
dBc
fout = 80 MHz
64
dBc
fout = 120 MHz
57
dBc
fout = 160 MHz
54
dBc
< –105
dB
fout = 80 MHz
–75
dB
fout = 120 MHz
–88
dB
fout = 160 MHz
–73
dB
fout = 10 MHz
< –105
dB
fout = 80 MHz
–78
dB
fout = 120 MHz
< –105
dB
fout = 160 MHz
–92
dB
Crosstalk (adjacent channels)
fout = 10 MHz
Crosstalk (non-adjacent channels)
Phase noise (SSB)
offset = 1 KHz
< –127
dBc/Hz
offset = 10 KHz
< –133
dBc/Hz
offset = 100 KHz
< –138
dBc/Hz
< –145
dBm/Hz
Average noise power density
1. This value corresponds to a M9505A chassis. This value can be improved with an external chassis clock or a system timing module.
2. This value corresponds to a M9005A PXIe chassis.
13 | Keysight | M3302A PXIe Arbitrary Waveform Generator and Digitizer Combo with Optional Real-Time Sequencing and FPGA Programming - Data Sheet
AC performance, typical
Figure 3. Single-tone spectrum @ fout = 10 MHz
Figure 4. Single-tone spectrum @ fout = 80 MHz
14 | Keysight | M3302A PXIe Arbitrary Waveform Generator and Digitizer Combo with Optional Real-Time Sequencing and FPGA Programming - Data Sheet
AC performance, typical
Figure 5. Single-tone spectrum @ fout = 120 MHz
Figure 6. Single-tone spectrum @ fout = 160 MHz
15 | Keysight | M3302A PXIe Arbitrary Waveform Generator and Digitizer Combo with Optional Real-Time Sequencing and FPGA Programming - Data Sheet
Digitizer Technical Specifications and Characteristics
General characteristics
M3302A-C22
Parameter
Min
Typ
Max
Units
Comments
Inputs and outputs
Channels
2
Out
Reference clock 1
1
Out
clock 2
Reference
1
In
Triggers/markers1, 3
1
In/out
Reconfigurable
Triggers/markers 2, 3
8
In/out
Reconfigurable
500
MSa/s
Input channels overview
Sampling rate 4
Voltage resolution
Input frequency
14
0
Bits
200
MHz
Real-time BW
200
MHz
Time skew
< 50
ps
Between channels
Built-in functionalities
Input conditioning blocks
2
1 per channel
Analog trigger processors
2
1 per channel
Data acquisition blocks
2
1 per channel
Onboard memory
RAM memory
1.
2.
3.
4.
16
2048
MBytes
At front panel
At backplane
Markers available from firmware version v3.0 or later
(-CLV) option: 100 to 500 MSa/s; (-CLF) option: fixed 500 MSa/s
16 | Keysight | M3302A PXIe Arbitrary Waveform Generator and Digitizer Combo with Optional Real-Time Sequencing and FPGA Programming - Data Sheet
I/O specifications
Analog input characteristics
Number of channels
C22
Sampling rate
500 MSa/s option -CLF
variable rate option -CLV
Configurable inputs: impedance
50 Ω or 1 MΩ (HiZ)
Configurable inputs: Coupling
AC or DC
Input voltage range (50 Ω)
125 mVpp to 8 Vpp (7 scales: 0.125, 0.25, 0,5, 1, 2, 4, 8 Vpp)
Input voltage range (HiZ)
200 mVpp to 16 Vpp (7 scales: 0.2, 0.4, 0.8, 2, 4, 8, 16 Vpp)
Bandwidth limit filters
200 MHz
Effective number of bits
(ENOB)1
10.6 bits @ 95 MHz (typical)
Noise floor1
-146 dBm/Hz
SINAD1
66 dB @ 95 MHz (typical)
Spurious free dynamic range (SFDR) + Total Harmonic
1.
Distorsion1
71 dBc @ 95 MHz (typical)
measured at -1 DBFS input signal with 1 Vpp 50 Ω
M3302A-C22
Parameter
Min
Typ
Max
Units
Comments
10 to 12.52
MHz
Generated from the internal clock. User selectable
Voltage
800
mVpp
On a 50 Ω load
Power
2
dBm
On a 50 Ω load
Source impedance
50
Ω
AC coupled
Reference clock output
Frequency
External I/O trigger/marker
VIH
2
5
V
VIL
0
0.8
V
VOH
2.4
3.3
V
On a high Z load
VOL
0
0.25
V
On a high Z load
Input impedance
10
KΩ
Source impedance
TTL
-
Speed
100
MHz
2.
CLF option is set to 10 MHz while with CLV option varies from 12.5 MHz to 10 MHz
17 | Keysight | M3302A PXIe Arbitrary Waveform Generator and Digitizer Combo with Optional Real-Time Sequencing and FPGA Programming - Data Sheet
Data acquisition blocks (DAQs) specifications
M3302A-C22
Parameter
Min
Typ
Max
Units
Comments
General specifications
DAQs
2
1 per channel
Aggregated speed
1000
Acquisition burst multiple
Acquisition RAM capacity
5
15
957M
Acquisition RAM capacity effic.
93.5
Trigger
MSa/s
For all onboard DAQs combined
Samples
Burst length must be a multiple of this value
Samples
Maximum depends on onboard RAM
%
Effic. = waveform size/waveform size in RAM
Selec.
Hardware trigger (analog channels, input trigger, backplane triggers),
Software trigger
DAQ specifications
Speed
500
Resolution
14
MSa/s
Per DAQ
Bits
Clock system specifications
M3302A-C22
Parameter
Min
Max
Units
Comments
Clock frequency (-CLF)
500
500
MHz
Fixed clock
Clock frequency (-CLV)
100
500
MHz
Variable clock
General specifications
18 | Keysight | M3302A PXIe Arbitrary Waveform Generator and Digitizer Combo with Optional Real-Time Sequencing and FPGA Programming - Data Sheet
System Specifications
Environmental specifications (PXI Express)
M3302A-C22
Parameter
Min
Typ
Max
Units
Comments
Slots
PXI Express (CompactPCI Express compatible)
–
Automatic gen negotiation, chassis dependent
Lanes
Automatic lane negotiation, chassis dependent
System bus
Slots
2
PCI Express type
Gen 1
Gen 2
PCI Express link
1
4
Power dissipation
3.3 V PXIe power supply
3
A
~ 10 W
12 V PXIe power supply
3.5
A
~ 40 W
Environmental 1
Temperature range
Operating
Non-operating
0 to +55°C (10,000 feet)
-40 to +70 °C (up to 15,000 feet)
Max operative altitude
4000 m (10,000 feet)
Operating Humidity range (%RH)
10 to 95% at 40 °C
Non-operating Humidity range (%RH): 5 to 95
5 to 95%
Calibration interval
1 year
EMC
Complies with European EMC Directive
– IEC/EN 61326-1
– CISPR Pub 11 Group 1, class A
This ISM device is in compliance with Canadian ICES-001
Cet appareil ISM est conforme à la norme NMB-001 du Canada.
This ISM device is in compliance with Australian and New Zealand RCM
This ISM device is in compliance with South Korea EMC KCC
1.
Samples of this product have been type tested in accordance with the Keysight Environmental Test Manual and verified to be robust against the environmental stresses of Storage, Transportation and End-use; those stresses include but are not limited to temperature, humidity, shock, vibration, altitude and
power line conditions. Test Methods are aligned with IEC 60068-2 and levels are similar to MIL-PRF-28800F Class 3.
19 | Keysight | M3302A PXIe Arbitrary Waveform Generator and Digitizer Combo with Optional Real-Time Sequencing and FPGA Programming - Data Sheet
Ordering Information 1
Product
Description
M3302A
Arbitrary waveform generator: 500 MSa/s, 16 Bits + digitizer: 500 MSa/s, 14 Bits
Options
Description
M3302A-C22
Two channels AWG + Two channels DIG 2
M3302A-CLV / -CLF
Variable sampling clock 2 / fixed sampling clock, low jitter
M3302A-DM1
Dual modulation capability for the AWG (amplitude and angle simultaneously)
M3302A-M01 / -M12 / -M20
Memory 16 MB, 8 MSamples 2 / 128 MB, 60 MSamples / 2 GB, 1 GSamples
HW programming options
Description
M3302A-HVI
Enabled HVI programming, requires an HVI design environment license (M3601A)
M3302A-FP1
Enabled FPGA programming, requires -K32 or -K41 option and an FPGA design environment license (M3602A)
M3302A-K32 / -K41
FPGA, Xilinx 7K325T / 7K410T, required for -FP1 option only (needs memory option -M20)
Related software
Description
M3601A
HVI design environment
M3602A
FPGA design environment
1. All options must be selected at time of purchase and are not upgradable
2. These options represent the standard configuration
20 | Keysight | M3302A PXIe Arbitrary Waveform Generator and Digitizer Combo with Optional Real-Time Sequencing and FPGA Programming - Data Sheet
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Asia Pacific
Australia
China
Hong Kong
India
Japan
Korea
Malaysia
Singapore
Taiwan
Other AP Countries
1 800 629 485
800 810 0189
800 938 693
1 800 11 2626
0120 (421) 345
080 769 0800
1 800 888 848
1 800 375 8100
0800 047 866
(65) 6375 8100
Europe & Middle East
Austria
Belgium
Finland
France
Germany
Ireland
Israel
Italy
Luxembourg
Netherlands
Russia
Spain
Sweden
Switzerland
United Kingdom
0800 001122
0800 58580
0800 523252
0805 980333
0800 6270999
1800 832700
1 809 343051
800 599100
+32 800 58580
0800 0233200
8800 5009286
800 000154
0200 882255
0800 805353
Opt. 1 (DE)
Opt. 2 (FR)
Opt. 3 (IT)
0800 0260637
For other unlisted countries:
www.keysight.com/find/contactus
(BP-9-7-17)
DEKRA Certified
ISO9001 Quality Management System
www.keysight.com/find/m3302a
www.keysight.com/go/quality
Keysight Technologies, Inc.
DEKRA Certified ISO 9001:2015
Quality Management System
This information is subject to change without notice.
© Keysight Technologies, 2017 - 2018
Published in USA, February 20, 2018
5992-1808EN
www.keysight.com
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