ESD8501V5 Transient Voltage Suppressors Features • Protection for the following IEC Standards: • IEC61000−4−2 Level 4: ±30 kV Contact Discharge IEC61000−4−5 (Lightning) 70 A (8/20 ms) These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS Compliant http://onsemi.com 1 Cathode 2 Anode MAXIMUM RATINGS Rating IEC 61000−4−2 (ESD) Symbol Value Unit ±30 ±30 kV TJ, Tstg −65 to +150 °C IPP 70 A Contact Air Operating Junction and Storage Temperature Range Maximum Peak Pulse Current 8/20 ms @ TA = 25°C Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. MARKING DIAGRAM UDFN2 CASE 517CZ A M AM = Specific Device Code = Date Code ORDERING INFORMATION Device Package Shipping† ESD8501V5MUT5G UDFN2 (Pb−Free) 8000 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. © Semiconductor Components Industries, LLC, 2014 November, 2014 − Rev. 1 1 Publication Order Number: ESD8501V5/D ESD8501V5 ELECTRICAL CHARACTERISTICS I (TA = 25°C unless otherwise noted) IF Parameter Symbol IPP Maximum Reverse Peak Pulse Current VC Clamping Voltage @ IPP VRWM IR VBR IT VC VBR VRWM Working Peak Reverse Voltage V IR VF IT Maximum Reverse Leakage Current @ VRWM Breakdown Voltage @ IT Test Current *See Application Note AND8308/D for detailed explanations of datasheet parameters. IPP Uni−Directional TVS ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise specified) Parameter Reverse Working Voltage Breakdown Voltage (Note 1) Symbol Conditions Min Typ VRWM VBR IT = 1 mA 6.0 Unit 5.0 V 9.0 V Reverse Leakage Current IR VRWM = 5 V 0.1 mA Clamping Voltage (Note 2) VC IPP = 1 A, tp = 8 x 20 ms 7.5 V Clamping Voltage (Note 2) VC IPP = 35 A, tp = 8 x 20 ms 9.5 V Clamping Voltage (Note 2) VC IPP = 70 A, tp = 8 x 20 ms 11.5 V Junction Capacitance CJ VR = 0 V, f = 1 MHz 16 pF Dynamic Resistance RDYN TLP Pulse 7.0 Max 0.04 W Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 1. Breakdown voltage is tested from pin 1 to 2 and pin 2 to 1. 2. Non−repetitive current pulse at TA = 25°C, per IEC61000−4−5 waveform. http://onsemi.com 2 ESD8501V5 14 9 8 12 7 10 Vpk (V) 5 4 3 8 6 4 2 2 1 0 0 0 5 10 15 20 25 30 0 10 20 30 40 50 60 70 Ipk (A) Ipk (A) Figure 1. Positive TLP I−V Curve Figure 2. Clamping Voltage vs. Peak Pulse Current (tp = 8/20 ms) 50 45 40 35 C (pF) Vpk (V) 6 30 25 20 15 10 5 0 0 1 2 3 4 VBias (V) Figure 3. CV Characteristics http://onsemi.com 3 5 6 80 ESD8501V5 Transmission Line Pulse (TLP) Measurement L Transmission Line Pulse (TLP) provides current versus voltage (I−V) curves in which each data point is obtained from a 100 ns long rectangular pulse from a charged transmission line. A simplified schematic of a typical TLP system is shown in Figure 4. TLP I−V curves of ESD protection devices accurately demonstrate the product’s ESD capability because the 10s of amps current levels and under 100 ns time scale match those of an ESD event. This is illustrated in Figure 5 where an 8 kV IEC 61000−4−2 current waveform is compared with TLP current pulses at 8 A and 16 A. A TLP I−V curve shows the voltage at which the device turns on as well as how well the device clamps voltage over a range of current levels. For more information on TLP measurements and how to interpret them please refer to AND9007/D. S Attenuator ÷ 50 W Coax Cable 10 MW IM 50 W Coax Cable VM DUT VC Oscilloscope Figure 4. Simplified Schematic of a Typical TLP System Figure 5. Comparison Between 8 kV IEC 61000−4−2 and 8 A and 16 A TLP Waveforms http://onsemi.com 4 ESD8501V5 IEC61000−4−2 Waveform IEC 61000−4−2 Spec. Ipeak Level Test Voltage (kV) First Peak Current (A) Current at 30 ns (A) Current at 60 ns (A) 1 2 7.5 4 2 2 4 15 8 4 3 6 22.5 12 6 4 8 30 16 8 100% 90% I @ 30 ns I @ 60 ns 10% tP = 0.7 ns to 1 ns Figure 6. IEC61000−4−2 Spec ESD Gun Oscilloscope TVS 50 W Cable 50 W Figure 7. Diagram of ESD Test Setup ESD Voltage Clamping at the device level. ON Semiconductor has developed a way to examine the entire voltage waveform across the ESD protection diode over the time domain of an ESD pulse in the form of an oscilloscope screenshot, which can be found on the datasheets for all ESD protection diodes. For more information on how ON Semiconductor creates these screenshots and how to interpret them please refer to AND8307/D. For sensitive circuit elements it is important to limit the voltage that an IC will be exposed to during an ESD event to as low a voltage as possible. The ESD clamping voltage is the voltage drop across the ESD protection diode during an ESD event per the IEC61000−4−2 waveform. Since the IEC61000−4−2 was written as a pass/fail spec for larger systems such as cell phones or laptop computers it is not clearly defined in the spec how to specify a clamping voltage % OF PEAK PULSE CURRENT 100 PEAK VALUE IRSM @ 8 ms tr 90 PULSE WIDTH (tP) IS DEFINED AS THAT POINT WHERE THE PEAK CURRENT DECAY = 8 ms 80 70 60 HALF VALUE IRSM/2 @ 20 ms 50 40 30 tP 20 10 0 0 20 40 t, TIME (ms) 60 Figure 8. 8 X 20 ms Pulse Waveform http://onsemi.com 5 80 ESD8501V5 PACKAGE DIMENSIONS UDFN2 1.6x1.0, 1.1P CASE 517CZ ISSUE A A B D PIN ONE REFERENCE 0.08 C 2X 2X ÉÉÉ ÉÉÉ NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. E DIM A A1 b D E e L 0.08 C TOP VIEW A 0.05 C MILLIMETERS MIN MAX 0.45 0.55 −−− 0.05 0.85 0.95 1.60 BSC 1.00 BSC 1.10 BSC 0.35 0.45 RECOMMENDED SOLDERING FOOTPRINT* 0.05 C A1 C SIDE VIEW 1.70 SEATING PLANE e 1 e/2 0.07 M C A B 1 2X b 2X BOTTOM VIEW 2X 1.00 0.58 DIMENSIONS: MILLIMETERS L 0.07 M *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. C A B ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. 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