ON MC33362DWR2 High voltage switching regulator Datasheet

MC33362
High Voltage Switching
Regulator
The MC33362 is a monolithic high voltage switching regulator that
is specifically designed to operate from a rectified 120 VAC line
source. This integrated circuit features an on−chip 500 V/2.0 A
SENSEFET power switch, 250 V active off−line startup FET, duty
cycle controlled oscillator, current limiting comparator with a
programmable threshold and leading edge blanking, latching pulse
width modulator for double pulse suppression, high gain error
amplifier, and a trimmed internal bandgap reference. Protective
features include cycle−by−cycle current limiting, input undervoltage
lockout with hysteresis, output overvoltage protection, and thermal
shutdown. This device is available in a 16−lead dual−in−line and wide
body surface mount packages.
• On−Chip 500 V, 2.0 A SENSEFET Power Switch
• Rectified 120 VAC Line Source Operation
• On−Chip 250 V Active Off−Line Startup FET
• Latching PWM for Double Pulse Suppression
• Cycle−By−Cycle Current Limiting
• Input Undervoltage Lockout with Hysteresis
• Output Overvoltage Protection Comparator
• Trimmed Internal Bandgap Reference
• Internal Thermal Shutdown
• Pb−Free Packages are Available
AC Input
Startup Input
http://onsemi.com
MARKING
DIAGRAMS
16
1
16
1
PDIP−16
P SUFFIX
CASE 648E
MC33362P
AWLYYWW
SO−16W
DW SUFFIX
CASE 751N
MC33362DW
AWLYYWW
A
WL
YY
WW
= Assembly Location
= Wafer Lot
= Year
= Work Week
PIN CONNECTIONS
Startup Input
1
VCC
3
1
16
4
13
5
12
RT
6
11
CT
7
10
Regulator Output
8
GND
GND
Regulator
Output
Startup
Mirror
VCC
Reg
8
UVLO
6
OVP
RT
CT
PWM Latch
OSC
7
Driver
S
Q
3
Overvoltage
Protection
Input
DC Output
11
16
Ipk
Power Switch
Drain
ORDERING INFORMATION
Device
MC33362DW
LEB
Compensation
Thermal
GND
4, 5, 12, 13
Voltage
Feedback
Input
Figure 1. Simplified Application
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
April, 2005 − Rev. 6
Shipping †
47 Units/Rail
MC33362DWG
SO−16W
(Pb−Free)
47 Units/Rail
MC33362DWR2
SO−16W
1000 Tape & Reel
MC33362DWR2G
SO−16W
(Pb−Free)
1000 Tape & Reel
MC33362P
PDIP−16
25 Units/Rail
10
This device contains 221 active transistors.
 Semiconductor Components Industries, LLC, 2005
Package
SO−16W
9
EA
9
Overvoltage
Protection Input
Voltage Feedback
Input
Compensation
(Top View)
R
PWM
Power Switch
Drain
1
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
Publication Order Number:
MC33362/D
MC33362
MAXIMUM RATINGS (Note 1)
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
ÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
ÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁ
ÁÁÁÁ
ÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁ
ÁÁÁÁ
ÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
ÁÁÁ
Symbol
Value
Unit
Power Switch (Pin 16)
Drain Voltage
Drain Current
Rating
VDS
IDS
500
2.0
V
A
Startup Input Voltage (Pin 1, Note 2)
Vin
400
V
Power Supply Voltage (Pin 3)
VCC
40
V
Input Voltage Range
Voltage Feedback Input (Pin 10)
Compensation (Pin 9)
Overvoltage Protection Input (Pin 11)
RT (Pin 6)
CT (Pin 7)
VIR
−1.0 to Vreg
V
Thermal Characteristics
P Suffix, Dual−In−Line Case 648E
Thermal Resistance, Junction−to−Air
Thermal Resistance, Junction−to−Case
(Pins 4, 5, 12, 13)
DW Suffix, Surface Mount Case 751N
Thermal Resistance, Junction−to−Air
Thermal Resistance, Junction−to−Case
(Pins 4, 5, 12, 13)
Refer to Figures 17 and 18 for additional thermal information.
°C/W
RqJA
RqJC
80
15
95
15
Operating Junction Temperature
TJ
− 25 to +150
°C
Storage Temperature
Tstg
− 55 to +150
°C
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit
values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied,
damage may occur and reliability may be affected.
1. This device series contains ESD protection and exceeds the following tests:
Human Body Model 2000 V per MIL−STD−883, Method 3015.
Machine Model Method 200 V.
ELECTRICAL CHARACTERISTICS (VCC = 20 V, RT = 10 k, CT = 390 pF, CPin 8 = 1.0 mF, for typical values TJ = 25°C,
for min/max values TJ is the operating junction temperature range that applies (Note 3), unless otherwise noted.)
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁÁÁÁ
ÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁÁÁÁ
ÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁÁÁÁ
ÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Characteristic
Symbol
Min
Typ
Max
Unit
Vreg
5.5
6.5
7.5
V
Line Regulation (VCC = 20 V to 40 V)
Regline
−
30
500
mV
Load Regulation (IO = 0 mA to 10 mA)
Regload
−
44
200
mV
Vreg
5.3
−
8.0
V
260
255
60
59
285
−
67.5
−
310
315
75
76
DfOSC/DV
−
0.1
2.0
kHz
VFB
2.52
2.6
2.68
V
Regline
−
0.6
5.0
mV
IIB
−
20
500
nA
REGULATOR (Pin 8)
Output Voltage (IO = 0 mA, TJ = 25°C)
Total Output Variation over Line, Load, and Temperature
OSCILLATOR (Pin 7)
Frequency
CT = 390 pF
CT = 2.0 nF
fOSC
TJ = 25°C (VCC = 20 V)
TJ = Tlow to Thigh (VCC = 20 V to 40 V)
TJ = 25°C (VCC = 20 V)
TJ = Tlow to Thigh (VCC = 20 V to 40 V)
Frequency Change with Voltage (VCC = 20 V to 40 V)
kHz
ERROR AMPLIFIER (Pins 9, 10)
Voltage Feedback Input Threshold
Line Regulation (VCC = 20 V to 40 V, TJ = 25°C)
Input Bias Current (VFB = 2.6 V)
2. Maximum power dissipation limits must be observed.
3. Tested junction temperature range for the MC33362:
Tlow = −25°C
Thigh = +125°C
4. Tested junction temperature range for the MC33362:
Tlow = −25°C
Thigh = +125°C
http://onsemi.com
2
MC33362
ELECTRICAL CHARACTERISTICS (continued) (VCC = 20 V, RT = 10 k, CT = 390 pF, CPin 8 = 1.0 mF, for typical values TJ = 25°C,
for min/max values TJ is the operating junction temperature range that applies (Note 3), unless otherwise noted.)
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁÁÁÁ
ÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁÁÁÁ
ÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁÁÁÁ
ÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁÁÁÁ
ÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁÁÁÁ
ÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁÁÁÁ
ÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Characteristic
Symbol
Min
Typ
Max
Unit
Open Loop Voltage Gain (TJ= 25°C)
AVOL
−
82
−
dB
Gain Bandwidth Product (f = 100 kHz, TJ= 25°C)
GBW
−
1.0
−
MHz
Output Voltage Swing
High State (ISource = 100 mA, VFB < 2.0 V)
Low State (ISink = 100 mA, VFB > 3.0 V)
VOH
VOL
4.0
−
5.3
0.2
−
0.35
Input Threshold Voltage
Vth
2.47
2.6
2.73
V
Input Bias Current (Vin = 2.6 V)
IIB
−
100
500
nA
DC(max)
DC(min)
48
−
50
0
52
0
−
−
4.4
−
6.0
12
ID(off)
−
0.2
50
mA
Rise Time
tr
−
50
−
ns
Fall Time
tf
−
50
−
ns
Ilim
0.7
0.9
1.1
A
2.0
2.0
5.0
5.0
8.0
8.0
ERROR AMPLIFIER (Pins 9, 10)
V
OVERVOLTAGE DETECTION (Pin 11)
PWM COMPARATOR (Pins 7, 9)
Duty Cycle
Maximum (VFB = 0 V)
Minimum (VFB = 2.7 V)
%
POWER SWITCH (Pin 16)
Drain−Source On−State Resistance (ID = 200 mA)
TJ = 25°C
TJ = Tlow to Thigh
RDS(on)
Drain−Source Off−State Leakage Current (VDS = 500 V)
W
OVERCURRENT COMPARATOR (Pin 16)
Current Limit Threshold (RT = 10 k)
STARTUP CONTROL (Pin 1)
Peak Startup Current (Vin = 50 V) (TJ = −25°C to 100°C)
VCC = 0 V
VCC = (Vth(on) − 0.2 V)
Istart
mA
Off−State Leakage Current (Vin = 50 V, VCC = 20 V)
ID(off)
−
40
200
mA
Vth(on)
11
14.5
18
V
VCC(min)
7.5
9.5
11.5
V
−
−
0.3
3.6
0.5
5.0
UNDERVOLTAGE LOCKOUT (Pin 3)
Startup Threshold (VCC Increasing)
Minimum Operating Voltage After Turn−On
TOTAL DEVICE (Pin 3)
Power Supply Current
Startup (VCC = 10 V, Pin 1 Open)
Operating
ICC
2. Maximum power dissipation limits must be observed.
3. Tested junction temperature range for the MC33362:
Tlow = −25°C
Thigh = +125°C
4. Tested junction temperature range for the MC33362:
Tlow = −25°C
Thigh = +125°C
http://onsemi.com
3
mA
f OSC, OSCILLATOR FREQUENCY (Hz)
1.0 M
VCC = 20 V
TA = 25°C
CT = 100 pF
500 k CT = 200 pF
I PK, POWER SWITCH PEAK DRAIN CURRENT (A
MC33362
CT = 500 pF
200 k
CT = 1.0 nF
100 k
CT = 2.0 nF
50 k
CT = 5.0 nF
20 k
CT = 10 nF
10 k
5.0
10
15
20
30
50
RT, TIMING RESISTOR (kW)
2.0
VCC = 20 V
CT = 1.0 mF
TA = 25°C
1.5
1.0
0.8
0.6
0.4
Inductor supply voltage and inductance value are
adjusted so that Ipk turn−off is achieved at 5.0 ms.
0.2
5.0
Dmax, MAXIMUM OUTPUT DUTY CYCLE (%)
VCC = 20 V
TA = 25°C
0.5
0.3
0.2
0.15
10
15
20
30
20
30
40
50
70
60
50
40
RC/RT Ratio
Charge Resistor
Pin 7 to Vreg
30
1.0
2.0
3.0
5.0
7.0
TIMING RESISTOR RATIO
Figure 5. Maximum Output Duty Cycle
versus Timing Resistor Ratio
Gain
60
0
30
60
Phase
40
90
20
120
0
150
100
1.0 k
10 k
100 k
θ, EXCESS PHASE (DEGREES)
VCC = 20 V
VO = 1.0 to 4.0 V
RL = 5.0 MW
CL = 2.0 pF
TA = 25°C
180
10 M
1.0 M
Vsat , OUTPUT SATURATION VOLTAGE (V)
RT, TIMING RESISTOR (kW)
80
50
VCC = 20 V
CT = 2.0 nF
TA = 25°C
RD/RT Ratio
Discharge Resistor
Pin 7 to GND
Figure 4. Oscillator Charge/Discharge
Current versus Timing Resistor
100
−20
10
15
Figure 3. Power Switch Peak Drain Current
versus Timing Resistor
1.0
0.1
5.0
10
RT, TIMING RESISTOR (kW)
Figure 2. Oscillator Frequency
versus Timing Resistor
0.7
7.0
0
Source Saturation)
(Load to Ground)
−1.0
Vref
−2.0
2.0
Sink Saturation
(Load to Vref)
VCC = 20 V
TA = 25°C
1.0
GND
0
0
0.2
0.4
0.6
0.8
f, FREQUENCY (Hz)
IO, OUTPUT LOAD CURRENT (mA)
Figure 6. Error Amp Open Loop Gain and
Phase versus Frequency
Figure 7. Error Amp Output Saturation
Voltage versus Load Current
http://onsemi.com
4
10
1.0
MC33362
VCC = 20 V
AV = −1.0
CL = 10 pF
TA = 25°C
3.00 V
0.5 V/DIV
20 mV/DIV
1.80 V
1.75 V
VCC = 20 V
AV = −1.0
CL = 10 pF
TA = 25°C
1.75 V
0.50 V
1.70 V
1.0 ms/DIV
1.0 ms/DIV
Figure 9. Error Amplifier Large Signal
Transient Response
8
0
Istart, STARTUP CURRENT (mA)
∆ V reg, REGULATOR VOLTAGE CHANGE (mV)
Figure 8. Error Amplifier Small Signal
Transient Response
VCC = 20 V
RT = 10 k
CPIN 8 = 1.0 mF
TA = 25°C
−20
−40
−60
0
4.0
8.0
12
16
6
5
4
3
2
1
0
20
0
2
4
6
8
10
12
Ireg, REGULATOR SOURCE CURRENT (mA)
VCC, POWER SUPPLY VOLTAGE (V)
Figure 10. Regulator Output Voltage
Change versus Source Current
Figure 11. Peak Startup Current
versus Power Supply Voltage
8
Istart, STARTUP CURRENT (mA)
−80
Vpin1 = 50 V
TA = 25°C
7
TA = 25°C
7
6
VCC = 0 V
5
4
3
VCC = 14 V
2
1
0
0
10
20
30
40
Vpin1, STARTUP PIN VOLTAGE (V)
Figure 12. Peak Startup Current versus
Startup Input Voltage
http://onsemi.com
5
50
14
16
COSS, DRAIN−SOURCE CAPACITANCE (pF)
10
ID = 200 mA
8.0
6.0
4.0
2.0
0
−50
Pulse tested at 5.0 ms with < 1.0% duty cycle
so that TJ is as close to TA as possible.
−25
0
25
50
75
100
125
150
100
50
0
0.5
150
COSS measured at 1.0 MHz with 50 mVpp.
5.0
Figure 14. Power Switch
Drain−Source Capacitance versus Voltage
100
2.4
1.6
RT = 10 k
Pin 1 = Open
Pin 4, 5, 10, 11,
12, 13 = GND
TA = 25°C
0.8
0
10
20
30
L = 12.7 mm of 2.0 oz.
copper. Refer to Figures
17 and 18.
Rθ JA , THERMAL RESISTANCE
JUNCTION−TO−AIR (° C/W)
CT = 2.0 nF
10
1.0
0.01
40
0.1
1.0
VCC, SUPPLY VOLTAGE (V)
2.4
ÎÎÎ
ÎÎ
ÎÎÎÎÎ
Printed circuit board heatsink example
70
2.0 oz
Copper
L
60
L
3.0 mm
Graphs represent symmetrical layout
50
2.0
1.6
1.2
0.8
RqJA
0.4
40
10
20
30
40
100
R θ JA, THERMAL RESISTANCE
JUNCTION−TO−AIR (° C/W)
2.8
PD(max) for TA = 50°C
80
100
Figure 16. DW and P Suffix Transient
Thermal Resistance
PD, MAXIMUM POWER DISSIPATION (W)
Rθ JA , THERMAL RESISTANCE
JUNCTION−TO−AIR (° C/W)
100
90
10
t, TIME (s)
Figure 15. Supply Current versus Supply Voltage
0
500
Figure 13. Power Switch Drain−Source
On−Resistance versus Temperature
3.2
30
50
VDS, DRAIN−SOURCE VOLTAGE (V)
CT = 390 pF
I CC, SUPPLY CURRENT (mA)
VCC = 20 V
TA = 25°C
TA, AMBIENT TEMPERATURE (°C)
4.0
0
200
0
50
ÎÎÎÎÎ
ÎÎ
ÎÎÎ
ÎÎÎÎÎ
Printed circuit board heatsink example
80
L
RqJA
60
2.0 oz
Copper
L
3.0 mm
Graphs represent symmetrical layout
40
4.0
3.0
2.0
PD(max) for TA = 70°C
20
0
5.0
0
L, LENGTH OF COPPER (mm)
10
20
1.0
30
40
50
0
P D , MAXIMUM POWER DISSIPATION (W)
R DS(on), DRAIN−SOURCE ON−RESISTANCE (Ω )
MC33362
L, LENGTH OF COPPER (mm)
Figure 17. DW Suffix (SOP−16L) Thermal Resistance and
Maximum Power Dissipation versus P.C.B. Copper Length
Figure 18. P Suffix (DIP−16) Thermal Resistance and
Maximum Power Dissipation versus P.C.B. Copper Length
http://onsemi.com
6
MC33362
PIN FUNCTION DESCRIPTION
ÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Pin
Function
Description
1
Startup Input
This pin connects directly to the rectified ac line voltage source. Internally Pin 1 is tied to the drain
of a high voltage startup MOSFET. During startup, the MOSFET supplies internal bias, and
charges an external capacitor that connects from the VCC pin to ground.
2
−
3
VCC
This is the positive supply voltage input. During startup, power is supplied to this input from Pin 1.
When VCC reaches the UVLO upper threshold, the startup MOSFET turns off and power is supplied from an auxiliary transformer winding.
4, 5, 12, 13
Ground
These pins are the control circuit grounds. They are part of the IC lead frame and provide a thermal path from the die to the printed circuit board.
6
RT
Resistor RT connects from this pin to ground. The value selected will program the Current Limit
Comparator threshold and affect the Oscillator frequency.
7
CT
Capacitor CT connects from this pin to ground. The value selected, in conjunction with resistor RT,
programs the Oscillator frequency.
8
Regulator Output
This 6.5 V output is available for biasing external circuitry. It requires an external bypass capacitor
of at least 1.0 mF for stability.
9
Compensation
This pin is the Error Amplifier output and is made available for loop compensation. It can be used
as an input to directly control the PWM Comparator.
10
Voltage Feedback
Input
This is the inverting input of the Error Amplifier. It has a 2.6 V threshold and normally connects
through a resistor divider to the converter output, or to a voltage that represents the converter
output.
11
Overvoltage
Protection Input
This input provides runaway output voltage protection due to an external component or connection failure in the control loop feedback signal path. It has a 2.6 V threshold and normally connects through a resistor divider to the converter output, or to a voltage that represents the converter output.
14, 15
−
These pins have been omitted for increased spacing between the high voltages present on the
Power Switch Drain, and the ground potential on Pins 12 and 13.
16
Power Switch Drain
This pin has been omitted for increased spacing between the rectified AC line voltage on Pin 1
and the VCC potential on Pin 3.
This pin is designed to directly drive the converter transformer and is capable of switching a maximum of 500 V and 2.0 A.
http://onsemi.com
7
MC33362
AC Input
Startup Input
Startup
Control
Current
Mirror
Regulator Output
6.5 V
8
Band Gap
Regulator
I
VCC
2.25 I
CT
Overvoltage
Protection
Input
14.5 V/
9.5 V
4I
11
OVP
2.6 V
Oscillator
7
DC
Output
3
UVLO
6
RT
1
16
PWM Latch
Power Switch
Drain
Driver
S
Q
R
PWM
Comparator
Leading Edge
Blanking
9.0
Thermal
Shutdown
Current Limit
Comparator
Compensation
450
270 µA
Gnd
9
Error
Amplifier
2.6 V
10
Voltage
Feedback Input
4, 5, 12, 13
Figure 19. Representative Block Diagram
2.6 V
Capacitor CT
0.6 V
Compensation
Oscillator Output
PWM
Comparator
Output
PWM Latch
Q Output
Current Limit
Propagation
Delay
Power Switch
Gate Drive
Current
Limit
Threshold
Leading Edge
Blanking Input
(Power Switch
Drain Current)
Normal PWM Operating Range
Figure 20. Timing Diagram
http://onsemi.com
8
Output Overload
MC33362
OPERATING DESCRIPTION
Introduction
The formula for the charge/discharge current along with
the oscillator frequency are given below. The frequency
formula is a first order approximation and is accurate for CT
values greater than 500 pF. For smaller values of CT, refer to
Figure 2. Note that resistor RT also programs the Current
Limit Comparator threshold.
The MC33362 represents a new higher level of integration
by providing all the active high voltage power, control, and
protection circuitry required for implementation of a
flyback or forward converter on a single monolithic chip.
This device is designed for direct operation from a rectified
120 VAC line source and requires a minimum number of
external components to implement a complete converter. A
description of each of the functional blocks is given below,
and the representative block and timing diagrams are shown
in Figures 19 and 20.
I
Current Limit Comparator and Power Switch
The MC33362 uses cycle−by−cycle current limiting as a
means of protecting the output switch transistor from
overstress. Each on−cycle is treated as a separate situation.
Current limiting is implemented by monitoring the output
switch current buildup during conduction, and upon sensing
an overcurrent condition, immediately turning off the switch
for the duration of the oscillator ramp−up period.
The Power Switch is constructed as a SENSEFET
allowing a virtually lossless method of monitoring the drain
current. It consists of a total of 3770 cells, of which 50 are
connected to a 9.0 W ground−referenced sense resistor. The
Current Sense Comparator detects if the voltage across the
sense resistor exceeds the reference level that is present at
the inverting input. If exceeded, the comparator quickly
resets the PWM Latch, thus protecting the Power Switch.
The current limit reference level is generated by the 2.25 I
output of the Current Mirror. This current causes a reference
voltage to appear across the 450 W resistor. This voltage
level, as well as the Oscillator charge/discharge current are
both set by resistor RT. Therefore when selecting the values
for RT and CT, RT must be chosen first to set the Power Switch
peak drain current, while CT is chosen second to set the
desired Oscillator frequency. A graph of the Power Switch
peak drain current versus RT is shown in Figure 3 with the
related formula below.
Current
Mirror
8
2.25 I
I
RC
Current
Limit
Reference
6
RT
4I
RD
CT
7
Oscillator
chgńdscg
4C
T
The pulse width modulator consists of a comparator with
the oscillator ramp voltage applied to the non−inverting
input, while the error amplifier output is applied into the
inverting input. The Oscillator applies a set pulse to the
PWM Latch while CT is discharging, and upon reaching the
valley voltage, Power Switch conduction is initiated. When
CT charges to a voltage that exceeds the error amplifier
output, the PWM Latch is reset, thus terminating Power
Switch conduction for the duration of the oscillator ramp−up
period. This PWM Comparator/Latch combination
prevents multiple output pulses during a given oscillator
clock cycle. The timing diagram shown in Figure 20
illustrates the Power Switch duty cycle behavior versus the
Compensation voltage.
The oscillator frequency is controlled by the values
selected for the timing components RT and CT. Resistor RT
programs the oscillator charge/discharge current via the
Current Mirror 4 I output, Figure 4. Capacitor CT is charged
and discharged by an equal magnitude internal current
source and sink. This generates a symmetrical 50 percent
duty cycle waveform at Pin 7, with a peak and valley
threshold of 2.6 V and 0.6 V respectively. During the
discharge of CT, the oscillator generates an internal blanking
pulse that holds the inverting input of the AND gate Driver
high. This causes the Power Switch gate drive to be held in
a low state, thus producing a well controlled amount of
output deadtime. The amount of deadtime is relatively
constant with respect to the oscillator frequency when
operating below 1.0 MHz. The maximum Power Switch
duty cycle at Pin 16 can be modified from the internal 50%
limit by providing an additional charge or discharge current
path to CT, Figure 21. In order to increase the maximum duty
cycle, a discharge current resistor RD is connected from
Pin 7 to ground. To decrease the maximum duty cycle, a
charge current resistor RC is connected from Pin 7 to the
Regulator Output. Figure 5 shows an obtainable range of
maximum output duty cycle versus the ratio of either RC or
RD with respect to RT.
1.0
f [
PWM Comparator and Latch
Oscillator and Current Mirror
Regulator Output
I
5.4
+ R
chgńdscg
T
Blanking
Pulse
PWM
Comparator
I
Figure 21. Maximum Duty Cycle Modification
http://onsemi.com
9
pk
+ 12.3
ǒ Ǔ
R
T − 1.115
1000
MC33362
The Power Switch is designed to directly drive the converter
transformer and is capable of switching a maximum of
500 V and 2.0 A. Proper device voltage snubbing and
heatsinking are required for reliable operation.
A Leading Edge Blanking circuit was placed in the
current sensing signal path. This circuit prevents a
premature reset of the PWM Latch. The premature reset is
generated each time the Power Switch is driven into
conduction. It appears as a narrow voltage spike across the
current sense resistor, and is due to the MOSFET gate to
source capacitance, transformer interwinding capacitance,
and output rectifier recovery time. The Leading Edge
Blanking circuit has a dynamic behavior in that it masks the
current signal until the Power Switch turn−on transition is
completed. The current limit propagation delay time is
typically 233 ns. This time is measured from when an
overcurrent appears at the Power Switch drain, to the
beginning of turn−off.
Power Switch. To prevent erratic switching as the threshold
is crossed, 5.0 V of hysteresis is provided.
Startup Control
An internal Startup Control circuit with a high voltage
enhancement mode MOSFET is included within the
MC33362. This circuitry allows for increased converter
efficiency by eliminating the external startup resistor, and its
associated power dissipation, commonly used in most
off−line converters that utilize a UC3842 type of controller.
Rectified ac line voltage is applied to the Startup Input,
Pin 1. This causes the MOSFET to enhance and supply
internal bias as well as charge current to the VCC bypass
capacitor that connects from Pin 3 to ground. When VCC
reaches the UVLO upper threshold of 14.5 V, the IC
commences operation and the startup MOSFET is turned
off. Operating bias is now derived from the auxiliary
transformer winding, and all of the device power is
efficiently converted down from the rectified ac line.
Error Amplifier
Regulator
An fully compensated Error Amplifier with access to the
inverting input and output is provided for primary side
voltage sensing, Figure 19. It features a typical dc voltage
gain of 82 dB, and a unity gain bandwidth of 1.0 MHz with
78 degrees of phase margin, Figure 6. The noninverting
input is internally biased at 2.6 V ±3.1% and is not pinned
out. The Error Amplifier output is pinned out for external
loop compensation and as a means for directly driving the
PWM Comparator. The output was designed with a limited
sink current capability of 270 mA, allowing it to be easily
overridden with a pull−up resistor. This is desirable in
applications that require secondary side voltage sensing,
Figure 22. In this application, the Voltage Feedback Input is
connected to the Regulator Output. This disables the Error
Amplifier by placing its output into the sink state, allowing
the optocoupler transistor to directly control the PWM
Comparator.
A low current 6.5 V regulated output is available for
biasing the Error Amplifier and any additional control
system circuitry. It is capable of up to 10 mA and has
short−circuit protection. This output requires an external
bypass capacitor of at least 1.0 mF for stability.
Thermal Shutdown and Package
Internal thermal circuitry is provided to protect the Power
Switch in the event that the maximum junction temperature
is exceeded. When activated, typically at 155°C, the Latch
is forced into a ‘reset’ state, disabling the Power Switch. The
Latch is allowed to ‘set’ when the Power Switch temperature
falls below 145°C. This feature is provided to prevent
catastrophic failures from accidental device overheating. It
is not intended to be used as a substitute for proper
heatsinking.
The MC33362 is contained in a heatsinkable plastic
dual−in−line package in which the die is mounted on a special
heat tab copper alloy lead frame. This tab consists of the four
center ground pins that are specifically designed to improve
thermal conduction from the die to the circuit board. Figures
17 and 18 show a simple and effective method of utilizing the
printed circuit board medium as a heat dissipater by soldering
these pins to an adequate area of copper foil. This permits the
use of standard layout and mounting practices while having
the ability to halve the junction to air thermal resistance. The
examples are for a symmetrical layout on a single−sided
board with two ounce per square foot of copper. Figure 23
shows a practical example of a printed circuit board layout
that utilizes the copper foil as a heat dissipater. Note that a
jumper was added to the layout from Pins 8 to 10 in order to
enhance the copper area near the device for improved thermal
conductivity. The application circuit requires two ounce
copper foil in order to obtain 20 watts of continuous output
power at room temperature.
Overvoltage Protection
An Overvoltage Protection Comparator is included to
eliminate the possibility of runaway output voltage. This
condition can occur if the control loop feedback signal path
is broken due to an external component or connection
failure. The comparator is normally used to monitor the
primary side VCC voltage. When the 2.6 V threshold is
exceeded, it will immediately turn off the Power Switch, and
protect the load from a severe overvoltage condition. This
input can also be driven from external circuitry to inhibit
converter operation.
Undervoltage Lockout
An Undervoltage Lockout comparator has been
incorporated to guarantee that the integrated circuit has
sufficient voltage to be fully functional before the output
stage is enabled. The UVLO comparator monitors the VCC
voltage at Pin 3 and when it exceeds 14.5 V, the reset signal
is removed from the PWM Latch allowing operation of the
http://onsemi.com
10
MC33362
F1
1.0 A D4
C1
47
D3
1N4004
92 to 138
Vac Input
D2
C5
4.0 nF
D1
D6
R5 MUR
39 120
Startup
Mirror
3
Reg
8
UVLO
14.5 V/
9.5 V
6
R1
8.2 k
C3
1.5 nF
7
11
D7
T1 MBR
2515L
C2
10
R4
16 k
C8
330
1
2
L1
5.0 µH
Driver
Q
C7
100 nF
R
PWM
ILimit
4
Thermal
9
R2
2.7 k
2.6 V
270 µA
10
EA
IC1 MC33362
4, 5, 12, 13
Figure 22. 20 W Off−Line Converter
Table 1. Converter Test Data
Test
Conditions
Results
Line Regulation
Vin = 92 Vac to 138 Vac, IO 4.0 A
D = 1.0 mV
Load Regulation
Vin = 115 Vac, IO = 1.0 A to 4.0 A
D = 9.0 mV
Output Ripple
Vin = 115 Vac, IO = 4.0 A
Triangular = 10 mVpp
Spike = 60 mVpp
Efficiency
Vin = 115 Vac, IO = 4.0 A
78.4%
This data was taken with the components listed below mounted on the printed circuit board shown in
Figure 23.
For high efficiency and small circuit board size, the Sanyo Os−Con capacitors are recommended for C8,
C9, C10 and C11.
C8, C9, C10 = Sanyo Os−Con #6SA330M, 330 mF 6.3 V.
C11 = Sanyo Os−Con #10SA220M, 220 mF 10 V.
D7 = MBR2515L mounted on Aavid #592502B03400 heatsink.
L1 = Coilcraft S5088−A, 5.0 mH, 0.11 W.
T1 = Coilcraft S5069−A
Primary: 58 turns of # 26 AWG, Pin 1 = start, Pin 8 = finish.
Two layers 0.002″ Mylar tape.
Secondary: 4 turns of # 18 AWG, 2 strands bifiliar wound, Pin 5 = start, Pin 4 = finish.
Two layers 0.002″ Mylar tape.
Auxiliary: 10 turns of # 26 AWG wound in center of bobbin, Pin 2 = start, Pin 7 = finish.
Two layers 0.002″ Mylar tape.
Gap: 0.014″ total for a primary inductance (LP) of 330 mH.
Core and Bobbin: Coilcraft PT1950, E187, 3F3 material.
http://onsemi.com
11
1
R10
2.74 k
5
LEB
5.05 V/4.0 A
DC Output
R8
220
R9
2.80 k
IC2
3
MOC
8103 IC3
TL431B 2
16
S
C9 C10
330 330
R3
2.7 k
OVP
2.6 V
PWM Latch
Osc
R7
2.2 k
1.0 W
D5
MUR
160
1
C4
1.0
C6
47 pF
R6
100 k
1.0 W
C11
220
C12
1.0
MC33362
Caution!
High
Voltages
DC Output
C4
R3
R3
R2
R9
J1
R1
D1
IC2
D2
R10
IC3
C3
C7
C12
C11
IC1
F1
AC
Line
Input
R8
R4
C2
L1
R5
D6
C10
D3
D4
D5
C9
R7
T1
C1
R6
D7
C5
C8
C6
1
(Top View)
2.75"
2.25"
MC33362
(Bottom View)
Figure 23. Printed Circuit Board and Component Layout (Circuit of Figure 22)
http://onsemi.com
12
MC33362
PACKAGE DIMENSIONS
PDIP−16
P SUFFIX
CASE 648E−01
ISSUE O
−A−
R
16
9
M
−B−
1
L
8
P
J
F
C
G
DIM
A
B
C
D
F
G
H
J
K
L
M
P
R
S
−T−
SEATING
PLANE
S
K
H
D 13 PL
0.25 (0.010)
M
T B
A
S
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION A AND B DOES NOT INCLUDE MOLD
PROTRUSION.
5. MOLD FLASH OR PROTRUSIONS SHALL NOT
EXCEED 0.25 (0.010).
6. ROUNDED CORNER OPTIONAL.
S
INCHES
MIN
MAX
0.740
0.760
0.245
0.260
0.145
0.175
0.015
0.021
0.050
0.070
0.100 BSC
0.050 BSC
0.008
0.015
0.120
0.140
0.295
0.305
0_
10 _
0.200 BSC
0.300 BSC
0.015
0.035
MILLIMETERS
MIN
MAX
18.80
19.30
6.23
6.60
3.69
4.44
0.39
0.53
1.27
1.77
2.54 BSC
1.27 BSC
0.21
0.38
3.05
3.55
7.50
7.74
0_
10 _
5.08 BSC
7.62 BSC
0.39
0.88
SO−16W
DW SUFFIX
CASE 751N−01
ISSUE O
−A−
T
16
9
−B−
1
P
0.010 (0.25)
M
B
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER
SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN
EXCESS OF D DIMENSION AT MAXIMUM
MATERIAL CONDITION.
M
8
13X
J
D
0.010 (0.25)
M
T A
S
B
S
F
R X 45 _
C
−T−
S
K
9X
SEATING
PLANE
M
G
http://onsemi.com
13
DIM
A
B
C
D
F
G
J
K
M
P
R
S
T
MILLIMETERS
MIN
MAX
10.15
10.45
7.40
7.60
2.35
2.65
0.35
0.49
0.50
0.90
1.27 BSC
0.25
0.32
0.10
0.25
0_
7_
10.05
10.55
0.25
0.75
2.54 BSC
3.81 BSC
INCHES
MIN
MAX
0.400
0.411
0.292
0.299
0.093
0.104
0.014
0.019
0.020
0.035
0.050 BSC
0.010
0.012
0.004
0.009
0_
7_
0.395
0.415
0.010
0.029
0.100 BSC
0.150 BSC
MC33362
The product described herein (MC33362), may be covered by one or more of the following U.S. patents: 4,553,084; 5,418,410; 5,477,175. There may be
other patents pending.
SENSEFET is a trademark of Semiconductor Components Industries, LLC (SCILLC)
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
N. American Technical Support: 800−282−9855 Toll Free
Literature Distribution Center for ON Semiconductor
USA/Canada
P.O. Box 61312, Phoenix, Arizona 85082−1312 USA
Phone: 480−829−7710 or 800−344−3860 Toll Free USA/Canada Japan: ON Semiconductor, Japan Customer Focus Center
2−9−1 Kamimeguro, Meguro−ku, Tokyo, Japan 153−0051
Fax: 480−829−7709 or 800−344−3867 Toll Free USA/Canada
Phone: 81−3−5773−3850
Email: [email protected]
http://onsemi.com
14
ON Semiconductor Website: http://onsemi.com
Order Literature: http://www.onsemi.com/litorder
For additional information, please contact your
local Sales Representative.
MC33362/D
Similar pages