Infineon ISO1H815G Galvanic isolated 8 channel high-side switch Datasheet

ISOFACE™
ISO1H815G
Galvanic Isolated 8 Channel High-Side Switch
Datasheet
Revision 2.4, 2014-10-20
Power Management & Multimarket
Edition 2014-10-20
Published by
Infineon Technologies AG
81726 Munich, Germany
© 2014 Infineon Technologies AG
All Rights Reserved.
Legal Disclaimer
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and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights
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Information
For further information on technology, delivery terms and conditions and prices, please contact the nearest
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ISOFACE™
ISO1H815G
Revision History
Page or Item
Subjects (major changes since previous revision)
Revision 2.4, 2014-10-20
Page 4
Typo in Headline corrected
Feature list updated, Vbb Monitoring included
Page 7
Page 7 Chapter 2 Block diagram updated
Page 9
Page 9 Chapter 3.3.3 Description for repetitive short circuit corrected
Page 9
Page 9 Chapter 3.4 Vbb Monitoring included in common diagnostic output description
Page 14
Page 14 Chapter 4.4 VISO changed to correct value ΔVISO = 500V
Page 15
Page 15 Chapter 4.5 Footnotes corrected
Page 16
Page 16 table 4.8 Timing parameter for CS delay split into tCSD and tCSDMD
Page 16
Page 16 table 4.8 Parameter tOR removed and replaced by tIOJ
Page 17
Page 17 table 4.10 Parameter Minimum Internal Gap removed
all
Correction of formats and typos
Revision 2.0
all
Final Datasheet
Trademarks of Infineon Technologies AG
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EconoPIM™, EconoPACK™, EiceDRIVER™, eupec™, FCOS™, HITFET™, HybridPACK™, I²RF™,
ISOFACE™, IsoPACK™, MIPAQ™, ModSTACK™, my-d™, NovalithIC™, OptiMOS™, ORIGA™,
POWERCODE™; PRIMARION™, PrimePACK™, PrimeSTACK™, PRO-SIL™, PROFET™, RASIC™,
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Other Trademarks
Advance Design System™ (ADS) of Agilent Technologies, AMBA™, ARM™, MULTI-ICE™, KEIL™,
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development partnership. Bluetooth™ of Bluetooth SIG Inc. CAT-iq™ of DECT Forum. COLOSSUS™,
FirstGPS™ of Trimble Navigation Ltd. EMV™ of EMVCo, LLC (Visa Holdings Inc.). EPCOS™ of Epcos AG.
FLEXGO™ of Microsoft Corporation. FlexRay™ is licensed by FlexRay Consortium. HYPERTERMINAL™ of
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Association Corporation. ISO™ of INTERNATIONAL ORGANIZATION FOR STANDARDIZATION. MATLAB™ of
MathWorks, Inc. MAXIM™ of Maxim Integrated Products, Inc. MICROTEC™, NUCLEUS™ of Mentor Graphics
Corporation. MIPI™ of MIPI Alliance, Inc. MIPS™ of MIPS Technologies, Inc., USA. muRata™ of MURATA
MANUFACTURING CO., MICROWAVE OFFICE™ (MWO) of Applied Wave Research Inc., OmniVision™ of
OmniVision Technologies, Inc. Openwave™ Openwave Systems Inc. RED HAT™ Red Hat, Inc. RFMD™ RF
Micro Devices, Inc. SIRIUS™ of Sirius Satellite Radio Inc. SOLARIS™ of Sun Microsystems, Inc. SPANSION™
of Spansion LLC Ltd. Symbian™ of Symbian Software Limited. TAIYO YUDEN™ of Taiyo Yuden Co.
TEAKLITE™ of CEVA, Inc. TEKTRONIX™ of Tektronix Inc. TOKO™ of TOKO KABUSHIKI KAISHA TA. UNIX™
of X/Open Company Limited. VERILOG™, PALLADIUM™ of Cadence Design Systems, Inc. VLYNQ™ of Texas
Instruments Incorporated. VXWORKS™, WIND RIVER™ of WIND RIVER SYSTEMS, INC. ZETEX™ of Diodes
Zetex Limited.
Last Trademarks Update 2011-11-11
Datasheet
3
Revision 2.4, 2014-10-20
ISOFACE™
ISO1H815G
Coreless Transformer Isolated Digital
Output 8 Channel 1.2 A High-Side Switch
Product Highlights
•
•
•
•
Coreless transformer isolated data interface
Galvanic isolation
8 High-side output switches 1.2A
µC compatible 8-bit parallel peripheral
Features
Typical Application
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Interface 3.3/5V CMOS operation compatible
Parallel interface
Direct control mode
High common mode transient immunity
Short circuit protection
Maximum current internally limited
Overload protection
Overvoltage protection (including load dump)
Undervoltage shutdown with autorestart and
hysteresis
Switching inductive loads
Common output disable pin
Thermal shutdown with restart
Thermal independence of separate channels
Common diagnostic output
ESD protection
Loss of GNDbb and loss of Vbb protection
Reverse Output Voltage protection
Isolated return path for DIAG signal
Vbb monitoring
RoHS compliant
Isolated switch for industrial applications (PLC)
All types of resistive, inductive and capacitive loads
µC compatible power switch for 24V DC
applications
Driver for solenoid, relays and resistive loads
•
Description
The ISO1H815G is a galvanically isolated 8 bit data
interface in PG-DSO-36 package that provides 8 fully
protected high-side power switches that are able to
handle currents up to 1.2A.
An 8 bit parallel µC compatible interface allows to
connect the IC directly to a µC system. The input
interface supports also a direct control mode and is
designed to operate with 3.3/5V CMOS compatible
levels.
The data transfer from input to output side is realized by
the integrated Coreless Transformer Technology.
Typical Application
VCC
VCC
VCCP1.x
DIS
AD0
CS
WR
WR
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
µC (i.e
C166)
D0
D1
D2
D3
D4
D5
D6
D7
Vbb
Vbb
CT
Control
Unit
DIAG
OUT0
Control
&
Protectio
n Unit
OUT1
Parallel
Interface
DIAG
OUT7
GND
ISO1H815G
GNDCC
GNDbb
Type
On-state Resistance
Package
ISO1H815G
200mΩ
PG-DSO36
Datasheet
4
Revision 2.4, 2014-10-20
ISOFACE™
ISO1H815G
Pin Configuration and Functionality
1
Pin Configuration and Functionality
1.1
Pin Configuration
Vbb
Pin
Symbol
1
N.C.
Not connected
2
VCC
Positive 3.3/5V logic supply
3
DIS
Output disable
4
Chip select
5
CS
WR
6
D0
Data input bit0
7
D1
Data input bit1
8
D2
Data input bit2
9
D3
Data input bit3
10
D4
Data input bit4
11
D5
Data input bit5
12
D6
Data input bit6
13
D7
Data input bit7
14
15
DIAG
GNDCC
16
N.C.
Not connected
17
N.C.
Not connected
18
N.C.
Not connected
Figure 1
19
GNDbb
Output driver ground
.
20
N.C
21
OUT7
High-side output of channel 7
22
OUT7
High-side output of channel 7
23
OUT6
High-side output of channel 6
24
OUT6
High-side output of channel 6
25
OUT5
High-side output of channel 5
26
OUT5
High-side output of channel 5
27
OUT4
High-side output of channel 4
28
OUT4
High-side output of channel 4
29
OUT3
High-side output of channel 3
30
OUT3
High-side output of channel 3
31
OUT2
High-side output of channel 2
32
OUT2
High-side output of channel 2
33
OUT1
High-side output of channel 1
34
OUT1
High-side output of channel 1
35
OUT0
High-side output of channel 0
36
OUT0
High-side output of channel 0
TAB
Vbb
Datasheet
Function
Parallel write
Common diagnostic output
Input logic ground
N.C.
VCC
1
2
DIS
CS
36
35
OUT0
OUT0
3
4
34
33
OUT1
OUT1
WR
D0
5
6
32
31
OUT2
OUT2
D1
D2
7
8
30
29
OUT3
OUT3
D3
D4
9
10
28
27
OUT4
OUT4
D5
D6
11
12
26
25
OUT5
OUT5
D7
DIAG
13
14
24
23
OUT6
OUT6
GNDCC
N.C.
15
16
22
21
OUT7
OUT7
N.C.
N.C.
17
18
20
19
N.C.
GNDbb
TAB
TAB
Vbb
Power SO-36 (430mil)
Not connected
Positive driver power supply voltage
5
Revision 2.4, 2014-10-20
ISOFACE™
ISO1H815G
Pin Configuration and Functionality
1.2
Pin Functionality
OUT0 ... OUT7 (High side output channel 0 ... 7)
The output high side channels are internally connected
to Vbb and controlled by the corresponding data input
pins D0 ... D7 in parallel mode.
VCC (Positive 3.3/5V logic supply)
The VCC supplies the input interface that is
galvanically isolated from the output driver stage. The
input interface can be supplied with 3.3/5V.
TAB (Vbb, Positive supply for output driver)
The heatslug is connected to the positive supply port of
the output interface.
DIS (Output disable)
The high-side outputs OUT0...OUT7 can be
immediately switched off by means of the low active pin
DIS that is an asynchronous signal. The input registers
are also reset by the DIS signal. The Output remains
switched off after low-high transition of DIS signal, till
new information is written into the input register.
Current Sink to GNDCC.
CS (Chip select)
The system microcontroller selects the ISO1H815G by
means of the low active pin CS to activate the parallel
interface. By connecting the CS pin and WR pin to
ground the parallel direct control is activated. Current
Source to VCC.
WR (Parallel write)
In parallel mode data at the input pins (D0 ... D7) are
latched by means of the rising edge of the low active
signal WR (write). Current Source to VCC.
D0 ... D7 (Data input bit0 ... bit7)
The present data can be latched on the rising edge of
the write signal WR. D0 ... D7 control the corresponding
output channels OUT0 ...OUT7. By connecting CS and
WR to ground, the signals at D0 ... D7 directly control
the outputs. Current Sink to GNDCC.
DIAG (Common diagnostic output)
The low active DIAG signal contains the OR-wired
information of the separated overtemperature detection
units for each channel.The output pin DIAG provides an
open drain functionality. A current source is also
connected to the pin DIAG. In normal operation the
signal DIAG is high. When overtemperature or Vbb
below ON-Limit is detected the signal DIAG changes to
low.
GNDCC (Ground for VCC domain)
This pin acts as the ground reference for the input
interface that is supplied by VCC.
GNDbb (Output driver ground domain)
This pin acts as the ground reference for the output
driver that is supplied by Vbb.
Datasheet
6
Revision 2.4, 2014-10-20
Datasheet
7
DIAG
D0
D1
D2
D3
D4
D5
D6
D7
WR
ISO1H815G
< D0 - D7 >
Parallel
Input Interface
Direct
Mode
Control
VCC
100µA
High-side Channel 7
Logic
Undervoltage
Charge Pump
Level shifter
Rectifier
Undervoltage
Shutdown with
Restart
Charge Pump
Level Shifter
Rectifier
Common
Diagnostic
Output
High-side Channel 0
Logic
to Logic
Channel 1 - 6
to Logic
Channel 1 - 6
Serial
to
Parallel
Overvoltage
Protection
Temperature Sensor
Overload Protection
Current Limitation
Limitation of Unclamped
Inductive Load
Vbb
Channel 1 ... 6
Gate
Protection
from
Temperature
Sensor
Channel 1 - 6
Temperature Sensor
Overload Protection
Current Limitation
Limitation of Unclamped
Inductive Load
Gate
Protection
Voltage
Source
OUT7
OUT6
OUT5
OUT4
OUT3
OUT2
OUT1
OUT0
GNDbb
Blockdiagram
CS
Parallel
to
Serial
CT
Figure 2
DIS
Logic
Blockdiagram
GNDCC
Undervoltage
Shutdown with
Restart
Vbb
2
Galvanic Isolation
VCC
ISOFACE™
ISO1H815G
Blockdiagram
Revision 2.4, 2014-10-20
ISOFACE™
ISO1H815G
Functional Description
3
Functional Description
3.1
Introduction
3.3.2
The ISOFACE ISO1H815G includes 8 high-side power
switches that are controlled by means of the integrated
parallel interface. The interface is 8bit µC compatible.
Furthermore a direct control mode can be selected that
allows the direct control of the outputs OUT0...OUT7 by
means of the inputs D0...D7 without any additional logic
signal. The IC can replace 8 optocouplers and the 8
high-side switches in conventional I/O-Applications as
a galvanic isolation is implemented by means of the
integrated coreless transformer technology. The µC
compatible interface allows a direct connection to the
ports of a microcontroller without the need for other
components. Each of the 8 high-side power switches is
protected
against
short to
Vbb,
overload,
overtemperature and against overvoltage by an active
zener clamp.
Each of the eight output stages has it own zener clamp
that causes a voltage limitation at the power transistor
when solenoid loads are switched off. VON is then
clamped to 47V (min.).
Vbb
Vbb
Vz
VON
OUTx
GNDbb
The diagnostic logic on the power chip recognizes the
overtemperature information of each power transistor
The information is send via the internal coreless
transformer to the pin DIAG at the input interface.
3.2
Power Transistor Overvoltage
Protection
Figure 3
Inductive and overvoltage output
clamp (each channel)
Energy is stored in the load inductance during an
inductive load switch-off.
Power Supply
EL = 1 ⁄ 2 × L × IL
2
The IC contains 2 galvanic isolated voltage domains
that are independent from each other. The input
interface is supplied at VCC and the output stage is
supplied at Vbb. The different voltage domains can be
switched on at different time. The output stage is only
enabled once the input stage enters a stable state.
Ebb
EAS
ELoad
Vbb
Dx
OUTx
L
3.3
Vbb
Output Stage
GNDbb
ZL
Each channel contains a high-side vertical power FET
that is protected by embedded protection functions.
RL
The continuous current for each channel is 1.2A (all
channels ON).
3.3.1
Figure 4
Output Stage Control
ER
Inductive load switch-off energy
dissipation (each channel)
While demagnetizing the load inductance, the energy
dissipation in the DMOS is
Each output is independently controlled by an output
latch and a common reset line via the pin DIS that
disables all eight outputs and resets the latches. The
parallel input data is transferred to the input latches
with a high-to-low transition of the signal WR (write)
while the CS is logic low. A low-to-high transition of CS
transfers then the data of the input latches to the output
buffer.
Datasheet
EL
E AS = E bb + E L – E R = V ON ( CL ) × i L ( t )dt
with an approximate solution for RL > 0Ω:
IL × L
IL × RL ⎞
E AS = ---------------- × ( V bb + V ON ( CL ) ) × ln ⎛ 1 + -----------------------⎝
2 × RL
V ON ( CL ) ⎠
8
Revision 2.4, 2014-10-20
ISOFACE™
ISO1H815G
Functional Description
3.3.3
Power Transistor Overcurrent
Protection
IN
The outputs are provided with a current limitation that
enters a repetitive switched mode after an initial peak
current has been exceeded. The initial peak short
circuit current limit is set to IL(SCp). During the repetitive
short circuit the current limit is set to IL(SCr). If this
operation leads to an overtemperature condition, a
second protection level (Tj > 135°C) will change the
output into a low duty cycle PWM (selective thermal
shutdown with restart) to prevent critical chip
temperatures.
t
VOUT
Normal
operation
IL
Output short to GND
IL(SCp)
t
IL(SCr)
t
DIAG
IN
t
t
VOUT
Short circuit in on-state, shut down
down by overtemperature, restart by
cooling
3.4
Common Diagnostic Output
t
TJ
The overtemperature detection information are ORwired in the common diagnostic output block. The
information is send via the integrated coreless
transformer to the input interface. In addition Vbb
undervoltage is indicated at the DIAG output.
t
DIAG
t
Figure 5
Figure 7
The output stage at pin DIAG has an open drain
functionality combined with a current source.
Overtemperature detection
The following figures show the timing for a turn on into
short circuit and a short circuit in on-state. Heating up
of the chip may require several milliseconds,
depending on external conditions.
VCC
100µA
DIAG
IN
t
VOUT
Figure 8
Output short to GND
IL
DIAG
CT
Common
Diagnostic
Output
IL(SCp)
Common diagnostic output
t
IL(SCr)
t
t
Figure 6
Datasheet
Turn on into short circuit, shut down by
overtemperature, restart by cooling
9
Revision 2.4, 2014-10-20
ISOFACE™
ISO1H815G
Functional Description
3.5
Parallel Interface
3.5.2
uC Control Mode
The ISO1H815G contains a parallel interface that can
be directly controlled by the microcontroller output
ports. The parallel interface can also be switched over
to a direct control that allows direct changes of the
outputs OUT0 ... OUT7 by means of the corresponding
inputs D0 ... D7 without additional logic signals. To
activate the parallel direct control mode pin CS and pin
WR have to be connected both to ground.
3.5.1
D0
P1
P2
D1
D2
P3
P4
D3
D4
P5
P6
D5
D6
P7
D7
Output lines
IC1
µC (i.e C166)
Number of adressed ICs = n
Number of necessary control and data ports = 9 n
Parallel input data can be written in from then on
Individual ICs are adressed by the chip select
The data in the input latches is transferred to the
output buffer
Figure 9
Parallel bus configuration
3.5.3
Direct Control Mode
Beside the use of the parallel µC compatible interface a
parallel direct control mode can be chosen. In this
mode the output OUT0...OUT7 can be directly
controlled via the inputs D0...D7 without the need for
additional logic signals. To activate this mode pin CS
and WR need to be connected to ground.
WR - Write. The system controller enables the write
procedure in the ISO1H815G by means of the signal
WR. A logic low state signal at pin WR writes the input
data into the input latches when the CS pin is in a logic
low state.
.
WR Logic low level:
VCC
VCC
Parallel input data at the pins D0 - D7 is written into
the input latches
VCC
CS
WR
P0
P1
P2
P3
P4
P5
P6
P7
WR Logic high level:
•
P0
Parallel
Interface
CS Low to high transition:
•
WR
DIAG
CS High to low transition:
•
CS
WR
Parallel Interface Signal
Description
CS - Chip select. The system microcontroller selects
the ISO1H815G by means of the CS pin. Whenever the
pin is in a logic low state, data can be transferred from
the µC.
•
AD0
The parallel input data is latched in the input
latches. Any changes at the pins D0 - D7 after the
low-to-high transition of WR do not affect the input
latches.
D0 ... D7 - Parallel input. Parallel data bits are fed into
the pins D0 ... D7. The data is written into the input
latches when WR is logic low.
Controller
D0
D1
D2
D3
D4
D5
D6
D7
DIAG
Parallel
Interface
Output lines
IC1
Figure 10
Datasheet
10
Parallel Direct Control
Revision 2.4, 2014-10-20
ISOFACE™
ISO1H815G
Functional Description
3.6
Parallel Interface Timing
CS
WR
tCSWR
t WHCS
t CSD
tWRPW
tDS
t DH
D0 - D7
DATA
ton/off
OUTPUT
OUT0 - OUT7
Figure 11
Parallel input - output timing diagram
3.7
Transmission Failure Detection
There is a failure detection unit integrated to ensure also a stable functionality during the integrated coreless
transformer transmission. This unit decides whether the transmitted data is valid or not. If four times serial data
coming in from the internal registers is not accepted, the output stages are switched off until the next valid data is
received.
Datasheet
11
Revision 2.4, 2014-10-20
ISOFACE™
ISO1H815G
Electrical Characteristics
4
Electrical Characteristics
Note: All voltages at pins 2 to 14 are measured with respect to ground GNDCC (pin 15). All voltages at pin 20 to
pin 36 and TAB are measured with respect to ground GNDbb (pin 19). The voltage levels are valid if other
ratings are not violated. The two voltage domains VCC and Vbb are internally galvanically isolated.
4.1
Absolute Maximum Ratings
Note: Absolute maximum ratings are defined as ratings, which when being exceeded may lead to destruction of
the integrated circuit. For the same reason make sure, that any capacitor that will be connected to pin 2
(VCC) and TAB (Vbb) is discharged before assembling the application circuit. Supply voltages higher than
Vbb(AZ) require an external current limit for the GNDbb pin, e.g. with a 15Ω resistor in GNDbb connection.
Operating at absolute maximum ratings can lead to a reduced lifetime.
Parameter
at Tj = -40 ... 135°C, unless otherwise specified
Symbol
Supply voltage input interface (VCC)
VCC
Limit Values
Unit
min.
max.
-0.5
6.5
1)
45
Supply voltage output interface (Vbb)
Vbb
-1
Continuos voltage at data inputs (D0 ... D7)
VDx
-0.5
6.5
Continuos voltage at pin CS
VCS
-0.5
6.5
Continuos voltage at pin WR
VWR
-0.5
6.5
Continuos voltage at pin DIS
VDIS
-0.5
6.5
Continuos voltage at pin DIAG
VDIAG
-0.5
6.5
V
Load current (short-circuit current)
IL
⎯
self limited
Reverse current through GNDbb1)
IGNDbb
-1.6
⎯
Operating Temperature
Tj
-25
internal limited °C
Extended Operation Temperature
Tj
-40
internal limited
⎯
3.3
Power Dissipation
2)
Ptot
3)
Inductive load switch-off energy dissipation single
pulse, Tj = 125°C, IL = 1.2A
one channel active
all channel simultaneously active (each channel)
EAS
Load dump protection3) VloadDump4)=VA + VS
VIN = low or high
td = 400ms, RI = 2Ω, RL = 27Ω, VA = 13.5V
td = 350ms, RI = 2Ω, RL = 57Ω, VA = 27V
VLoaddump
Electrostatic discharge voltage (Human Body Model)
according to JESD22-A114-B
VESD
Electrostatic discharge voltage (Charge Device Model)
according to ESD STM5.3.1 - 1999
VESD
Continuos reverse drain current1)3), each channel
IS
A
W
J
⎯
5
0.5
V
90
117
kV
2
kV
1
⎯
4
A
1) defined by Ptot
2) Device on 50mm*50mm*1.5mm epoxy PCB FR4 with 6cm² (one layer, 70µm thick) copper area for drain connection. PCB
is vertical without blown air.
3) not subject to production test, specified by design
4) VLoaddump is setup without the DUT connected to the generator per ISO7637-1 and DIN40839
Datasheet
12
Revision 2.4, 2014-10-20
ISOFACE™
ISO1H815G
Electrical Characteristics
4.2
Thermal Characteristics
Parameter
at Tj = -25 ... 125°C, Vbb=15...30V, VCC=3.0...5.5V, unless
otherwise specified
Symbol
Thermal resistance junction - case
RthJC
Thermal resistance @ min. footprint
Rth(JA)
Thermal resistance @ 6cm² cooling area1)
Rth(JA)
Limit Values
Unit Test Condition
min.
typ.
max.
⎯
⎯
⎯
⎯
⎯
⎯
1.5
K/W
50
38
1) Device on 50mm*50mm*1.5mm epoxy PCB FR4 with 6cm² (one layer, 70µm thick) copper area for drain connection. PCB
is vertical without blown air.
4.3
Load Switching Capabilities and Characteristics
Parameter
at Tj = -25 ... 125°C, Vbb=15...30V, VCC=3.0...5.5V, unless
otherwise specified
On-state resistance, IL = 0.5A, each channel
Tj = 25°C
Tj = 125°C
two parallel channels, Tj = 25°C:1)
four parallel channels, Tj = 25°C:1)
Nominal load current
Device on PCB 38K/W, Ta = 85°C, Tj < 125°C
one channel:1)
two parallel channels:1)
four parallel channels:1)
Symbol
RON
Limit Values
Unit
min.
typ.
max.
⎯
⎯
150
270
75
38
200
320
100
50
IL(NOM)
Test Condition
mΩ
1.4
2.2
4.4
A
Turn-on time to 90% VOUT2)
RL = 47Ω, VDx = 0 to 5V
ton
⎯
64
120
Turn-off time to 10% VOUT2)
RL = 47Ω, VDx = 5 to 0V
toff
⎯
89
170
Slew rate on 10 to 30% VOUT
RL = 47Ω, Vbb = 15V
dV/dton
⎯
1
2
Slew rate off 70 to 40% VOUT
RL = 47Ω, Vbb = 15V
-dV/dtoff
⎯
1
2
µs
V/µs
1) not subject to production test, specified by design
2) The turn-on and turn-off time includes the switching time of the high-side switch and the transmission time via the coreless
transformer in normal operating mode. During a failure on the coreless transformer transmission turn-on or turn-off time
can increase by up to 50µs.
Datasheet
13
Revision 2.4, 2014-10-20
ISOFACE™
ISO1H815G
Electrical Characteristics
4.4
Operating Parameters
Parameter
at Tj = -25 ... 125°C, Vbb=15...30V, VCC=3.0...5.5V, unless
otherwise specified
Symbol
Common mode transient immunity1)
Magnetic field immunity1)
Voltage domain Vbb
(Output interface)
Limit Values
Unit
min.
typ.
max.
ΔVISO/dt
-25
-
25
HIM
100
Operating voltage
Vbb
11
Undervoltage shutdown
Vbb(under)
7
Undervoltage restart
Vbb(u_rst)
Undervoltage hysteresis
ΔVbb(under)
Undervoltage current
Ibb(uvlo)
Operating current
IGNDL
⎯
⎯
⎯
⎯
Leakage output current
(included in Ibb(off))
VDx = low, each channel
IL(off)
Voltage domain VCC Operating voltage
(Input interface)
Undervoltage shutdown
Test Condition
kV/µs ΔVISO = 500V
A/m
IEC61000-4-8
⎯
⎯
⎯
10.5
0.5
⎯
1
2.5
mA
Vbb < 7V
10
14
mA
All Channels
ON - no load
⎯
5
30
µA
VCC
3.0
5.5
V
VCC(under)
2.5
⎯
⎯
⎯
0.1
⎯
1
2
mA
4.5
6
mA
Undervoltage restart
VCC(u_rst)
Undervoltage hysteresis
ΔVCC(under)
Undervoltage current
ICC(uvlo)
Operating current
ICC(on)
⎯
⎯
⎯
⎯
35
V
11
2.9
3
Vcc < 2.5V
1) not subject to production test
Datasheet
14
Revision 2.4, 2014-10-20
ISOFACE™
ISO1H815G
Electrical Characteristics
4.5
Output Protection Functions
Parameter1)
at Tj = -25 ... 125°C, Vbb=15...30V, VCC=3.0...5.5V, unless
otherwise specified
Symbol
Initial peak short circuit current limit, each channel IL(SCp)
Tj = -25°C, Vbb = 30V, tm = 700µs
Tj = 25°C
Tj = 125°C
two parallel channels:2)
four parallel channels:2)
Limit Values
Unit Test Condition
min.
typ.
max.
⎯
⎯
⎯
4.5
1.4
A
⎯
⎯
3.0
⎯
twice the current of one channel
four times the current of one channel
Repetitive short circuit current limit
IL(SCr)
Tj = Tjt (see timing diagrams)
each channel:2)
two parallel channels:2)
four parallel channels:2)
⎯
Output clamp (inductive load switch off)3)
at VOUT = Vbb - VON(CL)
VON(CL)
47
53
60
V
Overvoltage protection
Vbb(AZ)
47
Tjt
135
⎯
⎯
°C
⎯
10
⎯
⎯
⎯
2)4)
Thermal overload trip temperature
Thermal hysteresis
2)
ΔTjt
⎯
2.2
2.2
2.2
K
1) Integrated protection functions are designed to prevent IC destruction under fault conditions described in the data sheet.
Fault conditions are considered as “outside” normal operating range. Protection functions are not designed for continuous
repetitive operation.
2) not subject to production test, specified by design
3) If channels are connected in parallel, output clamp is usually accomplished by the channel with the lowest VON(CL)
4) Higher operating temperature at normal function for each channel available
4.6
Diagnostic Characteristics at pin DIAG
Parameter
at Tj = -25 ... 125°C, Vbb=15...30V, VCC=3.0...5.5V, unless
otherwise specified
Symbol
Common diagnostic sink current
(overtemperature of any channel) Tj = 135°C
Idiagsink
Common diagnostic source current
Idiagsource
Datasheet
Limit Values
min.
15
typ.
Unit Test Condition
max.
5
100
mA Vdiagon <
0.25xVCC
µA
Revision 2.4, 2014-10-20
ISOFACE™
ISO1H815G
Electrical Characteristics
4.7
Input Interface
Parameter
at Tj = -25 ... 125°C, Vbb=15...30V, VCC=3.0...5.5V, unless
otherwise specified
Symbol
Limit Values
Unit Test Condition
min.
typ.
max.
0.3 x
VCC
Input low state voltage
(D0 ... D7, DIS, CS, WR)
VIL
-0.3
⎯
Input high state voltage
(D0 ... D7, DIS, CS, WR)
VIH
0.7 x
VCC
⎯
Input voltage hysteresis
(D0 ... D7, DIS, CS, WR)
VIHys
100
mV
Input pull down current
(D0 ... D7, DIS)
IIdown
100
µA
Input pull up current
(CS, WR)
-IIup
100
Output disable time (transition DIS to logic low)1)2)
Normal operation
Turn-off time to 10% VOUT
RL = 47Ω
tDIS
---
85
170
Output disable time (transition DIS to logic low)1)2)3)
Disturbed operation
Turn-off time to 10% VOUT
RL = 47Ω
tDIS
---
---
230
V
VCC+
0.3
µs
1) The time includes the turn-on/off time of the high-side switch and the transmission time via the coreless transformer.
2) If Pin DIS is set to low the outputs are set to low; after DIS set to high a new write cycle is necessary to set the output again.
3) The parameter is not subject to production test - verified by design/characterization
4.8
Parallel Interface Input Timing
Parameter
at Tj = -25 ... 125°C, Vbb=15...30V, VCC=3.0...5.5V, unless
otherwise specified
Symbol
Limit Values
Unit Test Condition
min.
typ.
max.
tWRPW
20
Data setup time before WR
tDS
20
Data hold time after WR
tDH
10
Chip select valid to WR
tCSWR
0
WR logic high to CS logic high
tWHCS
10
tCSD
20
tCSDMD
20
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
tIOJ
8
⎯
20
WR pulse width
Delay to next CS cycle
Delay to next CS cycle for multiple device
synchronization1)
Input to output data transmission jitter in direct
mode1)
ns
µs
2)
2)
1) necessary CS delay time to ensure a proper data update for multiple devices
2) not subject to production test, specified by design
Datasheet
16
Revision 2.4, 2014-10-20
ISOFACE™
ISO1H815G
Electrical Characteristics
4.9
Reverse Voltage
Parameter
at Tj = -25 ... 125°C, Vbb=15...30V, VCC=3.0...5.5V, unless
otherwise specified
Symbol
Reverse voltage1) 2)
RGND = 0 Ω
RGND = 150 Ω
-Vbb
Diode forward on voltage
IF = 1.25A, VDx = low, each channel
-VON
Limit Values
Unit Test Condition
min.
typ.
max.
⎯
⎯
⎯
⎯
1
45
⎯
⎯
1.2
V
1) defined by Ptot
2) not subject to production test, specified by design
4.10
Isolation and Safety-Related Specification
Parameter
Measured from input terminals to output terminals,
unless otherwise specified
Value
Unit
Conditions
Rated dielectric isolation voltage VISO
500
VAC
1 - minute duration1)
Short term temporary overvoltage
1250
V
5s acc. DIN EN60664-1 1)
Minimum external air gap (clearance)
2.6
mm
shortest distance through air.
Minimum external tracking (creepage)
2.6
mm
shortest distance path along body.
1) not subject to production test, verified by characterization; Production Test with 1100V, 100ms duration
4.11
Reliability
For Qualification Report please contact your local Infineon Technologies office!
Datasheet
17
Revision 2.4, 2014-10-20
ISOFACE™
ISO1H815G
Electrical Characteristics
Datasheet
18
Revision 2.4, 2014-10-20
ISOFACE™
ISO1H815G
Electrical Characteristics
Datasheet
19
Revision 2.4, 2014-10-20
ISOFACE™
ISO1H815G
Package Outlines
Package Outlines
0.65
0.25 +0.13
15.74 ±0.1
(Heatslug)
+0.07
-0.02
B
2.8
6.3
0.1 C
(Mold)
5˚ ±3˚
0.25
0 +0.1
1.1 ±0.1
11 ±0.15 1)
1.3
(Plastic Dual Small
Outline Package)
3.25 ±0.1
PG-DSO-36
3.5 MAX.
5
Heatslug
0.95 ±0.15
36x
0.25 M A B C
14.2 ±0.3
0.25 B
19
19
1
18
10
36
5.9 ±0.1
(Metal)
36
3.2 ±0.1
(Metal)
Bottom View
Index Marking
1 x 45˚
15.9 ±0.1 1)
(Mold)
1)
Figure 12
Datasheet
A
13.7 -0.2
(Metal)
Does not include plastic or metal protrusion of 0.15 max. per side
1
Heatslug
gps09181_1
PG-DSO36
20
Revision 2.4, 2014-10-20
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Published by Infineon Technologies AG