LINER LT1054IS8 Switched-capacitor voltage converter with regulator Datasheet

LT1054/LT1054L
Switched-Capacitor Voltage
Converter with Regulator
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FEATURES
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DESCRIPTIO
The LT ®1054 is a monolithic, bipolar, switched-capacitor
voltage converter and regulator. The LT1054 provides
higher output current than previously available converters
with significantly lower voltage losses. An adaptive switch
driver scheme optimizes efficiency over a wide range of
output currents. Total voltage loss at 100mA output current
is typically 1.1V. This holds true over the full supply voltage
range of 3.5V to 15V. Quiescent current is typically 2.5mA.
Available in Space Saving SO-8 Package
Output Current: 100mA (LT1054)
125mA (LT1054L)
Reference and Error Amplifier for Regulation
Low Loss: 1.1V at 100mA
Operating Range:3.5V to 15V (LT1054)
3.5V to 7V (LT1054L)
External Shutdown
External Oscillator Synchronization
Can Be Paralleled
Pin Compatible with the LTC®1044/LTC7660
The LT1054 also provides regulation, a feature not previously available in switched-capacitor voltage converters.
By adding an external resistive divider a regulated output
can be obtained. This output will be regulated against
changes in both input voltage and output current. The
LT1054 can also be shut down by grounding the feedback
pin. Supply current in shutdown is less than 100µA.
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APPLICATIO S
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Voltage Inverter
Voltage Regulator
Negative Voltage Doubler
Positive Voltage Doubler
The internal oscillator of the LT1054 runs at a nominal
frequency of 25kHz. The oscillator pin can be used to adjust
the switching frequency or to externally synchronize the
LT1054.
The LT1054 is pin compatible with previous converters
such the LTC1044/LTC7660.
, LTC and LT are registered trademarks of Linear Technology Corporation.
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BLOCK DIAGRA
VREF
LT1054/LT1054L Voltage Loss
VIN
6
8
2
2.5V
REFERENCE
R
DRIVE
+
VOLTAGE LOSS (V)
CAP + 2
+
FEEDBACK/
SHUTDOWN
OSC
R
CIN*
Q
–
1
3.5V ≤ VIN ≤ 15V (LT1054)
3.5V ≤ VIN ≤ 7V (LT1054L)
CIN = COUT = 100µF
INDICATES GUARANTEED
TEST POINT
7
OSC
Q
CAP – 4
DRIVE
LT1054L
LT1054
1
TJ = 125°C
TJ = 25°C
TJ = –55°C
DRIVE
3 GND
+
*EXTERNAL CAPACITORS
0
COUT*
5 –VOUT
0
25
50
75
100
OUTPUT CURRENT (mA)
125
1054 TA01•
DRIVE
LT1054 • BD
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LT1054/LT1054L
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ABSOLUTE
RATI GS
(Note 1)
Supply Voltage (Note 2)
LT1054 ................................................................ 16V
LT1054L ................................................................ 7V
Input Voltage
Pin 1 ................................................. 0V ≤ VPIN1 ≤ V+
Pin 3 (S Package) ............................. 0V ≤ VPIN3 ≤ V+
Pin 7 ............................................. 0V ≤ VPIN7 ≤ VREF
Pin 13 (S Package) ...................... 0V ≤ VPIN13 ≤ VREF
Operating Junction Temperature Range
LT1054C/LT1054LC ............................. 0°C to 100°C
LT1054I ........................................... – 40°C to 100°C
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PACKAGE/ORDER I FOR ATIO
Maximum Junction Temperature (Note 3)
LT1054C/LT1054LC ........................................ 125°C
LT1054I ............................................................ 125°C
Storage Temperature Range
J8, N8 and S8 Packages .................... –55°C to 150°C
S Package ........................................ – 65°C to 150°C
Lead Temperature (Soldering, 10 sec)................. 300°C
(Note 6)
TOP VIEW
TOP VIEW
TOP VIEW
FB/SHDN 1
8
V+
CAP + 2
7
OSC
GND 3
6
VREF
CAP – 4
5
VOUT
N8 PACKAGE
8-LEAD PLASTIC DIP
TJMAX = 125°C, θJA = 130°C/ W (N8)
NC 1
16 NC
NC 2
15 NC
OSC
FB/SHDN 3
14 V +
CAP +
FB/SHDN 1
8
V+
CAP + 2
7
GND 3
6
VREF
CAP – 4
5
VOUT
S8 PACKAGE
8-LEAD PLASTIC SO
TJMAX = 125°C, θJA = 120°C/W
SEE REGULATION AND CAPACITOR SELECTION SECTIONS
IN THE APPLICATIONS INFORMATION FOR IMPORTANT
INFORMATION ON THE S8 DEVICE
4
13 OSC
GND 5
12 VREF
CAP – 6
11 VOUT
NC 7
10 NC
NC 8
9
NC
SW PACKAGE
16-LEAD PLASTIC SO
TJMAX = 125°C, θJA = 150°C/W
ORDER PART
NUMBER
LT1054CN8
LT1054IN8
J8 PACKAGE
8-LEAD CERAMIC DIP
TJMAX = 150°C, θJA = 100°C/ W (J8)
LT1054CJ8
LT1054MJ8
OBSOLETE PACKAGE
Consider N8 Package for Alternate Source
ORDER PART
NUMBER
ORDER PART
NUMBER
LT1054CS8
LT1054LCS8
LT1054IS8
LT1054CSW
LT1054ISW
S8 PART
MARKING
1054
1054L
1054I
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LT1054/LT1054L
ELECTRICAL CHARACTERISTICS
The ● denotes specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 7)
PARAMETER
Supply Current
Supply Voltage Range
Voltage Loss (VIN – VOUT)
Output Resistance
Oscillator Frequency
Reference Voltage
CONDITIONS
ILOAD = 0mA
MIN
LT1054:
VIN = 3.5V
VIN = 15V
LT1054L: VIN = 3.5V
VIN = 7V
●
●
LT1054
LT1054L
CIN = COUT = 100µF Tantalum (Note 4)
IOUT = 10mA
IOUT = 100mA
IOUT = 125mA (LT1054L)
∆IOUT = 10mA to 100mA (Note 5)
LT1054: 3.5V ≤ VIN ≤ 15V
LT1054L: 3.5V ≤ VIN ≤ 7V
IREF = 60µA, TJ = 25°C
●
●
●
●
●
●
Regulated Voltage
Line Regulation
Load Regulation
Maximum Switch Current
Supply Current in Shutdown
VIN = 7V, TJ = 25°C, RL = 500Ω (Note 6)
LT1054: 7V ≤ VIN ≤ 12V, RL = 500Ω (Note 6)
VIN = 7V, 100Ω ≤ RL ≤ 500Ω (Note 6)
●
VPIN1 = 0V
●
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: The absolute maximum supply voltage rating of 16V is for
unregulated circuits using LT1054. For regulation mode circuits using
LT1054 with VOUT ≤ 15V at Pin 5 (Pin 11 on S package), this rating may
be increased to 20V. The absolute maximum supply voltage for LT1054L
is 7V.
Note 3: The devices are guaranteed by design to be functional up to the
absolute maximum junction temperature.
Note 4: For voltage loss tests, the device is connected as a voltage
inverter, with pins 1, 6, and 7 (3, 12, and 13 S package) unconnected.
The voltage losses may be higher in other configurations.
●
MAX
4.0
5.0
4.0
5.0
15
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UNITS
mA
mA
mA
mA
V
V
0.35
1.10
1.35
10
25
25
2.50
0.55
1.60
1.75
15
40
35
2.65
2.75
– 5.20
25
50
V
V
V
Ω
kHz
kHz
V
V
V
mV
mV
mA
µA
3.5
3.5
●
●
●
●
●
TYP
2.5
3.0
2.5
3.0
15
15
2.35
2.25
– 4.70
– 5.00
5
10
300
100
200
Note 5: Output resistance is defined as the slope of the curve, (∆VOUT vs
∆IOUT), for output currents of 10mA to 100mA. This represents the linear
portion of the curve. The incremental slope of the curve will be higher at
currents < 10mA due to the characteristics of the switch transistors.
Note 6: All regulation specifications are for a device connected as a
positive-to-negative converter/regulator with R1 = 20k, R2 = 102.5k,
C1 = 0.002µF, (C1 = 0.05µF S package) CIN = 10µF tantalum,
COUT = 100µF tantalum.
Note 7: The S8 package uses a different die than the H, J8, N8 and S
packages. The S8 device will meet all the existing data sheet parameters.
See Regulation and Capacitor Selection in the Applications Information
section for differences in application requirements.
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LT1054/LT1054L
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TYPICAL PERFOR A CE CHARACTERISTICS
Shutdown Threshold
Supply Current
Oscillator Frequency
35
5
0.6
0.5
0.4
0.3
0.2
FREQUENCY (kHz)
4
VPIN1
SUPPLY CURRENT (mA)
SHUTDOWN THRESHOLD (V)
IL = 0
3
2
0
– 50 – 25
0
50
25
75
0
TEMPERATURE (˚C)
100
125
0
10
5
INPUT VOLTAGE (V)
15
–70 –50 –25 0
25 50 75
TEMPERATURE (°C)
15
LT1054 • TPC02
LT1054 • TPC01
Supply Current in Shutdown
Average Input Current
Output Voltage Loss
1.4
100
120
1.2
100
1.0
80
60
40
20
0
10
5
INPUT VOLTAGE (V)
VOLTAGE LOSS (V)
140
VPIN1 = 0V
80
60
40
20
20
100
60
80
40
OUTPUT CURRENT (mA)
INVERTER CONFIGURATION
COUT = 100µF TANTALUM
fOSC = 25kHz
0 10 20 30 40 50 60 70 80 90 100
INPUT CAPACITANCE (µF)
LT1054 • TPC06
Output Voltage Loss
INVERTER CONFIGURATION
CIN = 10µF TANTALUM
COUT = 100µF TANTALUM
INVERTER CONFIGURATION
CIN = 100µF TANTALUM
COUT = 100µF TANTALUM
2
VOLTAGE LOSS (V)
VOLTAGE LOSS (V)
IOUT = 10mA
0.4
LT1050 • TPC05
Output Voltage Loss
IOUT = 100mA
1
IOUT = 50mA
0.6
0
0
LT1054 • TPC04
2
IOUT = 100mA
0.8
0.2
0
15
100 125
LT1054 • TPC03
120
AVERAGE INPUT CURRENT (mA)
QUIESCENT CURRENT (µA)
VIN = 3.5V
1
0.1
0
VIN = 15V
25
IOUT = 50mA
IOUT = 100mA
1
IOUT = 50mA
IOUT = 10mA
IOUT = 10mA
0
0
1
10
OSCILLATOR FREQUENCY (kHz)
100
LT1054 • TPC07
1
10
OSCILLATOR FREQUENCY (kHz)
100
LT1054 • TPC08
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LT1054/LT1054L
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TYPICAL PERFOR A CE CHARACTERISTICS
Reference Voltage Temperature
Coefficient
Regulated Output Voltage
100
–4.8
80
REFERENCE VOLTAGE CHANGE (mV)
–4.7
OUTPUT VOLTAGE (V)
–4.9
–5.0
–5.1
–11.6
–11.8
–12.0
–12.2
–12.4
–12.6
–50 –25
50
25
0
75
TEMPERATURE (°C)
100
125
LT1054 • TPC09
VREF AT 0 = 2.500V
60
40
20
0
–20
–40
–60
–80
–100
–50 –25
50
25
0
75
TEMPERATURE (°C)
100
125
LT1054 • TPC10
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PIN FUNCTIONS
FB/SHDN (Pin 1): Feedback/Shutdown Pin. This pin has
two functions. Pulling Pin 1 below the shutdown threshold
(≈ 0.45V) puts the device into shutdown. In shutdown the
reference/regulator is turned off and switching stops. The
switches are set such that both CIN and COUT are discharged through the output load. Quiescent current in
shutdown drops to approximately 100µA (see Typical
Performance Characteristics). Any open-collector gate can
be used to put the LT1054 into shutdown. For normal
(unregulated) operation the device will start back up when
the external gate is shut off. In LT1054 circuits that use the
regulation feature, the external resistor divider can provide
enough pull-down to keep the device in shutdown until the
output capacitor (COUT) has fully discharged. For most
applications where the LT1054 would be run intermittently,
this does not present a problem because the discharge time
of the output capacitor will be short compared to the offtime of the device. In applications where the device has to
start up before the output capacitor (COUT) has fully discharged, a restart pulse must be applied to Pin 1 of the
LT1054. Using the circuit of Figure 5, the restart signal can
be either a pulse (tp > 100µs) or a logic high. Diode coupling
the restart signal into Pin 1 will allow the output voltage to
come up and regulate without overshoot. The resistor
divider R3/R4 in Figure 5 should be chosen to provide a
signal level at pin 1 of 0.7V to 1.1V.
Pin 1 is also the inverting input of the LT1054’s error
amplifier and as such can be used to obtain a regulated
output voltage.
CAP +/CAP – (Pin 2/Pin 4): Pin 2, the positive side of the
input capacitor (CIN), is alternately driven between V + and
ground. When driven to V +, Pin 2 sources current from V +.
When driven to ground Pin 2 sinks current to ground. Pin
4, the negative side of the input capacitor, is driven alternately between ground the VOUT. When driven to ground,
Pin 4 sinks current to ground. When driven to VOUT Pin 4
sources current from COUT. In all cases current flow in the
switches is unidirectional as should be expected using
bipolar switches.
VOUT (Pin 5): In addition to being the output pin this pin is
also tied to the substrate of the device. Special care must
be taken in LT1054 circuits to avoid pulling this pin
positive with respect to any of the other pins. Pulling Pin
5 positive with respect to Pin 3 (GND) will forward bias the
substrate diode which will prevent the device from starting.
This condition can occur when the output load driven by the
LT1054 is referred to its positive supply (or to some other
positive voltage). Note that most op amps present just such
a load since their supply currents flow from their V +
terminals to their V – terminals. To prevent start-up problems with this type of load an external transistor must be
added as shown in Figure 1. This will prevent VOUT (Pin 5)
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LT1054/LT1054L
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PIN FUNCTIONS
from being pulled above the ground pin (Pin 3) during
start-up. Any small, general purpose transistor such as
2N2222 or 2N2219 can be used. RX should be chosen to
provide enough base drive to the external transistor so that
it is saturated under nominal output voltage and maximum
output current conditions. In some cases an N-channel
enhancement mode MOSFET can be used in place of the
transistor.
RX ≤
(|VOUT|)β
IOUT
V+
IL
+
IQ
LOAD
FB/SHDN
+
CIN
OSC
CAP +
LT1054
GND
VREF
CAP –
–
V+
IOUT
RX
VOUT
LT1054 • F01
+
COUT
Figure 1
VREF (Pin 6): Reference Output. This pin provides a 2.5V
reference point for use in LT1054-based regulator circuits.
The temperature coefficient of the reference voltage has
been adjusted so that the temperature coefficient of the
regulated output voltage is close to zero. This requires the
reference output to have a positive temperature coefficient
as can be seen in the typical performance curves. This
nonzero drift is necessary to offset a drift term inherent in
the internal reference divider and comparator network tied
to the feedback pin. The overall result of these drift terms
is a regulated output which has a slight positive temperature coefficient at output voltages below 5V and a slight
negative TC at output voltages above 5V. Reference output
current should be limited, for regulator feedback networks,
to approximately 60µA. The reference pin will draw
≈100µA when shorted to ground and will not affect the
internal reference/regulator, so that this pin can also be
used as a pull-up for LT1054 circuits that require synchronization.
OSC (Pin 7): Oscillator Pin. This pin can be used to raise or
lower the oscillator frequency or to synchronize the device
to an external clock. Internally Pin 7 is connected to the
oscillator timing capacitor (Ct ≈ 150pF) which is alternately
charged and discharged by current sources of ±7µA so that
the duty cycle is ≈ 50%. The LT1054 oscillator is designed
to run in the frequency band where switching losses are
minimized. However the frequency can be raised, lowered,
or synchronized to an external system clock if necessary.
The frequency can be lowered by adding an external
capacitor (C1, Figure 2) from Pin 7 to ground. This will
increase the charge and discharge times which lowers the
oscillator frequency. The frequency can be increased by
adding an external capacitor (C2, Figure 2, in the range of
5pF to 20pF) from Pin 2 to Pin 7. This capacitor will couple
charge into CT at the switch transitions, which will shorten
the charge and discharge time, raising the oscillator frequency. Synchronization can be accomplished by adding
an external resistive pull-up from Pin 7 to the reference pin
(Pin 6). A 20k pull-up is recommended. An open collector
gate or an NPN transistor can then be used to drive the
oscillator pin at the external clock frequency as shown in
Figure 2. Pulling up Pin 7 to an external voltage is
not recommended. For circuits that require both frequency synchronization and regulation, an external reference can be used as the reference point for the top of the
R1/R2 divider allowing Pin 6 to be used as a pull-up point
for Pin 7.
FB/SHDN V +
VIN
C2
+
+
CIN
OSC
CAP
LT1054
GND
VREF
CAP
–
C1
VOUT
+
COUT
LT1054 • F02
Figure 2
V + (Pin 8): Input Supply. The LT1054 alternately charges
CIN to the input voltage when CIN is switched in parallel with
the input supply and then transfers charge to COUT when
CIN is switched in parallel with COUT. Switching occurs at
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LT1054/LT1054L
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PIN FUNCTIONS
the oscillator frequency. During the time that CIN is charging, the peak supply current will be approximately equal to
2.2 times the output current. During the time that CIN is
delivering charge to COUT the supply current drops to
approximately 0.2 times the output current. An input
supply bypass capacitor will supply part of the peak input
current drawn by the LT1054 and average out the current
drawn from the supply. A minimum input supply bypass
capacitor of 2µF, preferably tantalum or some other low
ESR type is recommended. A larger capacitor may be
desirable in some cases, for example, when the actual input
supply is connected to the LT1054 through long leads, or
when the pulse current drawn by the LT1054 might affect
other circuitry through supply coupling.
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APPLICATIONS INFORMATION
V1
Theory of Operation
V2
f
To understand the theory of operation of the LT1054, a
review of a basic switched-capacitor building block is
helpful.
In Figure 3 when the switch is in the left position, capacitor
C1 will charge to voltage V1. The total charge on C1 will be
q1 = C1V1. The switch then moves to the right, discharging
C1 to voltage V2. After this discharge time the charge on C1
is q2 = C1V2. Note that charge has been transferred from
the source V1 to the output V2. The amount of charge
transferred is:
∆q = q1 – q2 = C1(V1 – V2)
If the switch is cycled f times per second, the charge
transfer per unit time (i.e., current) is:
I = (f)(∆q) = (f)[C1(V1 – V2)]
To obtain an equivalent resistance for the switched-capacitor network we can rewrite this equation in terms of voltage
and impedance equivalence:
I = V1 – V2 = V1 – V2
(1/fC1) REQUIV
A new variable REQUIV is defined such that REQUIV = 1/fC1.
Thus the equivalent circuit for the switched-capacitor
network is as shown in Figure 4. The LT1054 has the same
switching action as the basic switched-capacitor building
block. Even though this simplification doesn’t include finite
switch on-resistance and output voltage ripple, it provides
an intuitive feel for how the device works.
These simplified circuits explain voltage loss as a function
of frequency (see Typical Performance Characteristics). As
frequency is decreased, the output impedance will eventu-
C1
C2
RL
LT1054 • F03
Figure 3. Switched-Capacitor Building Block
REQUIV
V1
REQUIV = 1
fC1
V2
C2
RL
LT1054 • F04
Figure 4. Switched-Capacitor Equivalent Circuit
ally be dominated by the 1/fC1 term and voltage losses will
rise.
Note that losses also rise as frequency increases. This is
caused by internal switching losses which occur due to
some finite charge being lost on each switching cycle. This
charge loss per-unit-cycle, when multiplied by the switching frequency, becomes a current loss. At high frequency
this loss becomes significant and voltage losses again rise.
The oscillator of the LT1054 is designed to run in the
frequency band where voltage losses are at a minimum.
Regulation
The error amplifier of the LT1054 servos the drive to the
PNP switch to control the voltage across the input capacitor (CIN) which in turn will determine the output voltage.
Using the reference and error amplifier of the LT1054, an
external resistive divider is all that is needed to set the
regulated output voltage. Figure 5 shows the basic regulator configuration and the formula for calculating the
appropriate resistor values. R1 should be chosen to be
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LT1054/LT1054L
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APPLICATIONS INFORMATION
R3
VIN
FB/SHDN
R4
CIN
10µF
TANTALUM
+
OSC
CAP +
LT1054
GND
VREF
CAP –
R1
R2
VOUT
C1
RESTART SHUTDOWN
)
)) )
|VOUT|
|VOUT|
R2 =
+1 ≈
+1
1.21V
VREF
R1
– 40mV
2
WHERE VREF = 2.5V NOMINAL
VOUT
FOR EXAMPLE: TO GET VOUT = –5V REFERRED TO THE GROUND
PIN OF THE LT1054, CHOOSE R1 = 20k, THEN
)
+2.2µF
V+
+
COUT
100µF
TANTALUM
LT1054 • F05
)
|–5V|
+ 1 = 102.6k*
2.5V
– 40mV
2
*CHOOSE THE CLOSEST 1% VALUE
R2 = 20k
voltage. For the basic configuration, |VOUT| referred to the
ground pin of the LT1054 must be less than the total of the
supply voltage minus the voltage loss due to the switches.
The voltage loss versus output current due to the switches
can be found in Typical Performance Characteristics. Other
configurations such as the negative doubler can provide
higher output voltages at reduced output currents (see
Typical Applications).
Figure 5
20k or greater because the reference output current is
limited to ≈ 100µA. R2 should be chosen to be in the range
of 100k to 300k. For optimum results the ratio of CIN/COUT
is recommended to be 1/10. C1, required for good load
regulation at light load currents, should be 0.002µF for all
output voltages.
A new die layout was required to fit into the physical
dimensions of the S8 package. Although the new die of the
LT1054CS8 will meet all the specifications of the existing
LT1054 data sheet, subtle differences in the layout of the
new die require consideration in some application circuits. In regulating mode circuits using the 1054CS8 the
nominal values of the capacitors, CIN and COUT, must be
approximately equal for proper operation at elevated
junction temperatures. This is different from the earlier
part. Mismatches within normal production tolerances
for the capacitors are acceptable. Making the nominal
capacitor values equal will ensure proper operation at
elevated junction temperatures at the cost of a small
degradation in the transient response of regulator circuits. For unregulated circuits the values of CIN and COUT
are normally equal for all packages. For S8 applications
assistance in unusual applications circuits, please consult
the factory.
It can be seen from the circuit block diagram that the
maximum regulated output voltage is limited by the supply
Capacitor Selection
For unregulated circuits the nominal values of CIN and COUT
should be equal. For regulated circuits see the section on
Regulation. While the exact values of CIN and COUT are
noncritical, good quality, low ESR capacitors such as solid
tantalum are necessary to minimize voltage losses at high
currents. For CIN the effect of the ESR of the capacitor will
be multiplied by four due to the fact that switch currents are
approximately two times higher than output current and
losses will occur on both the charge and discharge cycle.
This means that using a capacitor with 1Ω of ESR for CIN
will have the same effect as increasing the output impedance of the LT1054 by 4Ω. This represents a significant
increase in the voltage losses. For COUT the affect of ESR is
less dramatic. COUT is alternately charged and discharged
at a current approximately equal to the output current and
the ESR of the capacitor will cause a step function to occur
in the output ripple at the switch transitions. This step
function will degrade the output regulation for changes in
output load current and should be avoided. Realizing that
large value tantalum capacitors can be expensive, a technique that can be used is to parallel a smaller tantalum
capacitor with a large aluminum electrolytic capacitor to
gain both low ESR and reasonable cost. Where physical
size is a concern some of the newer chip type surface
mount tantalum capacitors can be used. These capacitors
are normally rated at working voltages in the 10V to 20V
range and exhibit very low ESR (in the range of 0.1Ω).
Output Ripple
The peak-to-peak output ripple is determined by the value
of the output capacitor and the output current. Peak-topeak output ripple may be approximated by the formula:
dV =
IOUT
2fCOUT
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APPLICATIONS INFORMATION
where dV = peak-to-peak ripple and f = oscillator frequency.
For output capacitors with significant ESR a second term
must be added to account for the voltage step at the switch
transitions. This step is approximately equal to:
Power Dissipation
The power dissipation of any LT1054 circuit must be
limited such that the junction temperature of the device
does not exceed the maximum junction temperature ratings. The total power dissipation must be calculated from
two components, the power loss due to voltage drops in the
switches and the power loss due to drive current losses.
The total power dissipated by the LT1054 can be calculated
from:
P ≈ (VIN – |VOUT|)(IOUT) + (VIN)(IOUT)(0.2)
where both VIN and VOUT are referred to the ground pin (Pin
3) of the LT1054. For LT1054 regulator circuits, the power
dissipation will be equivalent to that of a linear regulator.
Due to the limited power handling capability of the LT1054
packages, the user will have to limit output current requirements or take steps to dissipate some power external to the
LT1054 for large input/output differentials. This can be
accomplished by placing a resistor in series with CIN as
shown in Figure 6. A portion of the input voltage will then
be dropped across this resistor without affecting the output
regulation. Because switch current is approximately 2.2
times the output current and the resistor will cause a
voltage drop when CIN is both charging and discharging,
the resistor should be chosen as:
VIN
FB/SHDN V +
CIN
OSC
CAP +
LT1054
GND
VREF
CAP –
R1
R2
VOUT
C1
VOUT
+
RX
where
VX ≈ VIN – [(LT1054 Voltage Loss)(1.3) + |VOUT|]
and IOUT = maximum required output current. The factor of
1.3 will allow some operating margin for the LT1054.
(2IOUT)(ESR of COUT)
+
RX = VX/(4.4 IOUT)
COUT
LT1054 • F06
For example: assume a 12V to – 5V converter at 100mA
output current. First calculate the power dissipation without an external resistor:
P = (12V – | – 5V|)(100mA) + (12V)(100mA)(0.2)
P = 700mW + 240mW = 940mW
At θJA of 130°C/W for a commercial plastic device this
would cause a junction temperature rise of 122°C so that
the device would exceed the maximum junction temperature at an ambient temperature of 25°C. Now calculate the
power dissipation with an external resistor (RX). First find
how much voltage can be dropped across RX. The maximum voltage loss of the LT1054 in the standard regulator
configuration at 100mA output current is 1.6V, so
VX = 12V – [(1.6V)(1.3) + | – 5V|] = 4.9V and
RX = 4.9V/(4.4)(100mA) = 11Ω
This resistor will reduce the power dissipated by the
LT1054 by (4.9V)(100mA) = 490mW. The total power
dissipated by the LT1054 would then be (940mW –
490mW) = 450mW. The junction temperature rise would
now be only 58°C. Although commercial devices are
guaranteed to be functional up to a junction temperature
of 125°C, the specifications are only guaranteed up to a
junction temperature of 100°C, so ideally you should limit
the junction temperature to 100°C. For the above example
this would mean limiting the ambient temperature to 42°C.
Other steps can be taken to allow higher ambient temperatures. The thermal resistance numbers for the LT1054
packages represent worst case numbers with no heat
sinking and still air. Small clip-on type heat sinks can be
used to lower the thermal resistance of the LT1054 package. In some systems there may be some available airflow
which will help to lower the thermal resistance. Wide PC
board traces from the LT1054 leads can also help to
remove heat from the device. This is especially true for
plastic packages.
Figure 6
1054lfe
9
LT1054/LT1054L
U
TYPICAL APPLICATIONS N
Basic Voltage Inverter
100µF
FB/SHDN
OSC
CAP +
LT1054
GND
VREF
2µF
CAP –
–VOUT
100µF
OSC
CAP +
LT1054
GND
VREF
+
VOUT
V+
10µF
R2
CAP –
)
+
LT1054 • TAO2
R1
VOUT
0.002µF
)) )
|VOUT|
|VOUT|
R2 =
+1 =
+1 ,
1.21V
R1 VREF
– 40mV
2
VOUT
+
+
2µF
VIN
VIN
+
+
FB/SHDN V +
Basic Voltage Inverter/Regulator
100µF
LT1054 • TA03
REFER TO FIGURE 5
Negative Voltage Doubler
Positive Doubler
FB/SHDN V +
+
VOUT
+
+
100µF
OSC
CAP
LT1054
GND
VREF
VIN
CAP
2µF
–
–
+
VOUT
50mA
QX*
VOUT
100µF
VIN
1N4001 3.5V TO 15V
1N4001
–
RX*
+
+
+
FB/SHDN V +
OSC
CAP +
LT1054
GND
VREF
+
+
VIN
VIN = –3.5V TO –15V
VOUT = 2VIN + (LT1054 VOLTAGE LOSS) + (QX SATURATION VOLTAGE)
LT1054 • TAO4
*SEE FIGURE 3
2µF
10µF
100µF
VIN = 3.5V TO 15V
VOUT ≈ 2VIN – (VL + 2VDIODE)
VL = LT1054 VOLTAGE LOSS
CAP –
VOUT
LT1054 • TAO5
100mA Regulating Negative Doubler
VIN
3.5 TO 15V
+
2.2µF
FB/SHDN V +
FB/SHDN V +
+
10µF
OSC
CAP
LT1054 #1
GND
VREF
+
10µF
CAP –
1N4002
VOUT
SET
10µF
+
10µF
R1
40k
VOUT
0.002µF
+
100µF
VIN = 3.5 TO 15V
VOUT MAX ≈ –2VIN + [1054 VOLTAGE LOSS + 2(VDIODE)]
1N4002
)
)) )
+
10µF
1N4002
1N4002
R2
500k
HP5082-2810
+
OSC
CAP
LT1054 #2
GND
VREF
CAP –
20k
PIN 2
LT1054 #1
VOUT
10µF
1N4002
+
+
–VOUT
IOUT ≅ 100mA MAX
LT1054 • TAO6
+
|VOUT|
|VOUT|
R2 =
+1 =
+ 1 , REFER TO FIGURE 5
1.21V
R1 VREF
– 40mV
2
1054lfe
10
LT1054/LT1054L
U
TYPICAL APPLICATIONS N
Bipolar Supply Doubler
VIN
3.5V TO 15V
+
+
+
10µF
100µF
+VOUT
FB/SHDN V +
–
OSC
CAP +
LT1054
GND
VREF
+
10µF
CAP –
+
100µF
VOUT
+
10µF
–
100µF
VIN = 3.5V TO 15V
+VOUT ≈ 2VIN – (VL + 2VDIODE)
–VOUT ≈ –2VIN + (VL + 2VDIODE)
VL = LT1054 VOLTAGE LOSS
–VOUT
+
+
LT1054 • TAO7
= 1N4001
5V to ±12V Converter
VIN = 5V
+
5µF
FB/SHDN V
VOUT ≈ 12V
IOUT = 25mA
+
1N914
100µF
OSC
CAP
LT1054 #1
GND
VREF
10µF
CAP –
+
+
+
+
1N914
10µF
+
10µF
2N2219
VOUT
5µF
100µF
OSC
CAP +
LT1054 #2
GND
VREF
CAP –
+
+
1k
TO PIN 4
LT1054 #1
FB/SHDN V +
20k
VOUT
100µF
VOUT ≈ –12V
IOUT = 25mA
+
LT1054 • TAO8
Strain Gauge Bridge Signal Conditioner
5V
10k
INPUT TTL
OR CMOS
LOW FOR ON
+
10k
40Ω
2N2907
1
–
8
0.022µF
10k
ZERO
TRIM
2
100k
5k
A1
1/2 LT1013
6
3
100k
10k
5
350Ω
+
1µF
FB/SHDN V +
10µF
5k
GAIN
TRIM
301k
200k
+
10µF
OSC
CAP +
LT1054
GND
VREF
CAP –
–
1M
A2
1/2 LT1013
7
+
4
LT1054 • TAO9
5V
3k
2N2222
+ 100µF
A = 125 FOR 0V TO 3V OUT FROM FULL-SCALE
BRIDGE OUTPUT OF 24mV
TANTALUM
VOUT
1054lfe
11
LT1054/LT1054L
U
TYPICAL APPLICATIONS N
3.5V to 5V Regulator
20k
1
1N914
2
+
1N914
OSC
CAP +
LT1054
GND
VREF
+
10µF
CAP –
1µF
+
R1
20k
5µF
R2
125k
0.002µF
VOUT
+
R2
125k
7
LTC1044
3
6
4
5
+
FB/SHDN V +
1N914
8
100µF
1µF
3k
+
VIN
3.5V TO 5.5V
VOUT = 5V
–
VIN = 3.5V TO 5.5V
VOUT = 5V
IOUT(MAX) = 50mA
2N2219
1N914
LT1054 • TA10
1N5817
Regulating 200mA, 12V to – 5V Converter
5µF 12V
+
10Ω
1/2W
10µF
+
OSC
CAP +
LT1054 #1
GND
VREF
CAP –
)
HP5082-2810
FB/SHDN V +
FB/SHDN V +
R1
39.2k
+
10µF
R2
200k
VOUT
)) )
OSC
CAP +
LT1054 #2
GND
VREF
10Ω
1/2W
CAP –
0.002µF
VOUT
LT1054 • TA11
200µF
|VOUT|
|VOUT|
R2 =
+1 =
+1 ,
1.21V
R1 VREF
– 40mV
2
20k
VOUT = –5V
IOUT = 0mA to 200mA
+
REFER TO FIGURE 5
Digitally Programmable Negative Supply
15V
+
11
5µF
20k
10µF
OSC
CAP +
LT1054
GND
VREF
DIGITAL
INPUT
AD558
LT1004-2.5
2.5V
FB/SHDN V +
+
16
20k
14
13
12
LT1054 • TA12
CAP –
VOUT
VOUT = –VIN (PROGRAMMED)
100µF
+
1054lfe
12
LT1054/LT1054L
U
PACKAGE DESCRIPTION
J8 Package
8-Lead CERDIP (Narrow .300 Inch, Hermetic)
(Reference LTC DWG # 05-08-1110)
CORNER LEADS OPTION
(4 PLCS)
.023 – .045
(0.584 – 1.143)
HALF LEAD
OPTION
.045 – .068
(1.143 – 1.650)
FULL LEAD
OPTION
.005
(0.127)
MIN
.405
(10.287)
MAX
8
7
6
5
.025
(0.635)
RAD TYP
.220 – .310
(5.588 – 7.874)
1
.300 BSC
(7.62 BSC)
2
3
4
.200
(5.080)
MAX
.015 – .060
(0.381 – 1.524)
.008 – .018
(0.203 – 0.457)
0° – 15°
NOTE: LEAD DIMENSIONS APPLY TO SOLDER DIP/PLATE
OR TIN PLATE LEADS
.045 – .065
(1.143 – 1.651)
.014 – .026
(0.360 – 0.660)
.100
(2.54)
BSC
.125
3.175
MIN
J8 0801
OBSOLETE PACKAGE
1054lfe
13
LT1054/LT1054L
U
PACKAGE DESCRIPTION
N8 Package
8-Lead PDIP (Narrow .300 Inch)
(Reference LTC DWG # 05-08-1510)
.400*
(10.160)
MAX
8
7
6
5
1
2
3
4
.255 ± .015*
(6.477 ± 0.381)
.300 – .325
(7.620 – 8.255)
.065
(1.651)
TYP
.008 – .015
(0.203 – 0.381)
(
+.035
.325 –.015
8.255
+0.889
–0.381
.130 ± .005
(3.302 ± 0.127)
.045 – .065
(1.143 – 1.651)
)
.120
(3.048) .020
MIN (0.508)
MIN
.018 ± .003
.100
(2.54)
BSC
(0.457 ± 0.076)
N8 1002
NOTE:
1. DIMENSIONS ARE
INCHES
MILLIMETERS
*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .010 INCH (0.254mm)
S8 Package
8-Lead Plastic Small Outline (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1610)
.189 – .197
(4.801 – 5.004)
NOTE 3
.045 ±.005
.050 BSC
8
.245
MIN
7
6
5
.160 ±.005
.150 – .157
(3.810 – 3.988)
NOTE 3
.228 – .244
(5.791 – 6.197)
.030 ±.005
TYP
1
RECOMMENDED SOLDER PAD LAYOUT
.010 – .020
× 45°
(0.254 – 0.508)
.008 – .010
(0.203 – 0.254)
0°– 8° TYP
.016 – .050
(0.406 – 1.270)
NOTE:
1. DIMENSIONS IN
.053 – .069
(1.346 – 1.752)
.014 – .019
(0.355 – 0.483)
TYP
INCHES
(MILLIMETERS)
2. DRAWING NOT TO SCALE
3. THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .006" (0.15mm)
2
3
4
.004 – .010
(0.101 – 0.254)
.050
(1.270)
BSC
SO8 0303
1054lfe
14
LT1054/LT1054L
U
PACKAGE DESCRIPTION
SW Package
16-Lead Plastic Small Outline (Wide .300 Inch)
(Reference LTC DWG # 05-08-1620)
.050 BSC .045 ±.005
.030 ±.005
TYP
.398 – .413
(10.109 – 10.490)
NOTE 4
16
N
15
14
13
12
11 10
9
N
.325 ±.005
.420
MIN
.394 – .419
(10.007 – 10.643)
NOTE 3
1
2
3
N/2
N/2
RECOMMENDED SOLDER PAD LAYOUT
1
.005
(0.127)
RAD MIN
.009 – .013
(0.229 – 0.330)
.291 – .299
(7.391 – 7.595)
NOTE 4
.010 – .029 × 45°
(0.254 – 0.737)
3
4
5
6
7
.093 – .104
(2.362 – 2.642)
8
.037 – .045
(0.940 – 1.143)
0° – 8° TYP
NOTE 3
.016 – .050
(0.406 – 1.270)
NOTE:
1. DIMENSIONS IN
2
.050
(1.270)
BSC
.004 – .012
(0.102 – 0.305)
.014 – .019
(0.356 – 0.482)
TYP
INCHES
(MILLIMETERS)
2. DRAWING NOT TO SCALE
3. PIN 1 IDENT, NOTCH ON TOP AND CAVITIES ON THE BOTTOM OF PACKAGES ARE THE MANUFACTURING OPTIONS.
THE PART MAY BE SUPPLIED WITH OR WITHOUT ANY OF THE OPTIONS
4. THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .006" (0.15mm)
S16 (WIDE) 0502
1054lfe
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
15
LT1054/LT1054L
U
TYPICAL APPLICATIONS N
Negative Doubler with Regulator
Positive Doubler with Regulation
VIN
3.5V TO 15V
VIN = 5V
+
VOUT
8V
50mA
10µF
+
+
5.5k
10k
CAP
5V
–
–
2µF
OSC
CAP
LT1054
GND
VREF
+
OSC
CAP
LT1054
GND
VREF
10k
+
+
+
1N5817 0.03µF
100µF
FB/SHDN V +
2µF
FB/SHDN V +
10µF
CAP –
+
VOUT
10µF
R1, 20k
VOUT
+
50k
1N5817
1N4001
10k
R2
1M
100µF
0.002µF
1N4001
–VOUT
+
VIN = 3.5V TO 15V
VOUT(MAX) ≈ –2VIN + (VL + 2VDIODE)
VL = LT1054 VOLTAGE LOSS
LT1054 • TA13
0.1µF
)
100µF
+
2.5k
LT1006
)) )
|VOUT|
|VOUT|
R2 =
+1 =
+ 1 , REFER TO FIGURE 5
1.21V
R1 VREF
– 40mV
LT1054 • TA14
2
THE TYPICAL APPLICATIONS CIRCUITS WERE VERIFIED USING THE STANDARD LT1054. FOR S8 APPLICATIONS
ASSISTANCE IN ANY OF THE UNUSUAL APPLICATIONS CIRCUITS PLEASE CONSULT THE FACTORY
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PART NUMBER
DESCRIPTION
COMMENTS
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Switched-Capacitor Wide Input Range Voltage Converter
with Shutdown
Wide Input Voltage Range: 2V to 18V, ISD < 8µA, SO8
LTC1514/LTC1515
Step-Up/Step-Down Switched Capacitor DC/DC Converters
VIN: 2V to 10V, VOUT: 3.3V to 5V, IQ = 60µA, SO8
LT1611
150mA Output, 1.4mHz Micropower Inverting Switching Regulator
VIN: 0.9V to 10V, VOUT: ±34V ThinSOT
LT1614
250mA Output, 600kHz Micropower Inverting Switching Regulator
VIN: 0.9V to 6V, VOUT: ±30V, IQ = 1mA, MS8, SO8
LTC1911
250mA, 1.5MHz Inductorless Step-Down DC/DC Converter
VIN: 2.7V to 5.5V, VOUT: 1.5V/1.8V, IQ = 180µA, MS8
LTC3250/LTC3250-1.2/ Inductorless Step-Down DC/DC Converter
LTC3250-1.5
VIN: 3.1V to 5.5V, VOUT: 1.2V, 1.5V, IQ = 35µA, ThinSOT™
LTC3251
500mA Spread Spectrum Inductorless Step-Down DC/DC Converter VIN: 2.7V to 5.5V, VOUT: 0.9V to 1.6V, 1.2V, 1.5V,
IQ = 9µA, MS10E
LTC3252
Dual 250mA, Spread Spectrum Inductorless Step-Down
DC/DC Converter
VIN: 2.7V to 5.5V, VOUT: 0.9V to 1.6V, IQ = 50µA, DFN12
ThinSOT is a trademark of Linear Technology Corporation.
1054lfe
16
Linear Technology Corporation
LT/TP 0104 1K REV E • PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507
●
www.linear.com
 LINEAR TECHNOLOGY CORPORATION 1987