IC61S6432 Document Title 64K x 32 Pipelined Sync. SRAM Revision History Revision No History Draft Date Remark 0A Initial Draft September 13,2001 The attached datasheets are provided by ICSI. Integrated Circuit Solution Inc reserve the right to change the specifications and products. ICSI will answer to your questions about device. If you have any questions, please contact the ICSI offices. Integrated Circuit Solution Inc. SSR016-0A 09/13/2001 1 IC61S6432 64K x 32 SYNCHRONOUS PIPELINE STATIC RAM FEATURES DESCRIPTION • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and control • Pentium™ or linear burst sequence control using MODE input • Three chip enables for simple depth expansion and address pipelining • Common data inputs and data outputs • Power-down control by ZZ input • JEDEC 100-Pin LQFP and PQFP package • Single +3.3V power supply • Two Clock enables and one Clock disable to eliminate multiple bank bus contention • Control pins mode upon power-up: – MODE in interleave burst mode – ZZ in normal operation mode These control pins can be connected to GNDQ or VCCQ to alter their power-up state • Industrial temperature available The ICSI IC61S6432 is a high-speed, low-power synchronous static RAM designed to provide a burstable, high-performance, secondary cache for the Pentium™, 680X0™, and PowerPC™ microprocessors. It is organized as 65,536 words by 32 bits, fabricated with ICSI's advanced CMOS technology. The device integrates a 2-bit burst counter, high-speed SRAM core, and high-drive capability outputs into a single monolithic circuit. All synchronous inputs pass through registers controlled by a positive-edge-triggered single clock input. Write cycles are internally self-timed and are initiated by the rising edge of the clock input. Write cycles can be from one to four bytes wide as controlled by the write control inputs. Separate byte enables allow individual bytes to be written. BW1 controls DQ1-DQ8, BW2 controls DQ9-DQ16, BW3 controls DQ17-DQ24, BW4 controls DQ25-DQ32, conditioned by BWE being LOW. A LOW on GW input would cause all bytes to be written. Bursts can be initiated with either ADSP (Address Status Processor) or ADSC (Address Status Cache Controller) input pins. Subsequent burst addresses can be generated internally by the IC61S6432 and controlled by the ADV (burst address advance) input pin. Asynchronous signals include output enable (OE), sleep mode input (ZZ), clock (CLK) and burst mode input (MODE). A HIGH input on the ZZ pin puts the SRAM in the powerdown state. When ZZ is pulled LOW (or no connect), the SRAM normally operates after three cycles of the wake-up period. A LOW input, i.e., GNDQ, on MODE pin selects LINEAR Burst. A VCCQ (or no connect) on MODE pin selects INTERLEAVED Burst. FAST ACCESS TIME Symbol Parameter -200 (1) -166 -133 -117 -5 -6 -7 -8 Unit tKQ CLK Access Time 4 5 5 5 5 6 7 8 ns tKC Cycle Time 5 6 7.5 8.5 10 12 13 15 ns — Frequency 200 166 133 117 100 83 75 66 MHz Note: 1. ADVANCE INFORMATION ONLY. ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which may appear in this publication. © Copyright 2000, Integrated Circuit Solution Inc. 2 Integrated Circuit Solution Inc. SSR016-0A 09/13/2001 IC61S6432 BLOCK DIAGRAM MODE Q0 CLK CLK A0’ A0 BINARY COUNTER ADSC ADSP A15-A0 Q1 CE ADV A1’ A1 64K x 32 MEMORY ARRAY CLR 16 D Q 14 16 ADDRESS REGISTER CE CLK 32 GW BWE BW4 D 32 Q DQ32-DQ25 BYTE WRITE REGISTERS CLK D BW3 Q DQ24-DQ17 BYTE WRITE REGISTERS CLK D BW2 Q DQ16-DQ9 BYTE WRITE REGISTERS CLK D BW1 Q DQ8-DQ1 BYTE WRITE REGISTERS CLK CE1 4 Q CE2 D CE3 ENABLE REGISTER INPUT REGISTERS CLK 32 OUTPUT REGISTERS CLK DATA[32:1] OE CE CLK D Q ENABLE DELAY REGISTER CLK OE Integrated Circuit Solution Inc. SSR016-0A 09/13/2001 3 IC61S6432 PIN CONFIGURATION A6 A7 CE1 CE2 BW4 BW3 BW2 BW1 CE3 VCC GND CLK GW BWE OE ADSC ADSP ADV A8 A9 100-Pin LQFP and PQFP (Top View) 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 1 79 2 78 3 77 4 76 5 75 6 74 7 73 8 72 9 71 10 70 11 69 12 68 13 67 14 66 15 65 16 64 17 63 18 62 19 61 20 60 21 59 22 58 23 57 24 56 25 55 26 54 27 53 28 52 29 51 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 NC DQ16 DQ15 VCCQ GNDQ DQ14 DQ13 DQ12 DQ11 GNDQ VCCQ DQ10 DQ9 GND NC VCC ZZ DQ8 DQ7 VCCQ GNDQ DQ6 DQ5 DQ4 DQ3 GNDQ VCCQ DQ2 DQ1 NC MODE A5 A4 A3 A2 A1 A0 NC NC GND VCC NC NC A10 A11 A12 A13 A14 A15 NC NC DQ17 DQ18 VCCQ GNDQ DQ19 DQ20 DQ21 DQ22 GNDQ VCCQ DQ23 DQ24 VCCQ VCC NC GND DQ25 DQ26 VCCQ GNDQ DQ27 DQ28 DQ29 DQ30 GNDQ VCCQ DQ31 DQ32 NC PIN DESCRIPTIONS 4 A0-A15 Address Inputs OE Output Enable CLK Clock DQ1-DQ32 Data Input/Output ADSP Processor Address Status ZZ Sleep Mode ADSC Controller Address Status MODE Burst Sequence Mode ADV Burst Address Advance VCC +3.3V Power Supply BW1-BW4 Synchronous Byte Write Enable GND Ground BWE Byte Write Enable VCCQ Isolated Output Buffer Supply: +3.3V GW Global Write Enable GNDQ Isolated Output Buffer Ground CE1, CE2, CE3 Synchronous Chip Enable NC No Connect Integrated Circuit Solution Inc. SSR016-0A 09/13/2001 IC61S6432 TRUTH TABLE Operation Address Used CE1 CE2 CE3 Deselected, Power-down Deselected, Power-down Deselected, Power-down Deselected, Power-down Deselected, Power-down Read Cycle, Begin Burst Read Cycle, Begin Burst Write Cycle, Begin Burst Read Cycle, Begin Burst Read Cycle, Begin Burst Read Cycle, Continue Burst Read Cycle, Continue Burst Read Cycle, Continue Burst Read Cycle, Continue Burst Write Cycle, Continue Burst Write Cycle, Continue Burst Read Cycle, Suspend Burst Read Cycle, Suspend Burst Read Cycle, Suspend Burst Read Cycle, Suspend Burst Write Cycle, Suspend Burst Write Cycle, Suspend Burst None None None None None External External External External External Next Next Next Next Next Next Current Current Current Current Current Current H L L L L L L L L L X X H H X H X X H H X H X L X L X H H H H H X X X X X X X X X X X X X X H X H L L L L L X X X X X X X X X X X X ADSP ADSC X L L H H L L H H H H H X X H X H H X X H X L X X L L X X L L L H H H H H H H H H H H H ADV WRITE X X X X X X X X X X L L L L L L H H H H H H X X X X X X X L H H H H H H L L H H H H L L OE DQ X X X X X L H X L H L H L H X X L H L H X X High-Z High-Z High-Z High-Z High-Z Q High-Z D Q High-Z Q High-Z Q High-Z D D Q High-Z Q High-Z D D Notes: 1. All inputs except OE must meet setup and hold times for the Low-to-High transition of clock (CLK). 2. Wait states are inserted by suspending burst. 3. "X" means don't care. WRITE=L means any one or more byte write enable signals (BW1-BW4) and BWE are LOW or GW is LOW. WRITE=H means all byte write enable signals are HIGH. 4. For a Write operation following a Read operation, OE must be HIGH before the input data required setup time and held HIGH throughout the input data hold time. 5. ADSP LOW always initiates an internal READ at the Low-to-High edge of clock. A WRITE is performed by setting one or more byte write enable signals and BWE LOW or GW LOW for the subsequent L-H edge of clock. PARTIAL TRUTH TABLE Function READ READ WRITE Byte 1 WRITE All Bytes WRITE All Bytes GW BWE BW1 BW2 H H H X L H X L L X X H L L X X H H L X Integrated Circuit Solution Inc. SSR016-0A 09/13/2001 BW3 BW4 X H H L X X H H L X 5 IC61S6432 INTERLEAVED BURST ADDRESS TABLE (MODE = VCCQ or No Connect) External Address A1 A0 1st Burst Address A1 A0 2nd Burst Address A1 A0 3rd Burst Address A1 A0 00 01 10 11 01 00 11 10 10 11 00 01 11 10 01 00 LINEAR BURST ADDRESS TABLE (MODE = GNDQ) 0,0 A1’, A0’ = 1,1 0,1 1,0 ABSOLUTE MAXIMUM RATINGS(1,2,3) Symbol TBIAS TSTG PD IOUT VIN, VOUT VIN Parameter Temperature Under Bias Storage Temperature Power Dissipation Output Current (per I/O) Voltage Relative to GND for I/O Pins Voltage Relative to GND for for Address and Control Inputs Value –10 to +85 –55 to +150 1.8 100 –0.5 to VCCQ + 0.3 –0.5 to 5.5 Unit °C °C W mA V V Notes: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. This device contains circuity to protect the inputs against damage due to high static voltages or electric fields; however, precautions may be taken to avoid application of any voltage higher than maximum rated voltages to this high-impedance circuit. 3. This device contains circuitry that will ensure the output devices are in High-Z at power up. OPERATING RANGE Range Commercial Industrial 6 Ambient Temperature 0°C to +70°C –40°C to +85°C VCC 3.3V +10%, –5% 3.3V +10%, –5% Integrated Circuit Solution Inc. SSR016-0A 09/13/2001 IC61S6432 DC ELECTRICAL CHARACTERISTICS(1,2) (Over Operating Range) Symbol Parameter Test Conditions Min. Max. Unit VOH Output HIGH Voltage IOH = –5.0 mA 2.4 — V VOL Output LOW Voltage IOL = 5.0 mA — 0.4 V VIH Input HIGH Voltage 2.0 VCCQ + 0.3 V VIL Input LOW Voltage –0.3 0.8 V ILI Input Leakage Current GND ≤ VIN ≤ VCCQ(2) Com. Ind. –5 –10 5 10 µA ILO Output Leakage Current GND ≤ VOUT ≤ VCCQ, OE = VIH Com. Ind. –5 –10 5 10 µA Notes: 1. MODE pin have an internal pull-up. ZZ pin has an internal pull-down. These pins may be a No Connect, tied to GND,or tied to VCCQ. 2. MODE pin should be tied to Vcc or GND. They exhibit ±30 µA maximum leakage current when tied to ≤ GND + 0.2V or ≥ Vcc – 0.2V. POWER SUPPLY CHARACTERISTICS (Operating Range) -200(1) Min. Max. -166 Min. Max. -133 Min. Max. -117 Min. Max. Symbol Parameter TestConditions Unit ICC ACOperating SupplyCurrent DeviceSelected, All Inputs = VIL or VIH OE = VIH, Cycle Time ≥ tKC min. Com. Ind. — — 400 — — — 215 — — — 205 — — — 195 205 mA ISB StandbyCurrent DeviceDeselected, VCC = Max., CLK Cycle Time ≥ tKC min. Com. Ind. — — 100 — — — 70 — — — 60 — — — 50 60 mA IZZ Power-Down ModeCurrent ZZ = VCCQ, CLK Running All Inputs ≤ GND + 0.2V or ≥ VCC – 0.2V Com. Ind. — — 5 — — — 5 — — — 5 — — — 5 10 mA Note: 1. ADVANCE INFORMATION ONLY. -5 Min. Max. -6 Min. Max. -7 Min. Max. -8 Min. Max. Unit Symbol Parameter Test Conditions ICC ACOperating SupplyCurrent DeviceSelected, All Inputs = VIL or VIH OE = VIH, Cycle Time ≥ tKC min. Com. Ind. — — 175 185 — — 165 175 — — 150 160 — — 140 150 mA ISB StandbyCurrent DeviceDeselected, VCC = Max., CLK Cycle Time ≥ tKC min. Com. Ind. — — 25 35 — — 25 35 — — 25 35 — — 25 35 mA IZZ Power-Down ModeCurrent ZZ = VCCQ, CLK Running All Inputs ≤ GND + 0.2V or ≥ VCC – 0.2V Com. Ind. — — 5 10 — — 5 10 — — 5 10 — — 5 10 mA Integrated Circuit Solution Inc. SSR016-0A 09/13/2001 7 IC61S6432 CAPACITANCE(1,2) Symbol Parameter CIN Input Capacitance COUT Input/Output Capacitance Conditions Max. Unit VIN = 0V 6 pF VOUT = 0V 8 pF Notes: 1. Tested initially and after any design or process changes that may affect these parameters. 2. Test conditions: TA = 25°C, f = 1 MHz, Vcc = 3.3V. AC TEST CONDITIONS Parameter Input Pulse Level Input Rise and Fall Times Input and Output Timing and Reference Level Output Load Unit 0V to 3.0V 1.5 ns 1.5V See Figures 1 and 2 AC TEST LOADS 317 Ω 3.3V ZO = 50Ω OUTPUT Output Buffer 30 pF 50Ω 1.5V Figure 1 8 5 pF Including jig and scope 351 Ω Figure 2 Integrated Circuit Solution Inc. SSR016-0A 09/13/2001 IC61S6432 READ CYCLE SWITCHING CHARACTERISTICS (Over Operating Range) Symbol Parameter tKC Cycle Time tKH -200 (1) Min. Max. -166 Min. Max. -133 Min. Max. -117 Min. Max Unit 5 — 6 — 7.5 — 8.5 — ns Clock High Time 1.6 — 2.4 — 2.8 — 3 — ns tKL Clock Low Time 1.6 — 2.4 — 2.8 — 3 — ns tKQ Clock Access Time — 4 — 5 — 5 — 5 ns tKQX(2) Clock High to Output Invalid 1 — 1.5 — 1.5 — 1.5 — ns (2,3) Clock High to Output Low-Z 0 — 0 — 0 — 0 — ns (2,3) tKQHZ Clock High to Output High-Z 1 3.5 1.5 5 1.5 5 1.5 6 ns tOEQ Output Enable to Output Valid — 3.5 — 5 — 5 — 5 ns tKQLZ tOEQX(2) Output Disable to Output Invalid 0 — 0 — 0 — 0 — ns (2,3) Output Enable to Output Low-Z 0 — 0 — 0 — 0 — ns (2,3) tOEHZ Output Disable to Output High-Z — 3 — 3 — 3 — 4 ns tAS Address Setup Time 2 — 2.5 — 2.5 — 2.5 — ns tSS Address Status Setup Time 2 — 2.5 — 2.5 — 2.5 — ns tWS Write Setup Time 2 — 2.5 — 2.5 — 2.5 — ns tCES Chip Enable Setup Time 2 — 2.5 — 2.5 — 2.5 — ns tAVS Address Advance Setup Time 2 — 2.5 — 2.5 — 2.5 — ns tAH Address Hold Time 0.5 — 0.5 — 0.5 — 0.5 — ns tSH Address Status Hold Time 0.5 — 0.5 — 0.5 — 0.5 — ns tWH Write Hold Time 0.5 — 0.5 — 0.5 — 0.5 — ns tCEH Chip Enable Hold Time 0.5 — 0.5 — 0.5 — 0.5 — ns Address Advance Hold Time 0.5 — 0.5 — 0.5 — 0.5 — ns Configuration Setup 25 — 25 — 30 — 35 — ns tOELZ tAVH (4) tCFG Notes: 1. ADVANCE INFORMATION ONLY. 2. Guaranteed but not 100% tested. This parameter is periodically sampled. 3. Tested with load in Figure 2. 4. Configuration signal MODE is static and must not change during normal operation. Integrated Circuit Solution Inc. SSR016-0A 09/13/2001 9 IC61S6432 READ CYCLE SWITCHING CHARACTERISTICS (Over Operating Range) (Continued) -5 -6 -7 -8 Symbol Parameter Min. Max. Min. Max. Min. Max. Min. Max Unit tKC Cycle Time 10 — 12 — 13 — 15 — ns tKH Clock High Time 3.5 — 4 — 6 — 6 — ns tKL Clock Low Time 3.5 — 4 — 6 — 6 — ns tKQ Clock Access Time — 5 — 6 — 7 — 8 ns tKQX(1) Clock High to Output Invalid 1.5 — 1.5 — 2 — 2 — ns (1,2) Clock High to Output Low-Z 0 — 0 — 0 — 0 — ns (1,2) tKQHZ Clock High to Output High-Z 1.5 6 1.5 6 2 6 2 6 ns tOEQ Output Enable to Output Valid — 5 — 6 — 6 — 6 ns tKQLZ tOEQX(1) Output Disable to Output Invalid 0 — 0 — 0 — 0 — ns (1,2) Output Enable to Output Low-Z 0 — 0 — 0 — 0 — ns (1,2) tOEHZ Output Disable to Output High-Z — 4 — 5 — 6 — 6 ns tAS Address Setup Time 2.5 — 2.5 — 2.5 — 2.5 — ns tSS Address Status Setup Time 2.5 — 2.5 — 2.5 — 2.5 — ns tWS Write Setup Time 2.5 — 2.5 — 2.5 — 2.5 — ns tCES Chip Enable Setup Time 2.5 — 2.5 — 2.5 — 2.5 — ns tAVS Address Advance Setup Time 2.5 — 2.5 — 2.5 — 2.5 — ns tAH Address Hold Time 0.5 — 0.5 — 0.5 — 0.5 — ns tSH Address Status Hold Time 0.5 — 0.5 — 0.5 — 0.5 — ns tWH Write Hold Time 0.5 — 0.5 — 0.5 — 0.5 — ns tCEH Chip Enable Hold Time 0.5 — 0.5 — 0.5 — 0.5 — ns Address Advance Hold Time 0.5 — 0.5 — 0.5 — 0.5 — ns Configuration Setup 35 — 45 — 66.7 — 80 — ns tOELZ tAVH (3) tCFG Notes: 1. Guaranteed but not 100% tested. This parameter is periodically sampled. 2. Tested with load in Figure 2. 3. Configuration signal MODE is static and must not change during normal operation. 10 Integrated Circuit Solution Inc. SSR016-0A 09/13/2001 IC61S6432 READ CYCLE TIMING: PIPELINE tKC CLK tSS tSH tKH tKL ADSP is blocked by CE1 inactive ADSP tSS ADSC initiate read tSH ADSC tAVH tAVS Suspend Burst ADV tAS A15-A0 tAH RD1 RD3 RD2 tWS tWH tWS tWH GW BWE BW4-BW1 tCES tCEH tCES tCEH tCES tCEH CE1 Masks ADSP CE1 Unselected with CE2 CE2 and CE3 only sampled with ADSP or ADSC CE2 CE3 tOEHZ tOEQ OE DATAOUT tKQX tOEQX tOELZ High-Z 1a 2a 2b 2c 2d tKQLZ 3a tKQHZ tKQ DATAIN High-Z Pipelined Read Single Read Integrated Circuit Solution Inc. SSR016-0A 09/13/2001 Burst Read Unselected 11 IC61S6432 WRITE CYCLE SWITCHING CHARACTERISTICS (Over Operating Range) Symbol Parameter tKC Cycle Time tKH -200 (1) Min. Max. -166 Min. Max. -133 -117 Min. Max. Min. Max. Unit 5 — 6 — 7.5 — 8.5 — ns Clock High Time 1.6 — 2.4 — 2.8 — 3 — ns tKL Clock Low Time 1.6 — 2.4 — 2.8 — 3 — ns tAS Address Setup Time 2 — 2.5 — 2.5 — 2.5 — ns tSS Address Status Setup Time 2 — 2.5 — 2.5 — 2.5 — ns tWS Write Setup Time 2 — 2.5 — 2.5 — 2.5 — ns tDS Data In Setup Time 2 — 2.5 — 2.5 — 2.5 — ns tCES Chip Enable Setup Time 2 — 2.5 — 2.5 — 2.5 — ns tAVS Address Advance Setup Time 2 — 2.5 — 2.5 — 2.5 — ns tAH Address Hold Time 0.5 — 0.5 — 0.5 — 0.5 — ns tSH Address Status Hold Time 0.5 — 0.5 — 0.5 — 0.5 — ns tDH Data In Hold Time 0.5 — 0.5 — 0.5 — 0.5 — ns tWH Write Hold Time 0.5 — 0.5 — 0.5 — 0.5 — ns tCEH Chip Enable Hold Time 0.5 — 0.5 — 0.5 — 0.5 — ns tAVH Address Advance Hold Time 0.5 — 0.5 — 0.5 — 0.5 — ns tCFG(2) Configuration Setup 25 — 25 — 30 — 35 — ns Symbol Parameter tKC Cycle Time 10 — 12 — 13 — 15 — ns tKH Clock High Time 3.5 — 4 — 6 — 6 — ns tKL Clock Low Time 3.5 — 4 — 6 — 6 — ns tAS Address Setup Time 2.5 — 2.5 — 2.5 — 2.5 — ns tSS Address Status Setup Time 2.5 — 2.5 — 2.5 — 2.5 — ns tWS Write Setup Time 2.5 — 2.5 — 2.5 — 2.5 — ns tDS Data In Setup Time 2.5 — 2.5 — 2.5 — 2.5 — ns tCES Chip Enable Setup Time 2.5 — 2.5 — 2.5 — 2.5 — ns tAVS Address Advance Setup Time 2.5 — 2.5 — 2.5 — 2.5 — ns tAH Address Hold Time 0.5 — 0.5 — 0.5 — 0.5 — ns tSH Address Status Hold Time 0.5 — 0.5 — 0.5 — 0.5 — ns tDH Data In Hold Time 0.5 — 0.5 — 0.5 — 0.5 — ns tWH Write Hold Time 0.5 — 0.5 — 0.5 — 0.5 — ns tCEH Chip Enable Hold Time 0.5 — 0.5 — 0.5 — 0.5 — ns tAVH Address Advance Hold Time 0.5 — 0.5 — 0.5 — 0.5 — ns Configuration Setup 35 — 45 — 52 — 60 — ns (2) tCFG -5 Min. Max. -6 Min. Max. -7 -8 Min. Max. Min. Max. Unit Note: 1. ADVANCE INFORMATION ONLY. 2. Configuration signal MODE is static and must not change during normal operation. 12 Integrated Circuit Solution Inc. SSR016-0A 09/13/2001 IC61S6432 WRITE CYCLE TIMING tKC CLK tSS tSH tKH tKL ADSP is blocked by CE1 inactive ADSP ADSC initiate Write ADSC ADV must be inactive for ADSP Write tAVS tAVH ADV tAS A15-A0 tAH WR1 WR2 tWS tWH tWS tWH tWS tWH WR3 GW BWE BW4-BW1 WR1 tCES tCEH tCES tCEH tCES tCEH tWS tWH WR2 WR3 CE1 Masks ADSP CE1 Unselected with CE2 CE2 and CE3 only sampled with ADSP or ADSC CE2 CE3 OE DATAOUT High-Z tDS DATAIN High-Z Single Write Integrated Circuit Solution Inc. SSR016-0A 09/13/2001 tDH 1a BW4-BW1 only are applied to first cycle of WR2 2a 2b 2c 2d Burst Write 3a Write Unselected 13 IC61S6432 READ/WRITE CYCLE SWITCHING CHARACTERISTICS (Over Operating Range) Symbol Parameter tKC Cycle Time tKH tKL tKQ (2) tKQX (2,3) -200 (1) Min. Max. -166 Min. Max. -133 -117 Min. Max. Min. Max. Unit 5 — 6 — 7.5 — 8.5 — ns Clock High Time 1.6 — 2.4 — 2.8 — 3 — ns Clock Low Time 1.6 — 2.4 — 2.8 — 3 — ns Clock Access Time — 4 — 5 — 5 — 5 ns Clock High to Output Invalid 1 — 1.5 — 1.5 — 1.5 — ns — 0 — 0 — 0 — ns tKQLZ Clock High to Output Low-Z tKQHZ(2,3) Clock High to Output High-Z 1 3.5 1.5 5 1.5 5 1.5 6 ns tOEQ Output Enable to Output Valid — 3.5 — 5 — 5 — 5 ns (2) Output Disable to Output Invalid 0 — 0 — 0 — 0 — ns (2,3) tOELZ Output Enable to Output Low-Z 0 — 0 — 0 — 0 — ns tOEHZ(2,3) Output Disable to Output High-Z — 3 — 3 — 3 — 4 ns tAS Address Setup Time 2 — 2.5 — 2.5 — 2.5 — ns tSS Address Status Setup Time 2 — 2.5 — 2.5 — 2.5 — ns tWS Write Setup Time 2 — 2.5 — 2.5 — 2.5 — ns tCES Chip Enable Setup Time 2 — 2.5 — 2.5 — 2.5 — ns tAH Address Hold Time 0.5 — 0.5 — 0.5 — 0.5 — ns tSH Address Status Hold Time 0.5 — 0.5 — 0.5 — 0.5 — ns tWH Write Hold Time 0.5 — 0.5 — 0.5 — 0.5 — ns Chip Enable Hold Time 0.5 — 0.5 — 0.5 — 0.5 — ns Configuration Setup 25 — 25 — 30 — 35 — ns tOEQX tCEH (4) tCFG Notes: 1. ADVANCE INFORMATION ONLY. 2. Guaranteed but not 100% tested. This parameter is periodically sampled. 3. Tested with load in Figure 2. 4. Configuration signal MODE is static and must not change during normal operation. 14 Integrated Circuit Solution Inc. SSR016-0A 09/13/2001 IC61S6432 READ/WRITE CYCLE SWITCHING CHARACTERISTICS (Over Operating Range) (Continued) -5 Min. Max. -6 Min. Max. -7 -8 Min. Max. Min. Max. Symbol Parameter tKC Cycle Time 10 — 12 — 13 — 15 — ns tKH Clock High Time 3.5 — 4 — 6 — 6 — ns tKL Clock Low Time 3.5 — 4 — 6 — 6 — ns tKQ Clock Access Time — 5 — 6 — 7 — 8 ns tKQX(1) Unit Clock High to Output Invalid 1.5 — 1.5 — 2 — 2 — ns (1,2) Clock High to Output Low-Z 0 — 0 — 0 — 0 — ns (1,2) tKQHZ Clock High to Output High-Z 1.5 6 1.5 6 2 6 2 6 ns tOEQ Output Enable to Output Valid — 5 — 6 — 6 — 6 ns tOEQX(1) Output Disable to Output Invalid 0 — 0 — 0 — 0 — ns tOELZ(1,2) Output Enable to Output Low-Z 0 — 0 — 0 — 0 — ns tOEHZ Output Disable to Output High-Z — 4 — 5 — 6 — 6 ns tAS Address Setup Time 2.5 — 2.5 — 2.5 — 2.5 — ns tSS Address Status Setup Time 2.5 — 2.5 — 2.5 — 2.5 — ns tWS Write Setup Time 2.5 — 2.5 — 2.5 — 2.5 — ns tCES Chip Enable Setup Time 2.5 — 2.5 — 2.5 — 2.5 — ns tAH Address Hold Time 0.5 — 0.5 — 0.5 — 0.5 — ns tSH Address Status Hold Time 0.5 — 0.5 — 0.5 — 0.5 — ns tWH Write Hold Time 0.5 — 0.5 — 0.5 — 0.5 — ns Chip Enable Hold Time 0.5 — 0.5 — 0.5 — 0.5 — ns Configuration Setup 35 — 45 — 52 — 60 — ns tKQLZ (1,2) tCEH (3) tCFG Notes: 1. Guaranteed but not 100% tested. This parameter is periodically sampled. 2. Tested with load in Figure 2. 3. Configuration signal MODE is static and must not change during normal operation. Integrated Circuit Solution Inc. SSR016-0A 09/13/2001 15 IC61S6432 READ/WRITE CYCLE TIMING: PIPELINE tKC CLK tSS tSH tKH tKL ADSP is blocked by CE1 inactive ADSP tSS tSH ADSC ADV tAS A15-A0 tAH RD1 WR1 tWS tWH tWS tWH RD2 RD3 GW BWE tWS tWH WR1 BW4-BW1 tCES tCEH tCES tCEH tCES tCEH CE1 Masks ADSP CE1 CE2 and CE3 only sampled with ADSP or ADSC CE2 Unselected with CE3 CE3 tOEHZ tOEQ OE DATAOUT High-Z 2a 1a tKQLZ tKQ DATAIN tKQX tOEQX tOELZ 2c 2d tKQHZ tKQX tKQHZ High-Z 1a tDS Single Read 16 2b tDH Single Write Burst Read Unselected Integrated Circuit Solution Inc. SSR016-0A 09/13/2001 IC61S6432 SNOOZE AND RECOVERY CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range) Symbol Parameter tKC Cycle Time tKH tKL -200 (2) Min. Max. -166 Min. Max -133 -117 Min. Max. Min. Max. Unit 5 — 6 — 7.5 — 8.5 — ns Clock High Time 1.6 — 2.4 — 2.8 — 3 — ns Clock Low Time 1.6 — 2.4 — 2.8 — 3 — ns Clock Access Time — 4 — 5 — 5 — 5 ns Clock High to Output Invalid 1 — 1.5 — 1.5 — 1.5 — ns tKQLZ Clock High to Output Low-Z 0 — 0 — 0 — 0 — ns tKQHZ(3,4) Clock High to Output High-Z 1 3.5 1.5 5 1.5 5 1.5 6 ns tOEQ tKQ (3) tKQX (3,4) Output Enable to Output Valid — 3.5 — 5 — 5 — 5 ns (3) Output Disable to Output Invalid 0 — 0 — 0 — 0 — ns (3,4) tOELZ Output Enable to Output Low-Z 0 — 0 — 0 — 0 — ns tOEHZ(3,4) Output Disable to Output High-Z — 3 — 3 — 3 — 4 ns tAS Address Setup Time 2 — 2.5 — 2.5 — 2.5 — ns tSS Address Status Setup Time 2 — 2.5 — 2.5 — 2.5 — ns tCES Chip Enable Setup Time 2 — 2.5 — 2.5 — 2.5 — ns tAH Address Hold Time 2 — 2.5 — 2.5 — 2.5 — ns tSH Address Status Hold Time 2 — 2.5 — 2.5 — 2.5 — ns Chip Enable Hold Time 2 — 2.5 — 2.5 — 2.5 — ns tZZS ZZ Standby — 8 2 — 2 — 2 — cyc tZZREC(6) ZZ Recovery 8 — 2 — 2 — 2 — cyc tOEQX tCEH (5) Notes: 1. Configuration signal MODE is static and must not change during normal operation. 2. ADVANCE INFORMATION ONLY. 3. Guaranteed but not 100% tested. This parameter is periodically sampled. 4. Tested with load in Figure 2. 5. The assertion of ZZ allows the SRAM to enter a lower power state than when deselected within the time specified. Data retention is guaranteed when ZZ is asserted and clock remains active. 6. ADSC and ADSP must not be asserted for at least two cycles after leaving ZZ state. Integrated Circuit Solution Inc. SSR016-0A 09/13/2001 17 IC61S6432 SNOOZE AND RECOVERY CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range) (Continued) -5 Min. Max. -6 Min. Max. -7 -8 Min. Max. Min. Max. Symbol Parameter tKC Cycle Time 10 — 12 — 13 — 15 — ns tKH Clock High Time 3.5 — 4 — 6 — 6 — ns tKL Clock Low Time 3.5 — 4 — 6 — 6 — ns Clock Access Time — 5 — 6 — 7 — 8 ns tKQ (2) tKQX Unit Clock High to Output Invalid 1.5 — 1.5 — 2 — 2 — ns (2,3) Clock High to Output Low-Z 0 — 0 — 0 — 0 — ns (2,3) tKQHZ Clock High to Output High-Z 1.5 6 1.5 6 2 6 2 6 ns tOEQ Output Enable to Output Valid — 5 — 6 — 6 — 6 ns tKQLZ tOEQX(2) Output Disable to Output Invalid 0 — 0 — 0 — 0 — ns (2,3) Output Enable to Output Low-Z 0 — 0 — 0 — 0 — ns (2,3) tOEHZ Output Disable to Output High-Z — 4 — 5 — 6 — 6 ns tAS Address Setup Time 2.5 — 2.5 — 2.5 — 2.5 — ns tSS Address Status Setup Time 2.5 — 2.5 — 2.5 — 2.5 — ns tCES Chip Enable Setup Time 2.5 — 2.5 — 2.5 — 2.5 — ns tAH Address Hold Time 2.5 — 2.5 — 2.5 — 2.5 — ns tSH Address Status Hold Time 2.5 — 2.5 — 2.5 — 2.5 — ns Chip Enable Hold Time 2.5 — 2.5 — 2.5 — 2.5 — ns ZZ Standby 2 — 2 — 2 — 2 — cyc ZZ Recovery 2 — 2 — 2 — 2 — cyc tOELZ tCEH (4) tZZS (5) tZZREC Notes: 1. Configuration signal MODE is static and must not change during normal operation. 2. Guaranteed but not 100% tested. This parameter is periodically sampled. 3. Tested with load in Figure 2. 4. The assertion of ZZ allows the SRAM to enter a lower power state than when deselected within the time specified. Data retention is guaranteed when ZZ is asserted and clock remains active. 5. ADSC and ADSP must not be asserted for at least two cycles after leaving ZZ state. 18 Integrated Circuit Solution Inc. SSR016-0A 09/13/2001 IC61S6432 SNOOZE AND RECOVERY CYCLE TIMING tKC CLK tSS tSH tAS tAH tKH tKL ADSP ADSC ADV A15-A0 RD1 RD2 GW BWE BW4-BW1 tCES tCEH tCES tCEH tCES tCEH CE1 CE2 CE3 tOEHZ tOEQ OE tOEQX tOELZ DATAOUT High-Z 1a tKQLZ tKQ DATAIN tKQX tKQHZ High-Z tZZS tZZREC ZZ Single Read Integrated Circuit Solution Inc. SSR016-0A 09/13/2001 Snooze with Data Retention Read 19 IC61S6432 ORDERING INFORMATION Commercial Range: 0°C to +70°C Frequency (MHz) Order Part Number Package 200 IC61S6432-200TQ 14*20*1.4mm LQFP IC61S6432-200PQ 14*20*2.7mm PQFP 166 IC61S6432-166TQ 14*20*1.4mm LQFP IC61S6432-166PQ 14*20*2.7mm PQFP 133 IC61S6432-133TQ 14*20*1.4mm LQFP IC61S6432-133PQ 14*20*2.7mm PQFP 117 IC61S6432-117TQ 14*20*1.4mm LQFP IC61S6432-117PQ 14*20*2.7mm PQFP 100 IC61S6432-5TQ IC61S6432-5PQ 14*20*1.4mm LQFP 14*20*2.7mm PQFP 83 IC61S6432-6TQ IC61S6432-6PQ 14*20*1.4mm LQFP 14*20*2.7mm PQFP 75 IC61S6432-7TQ IC61S6432-7PQ 14*20*1.4mm LQFP 14*20*2.7mm PQFP 66 IC61S6432-8TQ IC61S6432-8PQ 14*20*1.4mm LQFP 14*20*2.7mm PQFP ORDERING INFORMATION Industrial Range: –40°C to +85°C Frequency (MHz) 117 20 Order Part Number Package IC61S6432-117TQI 14*20*1.4mm LQFP IC61S6432-117PQI 14*20*2.7mm PQFP 100 IC61S6432-5TQI IC61S6432-5PQI 14*20*1.4mm LQFP 14*20*2.7mm PQFP 83 IC61S6432-6TQI IC61S6432-6PQI 14*20*1.4mm LQFP 14*20*2.7mm PQFP 75 IC61S6432-7TQI IC61S6432-7PQI 14*20*1.4mm LQFP 14*20*2.7mm PQFP 66 IC61S6432-8TQI IC61S6432-8PQI 14*20*1.4mm LQFP 14*20*2.7mm PQFP Integrated Circuit Solution Inc. SSR016-0A 09/13/2001 IC61S6432 Integrated Circuit Solution Inc. HEADQUARTER: NO.2, TECHNOLOGY RD. V, SCIENCE-BASED INDUSTRIAL PARK, HSIN-CHU, TAIWAN, R.O.C. TEL: 886-3-5780333 Fax: 886-3-5783000 BRANCH OFFICE: 7F, NO. 106, SEC. 1, HSIN-TAI 5TH ROAD, HSICHIH TAIPEI COUNTY, TAIWAN, R.O.C. TEL: 886-2-26962140 FAX: 886-2-26962252 http://www.icsi.com.tw Integrated Circuit Solution Inc. SSR016-0A 09/13/2001 21