24-Bit, 8-/16-Channel, 250 kSPS, SigmaDelta ADC with True Rail-to-Rail Buffers AD7175-8 Data Sheet FEATURES GENERAL DESCRIPTION Fast and flexible output rate: 5 SPS to 250 kSPS Channel scan data rate of 50 kSPS/channel (20 µs settling) Performance specifications 17.2 noise free bits at 250 kSPS 20.2 noise free bits at 2.5 kSPS 24 noise free bits at 20 SPS INL: ±1 ppm of FSR 85 dB filter rejection of 50 Hz and 60 Hz with 50 ms settling User configurable input channels 8 fully differential channels or 16 single-ended channels Crosspoint multiplexer On-chip 2.5 V reference (±2 ppm/°C drift) True rail-to-rail analog and reference input buffers Internal or external clock Power supply: AVDD1 − AVSS = 5 V, AVDD2 = IOVDD = 2 V to 5 V (nominal) Split supply with AVDD1/AVSS at ±2.5 V ADC current: 8.4 mA Temperature range: −40°C to +105°C 3- or 4-wire serial digital interface (Schmitt trigger on SCLK) Serial port interface (SPI), QSPI, MICROWIRE, and DSP compatible The AD7175-8 is a low noise, fast settling, multiplexed, 8-/16channel (fully/pseudo differential) Σ-Δ analog-to-digital converter (ADC) for low bandwidth inputs. It has a maximum channel scan rate of 50 kSPS (20 µs) for fully settled data. The output data rates range from 5 SPS to 250 kSPS. The AD7175-8 integrates key analog and digital signal conditioning blocks to allow users to configure an individual setup for each analog input channel in use. Each feature can be user selected on a per channel basis. Integrated true rail-to-rail buffers on the analog inputs and external reference inputs provide easy to drive high impedance inputs. The precision 2.5 V low drift (2 ppm/°C) band gap internal reference (with output reference buffer) adds embedded functionality to reduce external component count. The digital filter allows simultaneous 50 Hz and 60 Hz rejection at a 27.27 SPS output data rate. The user can switch between different filter options according to the demands of each channel in the application. The ADC automatically switches through each selected channel. Further digital processing functions include offset and gain calibration registers, configurable on a per channel basis. The device operates with a 5 V AVDD1 − AVSS supply, or with ±2.5 V AVDD1/AVSS, and 2 V to 5 V AVDD2 and IOVDD nominal supplies. The specified operating temperature range is −40°C to +105°C. The AD7175-8 is available in a 40-lead LFCSP package. APPLICATIONS Process control: PLC/DCS modules Temperature and pressure measurement Medical and scientific multichannel instrumentation Chromatography FUNCTIONAL BLOCK DIAGRAM AVDD1 AVDD2 REGCAPA CROSSPOINT MULTIPLEXER AIN0/REF2– BUFFERED PRECISION REFERENCE 1.8V LDO AVDD IOVDD REGCAPD REF– REF+ REFOUT REFERENCE INPUT BUFFERS 1.8V LDO INT REF CS AIN1/REF2+ SCLK DIGITAL FILTER Σ-Δ ADC SERIAL INTERFACE AND CONTROL DIN DOUT/RDY SYNC ERROR AIN15 AVSS AIN16 ANALOG INPUT BUFFERS XTAL AND INTERNAL CLOCK OSCILLATOR CIRCUITRY I/O AND EXTERNAL MUX CONTROL AD7175-8 AVSS PDSW GPIO0 GPIO1 GPO2 GPO3 XTAL1 XTAL2/CLKIO DGND 12911-001 TEMPERATURE SENSOR Figure 1. Rev. 0 Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2015 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com AD7175-8 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 CRC Calculation......................................................................... 41 Applications ....................................................................................... 1 Integrated Functions ...................................................................... 43 General Description ......................................................................... 1 General-Purpose I/O ................................................................. 43 Functional Block Diagram .............................................................. 1 External Multiplexer Control ................................................... 43 Revision History ............................................................................... 2 Delay ............................................................................................ 43 Specifications..................................................................................... 3 16-Bit/24-Bit Conversions......................................................... 43 Timing Characteristics ................................................................ 6 DOUT_RESET ........................................................................... 43 Absolute Maximum Ratings ............................................................ 8 Synchronization .......................................................................... 43 Thermal Resistance ...................................................................... 8 Error Flags ................................................................................... 44 ESD Caution .................................................................................. 8 DATA_STAT ............................................................................... 44 Pin Configuration and Function Descriptions ............................. 9 IOSTRENGTH ........................................................................... 44 Typical Performance Characteristics ........................................... 11 Power-Down Switch .................................................................. 45 Noise Performance and Resolution .............................................. 17 Internal Temperature Sensor .................................................... 45 Getting Started ................................................................................ 18 Grounding and Layout .................................................................. 46 Power Supplies ............................................................................ 19 Register Summary .......................................................................... 47 Digital Communication............................................................. 19 Register Details ............................................................................... 49 AD7175-8 Reset .......................................................................... 20 Communications Register......................................................... 49 Configuration Overview ........................................................... 20 Status Register ............................................................................. 51 Circuit Description ......................................................................... 25 ADC Mode Register ................................................................... 52 Buffered Analog Input ............................................................... 25 Interface Mode Register ............................................................ 53 Crosspoint Multiplexer .............................................................. 25 Register Check ............................................................................ 54 AD7175-8 Reference .................................................................. 26 Data Register ............................................................................... 54 Buffered Reference Input ........................................................... 27 GPIO Configuration Register ................................................... 55 Clock Source ............................................................................... 27 ID Register................................................................................... 56 Digital Filters ................................................................................... 28 Channel Register 0 ..................................................................... 56 Sinc5 + Sinc1 Filter..................................................................... 28 Channel Register 1 to Channel Register 15 ............................ 58 Sinc3 Filter ................................................................................... 28 Setup Configuration Register 0 ................................................ 59 Single Cycle Settling ................................................................... 29 Setup Configuration Register 1 to Setup Configuration Register 7 ..................................................................................... 60 Enhanced 50 Hz and 60 Hz Rejection Filters ......................... 33 Operating Modes ............................................................................ 36 Continuous Conversion Mode ................................................. 36 Continuous Read Mode ............................................................. 37 Single Conversion Mode ........................................................... 38 Standby and Power-Down Modes............................................ 39 Calibration ................................................................................... 39 Digital Interface .............................................................................. 40 Checksum Protection................................................................. 40 Filter Configuration Register 0................................................. 61 Filter Configuration Register 1 to Filter Configuration Register 7 ..................................................................................... 62 Offset Register 0 ......................................................................... 62 Offset Register 1 to Offset Register 7....................................... 62 Gain Register 0............................................................................ 62 Gain Register 1 to Gain Register 7 ........................................... 63 Outline Dimensions ....................................................................... 64 Ordering Guide .......................................................................... 64 REVISION HISTORY 10/15—Revision 0: Initial Version Rev. 0 | Page 2 of 64 Data Sheet AD7175-8 SPECIFICATIONS AVDD1 = 4.5 V to 5.5 V, AVDD2 = 2 V to 5.5 V, IOVDD = 2 V to 5.5 V, AVSS = DGND = 0 V, REF+ = 2.5 V, REF− = AVSS, internal master clock (MCLK) = 16 MHz, TA = TMIN to TMAX (−40°C to +105°C), unless otherwise noted. Table 1. Parameter ADC SPEED AND PERFORMANCE Output Data Rate (ODR) No Missing Codes1 Resolution Noise ACCURACY Integral Nonlinearity (INL) Offset Error2 Offset Drift Gain Error2 Gain Drift1 REJECTION Power Supply Rejection Common-Mode Rejection At DC At 50 Hz, 60 Hz1 Normal Mode Rejection1 ANALOG INPUTS Differential Input Range Absolute Voltage Limits1 Input Buffers Disabled Input Buffers Enabled Analog Input Current Input Buffers Disabled Input Current Input Current Drift Input Buffers Enabled Input Current Input Current Drift Crosstalk INTERNAL REFERENCE Output Voltage Initial Accuracy3 Temperature Coefficient1 0°C to 105°C −40°C to +105°C Reference Load Current, ILOAD Power Supply Rejection Load Regulation Voltage Noise Voltage Noise Density Test Conditions/Comments Excluding sinc3 filter ≥ 125 kSPS See Table 19 to Table 23 See Table 19 to Table 23 Min 5 24 All input buffers enabled All input buffers disabled Internal short Internal short ±4.5 ±1 ±60 ±150 ±80 ±0.5 AVDD1, AVDD2, for VIN = 1 V VIN = 0.1 V 20 Hz output data rate (post filter), 50 Hz ± 1 Hz and 60 Hz ± 1 Hz 50 Hz ± 1 Hz and 60 Hz ± 1 Hz Internal clock, 20 SPS ODR (postfilter) External clock, 20 SPS ODR (postfilter) Typ 71 85 External clock Internal clock SPS Bits 10 ±4.5 ppm of FSR ppm of FSR µV nV/°C ppm of FSR ppm/°C ±110 ±0.75 dB dB dB 90 90 dB dB ±VREF V AVDD1 + 0.05 AVDD1 V V ±48 ±0.75 ±4 µA/V nA/V/°C nA/V/°C ±30 ±75 ±1 −120 nA pA/°C nA/°C dB 2.5 −0.12 +0.12 ±2 ±3 −10 Rev. 0 | Page 3 of 64 250,000 95 120 AVSS − 0.05 AVSS AVDD1, AVDD2 (line regulation) ∆VOUT/∆ILOAD eN, 0.1 Hz to 10 Hz, 2.5 V reference eN, 1 kHz, 2.5 V reference Unit 90 VREF = (REF+) − (REF−) AVDD1 − 0.2 V to AVSS + 0.2 V AVDD1 to AVSS 1 kHz input 100 nF external capacitor to AVSS REFOUT, with respect to AVSS REFOUT, TA = 25°C Max 95 32 4.5 215 ±5 ±10 +10 V % of V ppm/°C ppm/°C mA dB ppm/mA µV rms nV/√Hz AD7175-8 Parameter Turn-On Settling Time Short-Circuit Current, ISC EXTERNAL REFERENCE INPUTS Differential Input Range Absolute Voltage Limits1 Input Buffers Disabled Input Buffers Enabled REF+/REF− Input Current Input Buffers Disabled Input Current Input Current Drift Input Buffers Enabled Input Current Input Current Drift Normal Mode Rejection1 Common-Mode Rejection TEMPERATURE SENSOR Accuracy Sensitivity BURNOUT CURRENTS Source/Sink Current POWER-DOWN SWITCH RON Allowable Currents GENERAL-PURPOSE INPUTS/OUTPUTS (GPIO0, GPIO1, GPO2, GPO3) Input Mode Leakage Current1 Floating State Output Capacitance Output High Voltage, VOH1 Output Low Voltage, VOL1 Input High Voltage, VINH1 Input Low Voltage, VINL1 CLOCK Internal Clock Frequency Accuracy Duty Cycle Output Low Voltage, VOL Output High Voltage, VOH Crystal Frequency Start-Up Time External Clock (CLKIO) Duty Cycle1 Data Sheet Test Conditions/Comments 100 nF REFOUT capacitor Min Typ 200 25 Max Unit µs mA VREF = (REF+) − (REF−) 1 2.5 AVDD1 V AVDD1 + 0.05 AVDD1 V V AVSS − 0.05 AVSS ±72 ±1.2 ±6 µA/V nA/V/°C nA/V/°C ±800 1.2 nA nA/°C 95 dB After user calibration at 25°C ±2 470 °C µV/K Analog input buffers must be enabled ±10 µA External clock Internal clock See the Rejection parameter 24 16 Ω mA With respect to AVSS −10 +10 5 ISOURCE = 200 µA ISINK = 800 µA AVSS + 4 AVSS + 0.4 AVSS + 3 AVSS + 0.7 16 −2.5% +2.5% 50 0.4 0.8 × IOVDD 14 30 Rev. 0 | Page 4 of 64 16 10 16 50 16.384 16.384 70 µA pF V V V V MHz % % V V MHz µs MHz % Data Sheet Parameter LOGIC INPUTS Input High Voltage, VINH1 Input Low Voltage, VINL1 Hysteresis1 Leakage Current LOGIC OUTPUT (DOUT/RDY) Output High Voltage, VOH1 Output Low Voltage, VOL1 Leakage Current Output Capacitance SYSTEM CALIBRATION1 Full-Scale (FS) Calibration Limit Zero-Scale Calibration Limit Input Span POWER REQUIREMENTS Power Supply Voltage AVDD1 to AVSS AVDD2 to AVSS4 AVSS to DGND IOVDD to DGND4 IOVDD to AVSS POWER SUPPLY CURRENTS5 Full Operating Mode AVDD1 Current AVDD2 Current IOVDD Current Standby Mode (LDO On) Power-Down Mode AD7175-8 Test Conditions/Comments Min 2 V ≤ IOVDD < 2.3 V 0.65 × IOVDD 0.7 × IOVDD 2.3 V ≤ IOVDD ≤ 5.5 V 2 V ≤ IOVDD < 2.3 V 2.3 V ≤ IOVDD ≤ 5.5 V IOVDD ≥ 2.7 V IOVDD < 2.7 V Typ 0.35 × IOVDD 0.7 0.25 0.2 +10 0.8 × IOVDD 0.8 × IOVDD 0.8 × IOVDD 0.4 0.4 0.4 +10 −10 10 1.05 × FS Rev. 0 | Page 5 of 64 V V V V V V µA pF 2.1 × FS 5.5 5.5 0 5.5 6.35 V V V V V 1.4 1.65 mA 1.75 2 mA 13 16 mA 5 2.5 to 5 2.5 to 5 For AVSS < DGND All outputs unloaded, digital inputs connected to IOVDD or DGND Analog input and reference input buffers (AIN±, REF±) disabled, external reference Analog input and reference input buffers disabled, internal reference Analog input and reference input buffers enabled, external reference Each buffer: AIN+, AIN−, REF+, REF− External reference Internal reference External clock Internal clock External crystal Internal reference off, total current consumption Internal reference on, total current consumption Full power-down (including LDO and internal reference) V V V V V µA V V V −1.05 × FS 0.8 × FS 4.5 2 −2.75 2 Unit V 0.08 0.04 −10 IOVDD ≥ 4.5 V, ISOURCE = 1 mA 2.7 V ≤ IOVDD < 4.5 V, ISOURCE = 500 µA IOVDD < 2.7 V, ISOURCE = 200 µA IOVDD ≥ 4.5 V, ISINK = 2 mA 2.7 V ≤ IOVDD < 4.5 V, ISINK = 1 mA IOVDD < 2.7 V, ISINK = 400 µA Floating state Floating state Max 2.9 4.5 4.75 2.5 2.75 3 30 5 5.2 2.8 3.1 425 5 mA mA mA mA mA mA µA µA 10 µA AD7175-8 Data Sheet Parameter POWER DISSIPATION5 Full Operating Mode Test Conditions/Comments Min All buffers disabled, external clock and reference, AVDD2 = 2 V, IOVDD = 2 V All buffers disabled, external clock and reference, all supplies = 5 V All buffers disabled, external clock and reference, all supplies = 5.5 V All buffers enabled, internal clock and reference, AVDD2 = 2 V, IOVDD = 2 V All buffers enabled, internal clock and reference, all supplies = 5 V All buffers enabled, internal clock and reference, all supplies = 5.5 V Internal reference off, all supplies = 5 V Internal reference on, all supplies = 5 V Full power-down, all supplies = 5 V Standby Mode Power-Down Mode Typ Max Unit 21 mW 42 mW 52 mW 82 mW 105 mW 150 2.2 25 136 mW 50 µW mW µW 1 This specification is not production tested but is supported by characterization data at the initial product release. Following a system or internal zero-scale calibration, the offset error is in the order of the noise for the programmed output data rate selected. A system full-scale calibration reduces the gain error to the order of the noise for the programmed output data rate. 3 This specification includes moisture sensitivity level (MSL) preconditioning effects. 4 The nominal range is 2 V to 5 V. 5 This specification is with no load on the REFOUT and digital output pins. 2 TIMING CHARACTERISTICS IOVDD = 2 V to 5.5 V, DGND = 0 V, Input Logic 0 = 0 V, Input Logic 1 = IOVDD, CLOAD = 20 pF, unless otherwise noted. Table 2. Parameter SCLK t3 t4 READ OPERATION t1 t23 t55 t6 t7 WRITE OPERATION t8 t9 t10 t11 Limit at TMIN, TMAX Unit Description1, 2 25 25 ns min ns min SCLK high pulse width SCLK low pulse width 0 15 40 0 12.5 25 2.5 20 0 10 ns min ns max ns max ns min ns max ns max ns min ns max ns min ns min CS falling edge to DOUT/RDY active time IOVDD = 4.75 V to 5.5 V IOVDD = 2 V to 3.6 V SCLK active edge to data valid delay4 IOVDD = 4.75 V to 5.5 V IOVDD = 2 V to 3.6 V Bus relinquish time after CS inactive edge 0 8 8 5 ns min ns min ns min ns min CS falling edge to SCLK active edge setup time4 Data valid to SCLK edge setup time Data valid to SCLK edge hold time CS rising edge to SCLK edge hold time SCLK inactive edge to CS inactive edge SCLK inactive edge to DOUT/RDY high/low 1 Sample tested during initial release to ensure compliance. See Figure 2 and Figure 3. 3 This parameter is defined as the time required for the output to cross the VOL or VOH limits. 4 The SCLK active edge is the falling edge of SCLK. 5 DOUT/RDY returns high after a read of the data register. In single conversion mode and continuous conversion mode, the same data can be read again, if required, while DOUT/RDY is high, although care must be taken to ensure that subsequent reads do not occur close to the next output update. If the continuous read feature is enabled, the digital word can be read only once. 2 Rev. 0 | Page 6 of 64 Data Sheet AD7175-8 Timing Diagrams CS (I) t6 t1 t5 MSB DOUT/RDY (O) LSB t7 t2 t3 12911-003 SCLK (I) t4 I = INPUT, O = OUTPUT Figure 2. Read Cycle Timing Diagram CS (I) t11 t8 SCLK (I) t9 t10 MSB LSB I = INPUT, O = OUTPUT Figure 3. Write Cycle Timing Diagram Rev. 0 | Page 7 of 64 12911-004 DIN (I) AD7175-8 Data Sheet ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. THERMAL RESISTANCE Table 3. θJA is specified for a device soldered on a JEDEC test board for surface-mount packages. Parameter AVDD1, AVDD2 to AVSS AVDD1 to DGND IOVDD to DGND IOVDD to AVSS AVSS to DGND Analog Input Voltage to AVSS Reference Input Voltage to AVSS Digital Input Voltage to DGND Digital Output Voltage to DGND Analog Input/Digital Input Current Operating Temperature Range Storage Temperature Range Maximum Junction Temperature Lead Soldering, Reflow Temperature ESD Rating (Human Body Model) Rating −0.3 V to +6.5 V −0.3 V to +6.5 V −0.3 V to +6.5 V −0.3 V to +7.5 V −3.25 V to +0.3 V −0.3 V to AVDD1 + 0.3 V −0.3 V to AVDD1 + 0.3 V −0.3 V to IOVDD + 0.3 V −0.3 V to IOVDD + 0.3 V 10 mA −40°C to +105°C −65°C to +150°C 150°C 260°C 4 kV Table 4. Thermal Resistance Package Type 40-Lead, 6 mm × 6 mm LFCSP 1-Layer JEDEC Board 4-Layer JEDEC Board 4-Layer JEDEC Board with 16 Thermal Vias ESD CAUTION Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. Rev. 0 | Page 8 of 64 θJA Unit 114 54 34 °C/W °C/W °C/W Data Sheet AD7175-8 40 39 38 37 36 35 34 33 32 31 REF+ REF– GPO3 AIN15 AIN14 AIN13 AIN12 AIN11 AIN10 AIN9 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 1 2 3 4 5 6 7 8 9 10 AD7175-8 TOP VIEW (Not to Scale) 30 29 28 27 26 25 24 23 22 21 AIN8 AIN7 AIN6 AIN5 AIN4 GPO2 GPIO1 GPIO0 REGCAPD DGND NOTES 1. SOLDER THE EXPOSED PAD TO A SIMILAR PAD ON THE PCB UNDER THE EXPOSED PAD TO CONFER MECHANICAL STRENGTH AND FOR HEAT DISSIPATION. THE EXPOSED PAD MUST BE CONNECTED TO AVSS THROUGH THIS PAD ON THE PCB. 12911-005 PDSW XTAL1 XTAL2/CLKIO DOUT/RDY DIN SCLK CS ERROR SYNC IOVDD 11 12 13 14 15 16 17 18 19 20 AIN16 AIN0/REF2– AIN1/REF2+ AIN2 AIN3 REFOUT REGCAPA AVSS AVDD1 AVDD2 Figure 4. Pin Configuration Table 5. Pin Function Descriptions1 Pin No. 1 2 Mnemonic AIN16 AIN0/REF2− Type2 AI AI 3 AIN1/REF2+ AI 4 5 6 7 8 9 AIN2 AIN3 REFOUT REGCAPA AVSS AVDD1 AI AI AO AO P P 10 11 12 13 AVDD2 PDSW XTAL1 XTAL2/CLKIO P AO AI AI/DI 14 DOUT/RDY DO Description Analog Input 16. This pin is selectable through the crosspoint multiplexer. Analog Input 0 (AIN0)/Reference 2, Negative Input (REF2−). An external reference can be applied between REF2+ and REF2−. REF2− can span from AVSS to AVDD1 − 1 V. Analog Input 0 is selectable through the crosspoint multiplexer. Reference 2 can be selected through the REF_SELx bits in the setup configuration registers. Analog Input 1 (AIN0)/Reference 2, Positive Input (REF2+). An external reference can be applied between REF2+ and REF2−. REF2+ spans from AVDD1 to AVSS + 1 V. Analog Input 1 is selectable through the crosspoint multiplexer. Reference 2 can be selected through the REF_SELx bits in the setup configuration registers. Analog Input 2. This pin is selectable through the crosspoint multiplexer. Analog Input 3. This pin is selectable through the crosspoint multiplexer. Buffered Output of Internal Reference. The output is 2.5 V with respect to AVSS. Analog Low Dropout (LDO) Regulator Output. Decouple this pin to AVSS using a 1 µF capacitor. Negative Analog Supply. This supply ranges from 0 V to −2.75 V and is nominally set to 0 V. Analog Supply Voltage 1. This voltage is 5 V ± 10% with respect to AVSS. AVDD1 − AVSS can be a single 5 V supply or a ±2.5 V split supply. Analog Supply Voltage 2. This voltage ranges from 2 V to AVDD1 with respect to AVSS. Power-Down Switch Connected to AVSS. This pin is controlled by the PDSW bit in the GPIOCON register. Input 1 for Crystal. Input 2 for Crystal (XTAL2)/Clock Input or Output (CLKIO). See the CLOCKSEL bit settings in the ADCMODE register for more information. Serial Data Output (DOUT)/Data Ready Output (RDY). This pin serves a dual purpose. It functions as a serial data output pin to access the output shift register of the ADC. The output shift register can contain data from any of the on-chip data or control registers. The data-word/control word information is placed on the DOUT/RDY pin on the SCLK falling edge and is valid on the SCLK rising edge. When CS is high, the DOUT/RDY output is tristated. When CS is low, and a register is not being read, DOUT/RDY operates as a data ready pin, going low to indicate the completion of a conversion. If the data is not read after the conversion, the pin goes high before the next update occurs. The DOUT/RDY falling edge can be used as an interrupt to a processor, indicating that valid data is available. Rev. 0 | Page 9 of 64 AD7175-8 Data Sheet Pin No. 15 Mnemonic DIN Type2 DI 16 SCLK DI 17 CS DI 18 ERROR DI/O 19 SYNC DI 20 IOVDD P 21 22 DGND REGCAPD P AO 23 GPIO0 DI/O 24 GPIO1 DI/O 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 GPO2 AIN4 AIN5 AIN6 AIN7 AIN8 AIN9 AIN10 AIN11 AIN12 AIN13 AIN14 AIN15 GPO3 REF− DO AI AI AI AI AI AI AI AI AI AI AI AI DO AI 40 REF+ AI EP P 1 2 Description Serial Data Input to the Input Shift Register on the ADC. Data in this shift register is transferred to the control registers in the ADC, with the register address (RA) bits of the communications register identifying the appropriate register. Data is clocked in on the rising edge of SCLK. Serial Clock Input. This serial clock input is for data transfers to and from the ADC. SCLK has a Schmitt triggered input, making the interface suitable for opto-isolated applications. Chip Select Input. This pin is an active low logic input used to select the ADC. Use CS to select the ADC in systems with more than one device on the serial bus. CS can be hardwired low, allowing the ADC to operate in 3-wire mode with SCLK, DIN, and DOUT/RDY used to interface with the device. When CS is high, the DOUT/RDY output is tristated. Error input/output or General-Purpose Output. This pin can be used in one of the following three modes: Active low error input mode. This mode sets the ADC_ERROR bit in the STATUS register. Active low, open-drain error output mode. The status register error bits are mapped to the ERROR pin. The ERROR pins of multiple devices can be wired together to a common pull-up resistor so that an error on any device can be observed. General-purpose output mode. The status of the pin is controlled by the ERR_DAT bit in the GPIOCON register. The pin is referenced between IOVDD and DGND, as opposed to the AVDD1 and AVSS levels used by the GPIO1 and GPIO2 pins. The ERROR pin has an active pull-up circuit in this case. Synchronization Input. Allows synchronization of the digital filters and analog modulators when using multiple AD7175-8 devices. Digital I/O Supply Voltage. The IOVDD voltage ranges from 2 V to 5 V (nominal). IOVDD is independent of AVDD1 and AVDD2. For example, IOVDD can be operated at 3.3 V when AVDD1 or AVDD2 equals 5 V, or vice versa. If AVSS is set to −2.5 V, the voltage on IOVDD must not exceed 3.6 V. Digital Ground. Digital LDO Regulator Output. This pin is for decoupling purposes only. Decouple this pin to DGND using a 1 µF capacitor. General-Purpose Input/Output 0. Logic input/output on this this pin is referred to the AVDD1 and AVSS supplies. General-Purpose Input/Output 2. Logic input/output on this this pin is referred to the AVDD1 and AVSS supplies. General-Purpose Output 2. Logic output on this this pin is referred to the AVDD1 and AVSS supplies. Analog Input 4. This pin is selectable through the crosspoint multiplexer. Analog Input 5. This pin is selectable through the crosspoint multiplexer. Analog Input 6. This pin is selectable through the crosspoint multiplexer. Analog Input 7. This pin is selectable through the crosspoint multiplexer. Analog Input 8. This pin is selectable through the crosspoint multiplexer. Analog Input 9. This pin is selectable through the crosspoint multiplexer. Analog Input 10. This pin is selectable through the crosspoint multiplexer. Analog Input 11. This pin is selectable through the crosspoint multiplexer. Analog Input 12. This pin is selectable through the crosspoint multiplexer. Analog Input 13. This pin is selectable through the crosspoint multiplexer. Analog Input 14. This pin is selectable through the crosspoint multiplexer. Analog Input 15. This pin is selectable through the crosspoint multiplexer. General-Purpose Output 3. Logic output on this this pin is referred to the AVDD1 and AVSS supplies. Reference 1 Input Negative Terminal. REF− can span from AVSS to AVDD1 − 1 V. Reference 1 can be selected through the REF_SELx bits in the setup configuration registers. Reference 1 Input Positive Terminal. An external reference can be applied between REF+ and REF−. REF+ can span from AVDD1 to AVSS + 1 V. Reference 1 can be selected through the REF_SELx bits in the setup configuration registers. Exposed Pad. Solder the exposed pad to a similar pad on the PCB under the exposed pad to confer mechanical strength to the package and for heat dissipation. The exposed pad must be connected to AVSS through this pad on the PCB. Note that, throughout this data sheet, the dual function pin names are referenced by the relevant function only. AI = analog input, AO = analog output, P = power supply, DI = digital input, DO = digital output, and DI/O = bidirectional digital input/output. Rev. 0 | Page 10 of 64 Data Sheet AD7175-8 TYPICAL PERFORMANCE CHARACTERISTICS AVDD1 = 5 V, AVDD2 = 5 V, IOVDD = 3.3 V, TA = 25°C, unless otherwise noted. 1000 8390000 900 8389500 800 8389000 SAMPLE COUNT ADC CODE 700 8388500 8388000 8387500 600 500 400 300 8387000 200 8386500 0 100 200 300 400 500 600 700 SAMPLE NUMBER 800 900 1000 0 12911-205 8386000 8388460 8388461 8388462 8388463 8388464 8388465 8388466 ADC CODE Figure 5. Noise (Analog Input Buffers Disabled, VREF = 5 V, Output Data Rate = 5 SPS) 12911-208 100 Figure 8. Histogram (Analog Input Buffers Disabled, VREF = 5 V, Output Data Rate = 5 SPS) 120 8388480 8388475 100 SAMPLE COUNT ADC CODE 8388470 8388465 8388460 80 60 40 8388455 100 200 300 400 500 600 700 SAMPLE NUMBER 800 900 1000 0 ADC CODE 12911-209 0 12911-206 8388445 8388450 8388451 8388452 8388453 8388454 8388455 8388456 8388457 8388458 8388459 8388460 8388461 8388462 8388463 8388464 8388465 8388466 8388467 8388468 8388469 8388470 8388471 8388472 8388473 8388474 8388475 8388476 8388477 20 8388450 Figure 9. Histogram (Analog Input Buffers Disabled, VREF = 5 V, Output Data Rate = 10 kSPS) Figure 6. Noise (Analog Input Buffers Disabled, VREF = 5 V, Output Data Rate = 10 kSPS) 45 8388520 40 8388500 35 SAMPLE COUNT 8388460 8388440 30 25 20 15 10 8388420 0 100 200 300 400 500 600 700 SAMPLE NUMBER 800 900 1000 0 ADC CODE Figure 10. Histogram (Analog Input Buffers Disabled, VREF = 5 V, Output Data Rate = 250 kSPS) Figure 7. Noise (Analog Input Buffers Disabled, VREF = 5 V, Output Data Rate = 250 kSPS) Rev. 0 | Page 11 of 64 12911-210 8388400 8388420 8388422 8388424 8388426 8388428 8388430 8388432 8388434 8388436 8388438 8388440 8388442 8388444 8388446 8388448 8388450 8388452 8388454 8388456 8388458 8388460 8388462 8388464 8388466 8388468 8388470 8388472 8388474 8388476 8388478 8388480 8388482 8388484 8388486 8388488 8388490 8388492 8388494 8388496 8388498 8388500 8388502 8388504 5 12911-207 ADC CODE 8388480 Data Sheet 1000 8389500 900 8389000 800 8388500 700 8388000 8387500 8387000 600 500 400 8386500 300 8386000 200 8385500 100 8385000 0 100 200 300 400 500 600 700 SAMPLE NUMBER 800 900 1000 0 8388490 8388491 8388492 8388493 8388494 8388495 8388496 ADC CODE Figure 11. Noise (Analog Input Buffers Enabled, VREF = 5 V, Output Data Rate = 5 SPS) 12911-214 SAMPLE COUNT 8390000 12911-211 ADC CODE AD7175-8 Figure 14. Histogram (Analog Input Buffers Enabled, VREF = 5 V, Output Data Rate = 5 SPS) 8388520 100 90 8388515 80 8388510 SAMPLE COUNT ADC CODE 70 8388505 8388500 8388495 60 50 40 30 8388490 20 8388485 200 300 400 500 600 700 SAMPLE NUMBER 800 900 1000 0 ADC CODE Figure 15. Histogram (Analog Input Buffers Enabled, VREF = 5 V, Output Data Rate = 10 kSPS) 35 8388560 30 8388540 25 8388520 8388500 20 15 8388480 10 8388460 5 8388440 0 100 200 300 400 500 600 700 SAMPLE NUMBER 800 900 1000 0 8388460 8388462 8388464 8388466 8388468 8388470 8388472 8388474 8388476 8388478 8388480 8388482 8388484 8388486 8388488 8388490 8388492 8388494 8388496 8388498 8388500 8388502 8388504 8388506 8388508 8388510 8388512 8388514 8388516 8388518 8388520 8388522 8388524 8388526 8388528 8388530 8388532 SAMPLE COUNT 8388580 12911-213 ADC CODE Figure 12. Noise (Analog Input Buffers Enabled, VREF = 5 V, Output Data Rate = 10 kSPS) 12911-215 100 ADC CODE Figure 13. Noise (Analog Input Buffers Enabled, VREF = 5 V, Output Data Rate = 250 kSPS) Figure 16. Histogram (Analog Input Buffers Enabled, VREF = 5 V, Output Data Rate = 250 kSPS) Rev. 0 | Page 12 of 64 12911-216 0 12911-212 8388480 8388480 8388481 8388482 8388483 8388484 8388485 8388486 8388487 8388488 8388489 8388490 8388491 8388492 8388493 8388494 8388495 8388496 8388497 8388498 8388499 8388500 8388501 8388502 8388503 8388504 8388505 8388506 8388507 8388508 8388509 8388510 8388511 8388512 8388513 8388514 10 Data Sheet 0.000016 AD7175-8 0 ANALOG INPUT BUFFERS ON ANALOG INPUT BUFFERS OFF 0.000014 –20 0.000012 –40 CMRR (dB) NOISE (V) 0.000010 0.000008 0.000006 –60 –80 0.000004 –100 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 INPUT COMMON-MODE VOLTAGE (V) 4.5 –120 12911-217 0 5.0 1 1M –80 20 ANALOG INPUT BUFFERS OFF ANALOG INPUT BUFFERS ON –90 –100 14 –110 12 –120 CMRR (dB) 16 10 8 –130 –140 6 –150 4 –160 2 –170 0 2 4 6 8 10 FREQUENCY (MHz) 12 14 16 –180 10 12911-218 0 Figure 18. Noise vs. External Master Clock Frequency, Analog Input Buffers On and Off 16800000 30 40 50 VIN FREQUENCY (Hz) 60 70 Figure 21. Common-Mode Rejection Ratio (CMRR) vs. VIN Frequency (VIN = 0.1 V, 10 Hz to 70 Hz, Output Data Rate = 20 SPS, Enhanced Filter) –60 CONTINUOUS CONVERSION—REFERENCE DISABLED STANDBY—REFERENCE DISABLED STANDBY—REFERENCE ENABLED 16780000 20 12911-227 18 AVDD1—EXTERNAL 2.5V REFERENCE AVDD1—INTERNAL 2.5V REFERENCE –70 16760000 PSRR (dB) –80 16740000 16720000 –90 –100 –110 16680000 –120 16660000 1 10 100 SAMPLE NUMBER 1k 10k 12911-225 16700000 –130 1 10 100 1k 10k 100k VIN FREQUENCY (Hz) 1M 10M 100M Figure 22. Power Supply Rejection Ratio (PSRR) vs. VIN Frequency Figure 19. Internal Reference Settling Time Rev. 0 | Page 13 of 64 12911-228 NOISE (µV rms) 100k Figure 20. Common-Mode Rejection Ratio (CMRR) vs. VIN Frequency (VIN = 0.1 V, Output Data Rate = 250 kSPS) Figure 17. Noise vs. Input Common-Mode Voltage, Analog Input Buffers On and Off OUTPUT CODE 10k 100 1k VIN FREQUENCY (Hz) 10 12911-226 0.000002 AD7175-8 4 3 INL (ppm/FSR) 2 16 INT OSC BUFFERS OFF INT OSC BUFFERS ON EXT CRYSTAL BUFFERS OFF EXT CRYSTAL BUFFERS ON EXT CLK BUFFERS OFF EXT CLK BUFFERS ON 14 12 SAMPLE COUNT 5 Data Sheet 1 0 –1 10 8 6 –2 4 –3 Figure 23. Integral Nonlinearity (INL) vs. VIN (Differential Input, External 2.5 V Reference) 6 2.2 2.1 2.0 1.9 1.8 1.7 1.6 1.5 1.4 1.3 1.2 1.1 Figure 26. Integral Nonlinearity (INL) Distribution Histogram (All Input Buffers Disabled, Differential Input, VREF = 5 V External, 92 Units) 50 INT OSC BUFFERS OFF INT OSC BUFFERS ON EXT CRYSTAL BUFFERS OFF EXT CRYSTAL BUFFERS ON EXT CLK BUFFERS OFF EXT CLK BUFFERS ON 45 40 35 2 SAMPLE COUNT INL (ppm/FSR) 4 INL ERROR (ppm) 12911-029 VIN (V) 0 1.0 2.5 0.9 1.5 0.8 0.5 0.7 –0.5 0.6 –1.5 12911-023 –5 –2.5 0.5 2 –4 0 –2 30 25 20 15 10 –4 –4 –3 –2 –1 0 1 2 3 4 5 VIN (V) 16.04 16.05 16300000 16200000 FREQUENCY (Hz) 10 5 0 –5 16100000 16000000 15900000 15800000 –10 15700000 –15 –20 –2.5 16.00 16.01 16.02 16.03 FREQUENCY (MHz) 16400000 INT OSC BUFFERS OFF INT OSC BUFFERS ON EXT CRYSTAL BUFFERS OFF EXT CRYSTAL BUFFERS ON EXT CLK BUFFERS OFF EXT CLK BUFFERS ON –1.5 –0.5 0.5 1.5 VIN (V) 2.5 12911-025 INL (ppm/FSR) 15 15.99 15600000 –40 –20 0 20 40 60 TEMPERATURE (°C) 80 Figure 28. Internal Oscillator Frequency vs. Temperature Figure 25. Integral Nonlinearity (INL) vs. VIN (Differential Input, Internal 2.5 V Reference) Rev. 0 | Page 14 of 64 100 12911-236 20 15.98 Figure 27. Internal Oscillator Frequency/Accuracy Distribution Histogram (100 Units) Figure 24. Integral Nonlinearity (INL) vs. VIN (Differential Input, External 5 V Reference) 25 0 12911-024 –6 –5 12911-235 5 Data Sheet AD7175-8 1500 1000 140 120 500 SAMPLE COUNT REFERENCE ERROR (µV) 160 DEVICE 1 DEVICE 2 DEVICE 3 0 –500 100 80 60 40 –1000 1.4 12911-036 1.2 0 1.0 85 –0.04 0.8 0.6 0.4 0 0.2 84 GAIN ERROR (ppm of FSR) Figure 29. Absolute Reference Error vs. Temperature Figure 32. Gain Error Distribution Histogram (All Input Buffers Enabled, 611 Units) 35 160 30 140 120 SAMPLE COUNT 25 SAMPLE COUNT –0.2 TEMPERATURE (°C) –0.4 0 –0.6 10 20 30 40 50 60 70 80 90 100 110 120 –0.8 –60 –50 –40 –30 –20 –10 0 12911-237 –1500 –1.0 20 20 15 100 80 60 10 40 5 –74 –70 –66 –62 –58 –54 –50 –46 –42 –38 –34 –30 OFFSET ERROR (µV) 0 12911-034 0 74 75 76 77 78 79 80 81 82 83 GAIN ERROR (ppm of FSR) Figure 30. Offset Error Distribution Histogram (Internal Short, 92 Units) 12911-037 20 Figure 33. Gain Error Distribution Histogram (All Input Buffers Disabled, 647 Units) 14 20 18 12 16 SAMPLE COUNT 14 8 6 12 10 8 6 4 4 2 GAIN ERROR DRIFT (ppm of FSR/°C) Figure 34. Gain Error Drift Distribution Histogram (All Input Buffers Enabled, 79 Units) Figure 31. Offset Error Drift Distribution Histogram (Internal Short, 92 Units) Rev. 0 | Page 15 of 64 12911-038 –0.08 –0.12 –0.16 –0.20 –0.24 –0.28 –0.32 –0.36 0 –0.40 OFFSET DRIFT (nV/°C) 12911-035 2 0 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 160 170 180 190 200 SAMPLE COUNT 10 Data Sheet 18 16 16 14 14 12 12 10 8 6 10 8 6 GAIN ERROR DRIFT (ppm of FSR/°C) –1.2 –1.0 –0.8 –0.6 –0.4 –0.2 0 0.2 0.4 TEMPERATURE DELTA (°C) 12911-039 0.26 0.22 0.18 0.14 0.10 0 0.06 0 0.02 2 –0.02 2 –0.06 4 –0.10 4 Figure 35. Gain Error Drift over Temperature Distribution Histogram (All Input Buffers Disabled, 79 Units) 0.6 0.8 12911-246 SAMPLE COUNT 18 –0.14 SAMPLE COUNT AD7175-8 1.0 Figure 38. Temperature Sensor Distribution Histogram (Uncalibrated, 100 Units) 25 35 30 25 SAMPLE COUNT SUPPLY CURRENT (mA) 20 15 10 20 15 10 5 –20 0 20 40 60 TEMPERATURE (°C) 80 100 0 12911-244 0 –40 9.60 9.65 9.70 9.75 9.80 9.85 9.90 9.95 10.00 10.05 10.10 CURRENT (µA) Figure 36. Supply Current vs. Temperature (Continuous Conversion Mode) Figure 39. Burnout Current Distribution Histogram (100 Units) 700 100 –40°C, AIN– –40°C, AIN+ +25°C, AIN– +25°C, AIN+ +85°C, AIN– +85°C, AIN+ +105°C, AIN– +105°C, AIN+ 93 DEVICES 600 80 INPUT CURRRENT (nA) 500 400 300 200 60 40 20 0 –40 25 TEMPERATURE (°C) 105 Figure 37. Supply Current vs. Temperature (Standby Mode with Reference Enabled) 0 –5 –4 –3 –2 –1 0 1 2 3 4 INPUT VOLTAGE (V) Figure 40. Analog Input Current vs. Input Voltage (VCM = 2.5 V) Rev. 0 | Page 16 of 64 5 12911-041 100 12911-245 SUPPLY CURRENT (µA) 12911-247 5 ALL INPUT BUFFERS OFF ALL INPUT BUFFERS ON Data Sheet AD7175-8 NOISE PERFORMANCE AND RESOLUTION Table 6 and Table 7 show the rms noise, peak-to-peak noise, effective resolution, and the noise free (peak-to-peak) resolution of the AD7175-8 for various output data rates and filters. The numbers given are for the bipolar input range with an external 5 V reference. These numbers are typical and are generated with a differential input voltage of 0 V when the ADC is continuously converting on a single channel. It is important to note that the peak-to-peak resolution is calculated based on the peak-to-peak noise. The peak-to-peak resolution represents the resolution for which there is no code flicker. Table 6. RMS Noise and Peak-to-Peak Resolution vs. Output Data Rate Using a Sinc5 + Sinc1 Filter (Default)1 Output Data Rate (SPS) Input Buffers Disabled 250,000 62,500 10,000 1000 59.92 49.96 16.66 5 Input Buffers Enabled 250,000 62,500 10,000 1000 59.98 49.96 16.66 5 1 RMS Noise (µV rms) Effective Resolution (Bits) Peak-to-Peak Noise (µV p-p) Peak-to-Peak Resolution (Bits) 8.7 5.5 2.5 0.77 0.19 0.18 0.1 0.07 20.1 20.8 21.9 23.6 24 24 24 24 65 43 18.3 5.2 1.1 0.95 0.45 0.34 17.2 17.8 19.1 20.9 23.1 23.3 24 24 9.8 6.4 3 0.92 0.23 0.2 0.13 0.07 20 20.6 21.7 23.4 24 24 24 24 85 55 23 5.7 1.2 1 0.66 0.32 16.8 17.5 18.7 20.7 23.0 23.3 23.9 24 Selected rates only, 1000 samples. Table 7. RMS Noise and Peak-to-Peak Resolution vs. Output Data Rate Using a Sinc3 Filter1 Output Data Rate (SPS) Input Buffers Disabled 250,000 62,500 10,000 1000 60 50 16.66 5 Input Buffers Enabled 250,000 62,500 10,000 1000 60 50 16.66 5 1 RMS Noise (µV rms) Effective Resolution (Bits) Peak-to-Peak Noise (µV p-p) Peak-to-Peak Resolution (Bits) 210 5.2 1.8 0.56 0.13 0.13 0.07 0.05 15.5 20.9 22.4 24 24 24 24 24 1600 40 14 3.9 0.8 0.7 0.37 0.21 12.6 17.9 19.4 21.3 23.6 23.8 24 24 210 5.8 2.1 0.71 0.17 0.15 0.12 0.08 15.5 20.7 22.2 23.7 24 24 24 24 1600 48 16 4.5 1.1 0.83 0.6 0.35 12.6 17.7 19.3 21.1 23.1 23.5 24 24 Selected rates only, 1000 samples. Rev. 0 | Page 17 of 64 AD7175-8 Data Sheet GETTING STARTED The AD7175-8 offers the user a fast settling, high resolution, multiplexed ADC with high levels of configurability. The AD7175-8 includes the following features: • • • Eight fully differential or 16 single-ended analog inputs. A crosspoint multiplexer selects any analog input combination as the input signals to be converted, routing it to the modulator positive or negative input. True rail-to-rail buffered analog and reference inputs. Fully differential input or single-ended input relative to any analog input. Per channel configurability—up to eight different setups can be defined. A separate setup can be mapped to each of the channels. Each setup allows the user to configure whether the buffers are enabled or disabled, gain and offset correction, filter type, output data rate, and reference source selection (internal/external). The AD7175-8 includes two separate linear regulator blocks for both the analog and digital circuitry. The analog LDO regulates the AVDD2 supply to 1.8 V, supplying the ADC core. The user can tie the AVDD1 and AVDD2 supplies together for the easiest connection. If there is already a clean analog supply rail in the system in the range of 2 V (minimum) to 5.5 V (maximum), the user can also choose to connect this to the AVDD2 input, allowing lower power dissipation. 16MHz CX2 CX1 SEE THE BUFFERED ANALOG INPUT SECTION FOR FURTHER DETAILS OPTIONAL EXTERNAL CRYSTAL CIRCUITRY CAPACITORS XTAL1 12 2 AIN0/REF2– XTAL2/CLKIO 13 DOUT/RDY 14 3 DOUT/RDY AIN1/REF2+ DIN DIN 15 36 CS 37 AIN15 1 AIN16 SCLK SCLK 16 AIN14 CLKIN OPTIONAL EXTERNAL CLOCK INPUT CS 17 AD7175-8 IOVDD IOVDD 20 0.1µF DGND 21 REGCAPD 22 VIN 2 4.7µF 1 3 TP NC VIN 0.1µF 1µF AVDD1 9 NC 7 0.1µF 0.1µF AVDD2 ADR445 4 GND AVDD1 VOUT 6 TRIM TP 5 8 0.1µF 4.7µF 40 REF+ 39 REF– AVDD2 10 0.1µF 0.1µF REGCAPA 7 AVSS 8 Figure 41. Typical Connection Diagram Rev. 0 | Page 18 of 64 0.1µF 1µF 12911-040 • • The AD7175-8 includes a precision 2.5 V low drift (±2 ppm/°C) band gap internal reference. This reference can used for the ADC conversions, reducing the external component count. Alternatively, the reference can be output to the REFOUT pin to be used as a low noise biasing voltage for external circuitry. An example of this is using the REFOUT signal to set the input common mode for an external amplifier. Data Sheet AD7175-8 The linear regulator for the digital IOVDD supply performs a similar function, regulating the input voltage applied at the IOVDD pin to 1.8 V for the internal digital filtering. The serial interface signals always operate from the IOVDD supply seen at the pin. This means that if 3.3 V is applied to the IOVDD pin, the interface logic inputs and outputs operate at this level. Fast scanning of analog input channels using the internal multiplexer Fast scanning of analog input channels using an external multiplexer with automatic control from the GPIOs. High resolution at lower speeds in either channel scanning or ADC per channel applications High resolution applications requiring a highly integrated solution to save printed circuit board (PCB) area POWER SUPPLIES The AD7175-8 has three independent power supplies: AVDD1, AVDD2, and IOVDD. AVDD1 powers the crosspoint multiplexer and integrated analog and reference input buffers. AVDD1 is referenced to AVSS, and AVDD1 − AVSS = 5 V only. AVDD1 − AVSS can be a single 5 V supply or a ±2.5 V split supply. The split supply operation allows true bipolar inputs. When using split supplies, consider the absolute maximum ratings (see the Absolute Maximum Ratings section). 12911-052 Figure 42. SPI Mode 3 SCLK Edges Accessing the ADC Register Map The communications register controls access to the full register map of the ADC. This register is an 8-bit write only register. On power-up or after a reset, the digital interface defaults to a state where it is expecting a write to the communications register; therefore, all communication begins by writing to the communications register. The data written to the communications register determines which register is being accessed and if the next operation is a read or write. The register address bits (RA[5:0]) determine the specific register to which the read or write operation applies. When the read or write operation to the selected register is complete, the interface returns to its default state, where it expects a write operation to the communications register. Figure 43 and Figure 44 illustrate writing to and reading from a register by first writing the 8-bit command to the communications register, followed by the data for that register. 8-BIT COMMAND 8 BITS, 16 BITS, OR 24 BITS OF DATA CMD DATA CS AVDD2 powers the internal 1.8 V analog LDO regulator. This regulator powers the ADC core. AVDD2 is referenced to AVSS, and AVDD2 − AVSS can range from 2 V (minimum) to 5.5 V (maximum). IOVDD powers the internal 1.8 V digital LDO regulator. This regulator powers the digital logic of the ADC. IOVDD sets the voltage levels for the SPI interface of the ADC. IOVDD is referenced to DGND, and IOVDD − DGND can vary from 2 V (minimum) to 5.5 V (maximum). SAMPLE EDGE DIN SCLK 12911-053 The AD7175-8 can be used across a wide variety of applications, providing high resolution and accuracy. A sample of these scenarios is as follows: DRIVE EDGE Figure 43. Writing to a Register (8-Bit Command with Register Address Followed by Data of 8, 16, or 24 Bits; Data Length on DIN Is Dependent on the Register Selected) There is no specific requirement for a power supply sequence on the AD7175-8. When all power supplies are stable, a device reset is required; see the AD7175-8 Reset section for details on how to reset the device. 8-BIT COMMAND 8 BITS, 16 BITS, 24 BITS, OR 32 BITS OUTPUT CS DIGITAL COMMUNICATION DIN DOUT/RDY SCLK CMD DATA 12911-054 The AD7175-8 has a 3- or 4-wire SPI interface that is compatible with QSPI™, MICROWIRE®, and DSPs. The interface operates in SPI Mode 3 and can be operated with CS tied low. In SPI Mode 3, SCLK idles high, the falling edge of SCLK is the drive edge, and the rising edge of SCLK is the sample edge. This means that data is clocked out on the falling/drive edge and data is clocked in on the rising/sample edge. Figure 44. Reading from a Register (8-Bit Command with Register Address Followed by Data of 8, 16, or 24 Bits; Data Length on DOUT Is Dependent on the Register Selected) Rev. 0 | Page 19 of 64 AD7175-8 Data Sheet Figure 45 shows an overview of the suggested flow for changing the ADC configuration, divided into the following three blocks: Reading the ID register is the recommended method for verifying correct communication with the device. The ID register is a read only register and contains the value 0x3CDx for the AD7175-8. The communications register and the ID register details are described in Table 8 and Table 9, respectively. • • • AD7175-8 RESET In situations where interface synchronization is lost, a write operation of at least 64 serial clock cycles with DIN high returns the ADC to its default state by resetting the entire device, including the register contents. Alternatively, if CS is being used with the digital interface, returning CS high sets the digital interface to its default state and halts any serial interface operation. Channel Configuration The AD7175-8 has 16 independent channels and 8 independent setups. The user can select any of the analog input pairs on any channel, as well as any of the eight setups for any channel, giving the user full flexibility in the channel configuration. This also allows per channel configuration for up to eight channels when using differential inputs or single-ended inputs. Channel configuration can be shared across multiple channels. CONFIGURATION OVERVIEW After power-on or reset, the AD7175-8 default configuration are as follows. Note that only a few of the register setting options are shown; this list is just an example. For full register information, see the Register Details section. • • • • Channel Registers The channel registers are used to select which of the 17 analog input pins (AIN0 to AIN16) are used as either the positive analog input (AIN+) or the negative analog input (AIN−) for that channel. This register also contains a channel enable/disable bit and the setup selection bits, which are used to select from the eight available setups for this channel. Channel configuration. CH0 is enabled, AIN0 is selected as the positive input, and AIN1 is selected as the negative input. Setup 0 is selected. Setup configuration. The internal reference and the analog input buffers are enabled. The reference input buffers are disabled. Filter configuration. The sinc5 + sinc 1 filter is selected and the maximum output data rate is selected. ADC mode. Continuous conversion mode and the internal oscillator are enabled. Interface mode. CRC and the data + status output are disabled. When the AD7175-8 is operating with more than one channel enabled, the channel sequencer cycles through the enabled channels in sequential order, from Channel 0 to Channel 15. If a channel is disabled, it is skipped by the sequencer. Details of the channel register for Channel 0 are shown in Table 10. A CHANNEL CONFIGURATION SELECT POSITIVE AND NEGATIVE INPUT FOR EACH ADC CHANNEL SELECT ONE OF 8 SETUPS FOR ADC CHANNEL B SETUP CONFIGURATION 8 POSSIBLE ADC SETUPS SELECT FILTER ORDER, OUTPUT DATA RATE, AND MORE C ADC MODE AND INTERFACE MODE CONFIGURATION SELECT ADC OPERATING MODE, CLOCK SOURCE, ENABLE CRC, DATA + STATUS, AND MORE 12911-044 • Channel configuration (see Box A in Figure 45) Setup configuration (see Box B in Figure 45) ADC mode and interface mode configuration (see Box C in Figure 45) Figure 45. Suggested ADC Configuration Flow Table 8. Communications Register Reg. 0x00 Name COMMS Bits [7:0] Bit 7 WEN Bit 6 R/W Bit 5 Bits [15:8] [7:0] Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset 0x00 RW W Bit 2 Bit 1 Bit 0 Reset 0x3CDx RW R Bit 2 Reserved AINNEG0 Bit 1 Bit 0 AINPOS0[4:3] Reset 0x8001 RW RW RA Table 9. ID Register Reg. 0x07 Name ID Bit 4 Bit 3 ID[15:8] ID[7:0] Table 10. Channel 0 Register Reg. 0x10 Name CH0 Bits [15:8] [7:0] Bit 7 CH_EN0 Bit 6 Bit 5 Bit 4 Reserved SETUP_SEL[2:0] AINPOS0[2:0] Bit 3 Rev. 0 | Page 20 of 64 Data Sheet AD7175-8 ADC Setups Setup Configuration Registers The AD7175-8 has eight independent setups. Each setup consists of the following four registers: The setup configuration registers allow the user to select the output coding of the ADC by selecting between bipolar mode and unipolar mode. In bipolar mode, the ADC accepts negative differential input voltages, and the output coding is offset binary. In unipolar mode, the ADC accepts only positive differential voltages, and the coding is straight binary. In either case, the input voltage must be within the AVDD1/ AVSS supply voltages. The user can select the reference source using these registers. Three options are available: an internal 2.5 V reference, an external reference connected between the REF+ and REF− pins, or AVDD1 − AVSS. The analog input and reference input buffers can also be enabled or disabled using this register. Setup configuration register Filter configuration register Gain register Offset register For example, Setup 0 consists of Setup Configuration Register 0, Filter Configuration Register 0, Gain Register 0, and Offset Register 0. Figure 46 shows the grouping of these registers. The setup is selectable from the channel registers (see the Channel Configuration section), which allows each channel to be assigned to one of eight separate setups. Table 11 through Table 14 show the four registers associated with Setup 0. This structure is repeated for Setup 1 to Setup 3. SETUP CONFIG REGISTERS Filter Configuration Registers The filter configuration registers select which digital filter is used at the output of the ADC modulator. The order of the filter and the output data rate is selected by setting the bits in this register. For more information, see the Digital Filters section. FILTER CONFIG REGISTERS GAIN REGISTERS* OFFSET REGISTERS SETUPCON0 0x20 FILTCON0 0x28 GAIN0 0x38 OFFSET0 0x30 SETUPCON1 0x21 FILTCON1 0x29 GAIN1 0x39 OFFSET1 0x31 SETUPCON2 0x22 FILTCON2 0x2A GAIN2 0x3A OFFSET2 0x32 SETUPCON3 0x23 FILTCON3 0x2B GAIN3 0x3B OFFSET3 0x33 SETUPCON4 0x24 FILTCON4 0x2C GAIN4 0x3C OFFSET4 0x34 SETUPCON5 0x25 FILTCON5 0x2D GAIN5 0x3D OFFSET5 0x35 SETUPCON6 0x26 FILTCON6 0x2E GAIN6 0x3E OFFSET6 0x36 SETUPCON7 0x27 FILTCON7 0x2F GAIN7 0x3F INPUT BUFFERS REFERENCE BUFFERS BURNOUT REFERENCE SOURCE SELECT DIGITAL FILTER TYPE AND OUTPUT DATA RATE GAIN CORRECTION OPTIONALLY PROGRAMMED PER SETUP AS REQUIRED (*FACTORY CALIBRATED) OFFSET7 0x37 OFFSET CORRECTION OPTIONALLY PROGRAMMED PER SETUP AS REQUIRED SINC5 + SINC1 SINC3 SINC3 MAP ENHANCED 50Hz AND 60Hz 12911-045 SELECT PERIPHERAL FUNCTIONS FOR ADC CHANNEL Figure 46. ADC Setup Register Grouping Table 11. Setup Configuration 0 Register Reg. 0x20 Name Bits Bit 7 SETUPCON0 [15:8] [7:0] Bit 6 Reserved BURNOUT_EN0 Reserved Bit 5 Bit 4 Bit 3 BI_UNIPOLAR0 REFBUF0+ REF_SEL0 Bit 2 Bit 1 REFBUF0− AINBUF0+ Bit 0 AINBUF0− Reset 0x1320 RW RW Reset 0x0500 RW RW Reserved Table 12. Filter Configuration 0 Register Reg. 0x28 Name FILTCON0 Bits Bit 7 [15:8] SINC3_MAP0 [7:0] Reserved Bit 6 Bit 5 Bit 4 Reserved ORDER0 Bit 3 Bit 2 ENHFILTEN0 ODR0 Bit 1 Bit 0 ENHFILT0 Table 13. Gain Configuration 0 Register Reg. 0x38 Name GAIN0 Bits [23:0] Bit[23:0] GAIN0[23:0] Reset RW 0x5XXXX0 RW Bit[23:0] OFFSET0[23:0] Reset RW 0x800000 RW Table 14. Offset Configuration 0 Register Reg. 0x30 Name OFFSET0 Bits [23:0] Rev. 0 | Page 21 of 64 AD7175-8 Data Sheet Gain Registers ADC Mode and Interface Mode Configuration The gain registers are 24-bit registers that hold the gain calibration coefficient for the ADC. The gain registers are read/write registers. These registers are configured at power-on with factory calibrated coefficients. Therefore, every device has different default coefficients. The default value is automatically overwritten if a system full-scale calibration is initiated by the user or if the gain register is written to by the user. For more information on calibration, see the Operating Modes section. The ADC mode register and the interface mode register configure the core peripherals for use by the AD7175-8 and the mode for the digital interface. ADC Mode Register The ADC mode register primarily sets the conversion mode of the ADC to either continuous or single conversion. The user can also select the standby and power-down modes, as well as any of the calibration modes. In addition, this register contains the clock source select bits and the internal reference enable bits. The reference select bits are contained in the setup configuration registers (see the ADC Setups section for more information). Offset Registers The offset registers hold the offset calibration coefficient for the ADC. The power-on reset value of the offset registers is 0x800000. The offset registers are 24-bit read/write registers. The poweron reset value is automatically overwritten if an internal or system zero-scale calibration is initiated by the user or if the offset registers are written to by the user. Interface Mode Register The interface mode register configures the digital interface operation. This register allows the user to control data-word length, CRC enable, data + status read, and continuous read mode. The details of the ADC mode and interface mode registers are shown in Table 15 and Table 16, respectively. For more information, see the Digital Interface section. Table 15. ADC Mode Register Reg. 0x01 Name ADCMODE Bits [15:8] [7:0] Bit 7 REF_EN Reserved Bit 6 HIDE_DELAY Bit 5 SING_CYC Mode Bit 4 Bit 3 Reserved Bit 2 CLOCKSEL Bit 1 Bit 0 Delay Reserved Reset 0xA000 RW RW Reset 0x0000 RW RW Table 16. Interface Mode Register Reg. 0x02 Name IFMODE Bits [15:8] [7:0] Bit 7 CONTREAD Bit 6 Reserved DATA_STAT Bit 5 REG_CHECK Bit 4 ALT_SYNC Reserved Bit 3 Bit 2 Bit 1 IOSTRENGTH Reserved CRC_EN Reserved Rev. 0 | Page 22 of 64 Bit 0 DOUT_RESET WL16 Data Sheet AD7175-8 Understanding Configuration Flexibility The most straightforward implementation of the AD7175-8 is to use eight differential inputs with adjacent analog inputs and run all of them with the same setup, gain correction, and offset correction register. In this case, the user selects the following differential inputs: AIN0/AIN1, AIN2/AIN3, AIN4/AIN5, AIN6/AIN7, AIN8/AIN9, AIN10/AIN11, AIN12/AIN13, and AIN14/AIN15. In Figure 47, the registers shown in black font must be programmed for such a configuration. The registers shown in gray font are redundant in this configuration. Programming the gain and offset registers is optional for any use case, as indicated by the dashed lines between the register blocks. An alternative way to implement these eight fully differential inputs is by taking advantage of the eight available setups. Motivation for doing this includes having a different speed/noise requirement on some of the eight differential inputs vs. other inputs, or there may be a specific offset or gain correction for particular channels. Figure 48 shows how each of the differential inputs may use a separate setup, allowing full flexibility in the configuration of each channel. CHANNEL REGISTERS AIN0 CH0 0x10 AIN1 CH1 0x11 AIN2 CH2 0x12 AIN3 CH3 0x13 AIN4 CH4 0x14 AIN6 AIN7 AIN8 AIN9 CH5 CH6 CH7 CH8 CH9 GAIN REGISTERS* OFFSET REGISTERS SETUPCON0 0x20 FILTCON0 0x28 GAIN0 0x38 OFFSET0 0x30 SETUPCON1 0x21 FILTCON1 0x29 GAIN1 0x39 OFFSET1 0x31 SETUPCON2 0x22 FILTCON2 0x2A GAIN2 0x3A OFFSET2 0x32 SETUPCON3 0x23 FILTCON3 0x2B GAIN3 0x3B OFFSET3 0x33 SETUPCON4 0x24 FILTCON4 0x2C GAIN4 0x3C OFFSET4 0x34 SETUPCON5 0x25 FILTCON5 0x2D GAIN5 0x3D OFFSET5 0x35 SETUPCON6 0x26 FILTCON6 0x2E GAIN6 0x3E OFFSET6 0x36 SETUPCON7 0x27 FILTCON7 0x2F GAIN7 0x3F OFFSET7 0x37 0x15 0x16 0x17 0x18 0x19 AIN10 CH10 0x1A AIN11 CH11 0x1B AIN12 CH12 0x1C AIN13 CH13 0x1D AIN14 CH14 0x1E AIN15 CH15 0x1F AIN16 FILTER CONFIG REGISTERS SELECT ANALOG INPUT PAIRS ENABLE THE CHANNEL SELECT SETUP 0 SELECT PERIPHERAL FUNCTIONS FOR ADC CHANNEL INPUT BUFFERS REFERENCE BUFFERS BURNOUT REFERENCE SOURCE SELECT DIGITAL FILTER TYPE AND OUTPUT DATA RATE 250kSPS TO 5SPS SINC5 + SINC1 SINC3 OFFSET CORRECTION GAIN CORRECTION OPTIONALLY OPTIONALLY PROGRAMMED PROGRAMMED PER SETUP AS REQUIRED PER SETUP AS REQUIRED (*FACTORY CALIBRATED) 12911-046 AIN5 SETUP CONFIG REGISTERS SINC3 MAP ENHANCED 50Hz AND 60Hz Figure 47. Eight Fully Differential Inputs, All Using a Single Setup (SETUPCON0; FILTCON0; GAIN0; OFFSET0) CHANNEL REGISTERS CH0 0x10 AIN1 CH1 0x11 AIN2 CH2 0x12 AIN3 CH3 0x13 AIN4 CH4 0x14 AIN5 CH5 0x15 AIN6 CH6 0x16 AIN7 AIN8 CH7 0x17 CH8 0x18 AIN9 CH9 0x19 AIN10 CH10 0x1A AIN11 CH11 0x1B AIN12 CH12 0x1C AIN13 CH13 0x1D AIN14 CH14 0x1E AIN15 CH15 0x1F AIN16 SELECT ANALOG INPUT PAIRS ENABLE THE CHANNEL SELECT SETUP SETUP CONFIG REGISTERS FILTER CONFIG REGISTERS GAIN REGISTERS* SETUPCON0 0x20 FILTCON0 0x28 GAIN0 SETUPCON1 0x21 FILTCON1 0x29 SETUPCON2 0x22 FILTCON2 0x2A SETUPCON3 0x23 OFFSET REGISTERS 0x38 OFFSET0 0x30 GAIN1 0x39 OFFSET1 0x31 GAIN2 0x3A OFFSET2 0x32 FILTCON3 0x2B GAIN3 0x3B OFFSET3 0x33 SETUPCON4 0x24 FILTCON4 0x2C GAIN4 0x3C OFFSET4 0x34 SETUPCON5 0x25 FILTCON5 0x2D GAIN5 0x3D OFFSET5 0x35 SETUPCON6 0x26 FILTCON6 0x2E GAIN6 0x3E OFFSET6 0x36 SETUPCON7 0x27 FILTCON7 0x2F GAIN7 0x3F OFFSET7 0x37 SELECT PERIPHERAL FUNCTIONS FOR ADC CHANNEL INPUT BUFFERS REFERENCE BUFFERS BURNOUT REFERENCE SOURCE SELECT DIGITAL FILTER TYPE AND OUTPUT DATA RATE 250kSPS TO 5SPS SINC5 + SINC1 SINC3 OFFSET CORRECTION GAIN CORRECTION OPTIONALLY OPTIONALLY PROGRAMMED PROGRAMMED PER SETUP AS REQUIRED PER SETUP AS REQUIRED (*FACTORY CALIBRATED) SINC3 MAP ENHANCED 50Hz AND 60Hz Figure 48. Eight Fully Differential Inputs with a Setup per Channel Rev. 0 | Page 23 of 64 12911-047 AIN0 AD7175-8 Data Sheet Figure 49 shows an example of how the channel registers span between the analog input pins and the setup configurations downstream. In this random example, seven differential inputs and two single-ended inputs are required. The single-ended inputs are the AIN8/AIN16 and AIN15/AIN16 combinations. The first five differential input pairs (AIN0/AIN1, AIN2/AIN3, AIN4/AIN5, AIN6/AIN7, and AIN9/AIN10) use the same setup: SETUPCON0. The two single-ended input pairs (AIN8/AIN16 and AIN15/ AIN16) are set up as a diagnostics; therefore, use a separate setup: SETUPCON1. The final two differential inputs (AIN11/AIN12 and AIN13/AIN14) also use a separate setup: SETUPCON2. Given that three setups are selected for use, the SETUPCON0, SETUPCON1, and SETUPCON2 registers are programmed as required, and the FILTCON0, FILTCON1, and FILTCON2 registers are also programmed as required. Optional gain and offset correction can be employed on a per setup basis by programming the GAIN0, GAIN1, and GAIN2 registers and the OFFSET0, OFFSET1, and OFFSET2 registers. In the example shown in Figure 49, the CH0 to CH8 registers are used. Setting the MSB in each of these registers, the CH_EN0 to CH_EN8 bits, enables the nine combinations via the crosspoint multiplexer. When the AD7175-8 converts, the sequencer transitions in ascending sequential order from CH0 to CH1 to CH2, and then on to CH8 before looping back to CH0 to repeat the sequence. CHANNEL REGISTERS AIN0 CH0 0x10 AIN1 CH1 0x11 AIN2 CH2 0x12 AIN3 CH3 0x13 AIN4 CH4 0x14 AIN6 AIN7 AIN8 AIN9 AIN10 AIN11 AIN12 CH5 CH6 CH7 GAIN REGISTERS* OFFSET REGISTERS SETUPCON0 0x20 FILTCON0 0x28 GAIN0 0x38 OFFSET0 0x30 SETUPCON1 0x21 FILTCON1 0x29 GAIN1 0x39 OFFSET1 0x31 SETUPCON2 0x22 FILTCON2 0x2A GAIN2 0x3A OFFSET2 0x32 SETUPCON3 0x23 FILTCON3 0x2B GAIN3 0x3B OFFSET3 0x33 SETUPCON4 0x24 FILTCON4 0x2C GAIN4 0x3C OFFSET4 0x34 SETUPCON5 0x25 FILTCON5 0x2D GAIN5 0x3D OFFSET5 0x35 SETUPCON6 0x26 FILTCON6 0x2E GAIN6 0x3E OFFSET6 0x36 SETUPCON7 0x27 FILTCON7 0x2F GAIN7 0x3F OFFSET7 0x37 0x15 0x16 0x17 CH8 0x18 CH9 0x19 CH10 0x1A CH11 0x1B CH12 0x1C AIN13 CH13 0x1D AIN14 CH14 0x1E AIN15 CH15 0x1F AIN16 FILTER CONFIG REGISTERS SELECT ANALOG INPUT PAIRS ENABLE THE CHANNEL SELECT SETUP SELECT PERIPHERAL FUNCTIONS FOR ADC CHANNEL INPUT BUFFERS REFERENCE BUFFERS BURNOUT REFERENCE SOURCE SELECT DIGITAL FILTER TYPE AND OUTPUT DATA RATE 250kSPS TO 5SPS SINC5 + SINC1 SINC3 OFFSET CORRECTION GAIN CORRECTION OPTIONALLY OPTIONALLY PROGRAMMED PROGRAMMED PER SETUP AS REQUIRED PER SETUP AS REQUIRED (*FACTORY CALIBRATED) SINC3 MAP ENHANCED 50Hz AND 60Hz Figure 49. Mixed Differential and Single-Ended Configuration Using Multiple Shared Setups Rev. 0 | Page 24 of 64 12911-048 AIN5 SETUP CONFIG REGISTERS Data Sheet AD7175-8 CIRCUIT DESCRIPTION BUFFERED ANALOG INPUT AVDD1 The AD7175-8 has true rail-to-rail, integrated, precision unitygain buffers on both ADC analog inputs. The buffers provide the benefit of giving the user high input impedance with only ±30 nA typical input current, allowing high impedance sources to be connected directly to the analog inputs. The buffers fully drive the internal ADC switch capacitor sampling network, simplifying the analog front-end circuit requirements while consuming a very efficient 2.9 mA typical per buffer. Each analog input buffer amplifier is fully chopped, meaning that it minimizes the offset error drift and 1/f noise of the buffer. The 1/f noise profile of the ADC and buffer combined is shown in Figure 50. AIN0 AVSS AVDD1 Ø1 +IN AIN1 CS1 AVSS Ø2 Ø2 AVDD1 CS2 AIN14 AVSS 0 AVDD1 Ø1 –IN AIN15 –50 AVDD1 –100 AIN16 –150 AVSS 12911-050 AMPLITUDE (dB) AVSS Figure 51. Simplified Analog Input Circuit –250 0.1 1 10 100 1k 10k FREQUENCY (Hz) 12911-259 –200 Figure 50. Shorted Input FFT (Analog Input Buffers Enabled) The CS1 and CS2 capacitors each have a magnitude in the order of a number of picofarads. This capacitance is the combination of both the sampling capacitance and the parasitic capacitance. Fully Differential Inputs Because the AIN0 to AIN16 analog inputs are connected to a crosspoint multiplexer, any combination of signals can be used to create an analog input pair. This crosspoint multiplexer allows the user to select eight fully differential inputs or 16 single-ended inputs. The analog input buffers do not suffer from linearity degradation when operating at the rails, unlike many discrete amplifiers. When operating at or close to the AVDD1 and AVSS supply rails, there is an increase in input current. This increase is most notable at higher temperatures. Figure 40 shows the analog input current for various conditions. With the analog input buffers disabled, the average input current to the AD7175-8 changes linearly with the differential input voltage at a rate of ±48 µA/V. If eight fully differential input paths are connected to the AD7175-8, using adjacent analog input pins such as AIN0/AIN1 for the differential input pair is recommended. This is due to the relative locations of these pins to each other. Decouple all analog inputs to AVSS. CROSSPOINT MULTIPLEXER Single-Ended Inputs There are 17 analog input pins: AIN0 to AIN16. Each of these pins connects to the internal crosspoint multiplexer. The crosspoint multiplexer enables any of these inputs to be configured as an input pair, either single-ended or fully differential. The AD7175-8 can have up to 16 active channels. When more than one channel is enabled, the channels are automatically sequenced in order from the lowest enabled channel number to the highest enabled channel number. The output of the multiplexer is connected to the input of the integrated true rail-to-rail buffers. These can be bypassed and the multiplexer output can be directly connected to the switched-capacitor input of the ADC. The simplified analog input circuit is shown in Figure 51. The user can also choose to measure 16 different single-ended analog inputs. In this case, each of the analog inputs is converted as the difference between the single-ended input to be measured and a set analog input common pin. Because there is a crosspoint multiplexer, the user can set any of the analog inputs as the common pin. An example of such a scenario is to connect the AIN8 pin to AVSS or to the REFOUT voltage (that is, AVSS + 2.5 V) and select this input when configuring the crosspoint multiplexer. When using the AD7175-8 with single-ended inputs. Rev. 0 | Page 25 of 64 AD7175-8 Data Sheet AD7175-8 REFERENCE REF−/REF2− pin is connected directly to the AVSS potential. On power-up of the AD7175-8, the internal reference is enabled by default and is output on the REFOUT pin. When an external reference is used instead of the internal reference to supply the AD7175-8, attention must be paid to the output of the REFOUT pin. If the internal reference is not being used elsewhere in the application, ensure that the REFOUT pin is not hardwired to AVSS because this draws a large current on power-up. On power-up, if the internal reference is not being used, write to the ADC mode register, disabling the internal reference. This is controlled by the REF_EN bit (Bit 15) in the ADC mode register, which is shown in Table 18. The AD7175-8 offers the user the option of either supplying an external reference to the REF+ and REF− or REF2+ and REF2pins of the device or allowing the use of the internal 2.5 V, low noise, low drift reference. Select the reference source to be used by the analog input by setting the REF_SELx bits (Bits[5:4]) in the setup configuration registers appropriately. The structure of the Setup Configuration 0 register is shown in Table 17. The AD7175-8 defaults on power-up to use the internal 2.5 V reference. External Reference The AD7175-8 has a fully differential reference input applied through the REF+ and REF− or REF2+ and REF2 pins. Standard low noise, low drift voltage references, such as the ADR445, ADR444, and ADR441, are recommended for use. Apply the external reference to the AD7175-8 reference pins as shown in Figure 52. Decouple the output of any external reference to AVSS. As shown in Figure 52, the ADR445 output is decoupled with a 0.1 µF capacitor at its output for stability purposes. The output is then connected to a 4.7 µF capacitor, which acts as a reservoir for any dynamic charge required by the ADC, and followed by a 0.1 µF decoupling capacitor at the REF+ or REF2+ input. This capacitor is placed as close as possible to the REF+/REF2+ and REF−/REF2− pins. The Internal Reference The AD7175-8 includes its own low noise, low drift voltage reference. The internal reference has a 2.5 V output. The internal reference is output on the REFOUT pin after the REF_EN bit in the ADC mode register is set and is decoupled to AVSS with a 0.1 µF capacitor. The AD7175-8 internal reference is enabled by default on power-up and is selected as the reference source for the ADC. When using the internal reference, the INL performance degrades as shown in Figure 23. The REFOUT signal is buffered before being output to the pin. The signal can be used externally in the circuit as a common-mode source for external amplifier configurations. AD7175-8 5.5V TO 18V ADR4452 0.1µF 0.1µF 5V VREF 1 4.7µF 1 1 40 REF+ 39 REF– 0.1µF 1 FAMILY OF REFERENCES CAN BE USED. THE ADR444 AND ADR441 BOTH ENABLE REUSE OF THE 5V ANALOG SUPPLY NEEDED FOR AVDD1 TO POWER THE REFERENCE VIN. 12911-159 1 1ALL DECOUPLING IS TO AVSS. 2ANY OF THE ADRF440/ADR441/ADR443/ADR444/ADR445 Figure 52. External Reference ADR445 Connected to the AD7175-8 Reference Pins Table 17. Setup Configuration 0 Register Reg. 0x20 Name SETUPCON0 Bits [15:8] [7:0] Bit 7 Bit 6 Reserved BURNOUT_EN0 Reserved Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset RW BI_UNIPOLAR0 REFBUF0+ REFBUF0− AINBUF0+ AINBUF0− 0x1320 RW REF_SEL0 Reserved Table 18. ADC Mode Register Reg. 0x01 Name ADCMODE Bits [15:8] [7:0] Bit 7 REF_EN Reserved Bit 6 HIDE_DELAY Bit 5 SING_CYC Mode Bit 4 Bit 3 Reserved Rev. 0 | Page 26 of 64 Bit 2 CLOCKSEL Bit 1 Bit 0 Delay Reserved Reset 0xA000 RW RW Data Sheet AD7175-8 BUFFERED REFERENCE INPUT The AD7175-8 has true rail-to-rail, integrated, precision unity gain buffers on both ADC reference inputs. The buffers provide the benefit of giving the user high input impedance and allow high impedance external sources to be directly connected to the reference inputs. The integrated reference buffers can fully drive the internal reference switch capacitor sampling network, simplifying the reference circuit requirements while consuming a very efficient 2.9 mA typical per buffer. Each reference input buffer amplifier is fully chopped, meaning that it minimizes the offset error drift and 1/f noise of the buffer. When using an external reference, such as the ADR445, ADR444, and ADR441, these buffers are not required because these references, with proper decoupling, can drive the reference inputs directly. CLOCK SOURCE The AD7175-8 uses a nominal master clock of 16 MHz. The AD7175-8 sources its sampling clock from one of three sources: External Crystal If higher precision, lower jitter clock sources are required, the AD7175-8 can use an external crystal to generate the master clock. The crystal is connected to the XTAL1 and XTAL2/CLKIO pins. A recommended crystal for use is the FA-20H—a 16 MHz, 10 ppm, 9 pF crystal from Epson-Toyocom—which is available in a surface-mount package. As shown in Figure 53, insert two capacitors from the traces connecting the crystal to the XTAL1 and XTAL2/CLKIO pins. These capacitors allow for circuit tuning. Connect these capacitors to the DGND pin. The value for these capacitors depends on the length and capacitance of the trace connections between the crystal and the XTAL1 and XTAL2/CLKIO pins. Therefore, the values of these capacitors differ depending on the PCB layout and the crystal employed. AD7175-8 Cx1 Internal oscillator External crystal External clock source * XTAL1 12 XTAL2/CLKIO 13 All output data rates listed in the data sheet relate to a master clock rate of 16 MHz. Using a lower clock frequency from, for instance, an external source scales any listed data rate proportionally. To achieve the specified data rates, particularly rates for the rejection of 50 Hz and 60 Hz, use a 16 MHz clock. The source of the master clock is selected by setting the CLOCKSEL bits (Bits[3:2]) in the ADC mode register as shown in Table 18. The default operation on power-up and reset of the AD7175-8 is to operate with the internal oscillator. It is possible to fine tune the output data rate and filter notch at low output data rates using the SINC3_MAPx bit. See the Sinc3 Filter section for more information. Internal Oscillator The internal oscillator runs at 16 MHz and can be used as the ADC master clock. It is the default clock source for the AD7175-8 and is specified with an accuracy of ±2.5%. There is an option to allow the internal clock oscillator to be output on the XTAL2/CLKIO pin. The clock output is driven to the IOVDD logic level. Use of this option can affect the dc performance of the AD7175-8 due to the disturbance introduced by the output driver. The extent to which the performance is affected depends on the IOVDD voltage supply. Higher IOVDD voltages create a wider logic output swing from the driver and affect performance to a greater extent. This effect is further Cx2 * *DECOUPLE TO DGND. 12911-160 • • • exaggerated if the IOSTRENGTH bit is set at higher IOVDD levels (see Table 28 for more information). Figure 53. External Crystal Connections The external crystal circuitry can be sensitive to the SCLK edges, depending on SCLK frequency, IOVDD voltage, crystal circuitry layout, and the crystal used. During crystal startup, any disturbances caused by the SLCK edges may cause double edges on the crystal input, resulting in invalid conversions until the crystal voltage has reached a high enough level such that any interference from the SCLK edges is insufficient to cause double clocking. This double clocking can be avoided by ensuring that the crystal circuitry has reached a sufficient voltage level after startup before applying any SCLK signal. Due to the nature of the crystal circuitry, it is recommended that empirical testing of the circuit be performed under the required conditions, with the final PCB layout and crystal, to ensure correct operation. External Clock The AD7175-8 can also use an externally supplied clock. In systems where this is desirable, the external clock is routed to the XTAL2/CLKIO pin. In this configuration, the XTAL2/CLKIO pin accepts the externally sourced clock and routes it to the modulator. The logic level of this clock input is defined by the voltage applied to the IOVDD pin. Rev. 0 | Page 27 of 64 AD7175-8 Data Sheet DIGITAL FILTERS SINC3 FILTER The AD7175-8 has three flexible filter options to allow optimization of noise, settling time, and rejection. • • • The sinc3 filter achieves the best single-channel noise performance at lower rates and is, therefore, most suitable for single-channel applications. The sinc3 filter always has a settling time, tSETTLE, equal to Sinc5 + sinc1 filter Sinc3 filter Enhanced 50 Hz and 60 Hz rejection filters tSETTLE = 3/Output Data Rate SINC3 Figure 56 shows the frequency domain filter response for the sinc3 filter. The sinc3 filter has good roll-off over frequency and has wide notches for good notch frequency rejection. 0 –10 Figure 54. Digital Filter Block Diagram –20 SINC5 + SINC1 FILTER The sinc5 + sinc1 filter is targeted at multiplexed applications and achieves single cycle settling at output data rates of 10 kSPS and lower. The sinc5 block output is fixed at the maximum rate of 250 kSPS, and the sinc1 block output data rate can be varied to control the final ADC output data rate. Figure 55 shows the frequency domain response of the sinc5 + sinc1 filter at a 50 SPS ODR. The sinc5 + sinc1 filter has a slow roll-off over frequency and narrow notches. 0 FILTER GAIN (dB) –20 –40 –30 FILTER GAIN (dB) The filter and output data rate are configured by setting the appropriate bits in the filter configuration register for the selected setup. Each channel can use a different setup and therefore, a different filter and output data rate. See the Register Details section for more information. –40 –50 –60 –70 –80 –90 –100 –110 –120 0 50 The ODRs with the accompanying settling time and rms noise for the sinc3 filter are shown in Table 21 and Table 22. It is possible to finely tune the output data rate for the sinc3 filter by setting the SINC3_MAPx bits in the filter configuration registers. If this bit is set, the mapping of the filter register changes to directly program the decimation rate of the sinc3 filter. All other options are eliminated. The data rate when on a single channel can be calculated using the following equation: Output Data Rate = –80 0 50 100 150 FREQUENCY (Hz) 12911-059 –120 Figure 55. Sinc5 + Sinc1 Filter Response at 50 SPS ODR The ODRs with the accompanying settling time and rms noise for the sinc5 + sinc1 filter are shown in Table 19 and Table 20. 150 Figure 56. Sinc3 Filter Response –60 –100 100 FREQUENCY (Hz) 12911-060 SINC1 12911-058 SINC5 50Hz AND 60Hz POSTFILTER f MOD 32 × FILTCONx[14:0] where: fMOD is the modulator rate (MCLK/2) and is 8 MHz for a 16 MHz MCLK. FILTCONx[14:0] are the contents on the filter configuration registers excluding the MSB. For example, an output data rate of 50 SPS can be achieved with SINC3_MAPx enabled by setting the FILTCONx[14:0] bits to a value of 5000. Rev. 0 | Page 28 of 64 Data Sheet AD7175-8 By default, the AD7175-8 is configured with the SING_CYC bit in the ADC mode register set so that only fully settled data is output, effectively putting the ADC into a single cycle settling mode. This mode achieves single cycle settling by reducing the output data rate to be equal to the settling time of the ADC for the selected output data rate. This bit has no effect with the sinc5 + sinc1 filter at output data rates of 10 kSPS and lower. Figure 58 shows the same step on the analog input but with single cycle settling enabled. The analog input requires at least a single cycle for the output to be fully settled. The output data rate, as indicated by the RDY signal, is now reduced to equal the settling time of the filter at the selected output data rate. ANALOG INPUT FULLY SETTLED ADC OUTPUT Figure 57 shows a step on the analog input with this mode disabled and the sinc3 filter selected. The analog input requires at least three cycles after the step change for the output to reach the final settled value. 12911-062 SINGLE CYCLE SETTLING tSETTLE Figure 58. Step Input with Single Cycle Settling ANALOG INPUT FULLY SETTLED 12911-061 ADC OUTPUT 1/ODR Figure 57. Step Input Without Single Cycle Settling Table 19. Output Data Rate, Settling Time, and Noise Using the Sinc5 + Sinc1 Filter with Input Buffers Disabled Default Output Data Rate (SPS/Channel); SING_CYC = 1 or with Multiple Channels Enabled1 50,000 41,667 31,250 27,778 20,833 17,857 12,500 10,000 5000 2500 1000 500.0 397.5 200.0 100 59.92 49.96 20.00 16.66 10.00 5.00 1 2 Output Data Rate (SPS); SING_CYC = 0 and Single Channel Enabled1 250,000 125,000 62,500 50,000 31,250 25,000 15,625 10,000 5000 2500 1000 500 397.5 200 100 59.92 49.96 20 16.66 10 5 Settling Time1 20 µs 24 µs 32 µs 36 µs 48 µs 56 µs 80 µs 100 µs 200 µs 400 µs 1.0 ms 2.0 ms 2.516 ms 5.0 ms 10 ms 16.67 ms 20.016 ms 50.0 ms 60.02 ms 100 ms 200 ms Notch Frequency (Hz) 250,000 125,000 62,500 50,000 31,250 25,000 15,625 11,905 5435 2604 1016 504 400.00 200.64 100.16 59.98 50.00 20.01 16.66 10.00 5.00 Noise (µV rms) 8.7 7.2 5.5 5 4 3.6 2.9 2.5 1.7 1.2 0.77 0.57 0.5 0.36 0.25 0.19 0.18 0.11 0.1 0.08 0.07 Effective Resolution with 5 V Reference (Bits) 20.1 20.4 20.8 20.9 21.3 21.4 21.7 21.9 22.5 23.0 23.6 24 24 24 24 24 24 24 24 24 24 Noise (µV p-p)2 65 60 43 41 32 29 22 18.3 12 8.2 5.2 3.2 3 2 1.3 1.1 0.95 0.6 0.45 0.4 0.34 Peak-to-Peak Resolution with 5 V Reference (Bits) 17.2 17.3 17.8 17.9 18.3 18.4 18.8 19.1 19.7 20.2 20.9 21.6 21.7 22.3 22.9 23.1 23.3 24 24 24 24 The settling time is rounded to the nearest microsecond. This is reflected in the output data rate and channel switching rate. Channel switching rate = 1 ÷ settling time. Measurement taken using 1000 samples. Rev. 0 | Page 29 of 64 AD7175-8 Data Sheet Table 20. Output Data Rate, Settling Time, and Noise Using the Sinc5 + Sinc1 Filter with Input Buffers Enabled Default Output Data Rate (SPS/Channel); SING_CYC = 1 or with Multiple Channels Enabled1 50,000 41,667 31,250 27,778 20,833 17,857 12,500 10,000 5000 2500 1000 500.0 397.5 200.0 100 59.92 49.96 20.00 16.66 10.00 5.00 1 2 Output Data Rate (SPS); SING_CYC = 0 and Single Channel Enabled1 250,000 125,000 62,500 50,000 31,250 25,000 15,625 10,000 5000 2500 1000 500 397.5 200 100 59.92 49.96 20 16.66 10 5 Settling Time1 20 µs 24 µs 32 µs 36 µs 48 µs 56 µs 80 µs 100 µs 200 µs 400 µs 1.0 ms 2.0 ms 2.516 ms 5.0 ms 10 ms 16.67 ms 20.016 ms 50.0 ms 60.02 ms 100 ms 200 ms Notch Frequency (Hz) 250,000 125,000 62,500 50,000 31,250 25,000 15,625 11,905 5435 2604 1016 504 400.00 200.64 100.16 59.98 50.00 20.01 16.66 10.00 5.00 Noise (µV rms) 9.8 8.4 6.4 5.9 4.8 4.3 3.4 3 2.1 1.5 0.92 0.68 0.6 0.43 0.32 0.23 0.2 0.14 0.13 0.1 0.07 Effective Resolution with 5 V Reference (Bits) 20 20.2 20.6 20.7 21 21.1 21.5 21.7 22.2 22.7 23.4 23.8 24 24 24 24 24 24 24 24 24 Noise (µV p-p)2 85 66 55 49 39 33 26 23 16 10 5.7 3.9 3.7 2.2 1.7 1.2 1 0.75 0.66 0.47 0.32 Peak-to-Peak Resolution with 5 V Reference (Bits) 16.8 17.2 17.5 17.6 18.0 18.2 18.6 18.7 19.3 19.9 20.7 21.3 21.4 22.1 22.5 23 23.3 23.7 23.9 24 24 The settling time is rounded to the nearest microsecond. This is reflected in the output data rate and channel switching rate. Channel switching rate = 1 ÷ settling time. Measurement taken using 1000 samples. Rev. 0 | Page 30 of 64 Data Sheet AD7175-8 Table 21. Output Data Rate, Settling Time, and Noise Using the Sinc3 Filter with Input Buffers Disabled Default Output Data Rate (SPS/Channel); SING_CYC = 1 or with Multiple Channels Enabled1 83,333 41,667 20,833 16,667 10,417 8333 5208 3333 1667 833 333.3 166.7 133.3 66.7 33.33 19.99 16.67 6.67 5.56 3.33 1.67 1 2 Output Data Rate (SPS); SING_CYC = 0 and Single Channel Enabled1 250,000 125,000 62,500 50,000 31,250 25,000 15,625 10,000 5000 2500 1000 500 400 200 100 60 50 20 16.67 10 5 Settling Time1 12 μs 24 μs 48 μs 60 μs 96 μs 120 μs 192 μs 300 μs 6 μs 1.2 ms 3 ms 6 ms 7.5 ms 15 ms 30 ms 50.02 ms 60 ms 150 ms 180 ms 300 ms 600 ms Notch Frequency (Hz) 250,000 125,000 62,500 50,000 31,250 25,000 15,625 10,000 5000 2500 1000 500 400 200 100 59.98 50 20 16.67 10 5 Noise (μV rms) 210 28 5.2 4.2 3.2 2.9 2.2 1.8 1.3 0.91 0.56 0.44 0.4 0.25 0.2 0.13 0.13 0.08 0.07 0.06 0.05 Effective Resolution with 5 V Reference (Bits) 15.5 18.4 20.9 21.2 21.6 21.7 22.1 22.4 22.9 23.4 24 24 24 24 24 24 24 24 24 24 24 Noise (μV p-p)2 1600 200 40 34 26 23 17 14 9.5 6 3.9 2.5 2.3 1.4 1 0.8 0.7 0.42 0.37 0.28 0.21 Peak-to-Peak Resolution with 5 V Reference (Bits) 12.6 15.6 17.9 18.2 18.6 18.7 19.2 19.4 20 20.7 21.3 21.9 22.1 22.8 23.3 23.6 23.8 24 24 24 24 The settling time is rounded to the nearest microsecond. This is reflected in the output data rate and channel switching rate. Channel switching rate = 1 ÷ settling time. Measurement taken using 1000 samples. Rev. 0 | Page 31 of 64 AD7175-8 Data Sheet Table 22. Output Data Rate, Settling Time, and Noise Using the Sinc3 Filter with Input Buffers Enabled Default Output Data Rate (SPS/Channel); SING_CYC = 1 or with Multiple Channels Enabled1 83,333 41,667 20,833 16,667 10,417 8333 5208 3333 1667 833 333.3 166.7 133.3 66.7 33.33 19.99 16.67 6.67 5.56 3.33 1.67 1 2 Output Data Rate (SPS); SING_CYC = 0 and Single Channel Enabled1 250,000 125,000 62,500 50,000 31,250 25,000 15,625 10,000 5000 2500 1000 500 400 200 100 60 50 20 16.67 10 5 Settling Time1 12 µs 24 µs 48 µs 60 µs 96 µs 120 µs 192 µs 300 µs 6 µs 1.2 ms 3 ms 6 ms 7.5 ms 15 ms 30 ms 50.02ms 60 ms 150 ms 180 ms 300 ms 600 ms Notch Frequency (Hz) 250,000 125,000 62,500 50,000 31,250 25,000 15,625 10,000 5000 2500 1000 500 400 200 100 59.98 50 20 16.67 10 5 Noise (µV rms) 210 28 5.8 4.9 3.8 3.4 2.6 2.1 1.5 1.1 0.71 0.52 0.41 0.32 0.2 0.17 0.15 0.13 0.12 0.1 0.08 Effective Resolution with 5 V Reference (Bits) 15.5 18.4 20.7 21 21.3 21.5 21.9 22.2 22.7 23.1 23.7 24 24 24 24 24 24 24 24 24 24 Noise (µV p-p)2 1600 210 48 41 30 26 18 16 11 7 4.5 3 2.7 1.8 1.2 1.1 0.83 0.61 0.6 0.55 0.35 Peak-to-Peak Resolution with 5 V Reference (Bits) 12.6 15.5 17.7 17.9 18.3 18.6 19.1 19.3 19.8 20.4 21.1 21.7 21.8 22.4 23 23.1 23.5 24 24 24 24 The settling time is rounded to the nearest microsecond. This is reflected in the output data rate and channel switching rate. Channel switching rate = 1 ÷ settling time. Measurement taken using 1000 samples. Rev. 0 | Page 32 of 64 Data Sheet AD7175-8 ENHANCED 50 HZ AND 60 HZ REJECTION FILTERS The enhanced filters are designed to provide rejection of 50 Hz and 60 Hz simultaneously and to allow the user to trade off settling time and rejection. These filters can operate at up to 27.27 SPS or can reject up to 90 dB of 50 Hz ± 1 Hz and 60 Hz ± 1 Hz interference. These filters are realized by postfiltering the output of the sinc5 + sinc1 filter. For this reason, the sinc5 + sinc1 filter must be selected when using the enhanced filters to achieve the specified settling time and noise performance. Table 23 shows the output data rates with the accompanying settling time, rejection, and rms noise. Figure 59 to Figure 66 show the frequency domain plots of the responses from the enhanced filters. Table 23. Enhanced Filters Output Data Rate, Noise, Settling Time, and Rejection Using the Enhanced Filters Output Data Rate (SPS) Input Buffers Disabled 27.27 25 20 16.667 Input Buffers Enabled 27.27 25 20 16.667 1 Settling Time (ms) Simultaneous Rejection of 50 Hz ± 1 Hz and 60 Hz ± 1 Hz (dB)1 Noise (μV rms) Peak-to-Peak Resolution (Bits) Comments 36.67 40.0 50.0 60.0 47 62 85 90 0.22 0.2 0.2 0.17 22.7 22.9 22.9 23 See Figure 59 and Figure 62 See Figure 60 and Figure 63 See Figure 61 and Figure 64 See Figure 65 and Figure 66 36.67 40.0 50.0 60.0 47 62 85 90 0.22 0.22 0.21 0.21 22.7 22.7 22.8 22.8 See Figure 59 and Figure 62 See Figure 60 and Figure 63 See Figure 61 and Figure 64 See Figure 65 and Figure 66 Master clock = 16 MHz. Rev. 0 | Page 33 of 64 Data Sheet 0 –10 –10 –20 –20 –30 –30 –40 –50 –60 –60 –70 –80 –80 –90 –90 0 100 200 300 400 500 600 FREQUENCY (Hz) –100 40 50 55 60 65 70 Figure 62. 27.27 SPS ODR, 36.67 ms Settling Time at 50 Hz/60 Hz 0 0 –10 –10 –20 FILTER GAIN (dB) –30 –40 –50 –60 –30 –40 –50 –60 –70 –70 –80 –80 –90 –100 –100 40 100 200 300 400 500 600 FREQUENCY (Hz) –10 –20 –20 –30 –30 FILTER GAIN (dB) 0 –10 –40 –50 –60 –90 –90 FREQUENCY (Hz) 600 12468-067 –80 500 70 –60 –80 400 65 –50 –70 300 60 –40 –70 200 55 Figure 63. 25 SPS ODR, 40 ms Settling Time at 50 Hz/60 Hz 0 100 50 FREQUENCY (Hz) Figure 60. 25 SPS ODR, 40 ms Settling Time 0 45 Figure 61. 20 SPS ODR, 50 ms Settling Time –100 40 45 50 55 60 65 FREQUENCY (Hz) Figure 64. 20 SPS ODR, 50 ms Settling Time at 50 Hz/60 Hz Rev. 0 | Page 34 of 64 70 12911-068 0 12911-065 –90 12911-066 –20 –100 45 FREQUENCY (Hz) Figure 59. 27.27 SPS ODR, 36.67 ms Settling Time FILTER GAIN (dB) –50 –70 –100 FILTER GAIN (dB) –40 12911-064 FILTER GAIN (dB) 0 12911-063 FILTER GAIN (dB) AD7175-8 AD7175-8 0 –10 –10 –20 –20 –30 –30 –40 –50 –60 –40 –50 –60 –70 –70 –80 –80 –90 –90 –100 –100 40 0 100 200 300 400 500 FREQUENCY (Hz) 600 Figure 65. 16.667 SPS ODR, 60 ms Settling Time 45 50 55 60 65 70 FREQUENCY (Hz) Figure 66. 16.667 SPS ODR, 60 ms Settling Time at 50 Hz/60 Hz Rev. 0 | Page 35 of 64 12911-070 FILTER GAIN (dB) 0 12911-069 FILTER GAIN (dB) Data Sheet AD7175-8 Data Sheet OPERATING MODES The AD7175-8 has a number of operating modes that can be set from the ADC mode register and interface mode register (see Table 27 and Table 28). These modes are as follows and are described in the following sections: • • • • • • Continuous conversion mode Continuous read mode Single conversion mode Standby mode Power-down mode Calibration modes (three modes) CONTINUOUS CONVERSION MODE Continuous conversion is the default power-up mode. The AD7175-8 converts continuously, and the RDY bit in the status register goes low each time a conversion is complete. If CS is low, the RDY output also goes low when a conversion is complete. To read a conversion, the user writes to the communications register, indicating that the next operation is a read of the data register. When the data-word has been read from the data register, the DOUT/RDY pin goes high. The user can read this register additional times, if required. However, the user must ensure that the data register is not being accessed at the completion of the next conversion; otherwise, the new conversion word is lost. When several channels are enabled, the ADC automatically sequences through the enabled channels, performing one conversion on each channel. When all channels have been converted, the sequence starts again with the first channel. The channels are converted in order from lowest enabled channel to highest enabled channel. The data register is updated as soon as each conversion is available. The RDY output pulses low each time a conversion is available. The user can then read the conversion while the ADC converts the next enabled channel. If the DATA_STAT bit in the interface mode register is set to 1, the contents of the status register, along with the conversion data, are output each time the data register is read. The status register indicates the channel to which the conversion corresponds. CS 0x44 0x44 DIN DATA DATA 12911-071 DOUT/RDY SCLK Figure 67. Continuous Conversion Mode Rev. 0 | Page 36 of 64 Data Sheet AD7175-8 CONTINUOUS READ MODE To enable continuous read mode, set the CONTREAD bit in the interface mode register. When this bit is set, the only serial interface operations possible are reads from the data register. To exit continuous read mode, issue a dummy read of the ADC data register command (0x44) while the RDY output is low. Alternatively, apply a software reset, that is, 64 SCLK pulses with CS = 0 and DIN = 1. This resets the ADC and all register contents. These are the only commands that the interface recognizes after it is placed in continuous read mode. Hold DIN low in continuous read mode until an instruction is to be written to the device. In continuous read mode, it is not required to write to the communications register before reading ADC data; apply only the required number of SCLK pulses after RDY goes low to indicate the end of a conversion. When the conversion is read, RDY returns high until the next conversion is available. In this mode, the data can be read only once. The user must also ensure that the data-word is read before the next conversion is complete. If the user has not read the conversion before the completion of the next conversion or if insufficient serial clocks are applied to the AD7175-8 to read the data-word, the serial output register is reset shortly before the next conversion is complete, and the new conversion is placed in the output serial register. The ADC must be configured for continuous conversion mode to use continuous read mode. If multiple ADC channels are enabled, each channel is output in turn, with the status bits being appended to the data if DATA_STAT is set in the interface mode register. The status register indicates the channel to which the conversion corresponds. CS 0x02 0x0080 DIN DATA DATA DATA 12911-072 DOUT/RDY SCLK Figure 68. Continuous Read Mode Rev. 0 | Page 37 of 64 AD7175-8 Data Sheet SINGLE CONVERSION MODE In single conversion mode, the AD7175-8 performs a single conversion and is placed in standby mode after the conversion is complete. The RDY output goes low to indicate the completion of a conversion. When the data-word has been read from the data register, the DOUT/RDY pin goes high. The data register can be read several times, if required, even when the DOUT/RDY pin has gone high. If several channels are enabled, the ADC automatically sequences through the enabled channels and performs a conversion on each channel. When a conversion is started, the DOUT/RDY pin goes high and remains high until a valid conversion is available and CS is low. As soon as the conversion is available, the RDY output goes low. The ADC then selects the next channel and begins a conversion. The user can read the present conversion while the next conversion is being performed. As soon as the next conversion is complete, the data register is updated; therefore, the user has a limited period in which to read the conversion. When the ADC has performed a single conversion on each of the selected channels, it returns to standby mode. If the DATA_STAT bit in the interface mode register is set to 1, the contents of the status register, along with the conversion, are output each time the data register is read. The two LSBs of the status register indicate the channel to which the conversion corresponds. CS 0x01 0x8010 0x44 DIN DATA 12911-073 DOUT/RDY SCLK Figure 69. Single Conversion Mode Rev. 0 | Page 38 of 64 Data Sheet AD7175-8 STANDBY AND POWER-DOWN MODES In standby mode, most blocks are powered down. The LDOs remain active so that registers maintain their contents. The internal reference remains active if enabled, and the crystal oscillator remains active if selected. To power down the reference in standby mode, set the REF_EN bit in the ADC mode register to 0. To power down the clock in standby mode, set the CLOCKSEL bits in the ADC mode register to 00 (internal oscillator). In power-down mode, all blocks are powered down, including the LDOs. All registers lose their contents, and the GPIOx outputs are placed in three-state. To prevent accidental entry to powerdown mode, the ADC must first be placed in standby mode. Exiting power-down mode requires 64 SCLK pulses with CS = 0 and DIN = 1, that is, a serial interface reset. A delay of 500 µs is recommended before issuing a subsequent serial interface command to allow the LDO to power up. Figure 19 shows the internal reference settling time after returning from standby mode (setting REF_EN = 0 and then 1) and returning from power down. CALIBRATION The AD7175-8 allows a two-point calibration to be performed to eliminate any offset and gain errors. Three calibration modes eliminate these offset and gain errors on a per setup basis: • • • Internal zero-scale calibration mode System zero-scale calibration mode System full-scale calibration mode There is no internal full-scale calibration mode because this is calibrated in the factory at the time of production. Only one channel can be active during calibration. After each conversion, the ADC conversion result is scaled using the ADC calibration registers before being written to the data register. The default value of the offset register is 0x800000, and the nominal value of the gain register is 0x555555. The calibration range of the ADC gain is from 0.4 × VREF to 1.05 × VREF. The following equations show the calculations that are used. In unipolar mode, the ideal relationship—that is, not taking into account the ADC gain error and offset error—is as follows: 0.75 × VIN Gain Data = × 223 − (Offset − 0x800000 ) × ×2 V 0x400000 REF To start a calibration, write the relevant value to the mode bits in the ADC mode register. The DOUT/RDY pin and the RDY bit in the status register go high when the calibration initiates. When the calibration is complete, the contents of the corresponding offset or gain register are updated, the RDY bit in the status register is reset and the RDY output pin returns low (if CS is low), and the AD7175-8 reverts to standby mode. During an internal offset calibration, the selected positive analog input pin is disconnected, and both modulator inputs are connected internally to the selected negative analog input pin. For this reason, it is necessary to ensure that the voltage on the selected negative analog input pin does not exceed the allowed limits and is free from excessive noise and interference. System calibrations, however, expect the system zero-scale (offset) and system full-scale (gain) voltages to be applied to the ADC pins before initiating the calibration modes. As a result, errors external to the ADC are removed. From an operational point of view, treat a calibration like another ADC conversion. An offset calibration, if required, must always be performed before a full-scale calibration. Set the system software to monitor the RDY bit in the status register or the RDY output to determine the end of a calibration via a polling sequence or an interrupt driven routine. All calibrations require a time equal to the settling time of the selected filter and output data rate to be completed. An internal offset calibration, system zero-scale calibration, and system full-scale calibration can be performed at any output data rate. Using lower output data rates results in better calibration accuracy and is accurate for all output data rates. A new offset calibration is required for a given channel if the reference source for that channel is changed. The offset error is typically ±60 µV and an offset calibration reduces the offset error to the order of the noise. The gain error is factory calibrated at ambient temperature. Following this calibration, the gain error is typically ±80 ppm of FSR. The AD7175-8 provides the user with access to the on-chip calibration registers, allowing the microprocessor to read the calibration coefficients of the device and to write its own calibration coefficients. A read or write of the offset and gain registers can be performed at any time except during an internal or self calibration. In bipolar mode, the ideal relationship—that is, not taking into account the ADC gain error and offset error—is as follows: 0.75 × VIN Data = × 223 − (Offset − 0x800000 ) × VREF Gain + 0x800000 0x400000 Rev. 0 | Page 39 of 64 AD7175-8 Data Sheet DIGITAL INTERFACE Figure 2 and Figure 3 show timing diagrams for interfacing to the AD7175-8 using CS to decode the device. Figure 2 shows the timing for a read operation from the AD7175-8, and Figure 3 shows the timing for a write operation to the AD7175-8. It is possible to read from the data register several times even though the RDY output returns high after the first read operation. However, care must be taken to ensure that the read operations are completed before the next output update occurs. In continuous read mode, the data register can be read only once. The serial interface can operate in 3-wire mode by tying CS low. In this case, the SCLK, DIN, and DOUT/RDY pins are used to communicate with the AD7175-8. The end of the conversion can also be monitored using the RDY bit in the status register. The AD7175-8 can be reset by writing 64 SCLKs with CS = 0 and DIN = 1. A reset returns the interface to the state in which it expects a write to the communications register. This operation resets the contents of all registers to their power-on values. Following a reset, allow a period of 500 µs before addressing the serial interface. CHECKSUM PROTECTION x8 + x2 + x + 1 During read operations, the user can select between this polynomial and a simpler exclusive OR (XOR) function. The XOR function requires less time to process on the host microcontroller than the polynomial-based checksum. The CRC_EN bits in the interface mode register enable and disable the checksum and allow the user to select between the polynomial check and the simple XOR check. The checksum is appended to the end of each read and write transaction. The checksum calculation for the write transaction is calculated using the 8-bit command word and the 8-bit to 24-bit data. For a read transaction, the checksum is calculated using the command word and the 8-bit to 32-bit data output. Figure 70 and Figure 71 show SPI write and read transactions, respectively. 8-BIT COMMAND UP TO 24-BIT INPUT 8-BIT CRC CS DATA CRC CS DIN 12911-074 The DOUT/RDY pin also functions as a data ready signal, with the output going low if CS is low when a new data-word is available in the data register. The RDY output is reset high when a read operation from the data register is complete. The RDY output also goes high before updating the data register to indicate when not to read from the device to ensure that a data read is not attempted while the register is being updated. Take care to avoid reading from the data register when the RDY output is about to go low. The best method to ensure that no data read occurs is to always monitor the RDY output; start reading the data register as soon as the RDY output goes low; and ensure a sufficient SCLK rate, such that the read is complete before the next conversion result. CS is used to select a device. It can be used to decode the AD7175-8 in systems where several components are connected to the serial bus. For CRC checksum calculations during a write operation, the following polynomial is always used: SCLK Figure 70. SPI Write Transaction with CRC 8-BIT COMMAND UP TO 32-BIT OUTPUT 8-BIT CRC CS DIN DOUT/ RDY CMD DATA CRC SCLK 12911-075 The programmable functions of the AD7175-8 are controlled via the SPI serial interface. The serial interface of the AD7175-8 consists of four signals: CS, DIN, SCLK, and DOUT/RDY. The DIN input is used to transfer data into the on-chip registers, and the DOUT output is used to access data from the on-chip registers. SCLK is the serial clock input for the device, and all data transfers (either on the DIN input or on the DOUT output) occur with respect to the SCLK signal. Figure 71. SPI Read Transaction with CRC If checksum protection is enabled when continuous read mode is active, an implied read data command of 0x44 before every data transmission must be accounted for when calculating the checksum value. This implied read data command ensures a nonzero checksum value even if the ADC data equals 0x000000. The AD7175-8 has a checksum mode that can be used to improve interface robustness. Using the checksum ensures that only valid data is written to a register and allows data read from a register to be validated. If an error occurs during a register write, the CRC_ERROR bit is set in the status register. However, to ensure that the register write is successful, read back the register and verify the checksum. Rev. 0 | Page 40 of 64 Data Sheet AD7175-8 CRC CALCULATION Polynomial The checksum, which is eight bits wide, is generated using the polynomial x8 + x2 + x + 1 To generate the checksum, the data is left shifted by eight bits to create a number ending in eight Logic 0s. The polynomial is aligned so that its MSB is adjacent to the leftmost Logic 1 of the data. An XOR function is applied to the data to produce a new, shorter number. The polynomial is again aligned so that its MSB is adjacent to the leftmost Logic 1 of the new result, and the procedure is repeated. This process repeats until the original data is reduced to a value less than the polynomial. This is the 8-bit checksum. Example of a Polynomial CRC Calculation—24-Bit Word: 0x654321 (Eight Command Bits and 16-Bit Data) An example of generating the 8-bit checksum using the polynomial based checksum is as follows: Initial value 8 011001010100001100100001 2 x +x +x+1 01100101010000110010000100000000 left shifted eight bits = polynomial 100000111 100100100000110010000100000000 100000111 XOR result polynomial 100011000110010000100000000 100000111 XOR result polynomial 11111110010000100000000 100000111 XOR result polynomial value 1111101110000100000000 100000111 XOR result polynomial value 111100000000100000000 100000111 XOR result polynomial value 11100111000100000000 100000111 XOR result polynomial value 1100100100100000000 100000111 XOR result polynomial value 100101010100000000 100000111 XOR result polynomial value 101101100000000 100000111 1101011000000 100000111 101010110000 100000111 1010001000 100000111 10000110 XOR result polynomial value XOR result polynomial value XOR result polynomial value XOR result polynomial value checksum = 0x86 Rev. 0 | Page 41 of 64 AD7175-8 Data Sheet XOR Calculation The checksum, which is 8 bits wide, is generated by splitting the data into bytes and then performing an XOR of the bytes. Example of an XOR Calculation—24-Bit Word: 0x654321 (Eight Command Bits and 16-Bit Data) Using the previous example of a polynomial CRC calculation, divide the data into three bytes: 0x65, 0x43, and 0x21 01100101 0x65 01000011 0x43 00100110 XOR result 00100001 0x21 00000111 CRC Rev. 0 | Page 42 of 64 Data Sheet AD7175-8 INTEGRATED FUNCTIONS The AD7175-8 has integrated functions that improve the usefulness of a number of applications as well as serve diagnostic purposes in safety conscious applications. time, the delay can be absorbed by reducing the number of averages the digital filter performs, which keeps the conversion time the same but can affect the noise performance. GENERAL-PURPOSE I/O The effect on the noise performance depends on the delay time compared to the conversion time. It is possible to absorb the delay only for output data rates less than 10 kSPS with the exception of the following four rates, which cannot absorb any delay: 397.5 SPS, 59.92 SPS, 49.96 SPS, and 16.66 SPS. The AD7175-8 has two general-purpose digital input/output pins (GPIO0, GPIO1) and two general-purpose digital output pins (GPO2, GPO3). As the naming convention suggests, the GPIO0 and GPIO1 pins can be configured as inputs or outputs, but GPO2 and GPO3 are outputs only. The GPIOx and GPOx pins are enabled using the following bits in the GPIOCON register: IP_EN0, IP_EN1 (or OP_EN0, OP_EN1) for GPIO0 and GPIO1, and OP_EN2_3 for GPO2 and GPO3. When the GPIO0 or GPIO1 pin is enabled as an input, the logic level at the pin is contained in the GP_DATA0 or GP_DATA1 bit, respectively. When the GPIO0, GPIO1, GPO2, or GPO3 pin is enabled as an output, the GP_DATA0, GP_DATA1, GP_DATA2, or GP_DATA3 bit, respectively, determines the logic level output at the pin. The logic levels for these pins are referenced to AVDD1 and AVSS; therefore, outputs have an amplitude of 5 V. The ERROR pin can also be used as a general-purpose output. When the ERR_EN bits in the GPIOCON register are set to 11, the ERROR pin operates as a general-purpose output. In this configuration, the ERR_DAT bit in the GPIOCON register determines the logic level output at the pin. The logic level for the pin is referenced to IOVDD and DGND. Both GPIOs and the ERROR pin, when set as general-purpose outputs, have an active pull-up circuit. EXTERNAL MULTIPLEXER CONTROL If an external multiplexer is used to increase the channel count, the multiplexer logic pins can be controlled via the AD7175-8 GPIOx pins. With the MUX_IO bit, the GPIOx timing is controlled by the ADC; therefore, the channel change is synchronized with the ADC, eliminating any need for external synchronization. DELAY It is possible to insert a programmable delay before the AD7175-8 begins to take samples. This delay allows an external amplifier or multiplexer to settle and can alleviate the specification requirements for the external amplifier or multiplexer. Eight programmable settings, ranging from 0 µs to 1 ms, can be set using the delay bits in the ADC mode register (Register 0x01, Bits[10:8]). If a delay greater than 0 µs is selected and the HIDE_DELAY bit in the ADC mode register is set to 0, this delay is added to the conversion time, regardless of the selected output data rate. When using the sinc5 + sinc1 filter, it is possible to hide this delay such that the output data rate remains the same as the output data rate without the delay enabled. If the HIDE_DELAY bit is set to 1 and the selected delay is less than half of the conversion 16-BIT/24-BIT CONVERSIONS By default, the AD7175-8 generates 24-bit conversions. However, the width of the conversions can be reduced to 16 bits. Setting the WL16 bit in the interface mode register to 1 rounds all data conversions to 16 bits. Clearing this bit sets the width of the data conversions to 24 bits. DOUT_RESET The serial interface uses a shared DOUT/RDY pin. By default, this pin outputs the RDY signal. During a data read, this pin outputs the data from the register being read. After the read is complete, the pin reverts to outputting the RDY signal after a short fixed period of time (t7). However, this time may be too short for some microcontrollers and can be extended until the CS pin is brought high by setting the DOUT_RESET bit in the interface mode register to 1. This means that CS must be used to frame each read operation and compete the serial interface transaction. SYNCHRONIZATION Normal Synchronization When the SYNC_EN bit in the GPIOCON register is set to 1, the SYNC pin functions as a synchronization input. The SYNC input lets the user reset the modulator and the digital filter without affecting any of the setup conditions on the device. This feature lets the user start to gather samples of the analog input from a known point, the rising edge of the SYNC input. The SYNC input must be low for at least one master clock cycle to ensure that synchronization occurs. If multiple AD7175-8 devices are operated from a common master clock, they can be synchronized so that their analog inputs are sampled simultaneously. This synchronization is normally done after each AD7175-8 device has performed its own calibration or has calibration coefficients loaded into its calibration registers. A falling edge on the SYNC input resets the digital filter and the analog modulator and places the AD7175-8 into a consistent known state. While the SYNC input is low, the AD7175-8 is maintained in this known state. On the SYNC input rising edge, the modulator and filter are taken out of this reset state, and on the next master clock edge, the device starts to gather input samples again. The device is taken out of reset on the master clock falling edge following the SYNC input low to high transition. Therefore, Rev. 0 | Page 43 of 64 AD7175-8 Data Sheet when multiple devices are being synchronized, take the SYNC input high on the master clock rising edge to ensure that all devices are released on the master clock falling edge. If the SYNC input is not taken high in sufficient time, a difference of one master clock cycle between the devices is possible; that is, the instant at which conversions are available differs from device to device by a maximum of one master clock cycle. The SYNC input can also be used as a start conversion command for a single channel when in normal synchronization mode. In this mode, the rising edge of the SYNC input starts a conversion, and the falling edge of the RDY output indicates when the conversion is complete. The settling time of the filter is required for each data register update. After the conversion is complete, bring the SYNC input low in preparation for the next conversion start signal. Alternate Synchronization In alternate synchronization mode, the SYNC input operates as a start conversion command when several channels of the AD7175-8 are enabled. Setting the ALT_SYNC bit in the interface mode register to 1 enables an alternate synchronization scheme. When the SYNC input is taken low, the ADC completes the conversion on the current channel, selects the next channel in the sequence, and then waits until the SYNC input is taken high to commence the conversion. The RDY output goes low when the conversion is complete on the current channel, and the data register is updated with the corresponding conversion. Therefore, the SYNC input does not interfere with the sampling on the currently selected channel but allows the user to control the instant at which the conversion begins on the next channel in the sequence. Alternate synchronization mode can be used only when several channels are enabled. It is not recommended to use this mode when a single channel is enabled. ERROR FLAGS The status register contains three error bits—ADC_ERROR, CRC_ERROR, and REG_ERROR—that flag errors with the ADC conversion, errors with the CRC check, and errors caused by changes in the registers, respectively. In addition, the ERROR output can indicate that an error has occurred. ADC_ERROR The ADC_ERROR bit in the status register flags any errors that occur during the conversion process. The flag is set when an overrange or underrange result is output from the ADC. The ADC also outputs all 0s or all 1s when an undervoltage or overvoltage occurs. This flag is reset only when the overvoltage or undervoltage is removed. It is not reset by a read of the data register. CRC_ERROR If the CRC value that accompanies a write operation does not correspond with the information sent, the CRC_ERROR flag is set. The flag is reset as soon as the status register is explicitly read. REG_ERROR The REG_ERROR flag is used in conjunction with the REG_CHECK bit in the interface mode register. When the REG_CHECK bit is set, the AD7175-8 monitors the values in the on-chip registers. If a bit changes, the REG_ERROR bit is set. Therefore, for writes to the on-chip registers, set REG_CHECK to 0. When the registers have been updated, the REG_CHECK bit can be set to 1. The AD7175-8 calculates a checksum of the on-chip registers. If one of the register values has changed, the REG_ERROR bit is set. If an error is flagged, set REG_CHECK to 0 to clear the REG_ERROR bit in the status register. The register check function does not monitor the data register, status register, or interface mode register. ERROR Input/Output The ERROR pin functions as an error input/output pin or a general-purpose output pin. The ERR_EN bits in the GPIOCON register determine the function of the pin. When ERR_EN is set to 10, the ERROR pin functions as an open-drain error output, ERROR. The three error bits in the status register (ADC_ERROR, CRC_ERROR, and REG_ERROR) are OR’ed, inverted, and mapped to the ERROR output. Therefore, the ERROR output indicates that an error has occurred. The status register must be read to identify the error source. When ERR_EN is set to 01, the ERROR pin functions as an error input, ERROR. The error output of another component can be connected to the AD7175-8 ERROR input so that the AD7175-8 indicates when an error occurs on either itself or the external component. The value on the ERROR input is inverted and OR’ed with the errors from the ADC conversion, and the result is indicated via the ADC_ERROR bit in the status register. The value of the ERROR input is reflected in the ERR_DAT bit in the GPIO configuration register. The ERROR input/output is disabled when ERR_EN is set to 00. When the ERR_EN bits are set to 11, the ERROR pin operates as a general-purpose output. DATA_STAT The contents of the status register can be appended to each conversion on the AD7175-8. This function is useful if several channels are enabled. Each time a conversion is output, the contents of the status register are appended. The two LSBs of the status register indicate to which channel the conversion corresponds. In addition, the user can determine if any errors are being flagged by the error bits. IOSTRENGTH The serial interface can operate with a power supply as low as 2 V. However, at this low voltage, the DOUT/RDY pin may not have sufficient drive strength if there is moderate parasitic capacitance on the board or the SCLK frequency is high. The Rev. 0 | Page 44 of 64 Data Sheet AD7175-8 IOSTRENGTH bit in the interface mode register increases the drive strength of the DOUT/RDY pin. POWER-DOWN SWITCH Setting the PDSW bit in the GPIO configuration register allows the PDSW pin to sink current. This function can be used in applications where the switch controls the power-up/powerdown of the analog front-end sensor, for example, a bridge sensor. The PDSW pin can sink 16 mA maximum. INTERNAL TEMPERATURE SENSOR The AD7175-8 has an integrated temperature sensor. The temperature sensor can be used as a guide for the ambient temperature at which the device is operating. This can be used for diagnostic purposes or as an indicator of when the application circuit needs to rerun a calibration routine to take into account a shift in operating temperature. The temperature sensor is selected using the crosspoint multiplexer and is selected in the same way as an analog input channel. The temperature sensor requires that the analog input buffers be enabled on both analog inputs. If the buffers are not enabled, selecting the temperature sensor as an input forces the buffers to be enabled during the conversion. To use the temperature sensor, the first step is to calibrate the device in a known temperature (25°C) and take a conversion as a reference point. The temperature sensor has a nominal sensitivity of 470 µV/K; use the difference in this ideal slope and the slope measured to calibrate the temperature sensor. The temperature sensor is specified with a ±2°C typical accuracy after calibration at 25°C. The temperature can be calculated as follows: Rev. 0 | Page 45 of 64 Conversion Result – 273.15 Temperature (°C) = 470 μV AD7175-8 Data Sheet GROUNDING AND LAYOUT The analog inputs and reference inputs are differential and, therefore, most of the voltages in the analog modulator are common-mode voltages. The high common-mode rejection of the device removes common-mode noise on these inputs. The analog and digital supplies to the AD7175-8 are independent and connected to separate pins to minimize coupling between the analog and digital sections of the device. The digital filter provides rejection of broadband noise on the power supplies, except at integer multiples of the master clock frequency. possible to provide low impedance paths and reduce glitches on the power supply line. Shield fast switching signals like clocks with digital ground to prevent radiating noise to other sections of the board and never run clock signals near the analog inputs. Avoid crossover of digital and analog signals. Run traces on opposite sides of the board at right angles to each other. This technique reduces the effects of feedthrough on the board. A microstrip technique is by far the best method but is not always possible with a double sided board. The digital filter also removes noise from the analog and reference inputs, provided that these noise sources do not saturate the analog modulator. As a result, the AD7175-8 is more immune to noise interference than a conventional high resolution converter. However, because the resolution of the AD7175-8 is high and the noise levels from the converter are so low, take care with regard to grounding and layout. Good decoupling is important when using high resolution ADCs. The AD7175-8 has three power supply pins—AVDD1, AVDD2, and IOVDD. The AVDD1 and AVDD2 pins are referenced to AVSS, and the IOVDD pin is referenced to DGND. Decouple AVDD1 and AVDD2 with a 10 µF capacitor in parallel with a 0.1 µF capacitor to AVSS on each pin. Place the 0.1 µF capacitor as close as possible to the device on each supply, ideally right up against the device. Decouple IOVDD with a 10 µF capacitor in parallel with a 0.1 µF capacitor to DGND. Decouple all analog inputs to AVSS. If an external reference is used, decouple the REF+ and REF− pins to AVSS. The PCB that houses the ADC must be designed such that the analog and digital sections are separated and confined to certain areas of the board. A minimum etch technique is generally best for ground planes because it results in the best shielding. In any layout, the user must consider the flow of currents in the system, ensuring that the paths for all return currents are as close as possible to the paths the currents took to reach their destinations. Avoid running digital lines under the device because this couples noise onto the die and allows the analog ground plane to run under the AD7175-8 to prevent noise coupling. The power supply lines to the AD7175-8 must use as wide a trace as The AD7175-8 also has two on-board LDO regulators—one that regulates the AVDD2 supply and one that regulates the IOVDD supply. For the REGCAPA pin, it is recommended that 1 µF and 0.1 µF capacitors to AVSS be used. Similarly, for the REGCAPD pin, it is recommended that 1 µF and 0.1 µF capacitors to DGND be used. If using the AD7175-8 for split supply operation, a separate plane must be used for AVSS. Rev. 0 | Page 46 of 64 Data Sheet AD7175-8 REGISTER SUMMARY Table 24. Register Summary Reg. Name Bits Bit 7 Bit 6 0x00 COMMS [7:0] WEN R/W 0x00 STATUS [7:0] RDY ADC_ERROR CRC_ERROR 0x01 ADCMODE [15:8] REF_EN [7:0] RESERVED [15:8] [7:0] CONTREAD [23:16] [15:8] [7:0] HIDE_DELAY SING_CYC MODE 0x02 IFMODE 0x03 REGCHECK 0x04 DATA 0x06 GPIOCON 0x07 ID 0x10 CH0 0x11 0x12 0x13 CH1 CH2 CH3 0x14 CH4 0x15 CH5 0x16 CH6 0x17 CH7 0x18 CH8 0x19 CH9 0x1A CH10 0x1B CH11 0x1C CH12 0x1D CH13 0x1E CH14 0x1F CH15 0x20 0x21 0x22 0x23 0x24 SETUPCON0 SETUPCON1 SETUPCON2 SETUPCON3 SETUPCON4 [23:16] [15:8] [7:0] [15:8] RESERVED [7:0] GP_DATA3 [15:8] [7:0] [15:8] CH_EN0 [7:0] [15:8] CH_EN1 [7:0] [15:8] [7:0] [15:8] [7:0] CH_EN2 [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] CH_EN4 [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] RESERVED DATA_STAT PDSW GP_DATA2 AINPOS0[2:0] AINPOS1[2:0] Bit 5 Bit 4 Bit 3 REG_ERROR RESERVED CLOCKSEL ALT_SYNC IOSTRENGTH RESERVED CRC_EN REGISTER_CHECK[23:16] REGISTER_CHECK[15:8] REGISTER_CHECK[7:0] REG_CHECK SETUP_SEL2 SETUP_SEL3 AINPOS3[2:0] SETUP_SEL4 AINPOS4[2:0] CH_EN5 SETUP_SEL5 AINPOS5[2:0] CH_EN6 SETUP_SEL6 AINPOS6[2:0] CH_EN7 SETUP_SEL7 AINPOS7[2:0] CH_EN8 SETUP_SEL8 AINPOS8[2:0] CH_EN9 SETUP_SEL9 AINPOS9[2:0] CH_EN10 SETUP_SEL10 AINPOS10[2:0] CH_EN11 SETUP_SEL11 AINPOS11[2:0] CH_EN12 SETUP_SEL12 AINPOS12[2:0] CH_EN13 SETUP_SEL13 AINPOS13[2:0] CH_EN14 SETUP_SEL14 AINPOS14[2:0] CH_EN15 SETUP_SEL15 AINPOS15[2:0] BURNOUT_EN0 BURNOUT_EN1 BURNOUT_EN2 BURNOUT_EN3 BURNOUT_EN4 RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED Bit 1 Bit 0 Reset 0x00 RW W CHANNEL 0x80 R DELAY RESERVED RESERVED DOUT_RESET RESERVED WL16 0xA000 RW 0x0000 RW 0x000000 R 0x000000 R 0x0800 RW 0x3CDx R 0x8001 RW 0x0001 RW DATA[23:16] DATA[15:8] DATA[7:0] OP_EN2_3 MUX_IO SYNC_EN ERR_EN ERR_DAT IP_EN1 IP_EN0 OP_EN1 OP_EN0 GP_DATA1 GP_DATA0 ID[15:8] ID[7:0] SETUP_SEL0 RESERVED AINPOS0[4:3] AINNEG0 SETUP_SEL1 RESERVED AINPOS1[4:3] AINNEG1 AINPOS2[2:0] CH_EN3 Bit 2 RA BI_UNIPOLAR0 REF_SEL0 BI_UNIPOLAR1 REF_SEL1 BI_UNIPOLAR2 REF_SEL2 BI_UNIPOLAR3 REF_SEL3 BI_UNIPOLAR4 REF_SEL4 Rev. 0 | Page 47 of 64 RESERVED AINNEG2 RESERVED AINNEG3 AINPOS2[4:3] 0x0001 RW AINPOS3[4:3] 0x0001 RW RESERVED AINNEG4 RESERVED AINNEG5 RESERVED AINNEG6 RESERVED AINNEG7 RESERVED AINNEG8 RESERVED AINNEG9 RESERVED AINNEG10 RESERVED AINNEG11 RESERVED AINNEG12 RESERVED AINNEG13 RESERVED AINNEG14 RESERVED AINNEG15 AINPOS4[4:3] 0x0001 RW AINPOS5[4:3] 0x0001 RW AINPOS6[4:3] 0x0001 RW AINPOS7[4:3] 0x0001 RW AINPOS8[4:3] 0x0001 RW AINPOS9[4:3] 0x0001 RW AINPOS10[4:3] 0x0001 RW AINPOS11[4:3] 0x0001 RW AINPOS12[4:3] 0x0001 RW AINPOS13[4:3] 0x0001 RW AINPOS14[4:3] 0x0001 RW AINPOS15[4:3] 0x0001 RW AINBUF0− 0x1320 RW AINBUF1− 0x1320 RW AINBUF2− 0x1320 RW AINBUF3− 0x1320 RW AINBUF4− 0x1320 RW REFBUF0+ REFBUF1+ REFBUF2+ REFBUF3+ REFBUF4+ REFBUF0− AINBUF0+ RESERVED REFBUF1− AINBUF1+ RESERVED REFBUF2− AINBUF2+ RESERVED REFBUF3− AINBUF3+ RESERVED REFBUF4− AINBUF4+ RESERVED AD7175-8 Data Sheet Reg. Name Bits 0x25 SETUPCON5 [15:8] SETUPCON6 [7:0] [15:8] [7:0] 0x26 0x27 SETUPCON7 0x28 FILTCON0 0x29 FILTCON1 0x2A 0x2B 0x2C FILTCON2 FILTCON3 FILTCON4 0x2D FILTCON5 0x2E 0x2F FILTCON6 FILTCON7 Bit 7 Bit 6 Bit 5 Bit 4 RESERVED BURNOUT_EN5 BURNOUT_EN6 RESERVED RESERVED RESERVED BURNOUT_EN7 SINC3_MAP0 RESERVED [15:8] [7:0] [15:8] [7:0] [15:8] SINC3_MAP1 RESERVED SINC3_MAP2 RESERVED SINC3_MAP3 RESERVED ORDER1 RESERVED ORDER2 RESERVED [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] RESERVED SINC3_MAP4 RESERVED SINC3_MAP5 RESERVED SINC3_MAP6 RESERVED ORDER3 RESERVED ORDER4 RESERVED ORDER5 RESERVED ORDER6 SINC3_MAP7 RESERVED RESERVED ORDER7 0x30 0x31 0x32 0x33 0x34 0x35 OFFSET0 OFFSET1 OFFSET2 OFFSET3 OFFSET4 OFFSET5 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F OFFSET6 OFFSET7 GAIN0 GAIN1 GAIN2 GAIN3 GAIN4 GAIN5 GAIN6 GAIN7 [23:0] [23:0] [23:0] [23:0] [23:0] [23:0] [23:0] [23:0] [23:0] [23:0] Reset RW REFBUF5+ REFBUF5− AINBUF5+ AINBUF5− 0x1320 RW REFBUF6+ RESERVED REFBUF6− AINBUF6+ RESERVED AINBUF6− 0x1320 RW AINBUF7− 0x1320 RW 0x0500 RW ENHFILT1 0x0500 RW ENHFILT2 0x0500 RW ENHFILT3 0x0500 RW ENHFILT4 0x0500 RW ENHFILT5 0x0500 RW ENHFILT6 0x0500 RW ENHFILT7 0x0500 RW OFFSET0[23:0] OFFSET1[23:0] OFFSET2[23:0] OFFSET3[23:0] OFFSET4[23:0] OFFSET5[23:0] 0x800000 0x800000 0x800000 0x800000 0x800000 0x800000 RW RW RW RW RW RW OFFSET6[23:0] OFFSET7[23:0] GAIN0[23:0] GAIN1[23:0] GAIN2[23:0] GAIN3[23:0] GAIN4[23:0] GAIN5[23:0] GAIN6[23:0] GAIN7[23:0] 0x800000 0x800000 0x5XXXX0 0x5XXXX0 0x5XXXX0 0x5XXXX0 0x5XXXX0 0x5XXXX0 0x5XXXX0 0x5XXXX0 RW RW RW RW RW RW RW RW RW RW REF_SEL5 BI_UNIPOLAR6 REF_SEL6 [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [23:0] [23:0] [23:0] [23:0] [23:0] [23:0] Bit 3 BI_UNIPOLAR5 RESERVED RESERVED BI_UNIPOLAR7 REFBUF7+ REF_SEL7 RESERVED ENHFILTEN0 ORDER0 Bit 2 Bit 1 REFBUF7− AINBUF7+ RESERVED ENHFILT0 ODR0 ENHFILTEN1 Bit 0 ODR1 ENHFILTEN2 ODR2 ENHFILTEN3 ODR3 ENHFILTEN4 ODR4 ENHFILTEN5 ODR5 ENHFILTEN6 ODR6 ENHFILTEN7 ODR7 Rev. 0 | Page 48 of 64 Data Sheet AD7175-8 REGISTER DETAILS COMMUNICATIONS REGISTER Address: 0x00, Reset: 0x00, Name: COMMS All access to the on-chip registers must start with a write to the communications register. This write determines what register is accessed next and whether that operation is a write or a read. Table 25. Bit Descriptions for COMMS Bits 7 Bit Name WEN 6 R/W Settings 0 1 [5:0] RA 000000 000001 000010 000011 000100 000110 000111 010000 010001 010010 010011 010100 010101 010110 010111 011000 011001 011010 011011 011100 011101 011110 011111 100000 100001 100010 100011 100100 100101 100110 100111 101000 101001 101010 101011 101100 101101 101110 101111 Description This bit must be low to begin communications with the ADC. Reset 0x0 Access W This bit determines if the command is a read or write operation. Write command Read command The register address bits determine which register is to be read from or written to as part of the current communication. Status register ADC mode register Interface mode register Register checksum register Data register GPIO configuration register ID register Channel 0 register Channel 1 register Channel 2 register Channel 3 register Channel 4 register Channel 5 register Channel 6 register Channel 7 register Channel 8 register Channel 9 register Channel 10 register Channel 11 register Channel 12 register Channel 13 register Channel 14 register Channel 15 register Setup Configuration 0 register Setup Configuration 1 register Setup Configuration 2 register Setup Configuration 3 register Setup Configuration 4 register Setup Configuration 5 register Setup Configuration 6 register Setup Configuration 7 register Filter Configuration 0 register Filter Configuration 1 register Filter Configuration 2 register Filter Configuration 3 register Filter Configuration 4 register Filter Configuration 5 register Filter Configuration 6 register Filter Configuration 7 register 0x0 W 0x00 W Rev. 0 | Page 49 of 64 AD7175-8 Bits Bit Name Data Sheet Settings 110000 110001 110010 110011 110100 110101 110110 110111 111000 111001 111010 111011 111100 111101 111110 111111 Description Offset 0 register Offset 1 register Offset 2 register Offset 3 register Offset 4 register Offset 5 register Offset 6 register Offset 7 register Gain 0 register Gain 1 register Gain 2 register Gain 3 register Gain 4 register Gain 5 register Gain 6 register Gain 7 register Reset Rev. 0 | Page 50 of 64 Access Data Sheet AD7175-8 STATUS REGISTER Address: 0x00, Reset: 0x80, Name: STATUS The status register is an 8-bit register that contains ADC and serial interface status information. It can optionally be appended to the data register by setting the DATA_STAT bit in the interface mode register. Table 26. Bit Descriptions for STATUS Bits 7 Bit Name RDY Settings 0 1 6 ADC_ERROR 0 1 5 CRC_ERROR 0 1 4 REG_ERROR 0 1 [3:0] CHANNEL 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Description The status of RDY is output to the DOUT/RDY pin whenever CS is low and a register is not being read. This bit goes low when the ADC has written a new result to the data register. In ADC calibration modes, this bit goes low when the ADC has written the calibration result. RDY is brought high automatically by a read of the data register. New data result available Awaiting new data result This bit by default indicates if an ADC overrange or underrange has occurred. The ADC result is clamped to 0xFFFFFF for overrange errors and 0x000000 for underrange errors. This bit is updated when the ADC result is written and is cleared at the next update after removing the overrange or underrange condition. No error Error This bit indicates if a CRC error has taken place during a register write. For register reads, the host microcontroller determines if a CRC error has occurred. This bit is cleared by a read of this register. No error CRC error This bit indicates if the content of one of the internal registers has changed from the value calculated when the register integrity check was activated. The check is activated by setting the REG_CHECK bit in the interface mode register. This bit is cleared by clearing the REG_CHECK bit. No error Error These bits indicate which channel was active for the ADC conversion whose result is currently in the data register. This may be different from the channel currently being converted. The mapping is a direct map from the channel register; therefore, Channel 0 results in 0x0 and Channel 15 results in 0xF. Channel 0 Channel 1 Channel 2 Channel 3 Channel 4 Channel 5 Channel 6 Channel 7 Channel 8 Channel 9 Channel 10 Channel 11 Channel 12 Channel 13 Channel 14 Channel 15 Rev. 0 | Page 51 of 64 Reset 0x1 Access R 0x0 R 0x0 R 0x0 R 0x0 R AD7175-8 Data Sheet ADC MODE REGISTER Address: 0x01, Reset: 0xA000, Name: ADCMODE The ADC mode register controls the operating mode of the ADC and the master clock selection. A write to the ADC mode register resets the filter and the RDY bits and starts a new conversion or calibration. Table 27. Bit Descriptions for ADCMODE Bits 15 Bit Name REF_EN Settings 0 1 14 HIDE_DELAY 0 1 13 SING_CYC 0 1 [12:11] [10:8] RESERVED DELAY 000 001 010 011 100 101 110 111 7 [6:4] RESERVED MODE 000 001 010 011 100 110 111 [3:2] CLOCKSEL 00 01 10 11 [1:0] RESERVED Description Enables internal reference and outputs a buffered 2.5 V to the REFOUT pin. Disabled Enabled If a programmable delay is set using the delay bits, this bit allows the delay to be hidden by absorbing the delay into the conversion time for selected data rates with the sinc5 + sinc1 filter. See the Delay section for more information. Enabled Disabled This bit can be used when only a single channel is active to set the ADC to only output at the settled filter data rate. Disabled Enabled These bits are reserved; set these bits to 0. These bits allow a programmable delay to be added after a channel switch to allow the settling of external circuitry before the ADC starts processing its input. 0 µs 4 µs 16 µs 40 µs 100 µs 200 µs 500 µs 1 ms This bit is reserved; set this bit to 0. These bits control the operating mode of the ADC. See the Operating Modes section for more information. Continuous conversion mode Single conversion mode Standby mode Power-down mode Internal offset calibration System offset calibration System gain calibration These bits are used to select the ADC clock source. Selecting the internal oscillator also enables the internal oscillator. Internal oscillator Internal oscillator output on the XTAL2/CLKIO pin External clock input on the XTAL2/CLKIO pin External crystal on the XTAL1 and XTAL2/CLKIO pins These bits are reserved; set these bits to 0. Rev. 0 | Page 52 of 64 Reset 0x1 Access RW 0x0 RW 0x1 RW 0x0 0x0 R RW 0x0 0x0 R RW 0x0 RW 0x0 R Data Sheet AD7175-8 INTERFACE MODE REGISTER Address: 0x02, Reset: 0x0000, Name: IFMODE The interface mode register configures various serial interface options. Table 28. Bit Descriptions for IFMODE Bits [15:13] 12 Bit Name RESERVED ALT_SYNC Settings 0 1 11 IOSTRENGTH 0 1 [10:9] 8 RESERVED DOUT_RESET 0 1 7 CONTREAD 0 1 6 DATA_STAT 0 1 5 REG_CHECK 0 1 4 [3:2] RESERVED CRC_EN 00 01 10 1 RESERVED Description These bits are reserved; set these bits to 0. This bit enables a different behavior of the SYNC pin to allow the use of SYNC as a control for conversions when cycling channels (see the description of the SYNC_EN bit in the GPIO Configuration Register section for details). Disabled Enabled This bit controls the drive strength of the DOUT/RDY pin. Set this bit when reading from the serial interface at high speed with a low IOVDD supply and moderate capacitance. Disabled (default) Enabled These bits are reserved; set these bits to 0. See the DOUT_RESET section for more information. Disabled Enabled This bit enables the continuous read mode of the ADC data register. The ADC must be configured in continuous conversion mode to use continuous read mode. For more details, see the Operating Modes section. Disabled Enabled This bit enables the status register to be appended to the data register when read so that channel and status information are transmitted with the data. This is the only way to be sure that the channel bits read from the status register correspond to the data in the data register. Disabled Enabled This bit enables a register integrity checker, which can be used to monitor any change in the value of the user registers. To use this feature, configure all other registers as desired with this bit cleared. Then write to this register to set the REG_CHECK bit to 1. If the contents of any of the registers change, the REG_ERROR bit is set in the status register. To clear the error, set the REG_CHECK bit to 0. Neither the interface mode register nor the ADC data or status registers are included in the registers that are checked. If a register must have a new value written, this bit must first be cleared; otherwise, an error is flagged when the new register contents are written. Disabled Enabled This bit is reserved; set this bit to 0. These bits enable CRC protection of register reads/writes. CRC increases the number of bytes in a serial interface transfer by one. See the CRC Calculation section for more details. Disabled XOR checksum enabled for register read transactions; register writes still use CRC with these bits set CRC checksum enabled for read and write transactions This bit is reserved; set this bit to 0. Rev. 0 | Page 53 of 64 Reset 0x0 0x0 Access R RW 0x0 RW 0x0 0x0 R RW 0x0 RW 0x0 RW 0x0 RW 0x0 0x00 R RW 0x0 R AD7175-8 Bits 0 Bit Name WL16 Data Sheet Settings 0 1 Description This bit changes the ADC data register to 16 bits. The ADC is not reset by a write to the interface mode register; therefore, the ADC result is not rounded to the correct word length immediately after writing to these bits. The first new ADC result is correct. 24-bit data 16-bit data Reset 0x0 Access RW REGISTER CHECK Address: 0x03, Reset: 0x000000, Name: REGCHECK The register check register is a 24-bit checksum calculated by exclusively OR'ing the contents of the user registers. The REG_CHECK bit in the interface mode register must be set for this to operate; otherwise, the register reads 0. Table 29. Bit Descriptions for REGCHECK Bits [23:0] Bit Name REGISTER_CHECK Settings Description This register contains the 24-bit checksum of user registers when the REG_CHECK bit is set in the interface mode register. Reset 0x000000 Access R DATA REGISTER Address: 0x04, Reset: 0x000000, Name: DATA The data register contains the ADC conversion result. The encoding is offset binary, or it can be changed to unipolar by the BI_UNIPOLARx bits in the setup configuration registers. Reading the data register brings the RDY bit and the RDY output high if it is low. The ADC result can be read multiple times; however, because the RDY output is brought high, it is not possible to know if another ADC result is imminent. After the command to read the ADC register is received, the ADC does not write a new result into the data register. Table 30. Bit Descriptions for DATA Bits [23:0] Bit Name DATA Settings Description This register contains the ADC conversion result. If DATA_STAT is set in the interface mode register, the status register is appended to this register when read, making this a 32-bit register. If WL16 is set in the interface mode register, this register is reduced to 16 bits. Rev. 0 | Page 54 of 64 Reset 0x000000 Access R Data Sheet AD7175-8 GPIO CONFIGURATION REGISTER Address: 0x06, Reset: 0x0800, Name: GPIOCON The GPIO configuration register controls the general-purpose I/O pins of the ADC. Table 31. Bit Descriptions for GPIOCON Bits 15 14 Bit Name RESERVED PDSW 13 OP_EN2_3 12 MUX_IO 11 SYNC_EN Settings 0 1 [10:9] ERR_EN 00 01 10 11 8 ERR_DAT 7 6 5 GP_DATA3 GP_DATA2 IP_EN1 0 1 4 IP_EN0 0 1 Description These bits are reserved; set these bits to 0. This bit enables/disables the power-down switch function. Setting the bit allows the pin to sink current. This function can be used for bridge sensor applications where the switch controls the power-up/power-down of the bridge. This bit enables the GPO2 and GPO3 pins. Outputs are referenced between AVDD1 and AVSS. This bit allows the ADC to control an external multiplexer, using GPIO0/GPIO1/ GPO2/GPO3 in sync with the internal channel sequencing. The analog input pins used for a channel can still be selected on a per channel basis. Therefore, it is possible to have a 16-channel multiplexer in front of each analog input pair (AIN0/AIN1 to AIN14/AIN15), giving a total of 128 differential channels. However, only 16 channels at a time can be automatically sequenced. Following the sequence of 16 channels, the user changes the analog input to the next pair of input channels, and it sequences through the next 16 channels. A delay can be inserted after switching an external multiplexer (see the delay bits in the ADC Mode Register section). This bit enables the SYNC pin as a synchronization input. When the pin is low, this holds the ADC and filter in reset until the SYNC pin goes high. An alternative operation of the SYNC pin is available when the ALT_SYNC bit in the interface mode register is set. This mode only works when multiple channels are enabled. In this case, a low on the SYNC pin does not immediately reset the filter/modulator. Instead, if the SYNC pin is low when the channel is due to be switched, the modulator and filter are prevented from starting a new conversion. Bringing SYNC high begins the next conversion. This alternative sync mode allows SYNC to be used while cycling through channels. Disabled. Enabled. These bits enable the ERROR pin as an error input/output. Disabled. ERROR is an error input. The (inverted) readback state is OR'ed with other error sources and is available in the ADC_ERROR bit in the status register. The ERROR pin state can also be read from the ERR_DAT bit in this register. ERROR is an open-drain error output. The status register error bits are OR'ed, inverted, and mapped to the ERROR pin. The ERROR pins of multiple devices can be wired together to a common pull-up resistor so that an error on any device can be observed. ERROR is a general-purpose output. The status of the pin is controlled by the ERR_DAT bit in this register. This output is referenced between IOVDD and DGND, as opposed to the AVDD1 and AVSS levels used by the general-purpose I/O pins. The ERROR pin has an active pull-up in this case. This bit determines the logic level at the ERROR pin if the pin is enabled as a general-purpose output. This bit reflects the readback status of the pin if the pin is enabled as an input. This bit is the write data for GPO3. This bit is the write data for GPO2. This bit turns GPIO1 into an input. Inputs are referenced to AVDD1 or AVSS. Disabled. Enabled. This bit turns GPIO0 into an input. Inputs are referenced to AVDD1 or AVSS. Disabled. Enabled. Rev. 0 | Page 55 of 64 Reset 0x0 0x0 Access R RW 0x0 RW 0x0 RW 0x1 RW 0x0 RW 0x0 RW 0x0 0x0 0x0 W W RW 0x0 RW AD7175-8 Bits 3 Bit Name OP_EN1 Data Sheet Settings Description This bit turns GPIO1 into an output. Outputs are referenced between AVDD1 and AVSS. Disabled. Enabled. This bit turns GPIO0 into an output. Outputs are referenced between AVDD1 and AVSS. Disabled. Enabled. This bit is the readback or write data for GPIO1. This bit is the readback or write data for GPIO0. 0 1 2 OP_EN0 0 1 1 0 GP_DATA1 GP_DATA0 Reset 0x0 Access RW 0x0 RW 0x0 0x0 RW RW ID REGISTER Address: 0x07, Reset: 0x3CDx, Name: ID The ID register returns a 16-bit ID. For the AD7175-8, this ID is 0x3CDx. Table 32. Bit Descriptions for ID Bits [15:0] Bit Name ID Settings 0x3CDx Description The ID register returns a 16-bit ID code that is specific to the ADC. AD7175-8 Reset 0x3CDx Access R CHANNEL REGISTER 0 Address: 0x10, Reset: 0x8001, Name: CH0 The channel registers are 16-bit registers used to select which channels are currently active, which inputs are selected for each channel, and which setup is used to configure the ADC for that channel. Table 33. Bit Descriptions for CH0 Bits 15 Bit Name CH_EN0 Settings 0 1 [14:12] SETUP_SEL0 000 001 010 011 100 101 110 111 [11:10] [9:5] RESERVED AINPOS0 00000 00001 00010 00011 00100 00101 00110 00111 Description This bit enables Channel 0. If more than one channel is enabled, the ADC automatically sequences between them. Disabled Enabled (default) These bits identify which of the eight setups is used to configure the ADC for this channel. A setup comprises a set of four registers: setup configuration register, filter configuration register, offset register, and gain register. All channels can use the same setup, in which case the same 3-bit value must be written to these bits on all active channels, or up to eight channels can be configured differently. Setup 0 Setup 1 Setup 2 Setup 3 Setup 4 Setup 5 Setup 6 Setup 7 These bits are reserved; set these bits to 0. These bits select which input is connected to the positive input of the ADC for this channel. AIN0 (default) AIN1 AIN2 AIN3 AIN4 AIN5 AIN6 AIN7 Rev. 0 | Page 56 of 64 Reset 0x1 Access RW 0x0 RW 0x0 0x0 R RW Data Sheet Bits Bit Name [4:0] AINNEG0 AD7175-8 Settings 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 10010 10011 10100 10101 10110 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 10010 10011 10100 10101 10110 Description AIN8 AIN9 AIN10 AIN11 AIN12 AIN13 AIN14 AIN15 AIN16 Temperature sensor+ Temperature sensor− ((AVDD1 − AVSS)/5)+ (analog input buffers must be enabled) ((AVDD1 − AVSS)/5)− (analog input buffers must be enabled) REF+ REF− These bits select which input is connected to the negative input of the ADC for this channel. AIN0 AIN1 (default) AIN2 AIN3 AIN4 AIN5 AIN6 AIN7 AIN8 AIN9 AIN10 AIN11 AIN12 AIN13 AIN14 AIN15 AIN16 Temperature sensor+ Temperature sensor− ((AVDD1 − AVSS)/5)+ ((AVDD1 − AVSS)/5)− REF+ REF− Rev. 0 | Page 57 of 64 Reset Access 0x1 RW AD7175-8 Data Sheet CHANNEL REGISTER 1 TO CHANNEL REGISTER 15 Address: 0x11 to 0x1F, Reset: 0x0001, Name: CH1 to CH7 The remaining 15 channel registers share the same layout as Channel Register 0. Table 34. CH1 to CH15 Register Map Reg. Name 0x11 CH1 0x12 CH2 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F CH3 CH4 CH5 CH6 CH7 CH8 CH9 CH10 CH11 CH12 CH13 CH14 CH15 Bits Bit 7 [15:8] [7:0] [15:8] [7:0] CH_EN1 [15:8] [7:0] [15:8] [7:0] CH_EN3 [15:8] [7:0] [15:8] CH_EN5 [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] Bit 6 Bit 5 Bit 4 Bit 3 SETUP_SEL1 AINPOS1[2:0] CH_EN2 SETUP_SEL2 AINPOS2[2:0] SETUP_SEL3 AINPOS3[2:0] CH_EN4 SETUP_SEL4 AINPOS4[2:0] SETUP_SEL5 AINPOS5[2:0] CH_EN6 SETUP_SEL6 AINPOS6[2:0] CH_EN7 SETUP_SEL7 AINPOS7[2:0] CH_EN8 SETUP_SEL8 AINPOS8[2:0] CH_EN9 SETUP_SEL9 AINPOS9[2:0] CH_EN10 SETUP_SEL10 AINPOS10[2:0] CH_EN11 SETUP_SEL11 AINPOS11[2:0] CH_EN12 SETUP_SEL12 AINPOS12[2:0] CH_EN13 SETUP_SEL13 AINPOS13[2:0] CH_EN14 SETUP_SEL14 AINPOS14[2:0] CH_EN15 SETUP_SEL15 AINPOS15[2:0] Rev. 0 | Page 58 of 64 Bit 2 Bit 1 Bit 0 Reset RW RESERVED AINNEG1 RESERVED AINNEG2 AINPOS1[4:3] 0x0001 RW AINPOS2[4:3] 0x0001 RW RESERVED AINNEG3 RESERVED AINNEG4 AINPOS3[4:3] 0x0001 RW AINPOS4[4:3] 0x0001 RW RESERVED AINNEG5 RESERVED AINPOS5[4:3] 0x0001 RW AINPOS6[4:3] 0x0001 RW AINPOS7[4:3] 0x0001 RW AINPOS8[4:3] 0x0001 RW AINPOS9[4:3] 0x0001 RW AINPOS10[4:3] 0x0001 RW AINPOS11[4:3] 0x0001 RW AINPOS12[4:3] 0x0001 RW AINPOS13[4:3] 0x0001 RW AINPOS14[4:3] 0x0001 RW AINPOS15[4:3] 0x0001 RW AINNEG6 RESERVED AINNEG7 RESERVED AINNEG8 RESERVED AINNEG9 RESERVED AINNEG10 RESERVED AINNEG11 RESERVED AINNEG12 RESERVED AINNEG13 RESERVED AINNEG14 RESERVED AINNEG15 Data Sheet AD7175-8 SETUP CONFIGURATION REGISTER 0 Address: 0x20, Reset: 0x1320, Name: SETUPCON0 The setup configuration registers are 16-bit registers that configure the reference selection, input buffers, and output coding of the ADC. Table 35. Bit Descriptions for SETUPCON0 Bits [15:13] 12 Bit Name RESERVED BI_UNIPOLAR0 Settings 0 1 11 REFBUF0+ 0 1 10 REFBUF0− 0 1 9 AINBUF0+ 0 1 8 AINBUF0− 0 1 7 BURNOUT_EN0 6 [5:4] RESERVED REF_SEL0 00 01 10 11 [3:0] RESERVED Description These bits are reserved; set these bits to 0. This bit sets the output coding of the ADC for Setup 0. Unipolar coded output Bipolar coded output (offset binary) This bit enables or disables the REF+ input buffer. REF+ buffer disabled REF+ buffer enabled This bit enables or disables the REF− input buffer. REF− buffer disabled REF− buffer enabled This bit enables or disables the AIN+ input buffer. AIN+ buffer disabled AIN+ buffer enabled This bit enables or disables the AIN− input buffer. AIN− buffer disabled AIN− buffer enabled This bit enables a 10 µA current source on the positive analog input selected and a 10 µA current sink on the negative analog input selected. The burnout currents are useful in diagnosis of an open wire, whereby the ADC result goes to full scale. Enabling the burnout currents during measurement results in an offset voltage on the ADC. This means the strategy for diagnosing an open wire operates best by turning on the burnout currents at intervals, before or after precision measurements. These bits are reserved; set these bits to 0. These bits allow the user to select the reference source for ADC conversion on Setup 0. External reference. External Reference 2 supplied to AIN1/REF2+ and AIN0/REF2− pins. Internal 2.5 V reference. This must also be enabled in the ADC mode register. AVDD1 − AVSS. This can be used to as a diagnostic to validate other reference values. These bits are reserved; set these bits to 0. Rev. 0 | Page 59 of 64 Reset 0x0 0x1 Access R RW 0x0 RW 0x0 RW 0x1 RW 0x1 RW 0x00 R 0x00 0x2 R RW 0x0 R AD7175-8 Data Sheet SETUP CONFIGURATION REGISTER 1 TO SETUP CONFIGURATION REGISTER 7 Address: 0x21 to 0x27, Reset: 0x1320, Name: SETUPCON1 to SETUPCON7 The remaining seven setup configuration registers share the same layout as Setup Configuration Register 0. Table 36. SETUPCON1 to SETUPCON7 Register Map Reg. 0x21 0x22 0x23 0x24 0x25 0x26 0x27 Name Bits SETUPCON1 [15:8] [7:0] SETUPCON2 [15:8] [7:0] SETUPCON3 [15:8] [7:0] SETUPCON4 [15:8] [7:0] SETUPCON5 [15:8] [7:0] SETUPCON6 [15:8] [7:0] SETUPCON7 [15:8] [7:0] Bit 7 BURNOUT_EN1 BURNOUT_EN2 BURNOUT_EN3 BURNOUT_EN4 BURNOUT_EN5 BURNOUT_EN6 BURNOUT_EN7 Bit 6 RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED Bit 5 Bit 4 BI_UNIPOLAR1 REF_SEL1 BI_UNIPOLAR2 REF_SEL2 BI_UNIPOLAR3 REF_SEL3 BI_UNIPOLAR4 REF_SEL4 BI_UNIPOLAR5 REF_SEL5 BI_UNIPOLAR6 REF_SEL6 BI_UNIPOLAR7 REF_SEL7 Bit 3 REFBUF1+ Rev. 0 | Page 60 of 64 REFBUF2+ REFBUF3+ REFBUF4+ REFBUF5+ REFBUF6+ REFBUF7+ Bit 2 Bit 1 REFBUF1− AINBUF1+ RESERVED REFBUF2− AINBUF2+ RESERVED REFBUF3− AINBUF3+ RESERVED REFBUF4− AINBUF4+ RESERVED REFBUF5− AINBUF5+ RESERVED REFBUF6− AINBUF6+ RESERVED REFBUF7− AINBUF7+ RESERVED Bit 0 AINBUF1− Reset 0x1320 RW RW AINBUF2− 0x1320 RW AINBUF3− 0x1320 RW AINBUF4− 0x1320 RW AINBUF5− 0x1320 RW AINBUF6− 0x1320 RW AINBUF7− 0x1320 RW Data Sheet AD7175-8 FILTER CONFIGURATION REGISTER 0 Address: 0x28, Reset: 0x0500, Name: FILTCON0 The filter configuration registers are 16-bit registers that configure the ADC data rate and filter options. Writing to any of these registers resets any active ADC conversion and restarts converting at the first channel in the sequence. Table 37. Bit Descriptions for FILTCON0 Bits 15 Bit Name SINC3_MAP0 [14:12] 11 RESERVED ENHFILTEN0 Settings 0 1 [10:8] ENHFILT0 010 011 101 110 7 [6:5] RESERVED ORDER0 00 11 [4:0] ODR0 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 10010 10011 10100 Description If this bit is set, the mapping of the filter register changes to directly program the decimation rate of the sinc3 filter for Setup 0. All other options are eliminated. This allows fine tuning of the output data rate and filter notch for rejection of specific frequencies. The data rate when on a single channel equals fMOD/(32 × FILTCON0[14:0]). These bits are reserved; set these bits to 0. This bit enables various postfilters for enhanced 50 Hz/60 Hz rejection for Setup 0. The ORDER0 bits must be set to 00 to select the sinc5 + sinc1 filter for this to work. Disabled Enabled These bits select between various postfilters for enhanced 50 Hz/60 Hz rejection for Setup 0. 27 SPS, 47 dB rejection, 36.7 ms settling 25 SPS, 62 dB rejection, 40 ms settling 20 SPS, 86 dB rejection, 50 ms settling 16.67 SPS, 92 dB rejection, 60 ms settling This bit is reserved; set this bit to 0. These bits control the order of the digital filter that processes the modulator data for Setup 0. Sinc5 + sinc1 (default) Sinc3 These bits control the output data rate of the ADC and, therefore, the settling time and noise for Setup 0. Rates shown are for the sinc5 + sinc 1 filter. See Table 19 to Table 22. 250,000 125,000 62,500 50,000 31,250 25,000 15,625 10,000 5000 2500 1000 500 397.5 200 100 59.92 49.96 20 16.66 10 5 Rev. 0 | Page 61 of 64 Reset 0x0 Access RW 0x0 0x0 R RW 0x5 RW 0x0 0x0 R RW 0x0 RW AD7175-8 Data Sheet FILTER CONFIGURATION REGISTER 1 TO FILTER CONFIGURATION REGISTER 7 Address: 0x29 to 0x2F, Reset: 0x0500, Name: FILTCON1 to FILTCON7 The remaining seven filter configuration registers share the same layout as Filter Configuration Register 0. Table 38. FILTCON1 to FILTCON7 Register Map Reg. 0x29 Name FILTCON1 0x2A FILTCON2 0x2B 0x2C 0x2D 0x2E 0x2F FILTCON3 FILTCON4 FILTCON5 FILTCON6 FILTCON7 Bits [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] Bit 7 SINC3_MAP1 RESERVED SINC3_MAP2 RESERVED SINC3_MAP3 RESERVED SINC3_MAP4 RESERVED SINC3_MAP5 RESERVED SINC3_MAP6 RESERVED SINC3_MAP7 RESERVED Bit 6 Bit 5 Bit 4 RESERVED ORDER1 RESERVED ORDER2 RESERVED ORDER3 RESERVED ORDER4 RESERVED ORDER5 RESERVED ORDER6 RESERVED ORDER7 Bit 3 ENHFILTEN1 Bit 2 Bit 1 Bit 0 ENHFILT1 Reset 0x0500 RW RW ENHFILT2 0x0500 RW ENHFILT3 0x0500 RW ENHFILT4 0x0500 RW ENHFILT5 0x0500 RW ENHFILT6 0x0500 RW ENHFILT7 0x0500 RW ODR1 ENHFILTEN2 ODR2 ENHFILTEN3 ODR3 ENHFILTEN4 ODR4 ENHFILTEN5 ODR5 ENHFILTEN6 ODR6 ENHFILTEN7 ODR7 OFFSET REGISTER 0 Address: 0x30, Reset: 0x800000, Name: OFFSET0 The offset (zero-scale) registers are 24-bit registers that can be used to compensate for any offset error in the ADC or in the system. Table 39. Bit Descriptions for OFFSET0 Bits [23:0] Bit Name OFFSET0 Settings Description Offset calibration coefficient for Setup 0. Reset 0x800000 Access RW OFFSET REGISTER 1 TO OFFSET REGISTER 7 Address: 0x31 to 0x37, Reset: 0x800000, Name: OFFSET1 to OFFSET7 The remaining seven offset registers share the same layout as Offset Register 0. Table 40. OFFSET1 to OFFSET7 Register Map Reg. 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 Name OFFSET0 OFFSET1 OFFSET2 OFFSET3 OFFSET4 OFFSET5 OFFSET6 OFFSET7 Bits [23:0] [23:0] [23:0] [23:0] [23:0] [23:0] [23:0] [23:0] Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 OFFSET0[23:0] OFFSET1[23:0] OFFSET2[23:0] OFFSET3[23:0] OFFSET4[23:0] OFFSET5[23:0] OFFSET6[23:0] OFFSET7[23:0] Bit 2 Bit 1 Bit 0 Reset 0x800000 0x800000 0x800000 0x800000 0x800000 0x800000 0x800000 0x800000 RW RW RW RW RW RW RW RW RW GAIN REGISTER 0 Address: 0x38, Reset: 0x5XXXX0, Name: GAIN0 The gain (full-scale) registers are 24-bit registers that can be used to compensate for any gain error in the ADC or in the system. Table 41. Bit Descriptions for GAIN0 Bits [23:0] Bit Name GAIN0 Settings Description Gain calibration coefficient for Setup 0. Rev. 0 | Page 62 of 64 Reset 0x5XXXX0 Access RW Data Sheet AD7175-8 GAIN REGISTER 1 TO GAIN REGISTER 7 Address: 0x39 to 0x3F, Reset: 0x5XXXX0, Name: GAIN1 to GAIN7 The remaining seven gain registers share the same layout as Gain Register 0. Table 42. GAIN1 to GAIN7 Register Map Reg. 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F Name GAIN0 GAIN1 GAIN2 GAIN3 GAIN4 GAIN5 GAIN6 GAIN7 Bits [23:0] [23:0] [23:0] [23:0] [23:0] [23:0] [23:0] [23:0] Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 GAIN0[23:0] GAIN1[23:0] GAIN2[23:0] GAIN3[23:0] GAIN4[23:0] GAIN5[23:0] GAIN6[23:0] GAIN7[23:0] Rev. 0 | Page 63 of 64 Bit 2 Bit 1 Bit 0 Reset 0x5XXXX0 0x5XXXX0 0x5XXXX0 0x5XXXX0 0x5XXXX0 0x5XXXX0 0x5XXXX0 0x5XXXX0 RW RW RW RW RW RW RW RW RW AD7175-8 Data Sheet OUTLINE DIMENSIONS 6.10 6.00 SQ 5.90 31 40 30 0.50 BSC 1 0.80 0.75 0.70 0.45 0.40 0.35 10 11 20 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF SEATING PLANE 4.05 3.90 SQ 3.75 EXPOSED PAD 21 TOP VIEW PIN 1 INDICATOR BOTTOM VIEW 0.25 MIN FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COMPLIANT TO JEDEC STANDARDS MO-220-WJJD. 05-06-2011-A PIN 1 INDICATOR 0.30 0.25 0.18 Figure 72. 40-Lead Lead Frame Chip Scale Package [LFCSP_WQ] 6 mm × 6 mm Body, Very Very Thin Quad (CP-40-14) Dimensions shown in millimeters ORDERING GUIDE Model1 AD7175-8BCPZ AD7175-8BCPZ-RL AD7175-8BCPZ-RL7 1 Temperature Range −40°C to +105°C −40°C to +105°C −40°C to +105°C Package Description 40-Lead Lead Frame Chip Scale Package [LFCSP_WQ] 40-Lead Lead Frame Chip Scale Package [LFCSP_WQ] 40-Lead Lead Frame Chip Scale Package [LFCSP_WQ] Z = RoHS Compliant Part. ©2015 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D12911-0-10/15(0) Rev. 0 | Page 64 of 64 Package Option CP-40-14 CP-40-14 CP-40-14