TI MSP430F439IPNR Mixed signal microcontroller Datasheet

MSP430F43x
MIXED SIGNAL MICROCONTROLLER
SLAS713 -- JUNE 2010
D Low Supply-Voltage Range, 1.8 V to 3.6 V
D Ultralow-Power Consumption:
D
D
D
D
D
D
D
D
D
-- Active Mode: 300 µA at 1 MHz, 2.2 V
-- Standby Mode: 1.1 µA
-- Off Mode (RAM Retention): 0.1 µA
Five Power Saving Modes
Wake-Up From Standby Mode in Less
Than 6 µs
16-Bit RISC Architecture,
125-ns Instruction Cycle Time
Single-Channel Internal DMA
12-Bit A/D Converter With Internal
Reference, Sample-and-Hold and
Autoscan Feature
16-Bit Timer_A With Three
Capture/Compare Registers
16-Bit Timer_B With Three
Capture/Compare-With-Shadow Registers
On-Chip Comparator
Serial Communication Interface (USART),
Select Asynchronous UART or
Synchronous SPI by Software
D Brownout Detector
D Supply Voltage Supervisor/Monitor With
Programmable Level Detection
D Bootstrap Loader
D Serial Onboard Programming,
D
D
D
No External Programming Voltage Needed
Programmable Code Protection by Security
Fuse
Integrated LCD Driver for Up to
128 Segments
Family Members Include:
-- MSP430F438:
48KB+256B Flash Memory,
2KB RAM
-- MSP430F439:
60KB+256B Flash Memory,
2KB RAM
For Complete Module Descriptions, See
The MSP430x4xx Family User’s Guide,
Literature Number SLAU056
description
The Texas Instruments MSP430 family of ultralow power microcontrollers consists of several devices featuring
different sets of peripherals targeted for various applications. The architecture, combined with five low-power
modes, is optimized to achieve extended battery life in portable measurement applications. The device features
a powerful 16-bit RISC CPU, 16-bit registers, and constant generators that contribute to maximum code
efficiency. The digitally controlled oscillator (DCO) allows wake-up from low-power modes to active mode in less
than 6µs.
The MSP430F43x series are microcontroller configurations with two 16-bit timers, a high performance 12-bit
A/D converter, one universal synchronous/asynchronous communication interface (USART), DMA, 48 I/O pins,
and a liquid crystal display (LCD) driver.
Typical applications for this device include analog and digital sensor systems, digital motor control, remote
controls, thermostats, digital timers, hand-held meters, etc.
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range
from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage
because very small parametric changes could cause the device not to meet its published specifications. These devices have limited
built-in ESD protection.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright  2010, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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AVAILABLE OPTIONS
PACKAGED DEVICES
TA
PLASTIC 80-PIN QFP
(PN)
MSP430F438IPN
MSP430F439IPN
--40°C to 85°C
†
For the most current package and ordering information, see the Package Option Addendum at the end
of this document, or see the TI web site at www.ti.com.
‡ Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
P6.2/A2
P6.1/A1
P6.0/A0
RST/NMI
TCK
TMS
TDI/TCLK
TDO/TDI
XT2IN
XT2OUT
P1.0/TA0
P1.1/TA0/MCLK
P1.2/TA1
P1.3/TBOUTH/SVSOUT
AVCC
DVSS1
AVSS
PN PACKAGE
(TOP VIEW)
P1.4/TBCLK/SMCLK
P1.5/TACLK/ACLK
P1.6/CA0
pin designation, MSP430F438IPN, MSP430F439IPN
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
1
60
2
59
3
58
4
57
5
56
6
55
7
54
8
53
9
52
10
11
MSP430F43xIPN
51
50
12
49
13
48
14
47
15
46
16
45
17
44
18
43
19
42
20
41
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
P4.0/S9
S10
S11
S12
S13
S14
S15
S16
S17
P2.7/ADC12CLK/S18
P2.6/CAOUT/S19
S20
S21
S22
S23
P3.7/S24
P3.6/S25/DMAE0
P3.5/S26
P3.4/S27
P3.3/UCLK0/S28
DVCC1
P6.3/A3
P6.4/A4
P6.5/A5
P6.6/A6
P6.7/A7/SVSIN
VREF+
XIN
XOUT
VeREF+
VREF-- /VeREF-P5.1/S0/A12
P5.0/S1/A13
P4.7/S2/A14
P4.6/S3/A15
P4.5/S4
P4.4/S5
P4.3/S6
P4.2/S7
P4.1/S8
2
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P1.7/CA1
P2.0/TA2
P2.1/TB0
P2.2/TB1
P2.3/TB2
P2.4/UTXD0
P2.5/URXD0
DVSS2
DVCC2
P5.7/R33
P5.6/R23
P5.5/R13
R03
P5.4/COM3
P5.3/COM2
P5.2/COM1
COM0
P3.0/STE0/S31
P3.1/SIMO0/S30
P3.2/SOMI0/S29
MSP430F43x
MIXED SIGNAL MICROCONTROLLER
SLAS713 -- JUNE 2010
functional block diagram
XIN
XT2IN
XT2OUT
DVCC1/2 DVSS1/2
XOUT
AVCC
AVSS
P1
P2
8
P4
P3
8
8
8
P6
P5
8
8
ACLK
Oscillator
FLL+
Flash
SMCLK
60KB
48KB
MCLK
8 MHz
CPU
incl. 16
Registers
Emulation
Module
RAM
2KB
ADC12
Port 1
Port 2
12-Biit
12 Channels
<10µs Conv.
8 I/O
Interrupt
Capability
8 I/O
Interrupt
Capability
Port 3
Port 4
Port 5
Port 6
8 I/O
8 I/O
8 I/O
8 I/O
LCD
128
Segments
1,2,3,4 MUX
UART Mode
SPI Mode
MAB
MDB
POR/
SVS/
Brownout
JTAG
Interface
DMA
Controller
1 Channel
Watchdog
Timer
WDT
15/16-Bit
Timer_B3
3 CC Reg
Shadow
Reg
Timer_A3
3 CC Reg
Comparator_
A
Basic
Timer 1
1 Interrupt
Vector
USART0
fLCD
RST/NMI
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Terminal Functions
TERMINAL
PN
NAME
NO.
DESCRIPTION
I/O
DVCC1
1
P6.3/A3
2
I/O
General-purpose digital I/O / analog input a3—12-bit ADC
P6.4/A4
3
I/O
General-purpose digital I/O / analog input a4—12-bit ADC
P6.5/A5
4
I/O
General-purpose digital I/O / analog input a5—12-bit ADC
P6.6/A6
5
I/O
General-purpose digital I/O / analog input a6—12-bit ADC
P6.7/A7/SVSIN
6
I/O
General-purpose digital I/O / analog input a7—12-bit ADC / analog input to supply voltage
supervisor
VREF+
7
O
Positive output terminal of the reference voltage in the ADC
XIN
8
I
Input terminal of crystal oscillator XT1
XOUT
9
O
Output terminal of crystal oscillator XT1
VeREF+
10
I/O
Positive input terminal for an external reference voltage to the 12-bit ADC
VREF-- /VeREF--
11
I
P5.1/S0/A12
12
I/O
General-purpose digital I/O / LCD segment output 0/ analog input a12—12-bit ADC
P5.0/S1/A13
13
I/O
General-purpose digital I/O / LCD segment output 1/ analog input a13—12-bit ADC
P4.7/S2/A14
14
I/O
General-purpose digital I/O / LCD segment output 2/ analog input a14—12-bit ADC
P4.6/S3/A15
15
I/O
General-purpose digital I/O / LCD segment output 3/ analog input a15—12-bit ADC
P4.5/S4
16
I/O
General-purpose digital I/O / LCD segment output 4
P4.4/S5
17
I/O
General-purpose digital I/O / LCD segment output 5
P4.3/S6
18
I/O
General-purpose digital I/O / LCD segment output 6
P4.2/S7
19
I/O
General-purpose digital I/O / LCD segment output 7
P4.1/S8
20
I/O
General-purpose digital I/O / LCD segment output 8
P4.0/S9
21
I/O
General-purpose digital I/O / LCD segment output 9
S10
22
O
LCD segment output 10
S11
23
O
LCD segment output 11
S12
24
O
LCD segment output 12
S13
25
O
LCD segment output 13
S14
26
O
LCD segment output 14
S15
27
O
LCD segment output 15
S16
28
O
LCD segment output 16
S17
29
O
LCD segment output 17
P2.7/ADC12CLK/S18
30
I/O
General-purpose digital I/O / conversion clock—12-bit ADC / LCD segment output 18
P2.6/CAOUT/S19
31
I/O
General-purpose digital I/O / Comparator_A output / LCD segment output 19
S20
32
O
LCD segment output 20
S21
33
O
LCD segment output 21
S22
34
O
LCD segment output 22
S23
35
O
LCD segment output 23
P3.7/S24
36
I/O
General-purpose digital I/O / LCD segment output 24
P3.6/S25/DMAE0
37
I/O
General-purpose digital I/O / LCD segment output 25/DMA Channel 0 external trigger
P3.5/S26
38
I/O
General-purpose digital I/O / LCD segment output 26
P3.4/S27
39
I/O
General-purpose digital I/O / LCD segment output 27
4
Digital supply voltage, positive terminal.
Negative terminal for the 12-bit ADC reference voltage for both sources, the internal reference
voltage or an external applied reference voltage to the 12-bit ADC.
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Terminal Functions (Continued)
TERMINAL
PN
NAME
NO.
DESCRIPTION
I/O
P3.3/UCLK0/S28
40
I/O
General-purpose digital I/O / ext. clock i/p—USART0/UART or SPI mode, clock o/p—USART0/SPI mode
/ LCD segment output 28
P3.2/SOMI0/S29
41
I/O
General-purpose digital I/O / slave out/master in of USART0/SPI mode / LCD segment output 29
P3.1/SIMO0/S30
42
I/O
General-purpose digital I/O / slave out/master out of USART0/SPI mode / LCD segment output 30
P3.0/STE0/S31
43
I/O
General-purpose digital I/O / slave transmit enable-USART0/SPI mode / LCD segment output 31
COM0
44
O
Common output, COM0--3 are used for LCD backplanes.
P5.2/COM1
45
I/O
General-purpose digital I/O / common output, COM0--3 are used for LCD backplanes.
P5.3/COM2
46
I/O
General-purpose digital I/O / common output, COM0--3 are used for LCD backplanes.
P5.4/COM3
47
I/O
General-purpose digital I/O / common output, COM0--3 are used for LCD backplanes.
R03
48
I
P5.5/R13
49
I/O
General-purpose digital I/O / input port of third most positive analog LCD level (V4 or V3)
P5.6/R23
50
I/O
General-purpose digital I/O / input port of second most positive analog LCD level (V2)
P5.7/R33
51
I/O
General-purpose digital I/O / output port of most positive analog LCD level (V1)
DVCC2
52
DVSS2
53
P2.5/URXD0
54
I/O
General-purpose digital I/O / receive data in—USART0/UART mode
P2.4/UTXD0
55
I/O
General-purpose digital I/O / transmit data out—USART0/UART mode
P2.3/TB2
56
I/O
General-purpose digital I/O / Timer_B3 CCR2.
Capture: CCI2A/CCI2B input, compare: Out2 output
P2.2/TB1
57
I/O
General-purpose digital I/O / Timer_B3 CCR1.
Capture: CCI1A/CCI1B input, compare: Out1 output
P2.1/TB0
58
I/O
General-purpose digital I/O / Timer_B3 CCR0.
Capture: CCI0A/CCI0B input, compare: Out0 output
P2.0/TA2
59
I/O
General-purpose digital I/O / Timer_A
Capture: CCI2A input, compare: Out2 output
P1.7/CA13
60
I/O
General-purpose digital I/O / Comparator_A input
P1.6/CA0
61
I/O
General-purpose digital I/O / Comparator_A input
P1.5/TACLK/
ACLK
62
I/O
General-purpose digital I/O / Timer_A, clock signal TACLK input /
ACLK output (divided by 1, 2, 4, or 8)
P1.4/TBCLK/
SMCLK
63
I/O
General-purpose digital I/O / input clock TBCLK—Timer_B3 / submain system clock SMCLK output
P1.3/TBOUTH/
SVSOUT
64
I/O
General-purpose digital I/O / switch all PWM digital output ports to high impedance—Timer_B3 TB0 to TB2
/ SVS: output of SVS comparator
P1.2/TA1
65
I/O
General-purpose digital I/O / Timer_A, Capture: CCI1A, compare: Out1 output
P1.1/TA0/MCLK
66
I/O
General-purpose digital I/O / Timer_A. Capture: CCI0B / MCLK output. Note: TA0 is only an input on this
pin / BSL receive
P1.0/TA0
67
I/O
General-purpose digital I/O / Timer_A. Capture: CCI0A input, compare: Out0 output / BSL transmit
XT2OUT
68
O
Output terminal of crystal oscillator XT2
XT2IN
69
I
Input port for crystal oscillator XT2. Only standard crystals can be connected.
TDO/TDI
70
I/O
TDI/TCLK
71
I
Test data input or test clock input. The device protection fuse is connected to TDI/TCLK.
TMS
72
I
Test mode select. TMS is used as an input port for device programming and test.
TCK
73
I
Test clock. TCK is the clock input port for device programming and test.
Input port of fourth positive (lowest) analog LCD level (V5)
Digital supply voltage, positive terminal.
Digital supply voltage, negative terminal.
Test data output port. TDO/TDI data output or programming data input terminal
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Terminal Functions (Continued)
TERMINAL
PN
NAME
NO.
DESCRIPTION
I/O
RST/NMI
74
I
P6.0/A0
75
I/O
General-purpose digital I/O / analog input a0 -- 12-bit ADC
P6.1/A1
76
I/O
General-purpose digital I/O / analog input a1 -- 12-bit ADC
P6.2/A2
77
I/O
General-purpose digital I/O / analog input a2 -- 12-bit ADC
AVSS
78
Analog supply voltage, negative terminal. Supplies SVS, brownout, oscillator, comparator_A, port 1,
and LCD resistive divider circuitry.
DVSS1
79
Digital supply voltage, negative terminal.
AVCC
80
Analog supply voltage, positive terminal. Supplies SVS, brownout, oscillator, comparator_A, port 1,
and LCD resistive divider circuitry; must not power up prior to DVCC1/DVCC2.
6
Reset or nonmaskable interrupt input
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MSP430F43x
MIXED SIGNAL MICROCONTROLLER
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short-form description
CPU
The MSP430 CPU has a 16-bit RISC architecture
that is highly transparent to the application. All
operations, other than program-flow instructions,
are performed as register operations in
conjunction with seven addressing modes for
source operand and four addressing modes for
destination operand.
Program Counter
PC/R0
Stack Pointer
SP/R1
SR/CG1/R2
Status Register
Constant Generator
The CPU is integrated with 16 registers that
provide reduced instruction execution time. The
register-to-register operation execution time is
one cycle of the CPU clock.
Four of the registers, R0 to R3, are dedicated as
program counter, stack pointer, status register,
and constant generator respectively. The
remaining registers are general-purpose
registers.
Peripherals are connected to the CPU using data,
address, and control buses, and can be handled
with all instructions.
instruction set
The instruction set consists of 51 instructions with
three formats and seven address modes. Each
instruction can operate on word and byte data.
Table 1 shows examples of the three types of
instruction formats; Table 2 shows the address
modes.
CG2/R3
General-Purpose Register
R4
General-Purpose Register
R5
General-Purpose Register
R6
General-Purpose Register
R7
General-Purpose Register
R8
General-Purpose Register
R9
General-Purpose Register
R10
General-Purpose Register
R11
General-Purpose Register
R12
General-Purpose Register
R13
General-Purpose Register
R14
General-Purpose Register
R15
Table 1. Instruction Word Formats
Dual operands, source-destination
e.g. ADD R4,R5
R4 + R5 ------> R5
Single operands, destination only
e.g. CALL
PC ---->(TOS), R8----> PC
Relative jump, un/conditional
e.g. JNE
R8
Jump-on-equal bit = 0
Table 2. Address Mode Descriptions
ADDRESS MODE
S D
SYNTAX
EXAMPLE
Register
F F
MOV Rs,Rd
MOV R10,R11
Indexed
F F
MOV X(Rn),Y(Rm)
MOV 2(R5),6(R6)
Symbolic (PC relative)
F F
MOV EDE,TONI
Absolute
F F
MOV &MEM, &TCDAT
OPERATION
R10
—> R11
M(2+R5)—> M(6+R6)
M(EDE) —> M(TONI)
M(MEM) —> M(TCDAT)
Indirect
F
MOV @Rn,Y(Rm)
MOV @R10,Tab(R6)
M(R10) —> M(Tab+R6)
Indirect
autoincrement
F
MOV @Rn+,Rm
MOV @R10+,R11
M(R10) —> R11
R10 + 2—> R10
F
MOV #X,TONI
MOV #45,TONI
Immediate
NOTE: S = source
#45
—> M(TONI)
D = destination
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operating modes
The MSP430 has one active mode and five software selectable low-power modes of operation. An interrupt
event can wake up the device from any of the five low-power modes, service the request, and restore back to
the low-power mode on return from the interrupt program.
The following six operating modes can be configured by software:
D Active mode (AM)
--
All clocks are active
D Low-power mode 0 (LPM0)
--
CPU is disabled
--
ACLK and SMCLK remain active, MCLK is disabled
--
FLL+ loop control remains active
D Low-power mode 1 (LPM1)
--
CPU is disabled
--
FLL+ loop control is disabled
--
ACLK and SMCLK remain active, MCLK is disabled
D Low-power mode 2 (LPM2)
--
CPU is disabled
--
MCLK, FLL+ loop control, and DCOCLK are disabled
--
DCO’s dc-generator remains enabled
--
ACLK remains active
D Low-power mode 3 (LPM3)
--
CPU is disabled
--
MCLK, FLL+ loop control, and DCOCLK are disabled
--
DCO’s dc-generator is disabled
--
ACLK remains active
D Low-power mode 4 (LPM4)
8
--
CPU is disabled
--
ACLK is disabled
--
MCLK, FLL+ loop control, and DCOCLK are disabled
--
DCO’s dc-generator is disabled
--
Crystal oscillator is stopped
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interrupt vector addresses
The interrupt vectors and the power-up starting address are located in the address range 0FFFFh to 0FFE0h.
The vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence.
INTERRUPT SOURCE
INTERRUPT FLAG
SYSTEM INTERRUPT
WORD
ADDRESS
PRIORITY
Power-Up
External Reset
Watchdog
Flash Memory
WDTIFG
KEYV
(see Note 1)
Reset
0FFFEh
15, highest
NMI
Oscillator Fault
Flash Memory Access Violation
NMIIFG (see Notes 1 and 3)
OFIFG (see Notes 1 and 3)
ACCVIFG (see Notes 1 and 3)
(Non)maskable
(Non)maskable
(Non)maskable
0FFFCh
14
Timer_B3
TBCCR0 CCIFG0 (see Note 2)
Maskable
0FFFAh
13
Timer_B3
TBCCR1 CCIFG1, TBCCR2 CCIFG2,
TBIFG (see Notes 1 and 2)
Maskable
0FFF8h
12
Comparator_A
CAIFG
Maskable
0FFF6h
11
Watchdog Timer
WDTIFG
Maskable
0FFF4h
10
USART0 Receive
URXIFG0
Maskable
0FFF2h
9
USART0 Transmit
UTXIFG0
Maskable
0FFF0h
8
ADC12
ADC12IFG (see Notes 1 and 2)
Maskable
0FFEEh
7
Timer_A3
TACCR0 CCIFG0 (see Note 2)
Maskable
0FFECh
6
Timer_A3
TACCR1 CCIFG1 and TACCR2 CCIFG2,
TAIFG (see Notes 1 and 2)
Maskable
0FFEAh
5
I/O Port P1 (Eight Flags)
P1IFG.0 to P1IFG.7 (see Notes 1 and 2)
Maskable
0FFE8h
4
DMA
DMA0IFG (see Notes 1 and 2)
Maskable
0FFE6h
3
0FFE4h
2
I/O Port P2 (Eight Flags)
P2IFG.0 to P2IFG.7 (see Notes 1 and 2)
Maskable
0FFE2h
1
Basic Timer1
BTIFG
Maskable
0FFE0h
0, lowest
NOTES: 1. Multiple source flags
2. Interrupt flags are located in the module.
3. (Non)maskable: the individual interrupt-enable bit can disable an interrupt event, but the general-interrupt enable cannot disable
it.
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special function registers
The MSP430 special function registers(SFR) are located in the lowest address space and are organized as byte
mode registers. SFRs should be accessed with byte instructions.
interrupt enable 1 and 2
7
Address
0h
6
UTXIE0
rw–0
URXIE0
rw–0
5
4
ACCVIE
NMIIE
rw–0
3
2
1
OFIE
rw–0
rw–0
Watchdog timer interrupt enable. Inactive if watchdog mode is selected.
Active if watchdog timer is configured as a general-purpose timer.
OFIE:
Oscillator fault interrupt enable
NMIIE:
Nonmaskable interrupt enable
ACCVIE:
Flash access violation interrupt enable
URXIE0:
USART0: UART and SPI receive-interrupt enable
UTXIE0:
USART0: UART and SPI transmit-interrupt enable
7
6
5
WDTIE
rw–0
WDTIE:
Address
0
4
3
2
1
0
4
3
2
1
0
BTIE
01h
rw–0
BTIE:
Basic timer interrupt enable
interrupt flag register 1 and 2
7
Address
02h
6
UTXIFG0
rw–1
5
URXIFG0
NMIIFG
rw–0
WDTIFG:
rw–0
rw–1
Flag set on oscillator fault
NMIIFG:
Set via RST/NMI pin
URXIFG0:
USART0: UART and SPI receive flag
UTXIFG0:
USART0: UART and SPI transmit flag
7
03h
6
5
4
3
BTIFG
rw–0
BTIFG:
10
WDTIFG
rw–(0)
Set on watchdog timer overflow (in watchdog mode) or security key violation
Reset on VCC power-on or a reset condition at the RST/NMI pin in reset mode
OFIFG:
Address
OFIFG
Basic timer flag
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MIXED SIGNAL MICROCONTROLLER
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module enable registers 1 and 2
7
UTXE0
Address
04h
rw–0
6
URXE0
USPIE0
5
4
3
1
0
2
1
0
rw–0
URXE0:
USART0: UART mode receive enable
UTXE0:
USART0: UART mode transmit enable
USPIE0:
USART0: SPI mode transmit and receive enable
Address
2
7
6
5
4
3
05h
Legend: rw:
rw–0,1:
rw–(0,1):
Bit Can Be Read and Written
Bit Can Be Read and Written. It Is Reset or Set by PUC.
Bit Can Be Read and Written. It Is Reset or Set by POR.
SFR Bit Not Present in Device
memory organization
MSP430F438
MSP430F439
Memory
Main: interrupt vector
Main: code memory
Size
Flash
Flash
48KB
0FFFFh -- 0FFE0h
0FFFFh -- 04000h
60KB
0FFFFh -- 0FFE0h
0FFFFh -- 01100h
Information memory
Size
Flash
256 Byte
010FFh -- 01000h
256 Byte
010FFh -- 01000h
Boot memory
Size
ROM
1KB
0FFFh -- 0C00h
1KB
0FFFh -- 0C00h
Size
2KB
09FFh -- 0200h
2KB
09FFh -- 0200h
16-bit
8-bit
8-bit SFR
01FFh -- 0100h
0FFh -- 010h
0Fh -- 00h
01FFh -- 0100h
0FFh -- 010h
0Fh -- 00h
RAM
Peripherals
bootstrap loader (BSL)
The MSP430 bootstrap loader (BSL) enables users to program the flash memory or RAM using a UART serial
interface. Access to the MSP430 memory via the BSL is protected by user-defined password. For complete
description of the features of the BSL and its implementation, see the MSP430 Memory Programming User’s
Guide (SLAU265).
BSL Function
PN Package Pins
Data Transmit
67 -- P1.0
Data Receive
66 -- P1.1
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flash memory
The flash memory can be programmed via the JTAG port, the bootstrap loader, or in-system by the CPU. The
CPU can perform single-byte and single-word writes to the flash memory. Features of the flash memory include:
D Flash memory has n segments of main memory and two segments of information memory (A and B) of
128 bytes each. Each segment in main memory is 512 bytes in size.
D Segments 0 to n may be erased in one step, or each segment may be individually erased.
D Segments A and B can be erased individually, or as a group with segments 0 to n.
Segments A and B are also called information memory.
D New devices may have some bytes programmed in the information memory (needed for test during
manufacturing). The user should perform an erase of the information memory prior to the first use.
32KB
48KB
60KB
0FFFFh
0FFFFh
0FFFFh
0FE00h
0FDFFh
0FE00h
0FDFFh
0FE00h
0FDFFh
Segment 1
0FC00h
0FBFFh
0FC00h
0FBFFh
0FC00h
0FBFFh
Segment 2
0FA00h
0F9FFh
0FA00h
0F9FFh
0FA00h
0F9FFh
08400h
083FFh
04400h
043FFh
01400h
013FFh
08200h
081FFh
04200h
041FFh
01200h
011FFh
08000h
010FFh
04000h
010FFh
01100h
010FFh
01080h
0107Fh
01080h
0107Fh
01080h
0107Fh
01000h
01000h
01000h
Segment 0
w/ Interrupt Vectors
Main
Memory
Segment n-1
Segment n†
Segment A
†
Segment B
MSP430F439 flash segment n = 256 bytes.
12
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Memory
MSP430F43x
MIXED SIGNAL MICROCONTROLLER
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peripherals
Peripherals are connected to the CPU through data, address, and control busses and can be handled using
all instructions. For complete module descriptions, see the MSP430x4xx Family User’s Guide (SLAU056).
DMA controller
The DMA controller allows movement of data from one memory address to another without CPU intervention.
For example, the DMA controller can be used to move data from the ADC12 conversion memory to RAM. Using
the DMA controller can increase the throughput of peripheral modules. The DMA controller reduces system
power consumption by allowing the CPU to remain in sleep mode without having to awaken to move data to
or from a peripheral.
oscillator and system clock
The clock system in the MSP430F43x family of devices is supported by the FLL+ module that includes support
for a 32768-Hz watch crystal oscillator, an internal digitally-controlled oscillator (DCO), and a high-frequency
crystal oscillator. The FLL+ clock module is designed to meet the requirements of both low system cost and
low-power consumption. The FLL+ features digital frequency locked loop (FLL) hardware which in conjunction
with a digital modulator stabilizes the DCO frequency to a programmable multiple of the watch crystal frequency.
The internal DCO provides a fast turn-on clock source and stabilizes in less than 6 µs. The FLL+ module
provides the following clock signals:
D
D
D
D
Auxiliary clock (ACLK), sourced from a 32768-Hz watch crystal or a high-frequency crystal.
Main clock (MCLK), the system clock used by the CPU.
Sub-Main clock (SMCLK), the sub-system clock used by the peripheral modules.
ACLK/n, the buffered output of ACLK, ACLK/2, ACLK/4, or ACLK/8.
brownout, supply voltage supervisor
The brownout circuit is implemented to provide the proper internal reset signal to the device during power-on
and power-off. The supply voltage supervisor (SVS) circuitry detects if the supply voltage drops below a user
selectable level and supports both supply voltage supervision (the device is automatically reset) and supply
voltage monitoring (SVM, the device is not automatically reset).
The CPU begins code execution after the brownout circuit releases the device reset. However, VCC may not
have ramped to VCC(min) at that time. The user must insure the default FLL+ settings are not changed until VCC
reaches VCC(min). If desired, the SVS circuit can be used to determine when VCC reaches VCC(min).
digital I/O
There are six 8-bit I/O ports implemented—ports P1 through P6:
D
D
D
D
All individual I/O bits are independently programmable.
Any combination of input, output, and interrupt conditions is possible.
Edge-selectable interrupt input capability for all the eight bits of ports P1 and P2.
Read/write access to port-control registers is supported by all instructions.
Basic Timer1
The Basic Timer1 has two independent 8-bit timers which can be cascaded to form a 16-bit timer/counter. Both
timers can be read and written by software. The Basic Timer1 can be used to generate periodic interrupts and
clock for the LCD module.
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LCD drive
The LCD driver generates the segment and common signals required to drive an LCD display. The LCD
controller has dedicated data memory to hold segment drive information. Common and segment signals are
generated as defined by the mode. Static, 2-MUX, 3-MUX, and 4-MUX LCDs are supported by this peripheral.
watchdog timer
The primary function of the watchdog timer (WDT) module is to perform a controlled system restart after a
software problem occurs. If the selected time interval expires, a system reset is generated. If the watchdog
function is not needed in an application, the module can be configured as an interval timer and can generate
interrupts at selected time intervals.
USART0
The MSP430F43x has one hardware universal synchronous/asynchronous receive transmit (USART)
peripheral module that is used for serial data communication. The USART supports synchronous SPI (3 or 4
pin) and asynchronous UART communication protocols, using double-buffered transmit and receive channels.
Timer_A3
Timer_A3 is a 16-bit timer/counter with three capture/compare registers. Timer_A3 can support multiple
capture/compares, PWM outputs, and interval timing. Timer_A3 also has extensive interrupt capabilities.
Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare
registers.
Timer_A3 Signal Connections
Input Pin Number
PN
Device Input
Signal
Module Input
Name
62 - P1.5
TACLK
TACLK
ACLK
ACLK
SMCLK
SMCLK
62 - P1.5
TACLK
INCLK
67 - P1.0
TA0
CCI0A
66 - P1.1
TA0
CCI0B
DVSS
GND
65 - P1.2
59 - P2.0
14
Module
Block
Module Output
Signal
Timer
NA
Output Pin Number
PN
67 - P1.0
CCR0
TA0
DVCC
VCC
TA1
CCI1A
65 - P1.2
CAOUT (internal)
CCI1B
ADC12 (internal)
DVSS
GND
DVCC
VCC
TA2
CCI2A
ACLK (internal)
CCI2B
DVSS
GND
DVCC
VCC
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Timer_B3
Timer_B3 is a 16-bit timer/counter with three capture/compare registers. Timer_B3 can support multiple
capture/compares, PWM outputs, and interval timing. Timer_B3 also has extensive interrupt capabilities.
Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare
registers.
Timer_B3 Signal Connections
Input Pin Number
PN
Device Input
Signal
Module Input
Name
63 - P1.4
TBCLK
TBCLK
Module
Block
Module Output
Signal
Timer
NA
Output Pin Number
PN
ACLK
ACLK
SMCLK
SMCLK
63 - P1.4
TBCLK
INCLK
58 - P2.1
TB0
CCI0A
58 - P2.1
ADC12 (internal)
58 - P2.1
TB0
CCI0B
DVSS
GND
DVCC
VCC
57 - P2.2
TB1
CCI1A
57 - P2.2
57 - P2.2
TB1
CCI1B
ADC12 (internal)
DVSS
GND
DVCC
VCC
56 - P2.3
TB2
CCI2A
56 - P2.3
TB2
CCI2B
DVSS
GND
DVCC
VCC
CCR0
CCR1
TB0
TB1
56 - P2.3
CCR2
TB2
Comparator_A
The primary function of the Comparator_A module is to support precision slope analog-to-digital conversions,
battery-voltage supervision, and monitoring of external analog signals.
ADC12
The ADC12 module supports fast, 12-bit analog-to-digital conversions. The module implements a 12-bit SAR
core, sample select control, reference generator and a 16 word conversion-and-control buffer. The
conversion-and-control buffer allows up to 16 independent ADC samples to be converted and stored without
any CPU intervention.
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peripheral file map
PERIPHERALS WITH WORD ACCESS
Watchdog
Watchdog timer control
WDTCTL
0120h
Timer_B3
_
Capture/compare register 2
TBCCR2
0196h
Capture/compare register 1
TBCCR1
0194h
Capture/compare register 0
TBCCR0
0192h
Timer_B register
TBR
0190h
Capture/compare control 2
TBCCTL2
0186h
Capture/compare control 1
TBCCTL1
0184h
Capture/compare control 0
TBCCTL0
0182h
Timer_B control
TBCTL
0180h
Timer_B interrupt vector
TBIV
011Eh
Capture/compare register 2
TACCR2
0176h
Capture/compare register 1
TACCR1
0174h
Capture/compare register 0
TACCR0
0172h
Timer_A register
TAR
0170h
Capture/compare control 2
TACCTL2
0166h
Capture/compare control 1
TACCTL1
0164h
Capture/compare control 0
TACCTL0
0162h
Timer_A control
TACTL
0160h
Timer_A interrupt vector
TAIV
012Eh
Flash control 3
FCTL3
012Ch
Flash control 2
FCTL2
012Ah
Flash control 1
FCTL1
0128h
DMA module control 0
DMACTL0
0122h
DMA module control 1
DMACTL1
0124h
DMA channel 0 control
DMA0CTL
01E0h
DMA channel 0 source address
DMA0SA
01E2h
DMA channel 0 destination address
DMA0DA
01E4h
DMA channel 0 transfer size
DMA0SZ
01E6h
Timer_A3
_
Flash
DMA
16
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peripheral file map (continued)
PERIPHERALS WITH WORD ACCESS (CONTINUED)
ADC12
Conversion memory 15
ADC12MEM15
015Eh
See also Peripherals
with Byte
y Access
Conversion memory 14
ADC12MEM14
015Ch
Conversion memory 13
ADC12MEM13
015Ah
Conversion memory 12
ADC12MEM12
0158h
Conversion memory 11
ADC12MEM11
0156h
Conversion memory 10
ADC12MEM10
0154h
Conversion memory 9
ADC12MEM9
0152h
Conversion memory 8
ADC12MEM8
0150h
Conversion memory 7
ADC12MEM7
014Eh
Conversion memory 6
ADC12MEM6
014Ch
Conversion memory 5
ADC12MEM5
014Ah
Conversion memory 4
ADC12MEM4
0148h
Conversion memory 3
ADC12MEM3
0146h
Conversion memory 2
ADC12MEM2
0144h
Conversion memory 1
ADC12MEM1
0142h
Conversion memory 0
ADC12MEM0
0140h
Interrupt-vector-word register
ADC12IV
01A8h
Inerrupt-enable register
ADC12IE
01A6h
Inerrupt-flag register
ADC12IFG
01A4h
Control register 1
ADC12CTL1
01A2h
Control register 0
ADC12CTL0
01A0h
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peripheral file map (continued)
PERIPHERALS WITH BYTE ACCESS
LCD memory 20
:
LCD memory 16
LCDM20
:
LCDM16
0A4h
:
0A0h
LCD memory 15
:
LCD memory 1
LCD control and mode
LCDM15
:
LCDM1
LCDCTL
09Fh
:
091h
090h
ADC12
ADC memory-control register 15
(Memory control
ADC memory-control register 14
registers require byte
ADC memory-control register 13
access)
ADC memory-control register 12
ADC12MCTL15
08Fh
ADC12MCTL14
08Eh
ADC12MCTL13
08Dh
ADC12MCTL12
08Ch
ADC memory-control register 11
ADC12MCTL11
08Bh
ADC memory-control register 10
ADC12MCTL10
08Ah
ADC memory-control register 9
ADC12MCTL9
089h
ADC memory-control register 8
ADC12MCTL8
088h
ADC memory-control register 7
ADC12MCTL7
087h
ADC memory-control register 6
ADC12MCTL6
086h
ADC memory-control register 5
ADC12MCTL5
085h
ADC memory-control register 4
ADC12MCTL4
084h
ADC memory-control register 3
ADC12MCTL3
083h
ADC memory-control register 2
ADC12MCTL2
082h
ADC memory-control register 1
ADC12MCTL1
081h
ADC memory-control register 0
ADC12MCTL0
080h
U0TXBUF
077h
U0RXBUF
076h
Baud rate
U0BR1
075h
Baud rate
U0BR0
074h
Modulation control
U0MCTL
073h
Receive control
U0RCTL
072h
Transmit control
U0TCTL
071h
USART control
U0CTL
070h
Comparator_A port disable
CAPD
05Bh
Comparator_A control 2
CACTL2
05Ah
Comparator_A control 1
CACTL1
059h
SVS control register (Reset by brownout signal)
SVSCTL
056h
LCD
USART0
Transmit buffer
(UART or SPI mode) Receive buffer
Comparator_A
p
_
BrownOUT, SVS
18
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peripheral file map (continued)
PERIPHERALS WITH BYTE ACCESS (CONTINUED)
FLL+ Clock
FLL+ Control 1
FLL_CTL1
054h
FLL+ Control 0
FLL_CTL0
053h
System clock frequency control
SCFQCTL
052h
System clock frequency integrator
SCFI1
051h
System clock frequency integrator
SCFI0
050h
Basic Timer1
BT counter 2
BT counter 1
BT control
BTCNT2
BTCNT1
BTCTL
047h
046h
040h
Port P6
Port P6 selection
P6SEL
037h
Port P6 direction
P6DIR
036h
Port P6 output
P6OUT
035h
Port P6 input
P6IN
034h
Port P5 selection
P5SEL
033h
Port P5 direction
P5DIR
032h
Port P5 output
P5OUT
031h
Port P5 input
P5IN
030h
Port P4 selection
P4SEL
01Fh
Port P4 direction
P4DIR
01Eh
Port P4 output
P4OUT
01Dh
Port P4 input
P4IN
01Ch
Port P3 selection
P3SEL
01Bh
Port P3 direction
P3DIR
01Ah
Port P3 output
P3OUT
019h
Port P3 input
P3IN
018h
Port P2 selection
P2SEL
02Eh
Port P2 interrupt enable
P2IE
02Dh
Port P2 interrupt-edge select
P2IES
02Ch
Port P2 interrupt flag
P2IFG
02Bh
Port P2 direction
P2DIR
02Ah
Port P2 output
P2OUT
029h
Port P2 input
P2IN
028h
Port P1 selection
P1SEL
026h
Port P1 interrupt enable
P1IE
025h
Port P1 interrupt-edge select
P1IES
024h
Port P1 interrupt flag
P1IFG
023h
Port P1 direction
P1DIR
022h
Port P1 output
P1OUT
021h
Port P1 input
P1IN
020h
SFR module enable 2
ME2
005h
SFR module enable 1
ME1
004h
SFR interrupt flag 2
IFG2
003h
SFR interrupt flag 1
IFG1
002h
SFR interrupt enable 2
IE2
001h
SFR interrupt enable 1
IE1
000h
Port P5
Port P4
Port P3
Port P2
Port P1
Special
p
functions
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absolute maximum ratings over operating free-air temperature (unless otherwise noted)†
Voltage applied at VCC to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . --0.3 V to 4.1 V
Voltage applied to any pin (see Note) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . --0.3 V to VCC + 0.3 V
Diode current at any device terminal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±2 mA
Storage temperature, Tstg: Unprogrammed device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . --55°C to 150°C
Programmed device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . --40°C to 85°C
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE: All voltages referenced to VSS. The JTAG fuse-blow voltage, VFB, is allowed to exceed the absolute maximum rating. The voltage is applied
to the TDI/TCLK pin when blowing the JTAG fuse.
recommended operating conditions
MIN
Supply voltage during program execution (see Note 1), VCC (AVCC = DVCC1/2 = VCC)
Supply voltage during program execution, SVS enabled, PORON=1
(see Note 1 and Note 2), VCC (AVCC = DVCC1/2 = VCC)
Supply voltage during flash memory programming (see Note 1),
VCC (AVCC = DVCC1/2 = VCC)
Supply voltage, VSS (AVSS = DVSS1/2 = VSS)
Operating free-air temperature range, TA
LFXT1 crystal frequency, f(LFXT1)
(see Note 3)
LF selected,
XTS_FLL=0
Watch crystal
XT1 selected,
XTS_FLL=1
Ceramic resonator
XT1 selected,
XTS_FLL=1
Crystal
UNITS
3.6
V
2
3.6
V
2.7
3.6
V
0
0
V
--40
85
°C
kHz
450
8000
kHz
1000
8000
kHz
450
8000
1000
8000
VCC = 1.8 V
DC
4.15
VCC = 3.6 V
DC
8
Crystal
Processor frequency
freq enc (signal MCLK),
MCLK) f(System)
MAX
32.768
Ceramic resonator
XT2 crystal
cr stal frequency,
freq enc f(XT2)
NOM
1.8
kH
kHz
MH
MHz
NOTES: 1. It is recommended to power AVCC and DVCC from the same source. A maximum difference of 0.3 V between AVCC and DVCC can
be tolerated during power up and operation.
2. The minimum operating supply voltage is defined according to the trip point where POR is going active by decreasing the supply
voltage. POR is going inactive when the supply voltage is raised above the minimum supply voltage plus the hysteresis of the SVS
circuitry.
3. In LF mode, the LFXT1 oscillator requires a watch crystal. In XT1 mode, LFXT1 accepts a ceramic resonator or a crystal.
f(System) MHz
8 MHz
Supply voltage range,
MSP430F43x, during
program execution
Supply voltage range, MSP430F43x,
during flash memory programming
4.15 MHz
1.8
2.7
3
Supply Voltage -- V
3.6
Figure 1. Frequency vs Supply Voltage, Typical Characteristics
20
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electrical characteristics over recommended operating free-air temperature (unless otherwise
noted)
supply current into AVCC + DVCC1/2 excluding external current
PARAMETER
TEST CONDITIONS
I(AM)
Active mode, (see Note 1)
f(MCLK) = f(SMCLK) = 1 MHz,
f(ACLK) = 32,768 Hz
XTS_FLL=0, SELM=(0,1)
TA = --40°C
40°C to 85°C
I(LPM0)
Low power mode, (LPM0)
Low-power
(see Note 1 and Note 4)
TA = --40°C
40°C to 85°C
I(LPM2)
Low-power mode, (LPM2),
f(MCLK) = f (SMCLK) = 0 MHz,
f(ACLK) = 32,768 Hz, SCG0 = 0
(see Note 2 and Note 4)
TA = --40°C
40°C to 85°C
TYP
MAX
VCC= 2.2 V
300
370
VCC = 3 V
470
570
I(LPM3)
Low-power mode, (LPM3)
f(MCLK) = f(SMCLK) = 0 MHz,
MHz
f(ACLK) = 32,768 Hz, SCG0 = 1
((see Note 2,, Note 3,, and Note 4))
TA = 60°C
VCC = 2.2 V
55
70
VCC = 3 V
95
110
VCC = 2.2 V
11
14
VCC = 3 V
17
22
I(LPM4)
Low-power mode, (LPM4)
f(MCLK) = 0 MHz,
MHz f(SMCLK) = 0 MHz,
MHz
f(ACLK) = 0 Hz, SCG0 = 1 (see Note 2 and Note 4)
VCC = 2
2.2
2V
1
2.0
1.1
2.0
2
3
3.5
6
TA = --40°C
1.8
2.8
1.6
2.7
2.5
3.5
TA = 85°C
4.2
7.5
TA = --40°C
0.1
0.5
TA = 25°C
0.1
0.5
0.7
1.1
TA = 60°C
TA = 60°C
VCC = 3 V
VCC = 2
2.2
2V
TA = 85°C
1.7
3
TA = --40°C
0.1
0.8
0.1
0.8
0.8
1.2
1.9
3.5
TA = 25°C
TA = 60°C
µA
A
µA
A
TA = 85°C
TA = 25°C
UNIT
µA
A
TA = --40°C
TA = 25°C
MIN
VCC = 3 V
TA = 85°C
µA
A
µA
A
NOTES: 1. Timer_B is clocked by f(DCOCLK) = f(DCO) = 1 MHz. All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.
2. All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.
3. The current consumption in LPM3 is measured with active Basic Timer1 and LCD (ACLK selected). The current consumption of the
Comparator_A and the SVS module are specified in the respective sections. The LPM3 currents are characterized with a KDS
Daishinku DT--38 (6 pF) crystal and OSCCAPx=01h.
4. Current for brownout included.
Current consumption of active mode versus system frequency
I(AM) = I(AM) [1 MHz] × f(System) [MHz]
Current consumption of active mode versus supply voltage
I(AM) = I(AM) [3 V] + 175 µA/V × (VCC – 3 V)
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
21
MSP430F43x
MIXED SIGNAL MICROCONTROLLER
SLAS713 -- JUNE 2010
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
Schmitt-trigger inputs -- Ports P1, P2, P3, P4, P5, and P6; RST/NMI; JTAG: TCK, TMS, TDI/TCLK, TDO/TDI
PARAMETER
VIT+
Positi e going input
Positive-going
inp t threshold voltage
oltage
VIT--
Negati e going input
Negative-going
inp t threshold voltage
oltage
Vhys
Input voltage hysteresis (VIT+ -- VIT-- )
TEST CONDITIONS
MIN
TYP
MAX
VCC = 2.2 V
1.1
1.55
VCC = 3 V
1.5
1.98
VCC = 2.2 V
0.4
0.9
VCC = 3 V
0.9
1.3
VCC = 2.2 V
0.3
1.1
VCC = 3 V
0.5
1
UNIT
V
V
V
inputs Px.x, TAx, TBx
PARAMETER
t(int)
External interrupt timing
t(cap)
Timer_A, Timer_B capture
timing
f(TAext)
f(TBext)
f(TAint)
f(TBint)
TEST CONDITIONS
VCC
MIN
Port P1, P2: P1.x to P2.x, external trigger signal
for the interrupt flag, (see Note 1)
2.2 V
62
3V
50
TA0, TA1, TA2
2.2 V
62
TB0, TB1, TB2
3V
50
Timer_A, Timer_B clock
frequency externally applied
to pin
TACLK TBCLK
TACLK,
TBCLK, INCLK: t(H) = t(L)
Timer_A, Timer_B clock
frequency
SMCLK or ACLK signal selected
TYP
MAX
UNIT
ns
ns
2.2 V
8
3V
10
2.2 V
8
3V
10
MHz
MHz
NOTES: 1. The external signal sets the interrupt flag every time the minimum t(int) parameters are met. It may be set even with trigger signals
shorter than t(int).
leakage current -- Ports P1, P2, P3, P4, P5, and P6 (see Note 1)
PARAMETER
Ilkg(Px.y)
Leakage
current
TEST CONDITIONS
Port Px
V(Px.y) (see Note 2)
MIN
TYP
VCC = 2.2 V/3 V
NOTES: 1. The leakage current is measured with VSS or VCC applied to the corresponding pin(s), unless otherwise noted.
2. The port pin must be selected as input.
22
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MAX
UNIT
±50
nA
MSP430F43x
MIXED SIGNAL MICROCONTROLLER
SLAS713 -- JUNE 2010
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
outputs -- Ports P1, P2, P3, P4, P5, and P6
PARAMETER
VOH
VOL
High le el output
High-level
o tp t voltage
oltage
Low level output voltage
Low-level
TEST CONDITIONS
MIN
TYP
MAX
IOH(max) = --1.5 mA,
VCC = 2.2 V,
See Note 1
VCC --0.25
VCC
IOH(max) = --6 mA,
VCC = 2.2 V,
See Note 2
VCC --0.6
VCC
IOH(max) = --1.5 mA,
VCC = 3 V,
See Note 1
VCC --0.25
VCC
IOH(max) = --6 mA,
VCC = 3 V,
See Note 2
VCC --0.6
VCC
IOL(max) = 1.5 mA,
VCC = 2.2 V,
See Note 1
VSS
VSS+0.25
IOL(max) = 6 mA,
VCC = 2.2 V,
See Note 2
VSS
VSS+0.6
IOL(max) = 1.5 mA,
VCC = 3 V,
See Note 1
VSS
VSS+0.25
IOL(max) = 6 mA,
VCC = 3 V,
See Note 2
VSS
VSS+0.6
UNIT
V
V
NOTES: 1. The maximum total current, IOH(max) and IOL(max), for all outputs combined, should not exceed ±12 mA to satisfy the maximum
specified voltage drop.
2. The maximum total current, IOH(max) and IOL(max), for all outputs combined, should not exceed ±48 mA to satisfy the maximum
specified voltage drop.
output frequency
PARAMETER
f(Px.y)
(1 ≤ x ≤ 6, 0 ≤ y ≤ 7)
f(MCLK)
P1.1/TA0/MCLK,
f(SMCLK)
P1.4/TBCLK/SMCLK,
f(ACLK)
P1.5/TACLK/ACLK
t(Xdc)
Duty cycle of output frequency
TEST CONDITIONS
CL = 20 pF,
IL = ±1.5 mA
VCC = 2.2 V / 3 V
MIN
TYP
DC
CL = 20 pF
P1.5/TACLK/ACLK,
CL = 20 pF
VCC = 2.2 V / 3 V
f(ACLK) = f(LFXT1) = f(XT1)
40%
f(ACLK) = f(LFXT1) = f(LF)
30%
P1.1/TA0/MCLK,
CL = 20 pF,
VCC = 2.2 V / 3 V
f(MCLK) = f(XT1)
P1.4/TBCLK/SMCLK,
CL = 20 pF,
VCC = 2.2 V / 3 V
f(SMCLK) = f(XT2)
POST OFFICE BOX 655303
f(ACLK) = f(LFXT1)
f(MCLK) = f(DCOCLK)
f(SMCLK) = f(DCOCLK)
• DALLAS, TEXAS 75265
MAX
UNIT
fSystem
MHz
fSystem
MHz
60%
70%
50%
40%
60%
50%-15 ns
50%
50%+
15 ns
40%
60%
50%-15 ns
50%
50%+
15 ns
23
MSP430F43x
MIXED SIGNAL MICROCONTROLLER
SLAS713 -- JUNE 2010
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
outputs -- Ports P1, P2, P3, P4, P5, and P6 (continued)
TYPICAL LOW-LEVEL OUTPUT CURRENT
vs
LOW-LEVEL OUTPUT VOLTAGE
TYPICAL LOW-LEVEL OUTPUT CURRENT
vs
LOW-LEVEL OUTPUT VOLTAGE
25
TA = 25°C
VCC = 2.2 V
P2.7
14
12
I OL -- Typical Low-level Output Current -- mA
I OL -- Typical Low-level Output Current -- mA
16
TA = 85°C
10
8
6
4
2
0
0.0
0.5
1.0
1.5
2.0
2.5
VCC = 3 V
P2.7
TA = 25°C
20
TA = 85°C
15
10
5
0
0.0
0.5
VOL -- Low-Level Output Voltage -- V
1.0
I OL -- Typical High-level Output Current -- mA
I OL -- Typical High-level Output Current -- mA
--4
--6
--8
TA = 85°C
--12
TA = 25°C
1.0
1.5
2.0
2.5
VOH -- High-Level Output Voltage -- V
VCC = 3 V
P2.7
--5
--10
--15
--20
TA = 85°C
--25
--30
0.0
TA = 25°C
0.5
1.0
1.5
Figure 5
POST OFFICE BOX 655303
2.0
2.5
3.0
VOH -- High-Level Output Voltage -- V
Figure 4
24
3.5
0
VCC = 2.2 V
P2.7
0.5
3.0
TYPICAL HIGH-LEVEL OUTPUT CURRENT
vs
HIGH-LEVEL OUTPUT VOLTAGE
0
--14
0.0
2.5
Figure 3
TYPICAL HIGH-LEVEL OUTPUT CURRENT
vs
HIGH-LEVEL OUTPUT VOLTAGE
--10
2.0
VOL -- Low-Level Output Voltage -- V
Figure 2
--2
1.5
• DALLAS, TEXAS 75265
3.5
MSP430F43x
MIXED SIGNAL MICROCONTROLLER
SLAS713 -- JUNE 2010
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted)
wake-up LPM3
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
f = 1 MHz
td(LPM3)
f = 2 MHz
Delay time
UNIT
6
6
VCC = 2.2 V/3 V
f = 3 MHz
µs
6
RAM
PARAMETER
TEST CONDITIONS
VRAMh
MIN
CPU halted (see Note 1)
TYP
MAX
1.6
UNIT
V
NOTE 1: This parameter defines the minimum supply voltage when the data in program memory RAM remain unchanged. No program execution
should take place during this supply voltage condition.
LCD
PARAMETER
V(33)
V(23)
V(13)
TEST CONDITIONS
Analog voltage
oltage
Voltage at P5.6/R23
Voltage at P5.5/R13
V(33) -- V(03)
Voltage at R33 to R03
I(R03)
R03 = VSS
I(R13)
MIN
Voltage at P5.7/R33
Input
p leakage
g
I(R23)
P5.5/R13 = VCC/3
P5.6/R23 = 2 × VCC/3
V(Sxx2)
Segment line
voltage
I(Sxx) = --3
3 µA,
µA
2.5
V(Sxx3)
POST OFFICE BOX 655303
UNIT
V
[V(33) --V(03)] × 1/3 + V(03)
No load at all
segment and
common lines,
lines
VCC = 3 V
VCC = 3 V
MAX
VCC + 0.2
[V(33) --V(03)] × 2/3 + V(03)
VCC = 3 V
V(Sxx0)
V(Sxx1)
TYP
2.5
VCC + 0.2
±20
±20
nA
±20
V(03)
V(03) -- 0.1
V(13)
V(13) -- 0.1
V(23)
V(23) -- 0.1
V(33)
V(33) + 0.1
• DALLAS, TEXAS 75265
V
25
MSP430F43x
MIXED SIGNAL MICROCONTROLLER
SLAS713 -- JUNE 2010
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
Comparator_A (see Note 1)
PARAMETER
TEST CONDITIONS
I(CC)
CAON 1 CARSEL=0,
CAON=1,
CARSEL 0 CAREF=0
CAREF 0
I(Refladder/RefDiode)
CAON=1, CARSEL=0, CAREF=1/2/3,
No load at P1.6/CA0
P1 6/CA0 and
P1.7/CA1
V(Ref025)
V(Ref050)
Voltage @ 0.25 V
V
CC
Voltage @ 0.5 V
V
TYP
MAX
VCC = 2.2 V
25
40
VCC = 3 V
45
60
VCC = 2.2 V
30
50
VCC = 3 V
45
71
node
PCA0=1, CARSEL=1, CAREF=1,
No load at P1.6/CA0 and P1.7/CA1
VCC = 2.2 V / 3 V
0.23
0.24
0.25
node
PCA0=1, CARSEL=1, CAREF=2,
No load at P1.6/CA0 and P1.7/CA1
VCC = 2.2V / 3 V
0.47
0.48
0.5
CC
CC
MIN
CC
UNIT
µA
A
µA
A
V(RefVT)
see Figure 6 and Figure 7
PCA0=1, CARSEL=1, CAREF=3,
No load at P1.6/CA0
P1 6/CA0 and P1
P1.7/CA1;
7/CA1;
TA = 85°C
VCC = 2.2 V
390
480
540
VCC = 3 V
400
490
550
VIC
Common-mode input
voltage range
CAON=1
VCC = 2.2 V / 3 V
0
VCC --1
Vp --VS
Offset voltage
See Note 2
VCC = 2.2 V / 3 V
--30
30
mV
Vhys
Input hysteresis
CAON = 1
VCC = 2.2 V / 3 V
mV
TA = 25
25°C,
C,
Overdrive 10 mV, without filter: CAF = 0
VCC = 2.2 V
t(response LH)
t(response HL)
0
0.7
1.4
160
210
300
VCC = 3 V
80
150
240
TA = 25
25°C
C
Overdrive 10 mV, with filter: CAF = 1
VCC = 2.2 V
1.4
1.9
3.4
VCC = 3 V
0.9
1.5
2.6
TA = 25
25°C
C
Overdrive 10 mV, without filter: CAF = 0
VCC = 2.2 V
130
210
300
VCC = 3 V
80
150
240
TA = 25
25°C,
C,
Overdrive 10 mV, with filter: CAF = 1
VCC = 2.2 V
1.4
1.9
3.4
VCC = 3 V
0.9
1.5
2.6
mV
V
ns
µss
ns
µss
NOTES: 1. The leakage current for the Comparator_A terminals is identical to Ilkg(Px.x) specification.
2. The input offset voltage can be cancelled by using the CAEX bit to invert the Comparator_A inputs on successive measurements.
The two successive measurements are then summed together.
26
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• DALLAS, TEXAS 75265
MSP430F43x
MIXED SIGNAL MICROCONTROLLER
SLAS713 -- JUNE 2010
typical characteristics
REFERENCE VOLTAGE
vs
FREE-AIR TEMPERATURE
REFERENCE VOLTAGE
vs
FREE-AIR TEMPERATURE
650
650
VCC = 2.2 V
600
VREF -- Reference Voltage -- mV
VREF -- Reference Voltage -- mV
VCC = 3 V
Typical
550
500
450
400
--45
--25
--5
15
35
55
75
600
Typical
550
500
450
400
--45
95
--25
TA -- Free-Air Temperature -- °C
Figure 6. V(RefVT) vs Temperature
0V
0
--5
55
75
95
VCC
1
CAF
Low-Pass Filter
V--
35
Figure 7. V(RefVT) vs Temperature
CAON
V+
15
TA -- Free-Air Temperature -- °C
+
_
0
0
1
1
To Internal
Modules
CAOUT
Set CAIFG
Flag
τ ≈ 2 µs
Figure 8. Block Diagram of Comparator_A Module
VCAOUT
Overdrive
V-400 mV
V+
t(response)
Figure 9. Overdrive Definition
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
27
MSP430F43x
MIXED SIGNAL MICROCONTROLLER
SLAS713 -- JUNE 2010
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted)
POR/brownout reset (BOR) (see Note 1)
PARAMETER
TEST CONDITIONS
MIN
TYP
td(BOR)
VCC(start)
dVCC/dt ≤ 3 V/s (see Figure 10)
Brownout
(see Note 2)
V(B_IT--)
Vhys(B_IT--)
UNIT
2000
µs
0.7 × V(B_IT--)
dVCC/dt ≤ 3 V/s (see Figure 10 through Figure 12)
t(reset)
MAX
dVCC/dt ≤ 3 V/s (see Figure 10)
70
Pulse length needed at RST/NMI pin to accepted reset internally,
VCC = 2.2 V/3 V
2
130
V
1.71
V
180
mV
µs
NOTES: 1. The current consumption of the brownout module is already included in the ICC current consumption data. The voltage level
V(B_IT--) + Vhys(B_IT--) is ≤ 1.8V.
2. During power up, the CPU begins code execution following a period of td(BOR) after VCC = V(B_IT--) + Vhys(B_IT--). The default
FLL+ settings must not be changed until VCC ≥ VCC(min), where VCC(min) is the minimum supply voltage for the desired
operating frequency. See the MSP430x4xx Family User’s Guide (SLAU056) for more information on the brownout/SVS circuit.
typical characteristics
VCC
Vhys(B_IT--)
V(B_IT--)
VCC(start)
1
0
t d(BOR)
Figure 10. POR/Brownout Reset (BOR) vs Supply Voltage
VCC
3V
2
VCC(drop) -- V
1.5
VCC = 3 V
Typical Conditions
t pw
1
VCC(drop)
0.5
0
0.001
1
1000
1 ns
tpw -- Pulse Width -- µs
1 ns
tpw -- Pulse Width -- µs
Figure 11. VCC(drop) Level With a Square Voltage Drop to Generate a POR/Brownout Signal
28
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MSP430F43x
MIXED SIGNAL MICROCONTROLLER
SLAS713 -- JUNE 2010
typical characteristics
VCC
2
3V
VCC(drop) -- V
VCC = 3 V
1.5
t pw
Typical Conditions
1
VCC(drop)
0.5
tf = tr
0
0.001
1
1000
tf
tr
tpw -- Pulse Width -- µs
tpw -- Pulse Width -- µs
Figure 12. VCC(drop) Level With a Triangle Voltage Drop to Generate a POR/Brownout Signal
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted)
SVS (supply voltage supervisor/monitor)
PARAMETER
t(SVSR)
TEST CONDITIONS
MIN
dVCC/dt > 30 V/ms (see Figure 13)
5
dVCC/dt ≤ 30 V/ms
td(SVSon)
SVSon, switch from VLD=0 to VLD ≠ 0, VCC = 3 V
tsettle
VLD ≠ 0‡
V(SVSstart)
VLD ≠ 0, VCC/dt ≤ 3 V/s (see Figure 13)
20
1.55
VLD = 1
VCC/dt ≤ 3 V/s (see Figure 13)
VLD = 2 .. 14
Vhys(SVS_IT--)
hys(SVS IT--)
VCC/dt ≤ 3 V/s (see Figure 13), external voltage applied
on A7
VCC/dt ≤ 3 V/s (see Figure 13)
V(SVS_IT--)
(SVS IT )
VCC/dt ≤ 3 V/s (see Figure 13), external voltage applied
on A7
ICC(SVS)
(see Note 1)
NOM
VLD = 15
70
120
MAX
UNIT
150
µs
2000
µs
150
µs
12
µs
1.7
V
155
mV
V(SVS_IT--)
x 0.001
V(SVS_IT--)
x 0.016
4.4
20
VLD = 1
1.8
1.9
2.05
VLD = 2
1.94
2.1
2.23
VLD = 3
2.05
2.2
2.35
VLD = 4
2.14
2.3
2.46
VLD = 5
2.24
2.4
2.58
VLD = 6
2.33
2.5
2.69
VLD = 7
2.46
2.65
2.84
VLD = 8
2.58
2.8
2.97
VLD = 9
2.69
2.9
3.10
VLD = 10
2.83
3.05
3.26
VLD = 11
2.94
3.2
3.39
VLD = 12
3.11
3.35
3.58†
VLD = 13
3.24
3.5
3.73†
VLD = 14
3.43
3.7†
3.96†
VLD = 15
1.1
1.2
1.3
10
15
VLD ≠ 0, VCC = 2.2 V/3 V
mV
V
µA
†
The recommended operating voltage range is limited to 3.6 V.
tsettle is the settling time that the comparator o/p needs to have a stable level after VLD is switched VLD ≠ 0 to a different VLD value somewhere
between 2 and 15. The overdrive is assumed to be > 50 mV.
NOTE 1: The current consumption of the SVS module is not included in the ICC current consumption data.
‡
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
29
MSP430F43x
MIXED SIGNAL MICROCONTROLLER
SLAS713 -- JUNE 2010
typical characteristics
Software Sets VLD>0:
SVS is Active
VCC
V(SVS_IT--)
V(SVSstart)
Vhys(SVS_IT--)
Vhys(B_IT--)
V(B_IT--)
VCC(start)
BrownOut
Region
Brownout
Region
Brownout
1
0
td(BOR)
SVSOut
0
td(SVSon)
Set POR
1
t d(BOR)
SVS Circuit is Active From VLD > to VCC < V(B_IT--)
1
td(SVSR)
undefined
0
Figure 13. SVS Reset (SVSR) vs Supply Voltage
VCC
3V
t pw
2
Rectangular Drop
VCC(drop)
VCC(drop) -- V
1.5
Triangular Drop
1
1 ns
0.5
1 ns
VCC
t pw
3V
0
1
10
100
1000
tpw -- Pulse Width -- µs
VCC(drop)
tf = tr
tf
tr
t -- Pulse Width -- µs
Figure 14. VCC(drop) With a Square Voltage Drop and a Triangle Voltage Drop to Generate an SVS Signal
30
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MSP430F43x
MIXED SIGNAL MICROCONTROLLER
SLAS713 -- JUNE 2010
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted)
DCO
PARAMETER
VCC
f(DCOCLK)
N(DCO)=01Eh, FN_8=FN_4=FN_3=FN_2=0, D = 2; DCOPLUS= 0,
fCrystal = 32.738 kHz
f(DCO=2)
FN 8 FN 4 FN 3 FN 2 0 ; DCOPLUS = 1
FN_8=FN_4=FN_3=FN_2=0
f(DCO=27)
FN 8 FN 4 FN 3 FN 2 0 DCOPLUS = 1
FN_8=FN_4=FN_3=FN_2=0;
f(DCO=2)
FN 8 FN 4 FN 3 0 FN_2=1;
FN_8=FN_4=FN_3=0,
FN 2 1 DCOPLUS = 1
f(DCO=27)
FN 8 FN 4 FN 3 0 FN_2=1;
FN_8=FN_4=FN_3=0,
FN 2 1 DCOPLUS = 1
f(DCO=2)
FN 8 FN 4 0 FN_3=
FN_8=FN_4=0,
FN 3 1,
1 FN_2=x;
FN 2
DCOPLUS = 1
f(DCO=27)
FN 8 FN 4 0 FN_3=
FN_8=FN_4=0,
FN 3 1,
1 FN_2=x;
FN 2
DCOPLUS = 1
f(DCO=2)
FN 8 0 FN_4=
FN_8=0,
FN 4 1,
1 FN_3=
FN 3 FN_2=x;
FN 2
DCOPLUS = 1
f(DCO=27)
FN 8 0 FN_4=1,
FN_8=0,
FN 4 1 FN_3=
FN 3 FN_2=x;
FN 2
DCOPLUS = 1
f(DCO=2)
FN 8 1 FN_4=FN_3=FN_2=x;
FN_8=1,
FN 4 FN 3 FN 2
DCOPLUS = 1
f(DCO=27)
FN 8 1 FN 4 FN 3 FN 2
FN_8=1,FN_4=FN_3=FN_2=x;
DCOPLUS = 1
Sn
Step size between adjacent DCO taps:
Sn = fDCO(Tap n+1) / fDCO(Tap n) (see Figure 16 for taps 21 to 27)
Dt
Temperature drift, N(DCO) = 01Eh, FN_8=FN_4=FN_3=FN_2=0,
D = 2; DCOPLUS = 0
DV
Drift with VCC variation, N(DCO) = 01Eh, FN_8=FN_4=FN_3=FN_2=0,
D = 2; DCOPLUS = 0
f
f
TEST CONDITIONS
f
(DCO)
f
(DCO3V)
MIN
2.2 V/3 V
TYP
MAX
1
UNIT
MHz
2.2 V
0.3
0.65
1.25
3V
0.3
0.7
1.3
2.2 V
2.5
5.6
10.5
3V
2.7
6.1
11.3
2.2 V
0.7
1.3
2.3
3V
0.8
1.5
2.5
2.2 V
5.7
10.8
18
3V
6.5
12.1
20
2.2 V
1.2
2
3
3V
1.3
2.2
3.5
2.2 V
9
15.5
25
3V
10.3
17.9
28.5
2.2 V
1.8
2.8
4.2
3V
2.1
3.4
5.2
2.2 V
13.5
21.5
33
3V
16
26.6
41
2.2 V
2.8
4.2
6.2
3V
4.2
6.3
9.2
2.2 V
21
32
46
3V
30
46
70
1 < TAP ≤ 20
1.06
1.11
TAP = 27
1.07
1.17
2.2 V
–0.2
–0.3
–0.4
3V
–0.2
–0.3
–0.4
2.2 V/ 3 V
0
5
15
MH
MHz
MH
MHz
MH
MHz
MH
MHz
MH
MHz
MH
MHz
MH
MHz
MH
MHz
MH
MHz
MH
MHz
%/_C
%/V
(DCO)
(DCO20°C)
1.0
1.0
0
1.8
2.4
3.0
3.6
VCC -- V
--40
--20
0
20
40
60
85
TA -- °C
Figure 15. DCO Frequency vs Supply Voltage VCC and vs Ambient Temperature
POST OFFICE BOX 655303
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31
MSP430F43x
MIXED SIGNAL MICROCONTROLLER
SLAS713 -- JUNE 2010
Sn - Stepsize Ratio between DCO Taps
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
1.17
Max
1.11
1.07
1.06
Min
1
20
27
DCO Tap
Figure 16. DCO Tap Step Size
f(DCO)
Legend
Tolerance at Tap 27
DCO Frequency
Adjusted by Bits
29 to 25 in SCFI1 {N{DCO}}
Tolerance at Tap 2
Overlapping DCO Ranges:
Uninterrupted Frequency Range
FN_2=0
FN_3=0
FN_4=0
FN_8=0
FN_2=1
FN_3=0
FN_4=0
FN_8=0
FN_2=x
FN_3=1
FN_4=0
FN_8=0
FN_2=x
FN_3=x
FN_4=1
FN_8=0
FN_2=x
FN_3=x
FN_4=x
FN_8=1
Figure 17. Five Overlapping DCO Ranges Controlled by FN_x Bits
32
POST OFFICE BOX 655303
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MSP430F43x
MIXED SIGNAL MICROCONTROLLER
SLAS713 -- JUNE 2010
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted)
crystal oscillator, LFXT1 oscillator (see Notes 1 and 2)
PARAMETER
CXIN
CXOUT
Integrated input capacitance
(see Note 4)
Integrated output capacitance
(see Note 4)
TEST CONDITIONS
MIN
TYP
OSCCAPx = 0h, VCC = 2.2 V / 3 V
0
OSCCAPx = 1h, VCC = 2.2 V / 3 V
10
OSCCAPx = 2h, VCC = 2.2 V / 3 V
14
OSCCAPx = 3h, VCC = 2.2 V / 3 V
18
OSCCAPx = 0h, VCC = 2.2 V / 3 V
0
OSCCAPx = 1h, VCC = 2.2 V / 3 V
10
OSCCAPx = 2h, VCC = 2.2 V / 3 V
14
OSCCAPx = 3h, VCC = 2.2 V / 3 V
VIL
VIH
Input levels at XIN
VCC = 2
2.2
2 V/3 V (see Note 3)
MAX
UNIT
pF
pF
18
VSS
0.2×VCC
0.8×VCC
VCC
V
NOTES: 1. The parasitic capacitance from the package and board may be estimated to be 2 pF. The effective load capacitor for the crystal is
(CXIN x CXOUT) / (CXIN + CXOUT). This is independent of XTS_FLL.
2. To improve EMI on the low-power LFXT1 oscillator, particularly in the LF mode (32 kHz), the following guidelines should be observed.
-- Keep the trace between the MSP430 device and the crystal as short as possible.
-- Design a good ground plane around the oscillator pins.
-- Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT.
-----
Avoid running PCB traces underneath or adjacent to the XIN and XOUT pins.
Use assembly materials and praxis to avoid any parasitic load on the oscillator XIN and XOUT pins.
If conformal coating is used, ensure that it does not induce capacitive/resistive leakage between the oscillator pins.
Do not route the XOUT line to the JTAG header to support the serial programming adapter as shown in other
documentation. This signal is no longer required for the serial programming adapter.
3. Applies only when using an external logic-level clock source. XTS_FLL must be set. Not applicable when using a crystal or resonator.
4. External capacitance is recommended for precision real-time clock applications; OSCCAPx = 0h.
crystal oscillator, XT2 oscillator (see Note 1)
PARAMETER
TEST CONDITIONS
CXT2IN
Integrated input capacitance
VCC = 2.2 V/3 V
CXT2OUT
Integrated output capacitance
VCC = 2.2 V/3 V
VIL
VIH
Input levels at XT2IN
MIN
TYP
MAX
2
pF
2
VCC = 2
2.2
2 V/3 V (see Note 2)
UNIT
pF
VSS
0.2 × VCC
V
0.8 × VCC
VCC
V
NOTES: 1. The oscillator needs capacitors at both terminals, with values specified by the crystal manufacturer.
2. Applies only when using an external logic-level clock source. Not applicable when using a crystal or resonator.
USART0 (see Note 1)
PARAMETER
t(τ)
USART0: deglitch time
TYP
MAX
VCC = 2.2 V, SYNC = 0 , UART mode
TEST CONDITIONS
MIN
200
430
800
VCC = 3 V, SYNC = 0 , UART mode
150
280
500
UNIT
ns
NOTES: 1. The signal applied to the USART0 receive signal/terminal (URXD0) should meet the timing requirements of t(τ) to ensure that the
URXS flip-flop is set. The URXS flip-flop is set with negative pulses meeting the minimum-timing condition of t(τ). The operating
conditions to set the flag must be met independently from this timing constraint. The deglitch circuitry is active only on negative
transitions on the URXD0 line.
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33
MSP430F43x
MIXED SIGNAL MICROCONTROLLER
SLAS713 -- JUNE 2010
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
12-bit ADC, power supply and input range conditions (see Note 1)
PARAMETER
TEST CONDITIONS
MIN
AVCC
Analog supply voltage
AVCC and DVCC are connected together
AVSS and DVSS are connected together
V(AVSS) = V(DVSS) = 0 V
V(P6.x/Ax)
Analog input voltage
range (see Note 2)
All external Ax terminals. Analog inputs
selected in ADC12MCTLx register and P6Sel.x=1
V(AVSS) ≤ VAx ≤ V(AVCC)
IADC12
Operating supply current
into AVCC terminal
(see Note 3)
fADC12CLK = 5.0 MHz
ADC12ON = 1,
1 REFON = 0
SHT0=0, SHT1=0, ADC12DIV=0
Operating supply current
i t AVCC terminal
into
t
i l
(see Note 4)
IREF+
CI
RI
NOTES: 1.
2.
3.
4.
fADC12CLK = 5.0 MHz
ADC12ON = 0
0,
REFON = 1, REF2_5V = 0
MAX
3.6
V
0
VAVCC
V
0.65
1.3
VCC = 3 V
0.8
1.6
VCC = 3 V
0.5
0.8
VCC = 2.2 V
0.5
0.8
VCC = 3 V
0.5
0.8
Input capacitance
Only one terminal can be selected
at one time, Ax
VCC = 2.2 V
Input MUX ON resistance
0V ≤ VAx ≤ VAVCC
VCC = 3 V
UNIT
2.2
VCC = 2.2 V
fADC12CLK = 5.0 MHz
ADC12ON = 0,
REFON = 1, REF2_5V = 1
TYP
mA
mA
mA
40
pF
2000
Ω
The leakage current is defined in the leakage current table with Ax parameter.
The analog input voltage range must be within the selected reference voltage range VR+ to VR-- for valid conversion results.
The internal reference supply current is not included in current consumption parameter IADC12.
The internal reference current is supplied via terminal AVCC. Consumption is independent of the ADC12ON control bit, unless a
conversion is active. The REFON bit enables to settle the built-in reference before starting an A/D conversion.
12-bit ADC, external reference (see Note 1)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VeREF+
Positive external
reference voltage input
VeREF+ > VREF-- /VeREF-(see Note 2)
1.4
VAVCC
V
VREF-- /VeREF--
Negative external
reference voltage input
VeREF+ > VREF-- /VeREF-(see Note 3)
0
1.2
V
(VeREF+ -VREF--/VeREF-- )
Differential external
reference voltage input
VeREF+ > VREF-- /VeREF-(see Note 4)
1.4
VAVCC
V
IVeREF+
Static input current
0V ≤VeREF+ ≤ VAVCC
±1
µA
IVREF--/VeREF--
Static input current
NOTES: 1.
2.
3.
4.
34
VCC = 2.2 V/3 V
0V ≤ VeREF-- ≤ VAVCC
VCC = 2.2 V/3 V
±1
µA
The external reference is used during conversion to charge and discharge the capacitance array. The input capacitance, CI, is also
the dynamic load for an external reference during conversion. The dynamic impedance of the reference supply should follow the
recommendations on analog-source impedance to allow the charge to settle for 12-bit accuracy.
The accuracy limits the minimum positive external reference voltage. Lower reference voltage levels may be applied with reduced
accuracy requirements.
The accuracy limits the maximum negative external reference voltage. Higher reference voltage levels may be applied with reduced
accuracy requirements.
The accuracy limits minimum external differential reference voltage. Lower differential reference voltage levels may be applied with
reduced accuracy requirements.
POST OFFICE BOX 655303
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MSP430F43x
MIXED SIGNAL MICROCONTROLLER
SLAS713 -- JUNE 2010
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
12-bit ADC, built-in reference
PARAMETER
Positive built
built-in
in reference
voltage output
VREF+
AVCC minimum voltage,
Positive built-in
built in reference
active
AVCC(min)
TEST CONDITIONS
REF2_5V = 1 for 2.5 V
IVREF+max ≤ IVREF+≤ IVREF+min
VCC = 3 V
REF2_5V = 0 for 1.5 V
IVREF+max ≤ IVREF+≤ IVREF+min
VCC = 2.2 V/3 V
Load current regulation
Load-current
VREF+ terminal
IL(VREF)+
MAX
2.5
2.6
1.44
1.5
1.56
UNIT
V
REF2_5V = 0, IVREF+max ≤ IVREF+≤ IVREF+min
2.2
2.8
REF2_5V = 1, IVREF+min ≥ IVREF+≥ --1mA
2.9
IVREF+ = 500 µA +/-- 100 µA
Analog input voltage ~0.75
0 75 V;
REF2_5V = 0
TYP
2.4
REF2_5V = 1, IVREF+min ≥ IVREF+≥ --0.5mA
Load current out of VREF+
terminal
IVREF+
MIN
V
VCC = 2.2 V
0.01
--0.5
VCC = 3 V
0.01
--1
mA
VCC = 2.2 V
±2
VCC = 3 V
±2
IVREF+ = 500 µA ± 100 µA
Analog input voltage ~1.25 V;
REF2_5V = 1
VCC = 3 V
±2
LSB
20
ns
IDL(VREF) +
Load current regulation
VREF+ terminal
IVREF+ =100 µA → 900 µA,
CVREF+=5
5 µF,
F ax ~0.5
0 5 x VREF+
Error of conversion result ≤ 1 LSB
VCC = 3 V
CVREF+
Capacitance at pin VREF+
(see Note 1)
REFON =1,
0 mA ≤ IVREF+ ≤ IVREF+max
VCC = 2.2 V/3 V
TREF+
Temperature coefficient of
built-in reference
IVREF+ is a constant in the range of
0 mA ≤ IVREF+ ≤ 1 mA
VCC = 2.2 V/3 V
tREFON
Settle time of internal
reference voltage (see
Figure 18 and Note 2)
IVREF+ = 0.5 mA, CVREF+ = 10 µF,
VREF+ = 1.5 V, VAVCC = 2.2 V
5
10
LSB
µF
±100
17
ppm/°C
ms
NOTES: 1. The internal buffer operational amplifier and the accuracy specifications require an external capacitor. All INL and DNL tests uses
two capacitors between pins VREF+ and AVSS and VREF-- /VeREF-- and AVSS: 10 µF tantalum and 100 nF ceramic.
2. The condition is that the error in a conversion started after tREFON is less than ±0.5 LSB. The settling time depends on the external
capacitive load.
CVREF+
100 µF
tREFON ≈ .66 x CVREF+ [ms] with CVREF+ in µF
10 µF
1 µF
0
1 ms
10 ms
100 ms
tREFON
Figure 18. Typical Settling Time of Internal Reference tREFON vs External Capacitor on VREF+
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35
MSP430F43x
MIXED SIGNAL MICROCONTROLLER
SLAS713 -- JUNE 2010
From
Power
Supply
DVCC1/2
+
-10 µ F
100 nF
AVCC
+
-10 µ F
Apply External Reference [VeREF+]
or Use Internal Reference [VREF+]
100 nF
10 µ F
100 nF
VREF --/VeREF--
+
-10 µ F
MSP430F43x
AVSS
VREF+ or VeREF+
+
--
Apply
External
Reference
DVSS1/2
100 nF
Figure 19. Supply Voltage and Reference Voltage Design VREF--/VeREF-- External Supply
From
Power
Supply
DVCC1/2
+
-10 µ F
100 nF
AVCC
+
-10 µ F
Apply External Reference [VeREF+]
or Use Internal Reference [VREF+]
100 nF
MSP430F43x
AVSS
VREF+ or VeREF+
+
-10 µ F
DVSS1/2
100 nF
Reference Is Internally
Switched to AVSS
VREF-- /VeREF--
Figure 20. Supply Voltage and Reference Voltage Design VREF--/VeREF-- = AVSS, Internally Connected
36
POST OFFICE BOX 655303
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MSP430F43x
MIXED SIGNAL MICROCONTROLLER
SLAS713 -- JUNE 2010
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
12-bit ADC, timing parameters
PARAMETER
TEST CONDITIONS
fADC12CLK
fADC12OSC
tCONVERT
Internal ADC12
oscillator
Conversion time
MIN
TYP
MAX
UNIT
For specified performance of
ADC12 linearity parameters
VCC =
2.2V/3 V
0.45
5
6.3
MHz
ADC12DIV=0,
fADC12CLK=fADC12OSC
VCC =
2.2 V/ 3 V
3.7
5
6.3
MHz
CVREF+ ≥ 5 µF, Internal oscillator,
fADC12OSC = 3.7 MHz to 6.3 MHz
VCC =
2.2 V/ 3 V
2.06
3.51
µs
External fADC12CLK from ACLK, MCLK or SMCLK:
ADC12SSEL ≠ 0
tADC12ON
Turn on settling time of
the ADC
(see Note 1)
tSample
Sampling time
RS = 400 Ω, RI = 1000 Ω,
CI = 30 pF, τ = [RS + RI] x CI
(see Note 2)
13×ADC12DIV×
1/fADC12CLK
µs
100
VCC = 3 V
1220
VCC =
2.2 V
1400
ns
ns
NOTES: 1. The condition is that the error in a conversion started after tADC12ON is less than ±0.5 LSB. The reference and input signal are already
settled.
2. Approximately ten Tau (τ) are needed to get an error of less than ±0.5 LSB:
tSample = ln(2n+1) x (RS + RI) x CI+ 800 ns where n = ADC resolution = 12, RS = external source resistance.
12-bit ADC, linearity parameters
PARAMETER
TEST CONDITIONS
1.4 V ≤ (VeREF+ -- VREF-- /VeREF-- ) min ≤ 1.6 V
MIN
EI
Integral linearity error
ED
Differential linearity
error
EO
Offset error
(VeREF+ -- VREF-- /VeREF-- )min ≤ (VeREF+ -- VREF-- /VeREF-- ),
Internal impedance of source RS < 100 Ω,
CVREF+ = 10 µF (tantalum) and 100 nF (ceramic)
VCC =
2.2 V/3 V
EG
Gain error
(VeREF+ -- VREF-- /VeREF-- )min ≤ (VeREF+ -- VREF-- /VeREF-- ),
CVREF+ = 10 µF (tantalum) and 100 nF (ceramic)
ET
Total unadjusted
error
(VeREF+ -- VREF-- /VeREF-- )min ≤ (VeREF+ -- VREF-- /VeREF-- ),
CVREF+ = 10 µF (tantalum) and 100 nF (ceramic)
1.6 V < (VeREF+ -- VREF-- /VeREF-- ) min ≤ [VAVCC]
(VeREF+ -- VREF-- /VeREF-- )min ≤ (VeREF+ -- VREF-- /VeREF-- ),
CVREF+ = 10 µF (tantalum) and 100 nF (ceramic)
POST OFFICE BOX 655303
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TYP
MAX
±2
VCC =
2.2 V/3 V
±1.7
VCC =
2.2 V/3 V
UNIT
LSB
±1
LSB
±2
±4
LSB
VCC =
2.2 V/3 V
±1.1
±2
LSB
VCC =
2.2 V/3 V
±2
±5
LSB
37
MSP430F43x
MIXED SIGNAL MICROCONTROLLER
SLAS713 -- JUNE 2010
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
12-bit ADC, temperature sensor and built-in VMID
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
ISENSOR
Operating supply current into
AVCC terminal (see Note 1)
REFON = 0, INCH = 0Ah,
ADC12ON=NA, TA = 25_C
2.2 V
40
120
3V
60
160
VSENSOR
(see Note 2)
ADC12ON = 1, INCH = 0Ah,
TA = 0°C
2.2 V/
3V
986
ADC12ON = 1
1, INCH = 0Ah
2.2 V/
3V
3 55 3%
3.55±3%
TCSENSOR
mV/°C
Sample time required if
channel 10 is selected
(see Note 3)
ADC12ON = 1, INCH = 0Ah,
Error of conversion result ≤ 1 LSB
IVMID
Current into divider at
channel 11 (see Note 4)
ADC12ON = 1
1, INCH = 0Bh
0Bh,
VMID
AVCC divider
di ider at channel 11
ADC12ON = 1, INCH = 0Bh,
VMID is ~0.5 x VAVCC
2.2 V
1.1
1.1±0.04
3V
1.5
1.50±0.04
tVMID(sample)
Sample time required if
channel 11 is selected
(see Note 5)
ADC12ON = 1, INCH = 0Bh,
Error of conversion result ≤ 1 LSB
2.2 V
1400
3V
1220
30
3V
30
µA
A
mV
tSENSOR(sample)
2.2 V
UNIT
µss
2.2 V
NA
3V
NA
µA
A
V
ns
NOTES: 1. The sensor current ISENSOR is consumed if (ADC12ON = 1 and REFON=1), or (ADC12ON=1 AND INCH=0Ah and sample signal
is high). When REFON = 1, ISENSOR is already included in IREF+.
2. The temperature sensor offset can be as much as ±20_C. A single-point calibration is recommended in order to minimize the offset
error of the built-in temperature sensor.
3. The typical equivalent impedance of the sensor is 51 kΩ. The sample time required includes the sensor-on time tSENSOR(on)
4. No additional current is needed. The VMID is used during sampling.
5. The on-time tVMID(on) is included in the sampling time tVMID(sample); no additional on time is needed.
38
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MSP430F43x
MIXED SIGNAL MICROCONTROLLER
SLAS713 -- JUNE 2010
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted)
flash memory
TEST
CONDITIONS
PARAMETER
VCC(PGM/
VCC
MIN
TYP
MAX
UNIT
Program and Erase supply voltage
2.7
3.6
V
fFTG
Flash Timing Generator frequency
257
476
kHz
IPGM
Supply current from DVCC during program
2.7 V/ 3.6 V
3
5
mA
IERASE
Supply current from DVCC during erase
2.7 V/ 3.6 V
3
7
mA
tCPT
Cumulative program time
see Note 1
2.7 V/ 3.6 V
10
ms
tCMErase
Cumulative mass erase time
see Note 2
2.7 V/ 3.6 V
ERASE)
200
104
Program/Erase endurance
TJ = 25°C
ms
105
tRetention
Data retention duration
tWord
Word or byte program time
35
tBlock, 0
Block program time for 1st byte or word
30
tBlock, 1-63
Block program time for each additional byte or word
tBlock, End
Block program end-sequence wait time
tMass Erase
Mass erase time
5297
tSeg Erase
Segment erase time
4819
cycles
100
years
21
see Note 3
tFTG
6
NOTES: 1. The cumulative program time must not be exceeded when writing to a 64-byte flash block. This parameter applies to all programming
methods: individual word/byte write and block write modes.
2. The mass erase duration generated by the flash timing generator is at least 11.1ms ( = 5297x1/fFTG,max = 5297x1/476kHz). To
achieve the required cumulative mass erase time the Flash Controller’s mass erase operation can be repeated until this time is met.
(A worst case minimum of 19 cycles are required).
3. These values are hardwired into the Flash Controller’s state machine (tFTG = 1/fFTG).
JTAG interface
TEST
CONDITIONS
PARAMETER
fTCK
TCK input frequency
see Note 1
RInternal
Internal pull-up resistance on TMS, TCK, TDI/TCLK
see Note 2
VCC
MIN
2.2 V
0
TYP
MAX
UNIT
5
MHz
3V
0
10
MHz
2.2 V/ 3 V
25
60
90
kΩ
MIN
TYP
MAX
NOTES: 1. fTCK may be restricted to meet the timing requirements of the module selected.
2. TMS, TDI/TCLK, and TCK pull-up resistors are implemented in all versions.
JTAG fuse (see Note 1)
TEST
CONDITIONS
PARAMETER
VCC(FB)
Supply voltage during fuse-blow condition
VFB
Voltage level on TDI/TCLK for fuse-blow: F versions
IFB
Supply current into TDI/TCLK during fuse blow
tFB
Time to blow fuse
TA = 25°C
VCC
2.5
6
UNIT
V
7
V
100
mA
1
ms
NOTES: 1. Once the fuse is blown, no further access to the MSP430 JTAG/Test and emulation features is possible. The JTAG block is switched
to bypass mode.
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39
MSP430F43x
MIXED SIGNAL MICROCONTROLLER
SLAS713 -- JUNE 2010
APPLICATION INFORMATION
input/output schematic
port P1, P1.0 to P1.5, input/output with Schmitt trigger
Pad Logic
DVSS
DVSS
CAPD.x
P1SEL.x
0: Input
1: Output
0
P1DIR.x
Direction Control
From Module
1
0
1
P1OUT.x
Module X OUT
Bus
Keeper
P1.0/TA0
P1.1/TA0/MCLK
P1.2/TA1
P1.3/TBOUTH/SVSOUT
P1.4/TBCLK/SMCLK
P1.5/TACLK/ACLK
P1IN.x
EN
Module X IN
D
P1IE.x
P1IRQ.x
P1IFG.x
Q
EN
Interrupt
Edge
Select
Set
P1IES.x
P1SEL.x
Note: 0 ≤ x ≤ 5
Note: Port function is active if CAPD.x = 0
PnSEL.x
PnDIR.x
Dir. Control
from module
PnOUT.x
Module X
OUT
P1SEL.0
P1DIR.0
P1DIR.0
P1OUT0
Out0 sig.
P1SEL.1
P1DIR.1
P1SEL.2
P1SEL.3
P1SEL.4
P1SEL.5
†
‡
40
P1DIR.2
P1DIR.3
P1DIR.4
P1DIR.5
P1DIR.1
P1DIR.2
P1DIR.3
P1DIR.4
P1DIR5
P1OUT.1
P1OUT.2
P1OUT.3
P1OUT.4
P1OUT.5
†
MCLK
PnIN.x
Module X IN
P1IN.0
CCI0A
P1IN.1
†
Out1 sig.
SVSOUT
SMCLK
ACLK
P1IN.2
P1IN.3
P1IN.4
P1IN.5
†
†
CCI0B
†
CCI1A
‡
TBOUTH
TBCLK
TACLK
‡
†
Timer_A
Timer_B
POST OFFICE BOX 655303
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PnIE.x
PnIFG.x
PnIES.x
P1IE.0
P1IFG.0
P1IES.0
P1IE.1
P1IFG.1
P1IES.1
P1IE.2
P1IFG.2
P1IES.2
P1IE.3
P1IFG.3
P1IES.3
P1IE.4
P1IFG.4
P1IES.4
P1IE.5
P1IFG.5
P1IES.5
MSP430F43x
MIXED SIGNAL MICROCONTROLLER
SLAS713 -- JUNE 2010
input/output schematic (continued)
port P1, P1.6, P1.7, input/output with Schmitt trigger
Pad Logic
Note: Port function is active if CAPD.6 = 0
CAPD.6
P1SEL.6
0: Input
1: Output
0
P1DIR.6
1
P1DIR.6
P1.6/
CA0
0
P1OUT.6
1
DVSS
Bus
Keeper
P1IN.6
EN
unused
D
P1IE.7
P1IRQ.07
Q
P1IFG.7
EN
Interrupt
Edge
Select
Set
P1IES.x
P1SEL.x
Comparator_A
P2CA
AVcc
CAREF
CAEX
CA0
CAF
CCI1B
+
to Timer_Ax
--
CAREF
2
CA1
Reference Block
Pad Logic
CAPD.7
Note: Port function is active if CAPD.7 = 0
P1SEL.7
0: input
1: output
0
P1DIR.7
1
P1DIR.7
0
P1OUT.7
1
DVSS
P1.7/
CA1
Bus
keeper
P1IN.7
EN
unused
P1IRQ.07
D
P1IE.7
P1IFG.7
Q
EN
Set
Interrupt
Edge
Select
P1IES.7
P1SEL.7
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
41
MSP430F43x
MIXED SIGNAL MICROCONTROLLER
SLAS713 -- JUNE 2010
input/output schematic (continued)
port P2, P2.0, P2.4 to P2.5, input/output with Schmitt trigger
Pad Logic
DVSS
DVSS
P2SEL.x
0: Input
1: Output
0
P2DIR.x
Direction Control
From Module
1
0
1
P2OUT.x
Module X OUT
Bus
Keeper
P2.0/TA2
P2.4/UTXD0
P2IN.x
P2.5/URXD0
EN
D
Module X IN
P2IE.x
P2IRQ.x
P2IFG.x
Q
EN
Interrupt
Edge
Select
Set
P2IES.x
Note:
P2SEL.x
x {0,4,5}
PnSel.x
PnDIR.x
Dir. Control
from module
PnOUT.x
P2Sel.0
P2DIR.0
P2DIR.0
P2OUT.0
P2Sel.4
P2DIR.4
DVCC
P2OUT.4
P2Sel.5
P2DIR.5
DVSS
P2OUT.5
Module X
OUT
PnIN.x
Module X IN
PnIE.x
PnIFG.x
P2IN.0
CCI2A †
P2IE.0
P2IFG.0
P2IES.0
UTXD0
P2IN.4
unused
P2IE.4
P2IFG.4
P2IES.4
DVSS
P2IN.5
URXD0
P2IE.5
P2IFG.5
P2IES.5
Out2 sig. †
‡
‡
†Timer_A
‡USART0
42
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
PnIES.x
MSP430F43x
MIXED SIGNAL MICROCONTROLLER
SLAS713 -- JUNE 2010
input/output schematic (continued)
port P2, P2.1 to P2.3, input/output with Schmitt trigger
Pad Logic
DVSS
DVSS
Module IN of pin
P1.3/TBOUTH/SVSOUT
P1DIR.3
P1SEL.3
P2SEL.x
0: Input
1: Output
0
P2DIR.x
Direction Control
From Module
P2OUT.x
1
0
1
Module X OUT
Bus
Keeper
P2.1/TB0
P2.2/TB1
P2IN.x
P2.3/TB2
EN
D
Module X IN
P2IE.x
P2IRQ.x
P2IFG.x
Q
EN
Interrupt
Edge
Select
Set
P2IES.x
Note:
P2SEL.x
1<x <3
PnSel.x
PnDIR.x
Dir. Control
from module
PnOUT.x
Module X
OUT
PnIN.x
Module X IN
PnIE.x
PnIFG.x
P2Sel.1
P2DIR.1
P2DIR.1
P2OUT.1
Out0 sig. †
P2IN.1
CCI0A †
CCI0B
P2IE.1
P2IFG.1
P2IES.1
P2Sel.2
P2DIR.2
P2DIR.2
P2OUT.2
Out1 sig. †
P2IN.2
CCI1A †
CCI1B
P2IE.2
P2IFG.2
P2IES.2
P2Sel.3
P2DIR.3
P2DIR.3
P2OUT.3
Out2 sig. †
P2IN.3
CCI2A †
CCI2B
P2IE.3
P2IFG.3
P2IES.3
PnIES.x
†Timer_B
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
43
MSP430F43x
MIXED SIGNAL MICROCONTROLLER
SLAS713 -- JUNE 2010
input/output schematic (continued)
port P2, P2.6 to P2.7, input/output with Schmitt trigger
0: Port active
1: Segment xx function active
Pad Logic
Port/LCD‡
Segment xx‡
P2SEL.x
0: Input
1: Output
0
P2DIR.x
Direction Control
From Module
1
0
P2OUT.x
1
Module X OUT
Bus
Keeper
P2.6/CAOUT/S19
P2.7/ADC12CLK/S18
P2IN.x
EN
D
Module X IN
P2IE.x
P2IRQ.x
P2IFG.x
Q
EN
Set
Interrupt
Edge
Select
P2IES.x
Note:
†
§
44
P2SEL.x
6<x <7
PnSel.x
PnDIR.x
Dir. Control
from module
PnOUT.x
Module X
OUT
PnIN.x
Module X IN
PnIE.x
PnIFG.x
PnIES.x
Port/LCD
P2Sel.6
P2DIR.6
P2DIR.6
P2OUT.6
CAOUT †
P2IN.6
unused
P2IE.6
P2IFG.6
P2IES.6
0: LCDM<40h
P2Sel.7
P2DIR.7
P2DIR.7
P2OUT.7
ADC12CLK§
P2IN.7
unused
P2IE.7
P2IFG.7
P2IES.7
0: LCDM<40h
Comparator_A
ADC12
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MSP430F43x
MIXED SIGNAL MICROCONTROLLER
SLAS713 -- JUNE 2010
input/output schematic (continued)
port P3, P3.0 to P3.3, input/output with Schmitt trigger
MSP430x43xIPN (80-Pin) Only
0: Port active
1: Segment xx function active
LCDM.5
LCDM.6
LCDM.7
Pad Logic
Segment xx
x43xIPZ and x44xIPZ have not segment
Function on Port P3: Both lines are low.
P3SEL.x
0: Input
1: Output
0
P3DIR.x
Direction Control
From Module
1
0
1
P3OUT.x
Module X OUT
Bus
Keeper
P3.0/STE0/S31
P3.1/SIMO0/S30
P3.2/SOMI0/S29
P3.3/UCLK0/S28
P3IN.x
EN
Module X IN
D
Note: 0 ≤ x ≤ 3
Direction
PnOUT.x
Control
From Module
Module X
OUT
PnIN.x
Module X IN
DVSS
P3IN.0
STE0(in)
DCM_SIMO0 P3OUT.1
SIMO0(out)
P3IN.1
SIMO0(in)
P3DIR.2
DCM_SOMI0 P3OUT.2
SOMIO(out)
P3IN.2
SOMI0(in)
P3DIR.3
DCM_UCLK0 P3OUT.3
UCLK0(out)
P3IN.3
UCLK0(in)
PnSel.x
PnDIR.x
P3Sel.0
P3DIR.0
P3Sel.1
P3DIR.1
P3Sel.2
P3Sel.3
DVSS
P3OUT.0
Direction Control for SIMO0 and UCLK0
SYNC
MM
STC
DCM_SIMO0
DCM_UCLK0
Direction Control for SOMI0
SYNC
MM
DCM_SOMI0
STC
STE
STE
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
45
MSP430F43x
MIXED SIGNAL MICROCONTROLLER
SLAS713 -- JUNE 2010
input/output schematic (continued)
port P3, P3.4 to P3.7, input/output with Schmitt trigger
0: Port active
1: Segment xx function active
Pad Logic
LCDM.7
Segment xx
P3SEL.x
0: Input
1: Output
0
P3DIR.x
Direction Control
From Module
1
0
P3OUT.x
1
Module X OUT
Bus
Keeper
P3.4/S27
P3.5/S26
P3.6/S25/DMAE0
P3.7/S24
P3IN.x
EN
Module X IN
D
Note:
46
4<x <7
PnSel.x
PnDIR.x
Dir. Control
from module
PnOUT.x
Module X
OUT
PnIN.x
Module X IN
P3SEL.4
P3DIR.4
P3DIR.4
P3OUT.4
DVSS
P3IN.4
unused
P3SEL.5
P3DIR.5
P3DIR.5
P3OUT.5
DVSS
P3IN.5
unused
P3SEL.6
P3DIR.6
P3DIR.6
P3OUT.6
DVSS
P3IN.6
DMAE0
P3SEL.7
P3DIR.7
P3DIR.7
P3OUT.7
DVSS
P3IN.7
unused
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MSP430F43x
MIXED SIGNAL MICROCONTROLLER
SLAS713 -- JUNE 2010
input/output schematic (continued)
port P4, P4.0 to P4.5, input/output with Schmitt trigger
0: Port active
1: Segment xx function active
Pad Logic
Port/LCD
Segment xx
P4SEL.x
0: Input
1: Output
0
P4DIR.x
Direction Control
From Module
1
0
1
P4OUT.x
Module X OUT
Bus
Keeper
P4.0/S9
P4.1/S8
P4.2/S7
P4.3/S6
P4.4/S5
P4.5/S4
P4IN.x
EN
Module X IN
Note:
D
0<x<5
PnSEL.x
PnDIR.x
Direction
Control
From Module
P4SEL.0
P4DIR.0
P4DIR.0
P4OUT.0
P4SEL.1
P4DIR.1
P4DIR.1
P4SEL.2
P4DIR.2
P4SEL.3
Module X
PnIN.x
Module X IN
DVSS
P4IN.0
unused
P4OUT.1
DVSS
P4IN.1
unused
P4DIR.2
P4OUT.2
DVSS
P4IN.2
unused
P4DIR.3
P4DIR.3
P4OUT.3
DVSS
P4IN.3
unused
P4SEL.4
P4DIR.4
P4DIR.4
P4OUT.4
DVSS
P4IN.4
unused
P4SEL.5
P4DIR.5
P4DIR.5
P4OUT.5
DVSS
P4IN.5
unused
DEVICE
F43xIPN 80-pin QFP
PnOUT.x
OUT
PORT BITS
PORT FUNCTION
LCD SEG. FUNCTION
P4.0 to P4.5
LCDM < 020h
LCDM ≥ 020h
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
47
MSP430F43x
MIXED SIGNAL MICROCONTROLLER
SLAS713 -- JUNE 2010
input/output schematic (continued)
port P4, P4.6, input/output with Schmitt trigger
INCH=15#
a15 #
0: Segment S3 disabled
1: Segment S3 enabled
Pad Logic
1, if LCDM > 020h
Segment S3
P4SEL.6
0: input
1: output
0
P4DIR.6
Direction Control
From Module
1
0
P4OUT.6
1
Module XOUT
Bus
keeper
P4.6/S3/A15
P4IN.6
EN
D
Module X IN
#
Signal from or to ADC12
PnSEL.x
P4SEL.6
DEVICE
F43xIPN 80-pin QFP
48
PnDIR.x
P4DIR.6
Direction
PnOUT.x
Control
From Module
P4DIR.6
P4OUT.6
Module X
OUT
DVSS
PnIN.x
Module X IN
P4IN.6
unused
PORT BITS
PORT FUNCTION
LCD SEG. FUNCTION
P4.6
LCDM < 020h
LCDM ≥ 020h
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MSP430F43x
MIXED SIGNAL MICROCONTROLLER
SLAS713 -- JUNE 2010
input/output schematic (continued)
port P4, P4.7, input/output with Schmitt trigger
INCH=14#
OAADC0
a14#
0: Segment S2 disabled
1: Segment S2 enabled
Pad Logic
1, if LCDM > 020h
Segment S2
P4SEL.7
0: input
1: output
0
P4DIR.7
Direction Control
From Module
1
0
P4OUT.7
1
Module XOUT
Bus
keeper
P4.7/S2/A14
P4IN.7
EN
D
Module X IN
#
Signal from or to ADC12
PnSel.x
PnDIR.x
P4Sel.7
P4DIR.7
DEVICE
F43xIPN 80-pin QFP
Direction
PnOUT.x
Control
From Module
P4DIR.7
P4OUT.7
Module X
OUT
DVSS
PnIN.x
Module X IN
P4IN.7
Unused
PORT BITS
PORT FUNCTION
LCD SEG. FUNCTION
P4.7
LCDM < 020h
LCDM ≥ 020h
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
49
MSP430F43x
MIXED SIGNAL MICROCONTROLLER
SLAS713 -- JUNE 2010
input/output schematic (continued)
port P5, P5.0, input/output with Schmitt trigger
OAADC0
INCH=13#
a13 #
0: Segment S1 disabled
1: Segment S1 enabled
Pad Logic
1, if LCDM > 020h
Segment S1
P5SEL.0
0: input
1: output
0
P5DIR.0
Direction Control
From Module
1
0
P5OUT.0
1
Module XOUT
Bus
keeper
P5.0/S1/A13
P5IN.0
EN
D
Module X IN
#
Signal from or to ADC12
PnSEL.x
P5SEL.0
DEVICE
F43xIPN 80-pin QFP
50
PnDIR.x
P5DIR.0
Direction
PnOUT.x
Control
From Module
P5DIR.0
P5OUT.0
Module X
OUT
DVSS
PnIN.x
Module X IN
P5IN.0
unused
PORT BITS
PORT FUNCTION
LCD SEG. FUNCTION
P5.0
LCDM < 020h
LCDM ≥ 020h
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MSP430F43x
MIXED SIGNAL MICROCONTROLLER
SLAS713 -- JUNE 2010
input/output schematic (continued)
port P5, P5.1, input/output with Schmitt trigger
#
INCH=12
a12#
0: Segment S0 disabled
1: Segment S0 enabled
1, if LCDM > 020h
Pad Logic
Segment S0
P5SEL.1
0: input
1: output
0
P5DIR.1
Direction Control
From Module
1
0
P5OUT.1
1
Module XOUT
Bus
keeper
P5.1/S0/A12
P5IN.1
EN
D
Module X IN
#
Signal from or to ADC12
Function
Description
P5SEL.1
LCDM
ADC12
Channel 12, A12
1
X
LCD
Segment S0, initial state
0
≥ 20h
Port
P5.1
0
< 20h
PnSEL.x
PnDIR.x
Dir. Control
from Module
PnOUT.x
Module X
OUT
PnIN.x
Module X
IN
Segment
Port/LCD
P5SEL.1
P5DIR.1
P5DIR.1
P5OUT.1
DVSS
P5IN.1
Unused
S0
0: LCDM<20h
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
51
MSP430F43x
MIXED SIGNAL MICROCONTROLLER
SLAS713 -- JUNE 2010
input/output schematic (continued)
port P5, P5.2 to P5.4, input/output with Schmitt trigger
0: Port active
1: LCD function active
Port/LCD
LCD signal
P5SEL.x
Pad Logic
0: Input
1: Output
0
P5DIR.x
Direction Control
From Module
1
0
1
P5OUT.x
Module X OUT
Bus
Keeper
P5.2/COM1
P5.3/COM2
P5.4/COM3
P5IN.x
EN
Module X IN
D
Note:
52
2<x <4
Dir. Control
PnOUT.x
from module
Module X
OUT
PnIN.x
Module X IN
LCD signal
Port/LCD
P5OUT.2
DVSS
P5IN.2
Unused
COM1
P5SEL.2
P5DIR.3
P5OUT.3
DVSS
P5IN.3
Unused
COM2
P5SEL.3
P5DIR.4
P5OUT.4
DVSS
P5IN.4
Unused
COM3
P5SEL.4
PnSel.x
PnDIR.x
P5Sel.2
P5DIR.2
P5DIR.2
P5Sel.3
P5DIR.3
P5Sel.4
P5DIR.4
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MSP430F43x
MIXED SIGNAL MICROCONTROLLER
SLAS713 -- JUNE 2010
input/output schematic (continued)
port P5, P5.5 to P5.7, input/output with Schmitt trigger
0: Port active
1: LCD function active
Port/LCD
LCD signal
P5SEL.x
Pad Logic
0: Input
1: Output
0
P5DIR.x
Direction Control
From Module
1
0
1
P5OUT.x
Module X OUT
Bus
Keeper
P5.5/R13
P5.6/R23
P5.7/R33
P5IN.x
EN
Module X IN
D
Note:
5<x <7
Module X
OUT
PnIN.x
Module X IN
LCD signal
Port/LCD
P5OUT.5
DVSS
P5IN.5
Unused
R13
P5SEL.5
P5DIR.6
P5OUT.6
DVSS
P5IN.6
Unused
R23
P5SEL.6
P5DIR.7
P5OUT.7
DVSS
P5IN.7
Unused
R33
P5SEL.7
Dir. Control
PnOUT.x
from module
PnSel.x
PnDIR.x
P5Sel.5
P5DIR.5
P5DIR.5
P5Sel.6
P5DIR.6
P5Sel.7
P5DIR.7
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
53
MSP430F43x
MIXED SIGNAL MICROCONTROLLER
SLAS713 -- JUNE 2010
input/output schematic (continued)
port P6, P6.0, P6.2, and P6.4, input/output with Schmitt trigger
INCH=x
ax
†, #
†, #
P6SEL.x
†
†
P6DIR.x
Direction Control
From Module
†
P6OUT.x
0
1
0
1
Module XOUT
P6IN.x
Pad Logic
0: input
1: output
Bus
keeper
P6.0/A0
P6.2/A2
P6.4/A4
†
EN
†
Module X IN
D
† x = {0, 2, 4}
#
Signal from or to ADC12
PnSel.x
PnDIR.x
Dir. Control
From Module
PnOUT.x
Module X OUT
PnIN.x
Module X IN
P6Sel.0
P6DIR.0
P6DIR.0
P6OUT.0
DVSS
P6IN.0
unused
P6Sel.2
P6DIR.2
P6DIR.2
P6OUT.2
DVSS
P6IN.2
unused
P6Sel.4
P6DIR.4
P6DIR.4
P6OUT.4
DVSS
P6IN.4
unused
NOTE: The signal at pins P6.x/Ax is used by the 12-bit ADC module.
54
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MSP430F43x
MIXED SIGNAL MICROCONTROLLER
SLAS713 -- JUNE 2010
input/output schematic (continued)
port P6, P6.1, input/output with Schmitt trigger
INCH=1#
a1 #
P6SEL.1
0
P6DIR.1
Direction Control
From Module
P6OUT.1
1
Pad Logic
0: input
1: output
0
1
Module XOUT
Bus
keeper
P6.1/A1
P6IN.1
EN
Module X IN
#
D
Signal from or to ADC12
PnSel.x
PnDIR.x
Dir. Control
From Module
PnOUT.x
Module X OUT
PnIN.x
Module X IN
P6Sel.1
P6DIR.1
P6DIR.1
P6OUT.1
DVSS
P6IN.1
unused
NOTE: The signal at pins P6.x/Ax is used by the 12-bit ADC module.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
55
MSP430F43x
MIXED SIGNAL MICROCONTROLLER
SLAS713 -- JUNE 2010
input/output schematic (continued)
port P6, P6.3, input/output with Schmitt trigger
INCH=3#
a3 #
P6SEL.3
0
P6DIR.3
Direction Control
From Module
P6OUT.3
1
Pad Logic
0: input
1: output
0
1
Module XOUT
Bus
keeper
P6.3/A3
P6IN.3
EN
Module X IN
#
D
Signal from or to ADC12
PnSel.x
PnDIR.x
Dir. Control
From Module
PnOUT.x
Module X OUT
PnIN.x
Module X IN
P6Sel.3
P6DIR.3
P6DIR.3
P6OUT.3
DVSS
P6IN.3
unused
NOTE: The signal at pins P6.x/Ax is used by the 12-bit ADC module.
56
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MSP430F43x
MIXED SIGNAL MICROCONTROLLER
SLAS713 -- JUNE 2010
input/output schematic (continued)
port P6, P6.5, input/output with Schmitt trigger
INCH=5#
a5 #
P6SEL.5
0
P6DIR.5
Direction Control
From Module
P6OUT.5
1
Pad Logic
0: input
1: output
0
1
Module XOUT
Bus
keeper
P6.5/A5
P6IN.5
EN
Module X IN
#
D
Signal from or to ADC12
PnSel.x
PnDIR.x
Dir. Control
From Module
PnOUT.x
Module X OUT
PnIN.x
Module X IN
P6Sel.5
P6DIR.5
P6DIR.5
P6OUT.5
DVSS
P6IN.5
unused
NOTE: The signal at pins P6.x/Ax is used by the 12-bit ADC module.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
57
MSP430F43x
MIXED SIGNAL MICROCONTROLLER
SLAS713 -- JUNE 2010
input/output schematic (continued)
port P6, P6.6, input/output with Schmitt trigger
INCH=6#
0: Port active, T--Switch off
1: T--Switch is on, Port disabled
a6 #
P6SEL.6
0: input
1: output
0
P6DIR.6
Pad Logic
1
P6DIR.6
0
P6OUT.6
1
DVSS
Bus
keeper
P6.6/A6
P6IN.6
EN
D
#
Signal from or to ADC12
PnSel.x
PnDIR.x
Dir. Control
From Module
PnOUT.x
Module X OUT
PnIN.x
Module X IN
P6Sel.6
P6DIR.6
P6DIR.6
P6OUT.6
DVSS
P6IN.6
unused
NOTE: The signal at pins P6.x/Ax is used by the 12-bit ADC module.
58
POST OFFICE BOX 655303
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MSP430F43x
MIXED SIGNAL MICROCONTROLLER
SLAS713 -- JUNE 2010
input/output schematic (continued)
port P6, P6.7, input/output with Schmitt trigger
To SVS Mux (15) $
0: Port active, T--Switch off
1: T--Switch is on, Port disabled
INCH=7#
a7 #
’1’, if VLD=15
*
P6SEL.7
P6DIR.7
0
P6DIR.7
1
0: input
1: output
Pad Logic
0
P6OUT.7
1
DVSS
Bus
keeper
P6.7/A7/SVSIN
P6IN.7
EN
D
#
Signal from or to ADC12
$
Signal to SVS block, selected if VLD=15
*
VLD control bits are located in SVS
PnSel.x
PnDIR.x
Dir. Control
From Module
PnOUT.x
Module X OUT
PnIN.x
Module X IN
P6Sel.7
P6DIR.7
P6DIR.7
P6OUT.7
DVSS
P6IN.7
unused
NOTE: The signal at pins P6.x/Ax is used by the 12-bit ADC module.
The signal at pin P6.7/A7/SVSIN is also connected to the input multiplexer in the module brownout/supply voltage supervisor.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
59
MSP430F43x
MIXED SIGNAL MICROCONTROLLER
SLAS713 -- JUNE 2010
input/output schematic (continued)
JTAG pins TMS, TCK, TDI/TCLK, TDO/TDI, input/output with Schmitt trigger or output
TDO
Controlled by JTAG
Controlled by JTAG
TDO/TDI
JTAG
Controlled
by JTAG
DVCC
TDI
Burn and Test
Fuse
TDI/TCLK
Test
and
Emulation
DVCC
TMS
Module
TMS
DVCC
TCK
TCK
RST/NMI
Tau ~ 50 ns
Brownout
TCK
60
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
G
D
U
S
G
D
U
S
MSP430F43x
MIXED SIGNAL MICROCONTROLLER
SLAS713 -- JUNE 2010
JTAG fuse check mode
MSP430 devices that have the fuse on the TDI/TCLK terminal have a fuse check mode that tests the continuity
of the fuse the first time the JTAG port is accessed after a power-on reset (POR). When activated, a fuse check
current (I(TF)) of 1 mA at 3 V can flow from the TDI/TCLK pin to ground if the fuse is not burned. Care must be
taken to avoid accidentally activating the fuse check mode and increasing overall system power consumption.
Activation of the fuse check mode occurs with the first negative edge on the TMS pin after power up or if the
TMS is being held low during power up. The second positive edge on the TMS pin deactivates the fuse check
mode. After deactivation, the fuse check mode remains inactive until another POR occurs. After each POR the
fuse check mode has the potential to be activated.
The fuse check current only flows when the fuse check mode is active and the TMS pin is in a low state (see
Figure 21). Therefore, the additional current flow can be prevented by holding the TMS pin high (default
condition). The JTAG pins are terminated internally and therefore do not require external termination.
Time TMS Goes Low After POR
TMS
I(TF)
ITDI/TCLK
Figure 21. Fuse Check Mode Current
POST OFFICE BOX 655303
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61
MSP430F43x
MIXED SIGNAL MICROCONTROLLER
SLAS713 -- JUNE 2010
Revision History
Literature
Number
SLAS713
Summary
Production Data release
NOTE: Page and figure numbers refer to the respective document revision.
62
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PACKAGE OPTION ADDENDUM
www.ti.com
6-Oct-2010
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package
Drawing
Pins
Package Qty
Eco Plan
(2)
Lead/
Ball Finish
MSL Peak Temp
(3)
Samples
(Requires Login)
MSP430F438IPN
ACTIVE
LQFP
PN
80
119
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
Purchase Samples
MSP430F438IPNR
ACTIVE
LQFP
PN
80
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
Request Free Samples
MSP430F439IPN
ACTIVE
LQFP
PN
80
119
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
Purchase Samples
MSP430F439IPNR
ACTIVE
LQFP
PN
80
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
Request Free Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Oct-2010
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
MSP430F438IPNR
LQFP
PN
80
1000
330.0
24.4
14.6
14.6
1.9
20.0
24.0
Q2
MSP430F439IPNR
LQFP
PN
80
1000
330.0
24.4
14.6
14.6
1.9
20.0
24.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Oct-2010
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
MSP430F438IPNR
LQFP
PN
80
1000
346.0
346.0
41.0
MSP430F439IPNR
LQFP
PN
80
1000
346.0
346.0
41.0
Pack Materials-Page 2
MECHANICAL DATA
MTQF010A – JANUARY 1995 – REVISED DECEMBER 1996
PN (S-PQFP-G80)
PLASTIC QUAD FLATPACK
0,27
0,17
0,50
0,08 M
41
60
61
40
80
21
0,13 NOM
1
20
Gage Plane
9,50 TYP
12,20
SQ
11,80
14,20
SQ
13,80
0,25
0,05 MIN
0°– 7°
0,75
0,45
1,45
1,35
Seating Plane
0,08
1,60 MAX
4040135 / B 11/96
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
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