CXA1746Q Electronic Volume For the availability of this product, please contact the sales office. Description The CXA1746Q is a 2-channel electronic volume IC. A 34-bit serial data input controls the level and characteristics of the output signal. It may be used in car stereos and general audio systems. Features • Loudness • Volume control (from 0 dB to –87 dB, –∞ dB: Fine (1 dB-step) Coarse (8 dB-step) • Balance • Tone control (3-band, 2 dB-step from –15 dB to +15 dB) • Fader (2 dB-step to –20 dB, –25 dB, –35 dB, –45 dB, –60 dB, –∞ dB) • Input and gain selector (4 channels) • Serial data control (DATA, CLK, CE) • Single 8 V power supply • Zero-cross detection circuit • Timer • Power-off mute 48 pin QFP (Plastic) Absolute Maximum Ratings (Ta=25°C) • Supply voltage VCC 13 V • Operating temperature Topr –40 to +85 °C • Storage temperature Tstg –65 to +150 °C • Allowable power dissipation PD 350 mW (Ta = 85 °C) Recommended Operating Condition • Supply voltage VCC 6 to 12 V Structure Bipolar IC Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. —1— E94812D7Y CXA1746Q LDLC1 LDHC1 INAO1 VRIN1 TCHC1 TCMC11 TCMC12 TCLC11 TCLC12 TCO1 FDIN1 36 35 34 33 32 31 30 29 28 27 26 25 37 44 IN23 45 IN24 46 GAIN21 47 GAIN22 48 DGND 19 GND 18 VCC 17 VCT 16 DATA 15 TIMER 14 REO 13 FNTO2 LA TCH CONTROL LA TCH ZCDET SHIFT REGISTER V CTBUFF V CTBUFF V CTBUFF V OLUME 8dB STEP V OLUME 1dB STEP TONE FA DER LOUD 1 2 3 4 5 6 7 8 9 10 11 12 FDIN2 IN22 20 TCO2 43 V CTBUFF TCLC22 IN21 CLK TCLC21 42 21 TCMC22 IN11 V CTBUFF TCMC21 41 CE TCHC2 IN12 22 V CTBUFF VRIN2 40 REO1 FA DER INAO2 IN13 23 TONE LDHC2 39 FNTO LDLC2 IN14 INPUT SWITCH 38 24 8dB STEP 1dB STEP V OLUME V OLUME INPUT SWITCH GAIN11 LOUD GAIN234 GAIN12 GAIN134 Block Diagram and Pin Configuration —2— CXA1746Q Pin Description and Equivalent Circuit Pin No. Pin Name I/O Resistance Pin voltage Equivalent Circuit Description VCC 2 LDLC2 35 LDLC1 6.18k VCT Sets loudness low cut-off frequency. 2 35 GND VCC 3 LDHC2 34 LDHC1 8.92k VCT Set loudness high cut-off frequency 3 34 GND VCC 4 INAO2 33 INAO1 — VCT 4 Input selector output 33 GND VCC 5 VRIN2 32 VRIN1 10k VCT 5 Volume input 32 GND VCC 6 TCHC2 31 TCHC1 5k VCT 6 Set tone Treble frequency 31 GND —3— CXA1746Q Pin No. Pin Name I/O Resistance Pin voltage Equivalent Circuit Description VCC 7 TCMC21 30 TCMC11 4k VCT 7 Sets tone Mid frequency 30 GND VCC 8 TCMC22 29 TCMC12 4k VCT 8 Sets tone Mid frequency 29 GND VCC 9 TCLC21 28 TCLC11 8k VCT 9 Sets tone Bass frequency 28 GND VCC 10 TCLC22 27 TCLC12 8k VCT 10 Sets tone Bass frequency 27 GND VCC 11 TCO2 26 TCO1 — VCT 11 Tone control output 26 GND —4— CXA1746Q Pin No. Pin Name I/O Resistance Pin voltage Equivalent Circuit Description VCC 12 FDIN2 25 FDIN1 24k VCT 12 Fader input 25 GND VCC 13 REO2 24 REO1 — VCT 13 Rear output 24 GND VCC 14 FNT02 23 FNT01 — VCT 14 Front output 23 GND VCC 15 TIMER ~∞ 15 Sets timer constant — GND VCC 16 DATA ~∞ — 16 Serial data input GND —5— CXA1746Q Pin No. Pin Name 17 VCT 18 VCC 19 GND 20 DGND I/O Resistance Pin voltage Equivalent Circuit Description — VCT — VCC — Gnd — — 1/2 VCC Power supply input Ground Digital ground VCC 21 CLK ~∞ 21 Serial clock input — GND VCC 22 CE ~∞ 22 Latch enable input — GND VCC 1 36 37 38 47 49 GAIN234 GAIN134 GAIN12 GAIN11 GAIN21 GAIN22 1 36 ~∞ 37 VCT 38 External gain setting for input amplifier 47 48 39 40 41 42 43 44 45 46 IN14 IN13 IN12 IN11 IN21 IN22 IN23 IN24 GND VCC 50k VCT 39 40 41 42 43 44 45 46 Signal input GND —6— CXA1746Q Data Format First Bit Last Bit D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31 D32 D33 D34 D35 D36 NOP NOP ISW LOUD VRC1 VRF1 VRC2 VRF2 TONE BASS TONE MID TONE TREBLE FADER FADER SELECT —7— CXA1746Q ISW MODE IN14/IN24, GAIN134/GAIN234 IN13/IN23, GAIN134/GAIN234 IN12/IN22, GAIN12/GAIN22 IN11/IN21, GAIN11/GAIN21 D3 D4 1 1 0 0 1 0 1 0 LOUD MODE ON OFF D5 1 0 VRC1/VRC2 OUTPUT (dB) D6/D13 D7/D14 D8/D15 D9/D16 0 –8 –16 –24 –32 –40 –48 –56 –64 –72 –80 –∞ –∞ 1 1 1 1 1 1 1 1 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 1 1 0 0 1 1 0 0 1 1 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 0 —8— CXA1746Q VRF1/VRF2 OUTPUT (dB) D10/D17 D11/D18 D12/D19 0 –1 –2 –3 –4 –5 –6 –7 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 OUTPUT (dB) D20/D24/D28 D21/D25/D29 D22/D26/D30 15 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 BASS/MID/TREBLE 12 10 8 6 4 2 0 BOOST/CUT MODE BOOST CUT D23/D27/D31 1 0 —9— CXA1746Q FADER OUTPUT (dB) D32 D33 D34 D35 –∞ –60 –45 –35 –25 –20 –18 –16 –14 –12 –10 –8 –6 –4 –2 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 FADER SELECT MODE FRONT REAR D36 1 0 RESET Reset is performed automatically when power is first supplied to the IC; there is no reset pin. The following table shows the respective statuses of various settings after a reset has been performed. However, from the time when power is first supplied until the first data transfer, keep CE high by pulling it up to VCC, etc. MODE INPUT VRC1 VRF1 VRC2 VRF2 LOUD TONE BASS TONE MID TONE TREBLE FADER SET VALUE 1 – ∞dB –7 dB – ∞dB –7 dB OFF 0 dB 0 dB 0 dB 0 dB, REAR —10— CXA1746Q Timing Chart CE DATA D1 D2 D34 D35 D36 Invalid CLK t1 t1≥0.5µs t2≥0.5µs tck≥1.0µs tsu≥0.5µs th≥0.5µs tck tsu th t2 tL tL≥tT +0.5µs (tT is the maximum value for the timer operation time) CE tce tce≥4.0µs Timer Waiting Period Setting Chart (VCC = 6 to 12V, operating temperature = –40°C to 85°C) TIMER pin capacitance C C = 100pF C = 0.001µF C = 0.01µF C = 0.1µF C = 1µF C = 10µF Waiting period Min. Typ. Max. 3µs 5µs 9µs 30µs 50µs 90µs 300µs 500µs 900µs 3ms 5ms 9ms 30ms 50ms 90ms 300ms 500ms 900ms —11— CXA1746Q Electrical Characteristics VCC=8 V, Ta=25°C, Input=0 dB unless otherwise specified Item Symbol Conditions Min. Typ. Max. Unit Current consumption Total Harmonic distortion Output noise voltage Max output voltage Separation Max. attenuation factor Loudness LOW Loudness HIGH Bass max. boost gain Bass max. cut gain Mid max. boost gain Mid max. cut gain Treble max. boost gain Treble max. cut gain Input voltage HIGH Input voltage LOW Input voltage range ICC THD Vn Vom CS ATTm Glb Glh Gbb Gbc Gmb Gmc Gtb Gtc Vsh Vsl Vin No signal 1 kHz, 5 dBm output Short-circuit at input, A weight 1 kHz 1 kHz — — — 8 72 85 7 7 13 13 13 13 13 13 3 0 1 21 0.003 8 — 90 90 8 8 15 15 15 15 15 15 — — — 23 0.01 10 — — — 9 9 17 17 17 17 17 17 6 1.5 VCC-1 mV % µVrms dBm 100 Hz, VRC=–16 dB 10 kHz, VRC=–16dB DATA, CLK, CE DATA, CLK, CE IN11 to 14 IN21 to 24 VRIN1, 2 FDIN1, 2 —12— dB V A 48 47 GAIN21 46 IN24 45 IN23 44 IN22 43 IN21 42 IN11 41 IN12 40 IN13 39 IN14 1 2 3 C5 5 4 10µ 9 8 7 6 10 C13 10µ B V4 AC C17 10µ V6 A B AC 12 REO2 TIMER DATA VCT VCC GND DGND 10k R7 B S3 A R8 10k C20 R14 1k 0.01µ R9 S4 10k FNTO2 13 14 15 16 17 18 19 20 FNTO1 R13 24 10k R12 REO1 23 10k R11 CE 22 1k R10 CLK 21 1k 25 11 26 27 28 29 30 C18 A 10µ 31 10µ C14 32 B 33 38 GAIN11 37 GAIN22 A B S24 A B S23 A B S22 A B S21 A B S11 A B S13 B S14 A B S12 AC AC V14 V13 AC V11 V12 AC AC AC V21 V22 34 GAIN234 10k C1 LDLC2 0.047µ C3 AC 35 INAO2 V23 36 VRIN2 V24 A TCMC21 C7 0.0027µ C9 AC R1 10k R3 10µ TCMC22 0.033µ C11 GAIN12 R5 C6 TCLC21 R2 10k R4 10k 10k R5 GAIN134 10k C2 0.047µ LDLC1 C4 0.0022µ LDHC1 LDHC2 INAO1 0.0022µ VRIN1 C15 TCHC2 TCHC1 C8 0.0027µ C10 0.033µ C12 TCMC11 0.022µ 0.022µ TCMC12 S2 C15 TCLC11 0.39µ TCLC12 TCLC22 0.39µ R18 1k AC -60dBm V5 R15 R15 R17 10k 10k 10k VEE 3-6V TCO1 TCO2 C19 FDIN1 FDIN2 100µ V3 V2 VCC 3-6V S1 R19 S5_A S5_B —13— V1 1k Electrical Characteristic Test Circuit DATA CLK CE 220p R20 1k C21 OPAMP 5V 0V 5V 0V 5V 0V CXA1746Q 10k 48 GAIN22 C5 8 9 10µ C13 10 10µ C17 12 11 FNTO2 13 R7 R8 10k 10k C20 1k 0.01µ R9 C21 Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. 1 7 REO2 47 GAIN21 6 TIMER 46 IN24 45 IN23 5 14 DATA 10µ 15 VCT 44 IN22 4 16 VCC 3 17 GND 42 IN11 2 18 DGND 41 IN12 43 IN21 19 CLK 40 IN13 R5 20 CE REO1 FNTO1 R13 24 10k R12 23 10k R11 22 1k R10 21 1k 39 IN14 GAIN234 10k C1 LDLC2 38 GAIN11 37 INAO2 GAIN12 25 26 27 28 29 30 31 32 33 34 10µ C18 35 10µ C14 36 10µ VRIN2 INPUT SIGNAL SOURCES R1 C6 TCMC21 C7 0.0027µ C9 TCMC22 0.033µ C11 0.022µ R2 10k R4 10k R3 GAIN134 0.047µ C3 LDLC1 R5 10k C2 0.047µ C4 0.0022µ LDHC2 LDHC1 0.0022µ INAO1 TCHC2 VRIN1 C8 0.0027µ C10 0.033µ C12 TCHC1 0.022µ TCMC11 TCLC21 TCMC12 C15 10k C15 TCLC11 0.39µ TCLC12 TCLC22 TCO1 0.39µ C19 FDIN1 TCO2 —14— FDIN2 33µ Application Circuit TO POWER SUPPLY TO CPU OUTPUT SIGNAL CXA1746Q 10µ CXA1746Q Description of Operation (1) Gain of input amplifier The input selector stage may be configured as a buffer or a non-inverting amplifier. Gain=1+R2/R1 R2 R1 36 GAIN134 37 GAIN12 38 GAIN11 CXA1746Q VCT 39 IN14 40 IN13 41 IN12 42 IN11 33 INA01 Input amp of channel 1 (2) Loud The loudness function achieves the necessary frequency characteristics by using a filter as shown below. The resistors are built in so that fL and fH can be set by selecting C1 and C2. fL=1/(2πC1R1) fH=1/(2πC2R2) 3 LDHC1 4 LDHC2 C2 32 VRIN1 5 VRIN2 R2=8.92k 20k fH 25.7k R1=6.18k CXA1746Q fL VCT 3 LDLC1 C1 5 LDLC2 VCT —15— CXA1746Q (3) Tone control BASS: LPF fL=1/(2πC1R1//R2) R1=8k fL 8k R2=8k 8k VCT VCT CXA1746Q 27 TCLC12 18 TCLC22 C1 VCT MID: BPF fL=1/(2πC2R3) fH=1/(2πC3R4) HPF LPF R3=4k 16k 4k fH VCT 16k 4k R4=8k fM CXA1746Q 29 TCMC12 8 TCMC22 C2 38 TCMC11 7 TCMC21 C3 VCT fL VCT TREBLE: HPF fH=1/(2πC4R5) 10k 10k VCT fH 10k 10k R5=5k CXA1746Q 3 TCHC11 1 TCHC21 C4 VCT —16— CXA1746Q (4) Zero-cross detector and Timer A built-in zero-cross detection circuit is used to detect the zero-cross points of the input signal. When data arrived at the IC, they are executed at the next zero-cross point or when there is no input signal. This is to minimize 'click' noise during the transition of levels. The timer circuit is added to ensure that the data is executed even when a zero-cross point is not detected after a pre-determined period of time from the falling edge of the CE pulse. Time constant=(0.5/10µ)×C [sec] VCC 10µA 0.5V CE 15 CXA1746Q TIMER C (5) VCT pin The internal circuit of VCT pin has the following structure. Insert a buffer when using it as a reference voltage for an external circuit. VCC 100k VCT 17 100k CXA1746Q GND (6) Power-off Mute This function mutes the output pins FNTO1, FNTO2, REO1 and REO2, when the VCC goes below 5V, by turning off the bias of the output stage of the fader circuit. By so doing, the 'pop' noise caused by the drop in these pins potential from VCC/2 during power-off can be avoided. —17— CXA1746Q Examole if Reoresentative Characteristics Tone Control Frequency Characteristics 20 15 dB VOLTAGE (dB) 10 BASS MID TREBLE 0 –10 –15 dB –20 1 10 100 1k 10k 100k FREQUENCY (Hz) Loudness Frequency Characteristics 20 VOLTAGE (dB) 10 0 VRC=0 dB VRC=–8 dB VRC=–16 dB –10 VRC=–24 dB –20 –30 1 10 100 1k FREQUENCY (Hz) —18— 10k 100k CXA1746Q Package Outline Unit : mm 48PIN QFP (PLASTIC) 15.3 ± 0.4 + 0.1 0.15 – 0.05 + 0.4 12.0 – 0.1 0.15 36 25 24 13.5 37 48 + 0.2 0.1 – 0.1 13 12 0.8 + 0.15 0.3 – 0.1 0.24 M 0.9 ± 0.2 1 + 0.35 2.2 – 0.15 PACKAGE STRUCTURE SONY CODE QFP-48P-L04 EIAJ CODE QFP048-P-1212 JEDEC CODE PACKAGE MATERIAL EPOXY RESIN LEAD TREATMENT SOLDER / PALLADIUM PLATING LEAD MATERIAL 42/COPPER ALLOY PACKAGE MASS 0.7g —19—