CAT5112 32‐tap Digital Potentiometer (POT) with Buffered Wiper Description The CAT5112 is a single digital POT designed as an electronic replacement for mechanical potentiometers. Ideal for automated adjustments on high volume production lines, they are also well suited for applications where equipment requiring periodic adjustment is either difficult to access or located in a hazardous or remote environment. The CAT5112 contains a 32-tap series resistor array connected between two terminals RH and RL. An up/down counter and decoder that are controlled by three input pins, determines which tap is connected to the wiper, RWB. The CAT5112 wiper is buffered by an op amp that operates rail to rail. The wiper setting, stored in non-volatile memory, is not lost when the device is powered down and is automatically recalled when power is returned. The wiper can be adjusted to test new system values without effecting the stored setting. Wiper-control of the CAT5112 is accomplished with three input control pins, CS, U/D, and INC. The INC input increments the wiper in the direction which is determined by the logic state of the U/D input. The CS input is used to select the device and also store the wiper position prior to power down. The digital POT can be used as a buffered voltage divider. For applications where the potentiometer is used as a 2-terminal variable resistor, please refer to the CAT5114. The buffered wiper of the CAT5112 is not compatible with that application. Features 32-position Linear Taper Potentiometer Non-volatile EEPROM Wiper Storage; Buffered Wiper Low Power CMOS Technology Single Supply Operation: 2.5 V − 6.0 V Increment Up/Down Serial Interface Resistance Values: 10 kW, 50 kW and 100 kW Available in PDIP, SOIC, TSSOP and MSOP Packages These Devices are Pb-Free, Halogen Free/BFR Free and are RoHS Compliant Applications Automated Product Calibration Remote Control Adjustments Offset, Gain and Zero Control Tamper-proof Calibrations Contrast, Brightness and Volume Controls Motor Controls and Feedback Systems Programmable Analog Functions Semiconductor Components Industries, LLC, 2013 June, 2013 − Rev. 16 http://onsemi.com SOIC−8 V SUFFIX CASE 751BD MSOP−8 Z SUFFIX CASE 846AD PDIP−8 L SUFFIX CASE 646AA TSSOP−8 Y SUFFIX CASE 948AL PIN CONFIGURATIONS INC U/D RH GND 1 VCC CS RL RWB PDIP (L), SOIC (V), MSOP (Z) CS VCC INC U/D 1 RL RWB GND RH TSSOP (Y) (Top Views) PIN FUNCTION Pin Name Function INC Increment Control U/D Up/Down Control RH Potentiometer High Terminal GND Ground RWB Buffered Wiper Terminal RL Potentiometer Low Terminal CS Chip Select VCC Supply Voltage ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 10 of this data sheet. 1 Publication Order Number: CAT5112/D CAT5112 RH VCC RH U/D INC Control and Memory CS + – + RWB – Power On Recall RWB RL GND RL Figure 1. Functional Diagram Figure 2. Electronic Potentiometer Implementation Pin Description INC: Increment Control Input The INC input (on the falling edge) moves the wiper in the up or down direction determined by the condition of the U/D input. U/D: Up/Down Control Input The U/D input controls the direction of the wiper movement. When in a high state and CS is low, any high−to−low transition on INC will cause the wiper to move one increment toward the RH terminal. When in a low state and CS is low, any high-to-low transition on INC will cause the wiper to move one increment towards the RL terminal. RH: High End Potentiometer Terminal RH is the high end terminal of the potentiometer. It is not required that this terminal be connected to a potential greater than the RL terminal. Voltage applied to the RH terminal cannot exceed the supply voltage, VCC or go below ground, GND. RWB: Wiper Potentiometer Terminal (Buffered) RWB is the buffered wiper terminal of the potentiometer. Its position on the resistor array is controlled by the control inputs, INC, U/D and CS. RL: Low End Potentiometer Terminal RL is the low end terminal of the potentiometer. It is not required that this terminal be connected to a potential less than the RH terminal. Voltage applied to the RL terminal cannot exceed the supply voltage, VCC or go below ground, GND. RL and RH are electrically interchangeable. CS: Chip Select The chip select input is used to activate the control input of the CAT5112 and is active low. When in a high state, activity on the INC and U/D inputs will not affect or change the position of the wiper. Device Operation The CAT5112 operates like a digitally controlled potentiometer with RH and RL equivalent to the high and low terminals and RWB equivalent to the mechanical potentiometer’s wiper. There are 32 available tap positions including the resistor end points, RH and RL. There are 31 resistor elements connected in series between the RH and RL terminals. The wiper terminal is connected to one of the 32 taps and controlled by three inputs, INC, U/D and CS. These inputs control a five-bit up/down counter whose output is decoded to select the wiper position. The selected wiper position can be stored in nonvolatile memory using the INC and CS inputs. With CS set LOW the CAT5112 is selected and will respond to the U/D and INC inputs. HIGH to LOW transitions on INC will increment or decrement the wiper (depending on the state of the U/D input and five-bit counter). The wiper, when at either fixed terminal, acts like its mechanical equivalent and does not move beyond the last position. The value of the counter is stored in nonvolatile memory whenever CS transitions HIGH while the INC input is also HIGH. When the CAT5112 is powered-down, the last stored wiper counter position is maintained in the nonvolatile memory. When power is restored, the contents of the memory are recalled and the counter is set to the value stored. With INC set low, the CAT5112 may be deselected and powered down without storing the current wiper position in nonvolatile memory. This allows the system to always power up to a preset value stored in nonvolatile memory. http://onsemi.com 2 CAT5112 Table 1. OPERATION MODES INC CS U/D Operation High to Low Low High Wiper toward RH High to Low Low Low Wiper toward RL High Low to High X Store Wiper Position Low Low to High X No Store, Return to Standby X High X Standby RH CH RWI RWB CW CL RL Figure 3. Potentiometer Equivalent Circuit Table 2. ABSOLUTE MAXIMUM RATINGS Parameters Ratings Supply Voltage VCC to GND −0.5 to +7 Inputs CS to GND −0.5 to VCC +0.5 Units V V INC to GND −0.5 to VCC +0.5 V U/D to GND −0.5 to VCC +0.5 V RH to GND −0.5 to VCC +0.5 V RL to GND −0.5 to VCC +0.5 V RWB to GND −0.5 to VCC +0.5 V Operating Ambient Temperature Commercial (‘C’ or Blank suffix) C 0 to 70 Industrial (‘I’ suffix) −40 to +85 C Junction Temperature +150 C Storage Temperature −65 to +150 C +300 C Lead Soldering (10 s max) Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. Table 3. RELIABILITY CHARACTERISTICS Symbol Parameter VZAP (Note 1) ESD Susceptibility MIL−STD−883, Test Method 3015 2000 V Latch-Up JEDEC Standard 17 100 mA Data Retention MIL−STD−883, Test Method 1008 100 Years Endurance MIL−STD−883, Test Method 1003 1,000,000 Stores ILTH (Notes 1, 2) TDR NEND Test Method Min Typ 1. This parameter is tested initially and after a design or process change that affects the parameter. 2. Latch-up protection is provided for stresses up to 100 mA on address and data pins from −1 V to VCC + 1 V http://onsemi.com 3 Max Units CAT5112 Table 4. DC ELECTRICAL CHARACTERISTICS (VCC = +2.5 V to +6 V unless otherwise specified) Min Typ Max Units 2.5 – 6 V VCC = 6 V, f = 1 MHz, IW = 0 – – 200 mA VCC = 6 V, f = 250 kHz, IW = 0 – – 100 mA Programming, VCC = 6 V – – 1000 mA VCC = 3 V – – 500 mA Supply Current (Standby) CS = VCC − 0.3 V U/D, INC = VCC − 0.3 V or GND – 75 150 mA IIH Input Leakage Current VIN = VCC – – 10 mA IIL Input Leakage Current VIN = 0 V – – −10 mA VIH1 TTL High Level Input Voltage 4.5 V VCC 5.5 V 2 – VCC V VIL1 TTL Low Level Input Voltage 0 – 0.8 V VIH2 CMOS High Level Input Voltage VCC x 0.7 – VCC + 0.3 V VIL2 CMOS Low Level Input Voltage −0.3 – VCC x 0.2 V Symbol Parameter Conditions POWER SUPPLY VCC Operating Voltage Range ICC1 Supply Current (Increment) ICC2 Supply Current (Write) ISB1 (Note 4) LOGIC INPUTS 2.5 V VCC 6 V POTENTIOMETER CHARACTERISTICS RPOT Potentiometer Resistance −10 Device 10 −50 Device 50 −00 Device 100 Pot. Resistance Tolerance 20 % VRH Voltage on RH pin 0 VCC V VRL Voltage on RL pin 0 VCC V Resolution 1 % INL Integral Linearity Error IW 2 mA 0.5 1 LSB DNL Differential Linearity Error IW 2 mA 0.25 0.5 LSB ROUT Buffer Output Resistance 0.05 VCC VWB 0.95 VCC, VCC = 5 V 1 W IOUT Buffer Output Current 0.05 VCC VWB 0.95 VCC, VCC = 5 V 3 mA TCRPOT TC of Pot Resistance 300 ppm/C TCRATIO Ratiometric TC 20 ppm/C 8/8/25 pF CRH/CRL/CRW 3. 4. 5. 6. kW Potentiometer Capacitances fc Frequency Response Passive Attenuator, 10 kW VWB(SWING) Output Voltage Range IOUT 100 mA, VCC = 5 V 1.7 0.01 VCC This parameter is tested initially and after a design or process change that affects the parameter. Latch-up protection is provided for stresses up to 100 mA on address and data pins from −1 V to VCC + 1 V IW = source or sink These parameters are periodically sampled and are not 100% tested. http://onsemi.com 4 MHz 0.99 VCC CAT5112 Table 5. AC TEST CONDITIONS VCC Range 2.5 V VCC 6 V Input Pulse Levels 0.2 VCC to 0.7 VCC Input Rise and Fall Times 10 ns Input Reference Levels 0.5 VCC Table 6. AC OPERATING CHARACTERISTICS (VCC = +2.5 V to +6.0 V, VH = VCC, VL = 0 V, unless otherwise specified) Parameter Symbol Min Typ (Note 7) Max Units 100 − − ns tCI CS to INC Setup tDI U/D to INC Setup 50 − − ns tID U/D to INC Hold 100 − − ns tIL INC LOW Period 250 − − ns tIH INC HIGH Period 250 − − ns tIC INC Inactive to CS Inactive 1 − − ms tCPH CS Deselect Time (NO STORE) 100 − − ns tCPH CS Deselect Time (STORE) 10 − − ms INC to VOUT Change − 1 5 ms INC Cycle Time 1 − − ms INC Input Rise and Fall Time − − 500 ms Power-up to Wiper Stable – – 1 ms Store Cycle – 5 10 ms tIW tCYC tR, tF (Note 8) tPU (Note 8) tWR 7. Typical values are for TA = 25C and nominal supply voltage. 8. This parameter is periodically sampled and not 100% tested. 9. MI in the A.C. Timing diagram refers to the minimum incremental change in the W output due to a change in the wiper position. CS tCI tIL tCYC tIC tIH (store) tCPH 90% INC 90% 10% tDI tID tF U/D tR MI(3) tIW RWB Figure 4. A.C. Timing http://onsemi.com 5 CAT5112 PACKAGE DIMENSIONS PDIP−8, 300 mils CASE 646AA ISSUE A SYMBOL MIN NOM A E1 5.33 A1 0.38 A2 2.92 3.30 4.95 b 0.36 0.46 0.56 b2 1.14 1.52 1.78 c 0.20 0.25 0.36 D 9.02 9.27 10.16 E 7.62 7.87 8.25 E1 6.10 6.35 7.11 e PIN # 1 IDENTIFICATION MAX 2.54 BSC eB 7.87 L 2.92 10.92 3.30 3.80 D TOP VIEW E A2 A A1 c b2 L e eB b SIDE VIEW END VIEW Notes: (1) All dimensions are in millimeters. (2) Complies with JEDEC MS-001. http://onsemi.com 6 CAT5112 PACKAGE DIMENSIONS SOIC 8, 150 mils CASE 751BD ISSUE O E1 E SYMBOL MIN A 1.35 1.75 A1 0.10 0.25 b 0.33 0.51 c 0.19 0.25 D 4.80 5.00 E 5.80 6.20 E1 3.80 MAX 4.00 1.27 BSC e PIN # 1 IDENTIFICATION NOM h 0.25 0.50 L 0.40 1.27 θ 0º 8º TOP VIEW D h A1 θ A c e b L END VIEW SIDE VIEW Notes: (1) All dimensions are in millimeters. Angles in degrees. (2) Complies with JEDEC MS-012. http://onsemi.com 7 CAT5112 PACKAGE DIMENSIONS TSSOP8, 4.4x3 CASE 948AL ISSUE O b SYMBOL MIN NOM 1.20 A E1 E MAX A1 0.05 A2 0.80 b 0.19 0.15 0.90 1.05 0.30 c 0.09 D 2.90 3.00 3.10 E 6.30 6.40 6.50 E1 4.30 4.40 4.50 0.20 0.65 BSC e L 1.00 REF L1 0.50 θ 0º 0.60 0.75 8º e TOP VIEW D A2 c q1 A A1 L1 SIDE VIEW L END VIEW Notes: (1) All dimensions are in millimeters. Angles in degrees. (2) Complies with JEDEC MO-153. http://onsemi.com 8 CAT5112 PACKAGE DIMENSIONS MSOP 8, 3x3 CASE 846AD ISSUE O SYMBOL MIN NOM MAX 1.10 A E A1 0.05 0.10 0.15 A2 0.75 0.85 0.95 b 0.22 0.38 c 0.13 0.23 D 2.90 3.00 3.10 E 4.80 4.90 5.00 E1 2.90 3.00 3.10 E1 0.65 BSC e L 0.60 0.40 0.80 L1 0.95 REF L2 0.25 BSC θ 0º 6º TOP VIEW D A A2 A1 DETAIL A e b c SIDE VIEW END VIEW q L2 Notes: (1) All dimensions are in millimeters. Angles in degrees. (2) Complies with JEDEC MO-187. L L1 DETAIL A http://onsemi.com 9 CAT5112 Table 7. ORDERING INFORMATION Device Order Number Specific Device Marking Package Type Temperature Range Lead Finish Shipping† CAT5112VI−10−GT3 CAT5112V SOIC−8 −40C to +85C NiPdAu Tape & Reel, 3,000 Units / Reel CAT5112VI−50−GT3 CAT5112V SOIC−8 −40C to +85C NiPdAu Tape & Reel, 3,000 Units / Reel CAT5112VI−00−GT3 CAT5112V SOIC−8 −40C to +85C NiPdAu Tape & Reel, 3,000 Units / Reel CAT5112YI−10−GT3 A22 TSSOP−8 −40C to +85C NiPdAu Tape & Reel, 3,000 Units / Reel CAT5112YI−50−GT3 A24 TSSOP−8 −40C to +85C NiPdAu Tape & Reel, 3,000 Units / Reel CAT5112YI−00−GT3 A25 TSSOP−8 −40C to +85C NiPdAu Tape & Reel, 3,000 Units / Reel CAT5112ZI−10−GT3 ABPN MSOP−8 −40C to +85C NiPdAu Tape & Reel, 3,000 Units / Reel CAT5112ZI−50−GT3 ABPN MSOP−8 −40C to +85C NiPdAu Tape & Reel, 3,000 Units / Reel CAT5112ZI−00−GT3 ABPN MSOP−8 −40C to +85C NiPdAu Tape & Reel, 3,000 Units / Reel CAT5112LI−10−G CAT5112L PDIP−8 −40C to +85C NiPdAu Rail, 50 Units CAT5112LI−50−G CAT5112L PDIP−8 −40C to +85C NiPdAu Rail, 50 Units CAT5112LI−00−G CAT5112L PDIP−8 −40C to +85C NiPdAu Rail, 50 Units †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. 10. 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