MP7770 2 x 45W Stereo Single-Ended or 90W Mono BTL Class-D Audio Amplifier The Future of Analog IC Technology DESCRIPTION FEATURES MP7770 is an analog class-D audio amplifier that can drive either stereo speakers in singleended configuration or a mono speaker in a bridge-tied-load configuration. It is part of MPS’s family of fully-integrated audio amplifiers that dramatically reduce footprint size by integrating: 100mΩ power MOSFETs Startup/Shutdown pop elimination Short-circuit protection circuits The MP7770 is capable of delivering 45W per channel into 4Ω speaker in single-ended output structure, or delivering 90W into 8Ω speaker in bridge-tied-load output structure under 36V VDD. MPS’s class D audio amplifiers exhibit the high fidelity of a Class A/B amplifier at higher efficiencies. The circuit is based on the MPS’s proprietary variable-frequency topology, which delivers excellent linearity, fast response time and operates from a single power supply. 9.5V-to-36V Operation from a Single Supply ±8.5A Peak Current Output Output Power at 36V and 10%THD: - Stereo Single-Ended: 2 x 45W into 4Ω Load, - Bridge-Tied Load: 90W into 8Ω Load THD+N = 0.03% at 1W, 8Ω > 90% Efficiency at 10%THD Low Noise Switching Frequency of up to 1MHz Integrated Startup and Shutdown Pop Elimination Circuit Programmable UVP Thermal and Short-Circuit Protection Output Fault Flag and Thermal Warning Integrated Power FETs TSSOP28-EP Package with Exposed Pad on Bottom TSSOP28-EPR Package with Exposed Pad on Top, Please Contact Factory for the Availability APPLICATIONS DVD Receiver Mini Combo System Home Theater Systems Surround Sound Systems Audio Docking or High-Power Sound Box All MPS parts are lead-free and adhere to the RoHS directive. For MPS green status, please visit MPS website under Quality Assurance “MPS” and “The Future of Analog IC Technology” are Registered Trademarks of Monolithic Power Systems, Inc. MP7770 Rev.1.0 12/4/2012 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2012 MPS. All Rights Reserved. 1 MP7770 –2 X 45W STEREO SE OR 90W MONO BTL CLASS D AUDIO AMPLIFIER TYPICAL APPLICATIONS CH1 INPUT CH1 OUTPUT IN1 SW1 REF1 BST1 TIMER1 PGND1 TIMER2 PGND2 OFF ON EN UVP MP7770 OTW VDD1 FAULT VDD2 VDD AGND1 AGND2 BST2 CH2 OUTPUT REF2 SW2 CH2 INPUT IN2 Stereo SE Application Circuit TIMER1 SW1 TIMER2 BST1 INPUT+ IN1 REF1 REF2 INPUT- IN2 PGND1 MP7770 EN OFF ON OUTPUT PGND2 VDD V DD1 UVP OTW V DD2 BST2 FAULT AGND1 SW2 AGND2 Mono BTL Application Circuit MP7770 Rev.1.0 12/4/2012 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2012 MPS. All Rights Reserved. 2 MP7770 –2 X 45W STEREO SE OR 90W MONO BTL CLASS D AUDIO AMPLIFIER ORDERING INFORMATION Part Number* MP7770GF **MP7770GFR Package TSSOP28-EP TSSOP28-EPR Top Marking MP7770 MP7770R * For Tape & Reel, add suffix –Z (e.g. MP7770GF–Z); ** Contact Factory for TSSOP28F-EPR Availability PACKAGE REFERENCE BST1 OTW PGND1 FAULT PGND1 N/C TIMER1 SW1 IN1 SW1 REF1 AGND1 AGND2 VDD1 VDD1 EXPOSED PAD ON TOP VDD2 VDD2 REF2 IN2 SW2 TIMER2 SW2 N/C PGND2 UVP PGND2 BST2 EN TSSOP28-EPR TSSOP28-EP ABSOLUTE MAXIMUM RATINGS (1) Supply Voltage VDD ...................................... 40V BS Voltage .............. (VSW - 0.3V) to (VSW + 6.5V) VOTW, VFAULT, VUVP, VTIMER, VEN ....... –0.3V to +6V VSW ....................................... –0.3V to (VDD + 1V) VREF, VIN ....................................... –0.3V to +34V AGND to PGND .......................... –0.3V to +0.3V (2) Continuous Power Dissipation (TA = 25°C) ............................................................ 3.9 W Junction Temperature ............................... 150°C Lead Temperature ....................................260°C Storage Temperature .............. –65°C to +150°C Recommended Operating Conditions (3) Supply Voltage VDD .......................... 9.5V to 36V Operating Junction Temp. (TJ). ........................... ........................................... -40°C to +125°C MP7770 Rev.1.0 12/4/2012 Thermal Resistance (4) θJA θJC TSSOP28F-EP ....................... 32 ....... 6.... °C/W TSSOP28F-EPR ...................... .. ........ 6.... °C/W The TSSOP28F-EPR is not intended to be used without a heatsink. Therefore, RθJA of TSSOP28F-EPR is not specified. Notes: 1) Exceeding these ratings may damage the device. 2) The maximum allowable power dissipation is a function of the maximum junction temperature TJ (MAX), the junction-toambient thermal resistance θJA, and the ambient temperature TA. The maximum allowable continuous power dissipation at any ambient temperature is calculated by PD (MAX) = (TJ (MAX)-TA)/θJA. Exceeding the maximum allowable power dissipation will cause excessive die temperature, and the regulator will go into thermal shutdown. Internal thermal shutdown circuitry protects the device from permanent damage. 3) The device is not guaranteed to function outside of its operating conditions. 4) Measured on JESD51-7, 4-layer PCB. www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2012 MPS. All Rights Reserved. 3 MP7770 –2 X 45W STEREO SE OR 90W MONO BTL CLASS D AUDIO AMPLIFIER ELECTRICAL CHARACTERISTICS (5, 6) VDD = 24V, VEN = 5V, TA = 25°C, unless otherwise noted. Parameters Standby Current Quiescent Current SW ON Resistance Short-Circuit Current EN Enable Threshold Voltage EN Enable Input Current External Under-Voltage Detection External Under-Voltage Detection Hysteresis Voltage Thermal Shutdown Trip Point (7) Thermal Shutdown Hysteresis(7) Thermal Warning Trip Point(7) Thermal Warning Hysteresis(7) Symbol Condition VEN = 0V,REF=IN=Float IQ SW=Low Sourcing and Sinking Sourcing and Sinking VEN Rising VEN Falling VEN = 5V VUVP Min 6.2 0.4 2 VHys TJ Rising Typ 120 3 0.1 8.5 1.4 1.0 5 Max 140 4 0.15 2.2 2.4 2.0 Units µA mA Ω A V V µA V 0.3 V 150 20 125 10 °C °C °C °C Notes: 5) The device is not guaranteed to function outside its operating rating. 6) Electrical Characteristics are for the IC only with no external components except bypass capacitors. 7) Not production tested. MP7770 Rev.1.0 12/4/2012 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2012 MPS. All Rights Reserved. 4 MP7770 –2 X 45W STEREO SE OR 90W MONO BTL CLASS D AUDIO AMPLIFIER OPERATING SPECIFICATIONS (8) Circuit of Figure 6, Single-Ended Output Configuration; VDD = 34V, Gain=8.2V/V; VEN = 5V, TA = 25°C, unless otherwise noted. Parameters Standby Current Quiescent Current Power Output THD + Noise Efficiency Maximum Power Bandwidth Dynamic Range Noise Floor Power Supply Rejection Symbol Condition VEN = 0V Switching, no load f = 1kHz, THD+N = 10%, 4Ω Load f = 1kHz, THD+N = 1%, 4Ω Load f = 1kHz, THD+N = 10%, 8Ω Load f = 1kHz, THD+N = 1%, 8Ω Load POUT = 1W, f = 1kHz, 4Ω Load POUT = 1W, f = 1kHz, 8Ω Load f = 1kHz, POUT = 41W, 4Ω Load f = 1kHz, POUT = 22W, 8Ω Load Min A-Weighted VRIPPLE=300mVPP CR=100μF f = 1k Hz f = 217 Hz Typ 120 29 41 32 22 17 0.05 0.03 91 95 20 102 90 -60 -60 Max Units μA mA W W W W % % % % kHz dB μV dB dB Circuit of Figure 7, BTL Output Configuration; VDD = 34V, Gain=15V/V; VEN = 5V, TA = 25°C, unless otherwise noted. Parameters Standby Current Quiescent Current Power Output THD+ Noise Efficiency Symbol Condition VEN = 0V Switching, no load f = 1kHz, THD+N = 10%, 6Ω Load f = 1kHz, THD+N = 1%,6Ω Load POUT = 1W, f = 1kHz, 6Ω Load POUT = 1W, f = 1kHz, 8Ω Load f = 1kHz, POUT = 108W, 6Ω Load f = 1kHz, POUT = 84W, 8Ω Load Maximum Power Bandwidth Dynamic Range Noise Floor A-Weighted Power Supply Rejection VRIPPLE=300mVPP f = 1k Hz f = 217 Hz Min Typ 120 32 108 83 0.06 0.04 91 95 20 105 120 -60 -60 Max Units μA mA W W % % % % kHz dB μV dB dB Note: 8) Operating Specifications are for the IC in Typical Application circuit (Figure 6 and Figure 7). MP7770 Rev.1.0 12/4/2012 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2012 MPS. All Rights Reserved. 5 MP7770 –2 X 45W STEREO SE OR 90W MONO BTL CLASS D AUDIO AMPLIFIER PIN FUNCTIONS EP on Bottom EP on Top Pin # Pin # Name 1 14 OTW 2 13 FAULT 3, 12 3, 12 N/C 4 4 TIMER1 5 5 IN1 6 6 REF1 7 7 AGND1 8 8 AGND2 9 9 REF2 10 10 IN2 11 11 TIMER2 13 2 UVP 14 1 EN 15 15 BST2 16, 17 18, 19 16, 17 18, 19 PGND2 SW2 20, 21 20, 21 VDD2 22, 23 22, 23 VDD1 24, 25 24, 25 SW1 26,27 26,27 PGND1 28 28 BST1 MP7770 Rev.1.0 12/4/2012 Description Over Temperature Warning. A low output at OTWB indicates that the die temperature rises above 125°C. This output is open drain. Fault Output. A low output at FAULT indicates that the IC has detected an over-temperature or over-current condition. This output is open drain. Not Connected. Internal Timer Input for Amplifier 1. A capacitor from TIMER1 to AGND sets the internal timer which is used for start-up pop elimination. Inverting Input for Amplifier 1 . Internal Analog Reference (VDD/2) for Amplifier 1. For SE configuration, connect a bypass capacitor from REF1 to AGND (10μF). Analog Ground for Amplifier 1. Connect AGND1 to AGND2. Connect PGND to AGND at a single point. Analog Ground for Amplifier 2. Connect AGND2 to AGND1. Internal Analog Reference (VDD/2) for Amplifier 2. For BTL configuration, connect a bypass capacitor from REF2 to AGND (10μF). Inverting Input for Amplifier 2. Internal Timer Input for Amplifier 2. Use a capacitor from TIMER2 to AGND to set the internal timer for start-up pop elimination. Under-Voltage Protection Reference Input. Enable Input for Amplifier 1. Drive EN1 high to turn on the Amplifier 1, low to turn it off. High-Side MOSFET Bootstrap Input for Amplifier 2. Connect a capacitor from BST2 to SW2 to supplies the gate drive to the internal High-Side MOSFET. Power Ground for Amplifier 2. Connect PGND2 to PGND1. Switched Power Output for Amplifier 2. Power Supply Input for Amplifier 2. Bypass VDD2 to PGND2 with a 1μF X7R capacitor (in addition to the main bulk capacitor), placed close to the VDD2 and PGND2 pins. Power Supply Input for Amplifier 1. Bypass VDD1 to PGND1 with a 1μF X7R capacitor (in addition to the main bulk capacitor), placed close to the VDD1 and PGND1 pins. Switched Power Output for Amplifier 1. Power Ground for Amplifier 1. Connect PGND1 to PGND2. Connect PGND to AGND at a single point. High-Side MOSFET Bootstrap Input for Amplifier 1. A capacitor from BST1 to SW1 supplies the gate drive current to the internal High-Side MOSFET. www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2012 MPS. All Rights Reserved. 6 MP7770 –2 X 45W STEREO SE OR 90W MONO BTL CLASS D AUDIO AMPLIFIER TYPICAL PERFORMANCE CURVES Circuit of Figure 6, single-ended output configuration, VDD=34V, VEN=5V, AV=8.2V/V, TA = +25C, unless otherwise noted. MP7770 Rev.1.0 12/4/2012 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2012 MPS. All Rights Reserved. 7 MP7770 –2 X 45W STEREO SE OR 90W MONO BTL CLASS D AUDIO AMPLIFIER TYPICAL PERFORMANCE CURVES (continued) Circuit of Figure 6, single-ended output configuration, VDD=34V, VEN=5V, AV=8.2V/V, TA = +25C, unless otherwise noted. MP7770 Rev.1.0 12/4/2012 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2012 MPS. All Rights Reserved. 8 MP7770 –2 X 45W STEREO SE OR 90W MONO BTL CLASS D AUDIO AMPLIFIER TYPICAL PERFORMANCE CURVES (continued) Circuit of Figure 6, single-ended output configuration, VDD=34V, VEN=5V, AV=8.2V/V, TA = +25C, unless otherwise noted. MP7770 Rev.1.0 12/4/2012 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2012 MPS. All Rights Reserved. 9 MP7770 –2 X 45W STEREO SE OR 90W MONO BTL CLASS D AUDIO AMPLIFIER TYPICAL PERFORMANCE CURVES (continued) Circuit of Figure 7, bridge-tied-load output configuration, VDD=34V, VEN=5V, AV=15V/V, TA = +25C, unless otherwise noted. MP7770 Rev.1.0 12/4/2012 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2012 MPS. All Rights Reserved. 10 MP7770 –2 X 45W STEREO SE OR 90W MONO BTL CLASS D AUDIO AMPLIFIER TYPICAL PERFORMANCE CURVES (continued) Circuit of Figure 7, bridge-tied-load output configuration, VDD=34V, VEN=5V, AV=15V/V, TA = +25C, unless otherwise noted. MP7770 Rev.1.0 12/4/2012 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2012 MPS. All Rights Reserved. 11 MP7770 –2 X 45W STEREO SE OR 90W MONO BTL CLASS D AUDIO AMPLIFIER FUNCTIONAL BLOCK DIAGRAM VDD1 REF1 BST1 Reference VDD IN1 TIMER1 AAMTM Modulator SW1 Control & Gate Drive UVP EN Control Processor PGND1 OTP OCP OTW VDD2 FAULT BST2 OTW REF2 VDD Reference IN2 TIMER2 AAMTM Modulator SW2 Control & Gate Drive PGND2 AGND1, 2 Figure 1: Functional Block Diagram MP7770 Rev.1.0 12/4/2012 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2012 MPS. All Rights Reserved. 12 MP7770 –2 X 45W STEREO SE OR 90W MONO BTL CLASS D AUDIO AMPLIFIER OPERATION The MP7770 is a Class D Audio Amplifier that drives stereo speakers in single-ended configuration or a mono speaker in bridge-tiedload configuration. It uses MPS’s patented Analog Adaptive ModulationTM technology to convert the audio input signal into pulses. These pulses drive an internal high-current output stage and—when filtered through an external inductor-capacitor filter—reproduce the input signal across the load. Because of the switching Class D output stage, power dissipation in the amplifier is drastically reduced when compared against Class A, B or A/B amplifiers, and maintains high fidelity with low distortion. REF1 and REF2 are the positive inputs of two amplifiers. They are set to half the power supply input voltage (VDD/2) by internal circuit. The input capacitor decouples the AC signal at the input. the DC the CIN The input resister RIN and the feedback resistor RFB set the amplifier voltage gain as calculated by the equation: AV R FB R IN Where: Channel 1: RFB=RFB1 and RIN=RIN1 Channel 2: RFB=RFB2 and RIN=RIN2. The MP7770 includes four high-power MOSFETs; For each channel, the output driver stage uses two 100mΩ N-channel MOSFETs to deliver pulses to the LC output filter to drive the load. To enhance the high-side MOSFET (HSFET), the gate is driven to a voltage higher than the source by the bootstrap capacitor between SW and BS. When the output is low, the bootstrap capacitor is charged from VDD through an internal circuit on the MP7770. The gate of the HS-FET is driven high by the BST voltage, forcing the MOSFET gate to a voltage higher than VDD, thus allowing the MOSFET to turn on and reducing amplifier power loss. MP7770 Rev.1.0 12/4/2012 Pop Elimination When used in a single-ended output configuration, the capacitors COUT1 and COUT2 block the DC signal and pass the AC signals to the load. To insure that the amplifier only passes low-frequency signals, the time constant of COUT*RLOAD is large. However, when EN goes high, the capacitor charges over a long period and can result in turn-on/turn-off “pop” In typical amplifiers. The MP7770 integrates a source-current function to charge the DC block capacitors COUT1 and COUT2 and CIN1 and CIN2 at start-up. Two internally-generated currents flow to the SW pin (Iinitialization_SW) and the IN pin (Iinitialization_IN) during start-up, which helps to eliminate turn-on pop. The rising/falling slew rate of the SW node start-up current (Iinitialization_SW) is out of audio band (means rise and falling gradually), can be adjusted from the timer capacitor CTIMER and the voltage of SW node; The larger the CTIMER capacitance, the smaller the slew rate of the Iinitialization_SW. After driving the EN pin low, the output SW immediately switches to high impedance to eliminate turn-off pop. Short Circuit/Overload Protection and Monitoring The MP7770 is fully-protected against overcurrent and thermal overload conditions as explained below and \shown in Figure2. Short Circuit/Overload Protection The MP7770 has internal overload and shortcircuit protection. The currents in both the highside and low-side MOSFETs (LS-FETs) are measured and if the current exceeds the short circuit current limit (typically 8A), both MOSFETs will be turned off for a fixed duration (around 1ms) before resuming normal operation. After the fixed duration and the short circuit condition is removed, the MP7770 will restart with the start-up sequence that is used for normal starting to prevent a pop from occurring. www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2012 MPS. All Rights Reserved. 13 MP7770 –2 X 45W STEREO SE OR 90W MONO BTL CLASS D AUDIO AMPLIFIER Over-Temperature Shutdown Thermal monitoring is also integrated into the MP7770. If the die temperature rises above 150°C, all switches turn off. The temperature must fall below 130°C before normal operation resumes, with the same power-up sequence used to prevent popping noise. Over-Temperature Warning Output The MP7770 includes an open drain, active low fault indicator output to act as an overtemperature warning (OTW). The OTW pin is asserted when the die temperature reaches 125°C and goes low until the temperature drops below 115°C. Do not apply more than 6V to the OTW pin. Fault Output The MP7770 includes an open drain, active low fault indicator output on the FAULTB pin. A fault triggers if either the current limit or thermal shutdown is tripped. A fault on any channel will cause the FAULTB pin to pull low. A fault on either channel will cause the all outputs to go into high impedance. When the fault goes away, the MP7770 will resume normal operation. Normal Operation No Overcurrent detected? No No TEMP>125 °C ？ TEMP>150 °C ？ Yes Yes Yes Disable output, Fault =L OTW =L Disable output , Fault =L No No Around 1ms time out finished? Yes Meet restart condition (start up sequence )? No No TEMP<115 °C ？ TEMP<130 °C ？ Yes Yes OTW=H No Meet restart condition (start up sequence)? Yes Yes Enable output , Fault=H Enable output , Fault =H Figure 2: Fault Timing Chart Do not apply more than 6V to the FAULTB pin. MP7770 Rev.1.0 12/4/2012 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2012 MPS. All Rights Reserved. 14 MP7770 –2 X 45W STEREO SE OR 90W MONO BTL CLASS D AUDIO AMPLIFIER Enable Function The MP7770 EN input is an active-high–enable control. To enable the MP7770, drive EN with a voltage 2.0V or higher; to disable the amplifier, drive it below 0.4V. While the MP7770 is disabled, the VDD operating current is around 250μA and the output driver MOSFETs are turned off. Programmable UVP MP7770 integrate programmable UVP function, which can be used to shutdown the MP7770 to escape the pop, by controlling the UVP node voltage. The VDD shutdown voltage can be flexibly adjusted by the external resistor, as shown in the figure 3. R H_internal UVP + RL_internal RL +2.2V The thermally-augmented TSSOP-EPR package with the exposed pad on top is designed to interface directly with heat sinks using a thermal interface compound. The heat sink then absorbs heat from the ICs and couples it to the local air. If louvers or fans are used, this process can reach equilibrium and heat can be continually removed from the ICs. Because of the efficiency of the MP7770, heat sinks can be smaller than those required for linear amplifiers. The TSSOP28-EPR is not intended for use without a heatsink. For cases without a heatsink, please use the TSSOP28-EP with the exposed pad on the bottom. VDD RH Thermal Information The MP7770 is available in a thermallyenhanced TSSOP28 package. The user can choose between two package options, with the exposed pad on top or bottom. - AGND Figure 3: UVP Block Diagram If external resistor RH and RL is low enough (e.g. RH, RL < 50kΩ) compared with internal resistor, the VDD shutdown voltage (rising threshold) can be calculated by the equation: VVDD _ shutdown 2.2 * (RH RL ) RL If the UVP pin is NC, the default VDD shutdown voltage (rising threshold) is 8.4V since there is internal voltage divided circuit. For example, please see the table 1 for recommended UVP setting for reduce the power off pop. Table 1 VDD (V) 12 24 36 VDD_shutdown (V) 8.6 19 26 MP7770 Rev.1.0 12/4/2012 RH RL 15k 39k 56k 5.1k 5.1k 5.1k www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2012 MPS. All Rights Reserved. 15 MP7770 –2 X 45W STEREO SE OR 90W MONO BTL CLASS D AUDIO AMPLIFIER APPLICATION INFORMATION Component Selection The MP7770 uses a minimal number of external components to complete a stereo SE or mono BTL Class D audio amplifier. The circuit in Figure 6 (stereo SE application circuit) and Figure 7 (mono BLT application circuit) are optimized for a 24V power supply. This circuit should be suitable for most applications. Use the following sections to design custom circuits. Setting the Voltage Gain The maximum output-voltage swing is the power supply. To achieve the output power, set the gain such maximum input signal results in the output voltage swing. Table 2: Switching Frequency Setting For SE Output Configuration VDD Gain RFB RIN (V) (V/V) (kΩ) (kΩ) limited by maximum that the maximum For a single-ended (SE) output configuration, the maximum output voltage VOUT(PK) is VDD/2. For a bridge-tied-load (BTL) output configuration, the maximum output voltage VOUT(PK) is VDD. For a given input signal voltage, where VIN(PK) is the peak input voltage, the maximum voltage gain is: A V (MAX) greater than 50kHz plus the left channel’s switching frequency by using a different timing capacitor CINT. For details, refer to the Table 2 for recommended SE output configuration design, and Table 3 for recommended BTL output configuration design. VOUT(PK ) VIN(PK ) This voltage-gain setting results in the peak output voltage approaching its maximum for the maximum input signal. In some cases the amplifier is allowed to overdrive slightly, allowing the THD to increase at high power levels, and so a higher gain than AV (max) is required. Left Right channel channel CINT1 FSW1 CINT2 FSW2 (nF) (kHz) (nF) (kHz) 12 10 100 10 2.2 635 1.8 705 12 20 100 4.99 2.2 635 1.8 705 24 10 75 7.5 5.6 700 4.7 740 24 20 150 7.5 2.2 780 2.7 665 30 10 51 5.1 8.2 780 10 680 30 20 150 7.5 3.3 710 2.7 780 30 30 150 4.99 3.3 710 2.7 780 34 10 51 5.1 10 785 12 610 34 20 100 4.99 4.7 780 5.6 740 34 30 150 4.99 3.9 700 3.3 775 Table 3: Switching Frequency Setting for BTL Output Configuration VDD Gain RFB RIN (V) (V/V) (kΩ) (kΩ) CINT1 FSW1 (nF) (kHz) 12 10 100 10 2.2 435 Setting the Switching Frequency 12 20 100 4.99 2.2 435 The idle switching frequency (the switching frequency when no audio input is present) is a function of several variables: The supply voltage VDD, the integral capacitor CINT and the feedback resistor RFB. Lower switching frequencies result in greater inductor ripple, causing more quiescent output voltage ripple, and increasing the output noise and distortion. Higher switching frequencies result in greater power loss. The optimum quiescent switching frequency is approximately 600kHz. When used to drive stereo speakers in single-ended configuration, set right channel to an idle switching frequency 12 30 150 4.99 1.0 440 24 10 100 10 3.3 490 24 20 100 4.99 2.2 570 24 30 150 4.99 1.5 480 30 10 100 10 2.2 465 30 20 100 4.99 3.3 535 30 30 150 4.99 2.2 450 34 10 100 10 3.3 560 34 20 100 4.99 3.3 560 34 30 150 4.99 2.2 470 MP7770 Rev.1.0 12/4/2012 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2012 MPS. All Rights Reserved. 16 MP7770 –2 X 45W STEREO SE OR 90W MONO BTL CLASS D AUDIO AMPLIFIER Choosing the Output LC Filter The inductor-capacitor (LC) filter converts the pulses at SW to the output voltage that drives the speaker. There are two kinds of LC filter structure depending on the output configuration. COUT LF SW1/2 CF RLOAD Figure 4: SE Filter Configuration LF1 SW1 CY1 CY2 SW2 CX RLOAD LF2 Figure 5: BTL Filter Configuration Where: LF LF1 LF2 , CF C X CY1 CY2 , CY1 CY2 LF1 LF2 ; CY1 CY2 The characteristic frequency of the LC filter needs to be high enough to allow high frequency audio to the output, yet needs to be low enough to filter out high frequency products of the pulses from the SW pin. The characteristic frequency of the LC filter is: f0 1 2 LF CF The quality factor (Q) of the LC filter is important: If this is too low, output noise will increase; if this is too high, then peaking may occur at high frequencies and reduce the passband flatness. The circuit Q is set by the load resistance (speaker resistance, typically 4Ω or 8Ω). Q is calculated as: Q MP7770 Rev.1.0 12/4/2012 RLOAD RLOAD 0 LF 2 f0 LF 0 is the characteristic frequency in radians/second and f0 is in Hz. Use an LC filter with Q between 0.7 and 1. The type of inductor and capacitor used in the LC filter.greatly affects the output ripple and noise. Use a film capacitor and an inductor with sufficient power rating to supply the output current to the load. The inductor must exhibit soft saturation characteristics: If the inductor exhibits hard saturation, it should operate well below the saturation current. Use toroidal cores made of gapped ferrite, MPP, powdered iron, or similar materials. If using either an open or shielded bobbin ferrite core for multi-channel designs, make sure that the start windings of each inductor align (all starting toward the SW pin, or all starting toward the output) to prevent crosstalk or other channel-to-channel interference. Output Coupling Capacitor for SE Output The output AC coupling capacitor—COUT— serves to pass only the amplified AC signal from the LC filter to the load and to block DC signals. The combination of the coupling capacitor, COUT and the load resistance results in a first-order high-pass filter. Select COUT so that the required minimum frequency passes. The output corner frequency (-3dB point), fOUT, can be calculated as: f OUT 1 2 R LOAD C OUT Set the output corner frequency (fOUT) at or below the minimum required frequency. The output coupling capacitor carries the full load current, so chose a capacitor such that its ripple current rating is greater than the maximum load current. Use low-ESR aluminum electrolytic capacitors for best results. Input Coupling Capacitor The input coupling capacitors CIN1 and CIN2 pass only the AC signal at the input. For a typical system application, the source input signal centers around the circuit ground, while the MP7770 input is at half the power supply voltage (VDD/2). The input coupling capacitor transmits the AC signal from the source www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2012 MPS. All Rights Reserved. 17 MP7770 –2 X 45W STEREO SE OR 90W MONO BTL CLASS D AUDIO AMPLIFIER to the MP7770 while blocking the DC voltage. Choose an input coupling capacitor such that the corner frequency (fIN) is less than the passband frequency. The corner frequency is calculated as: fIN 1 2 RIN CIN Timer capacitor The start-up source current slew rate is adjusted from the timing capacitor, CTIMER: The larger the CTIMER capacitance is, the smaller the start-up current slew rate is. Select a CTIMER value larger than 312nF, so the start-up current slew rate would be smaller than 20mA/50ms which helps eliminate the turn-on pop. The recommended 2.2μF capacitor CTIMER results in a start-up current slew rate of approximately 20mA/350ms. Power Source For maximum output power, the amplifier circuit requires a regulated external power source. A high power-supply voltage can deliver more power to a given load resistance, but a powersource voltage exceeding the maximum voltage of 36V can damage the MP7770. The MP7770’s power supply rejection is excellent, though power-supply noise can pass to the output, so care must be taken to minimize power supply noise within the pass-band frequencies. Bypass the power supply with a large capacitor (typically aluminum electrolytic) along with a smaller 1μF ceramic capacitor at the MP7770 VDD supply pins. PCB Layout Circuit layout is critical for optimal performance, low output distortion, and noise. Duplicate the EVB layout for best results. For layout changes, follow these guidelines and use Figure 8 as SE layout references, use Figure 9 as BTL layout reference. Bootstrap Capacitors CBS1 and CBS2 supply the gate drive current to the internal HS-FET. Place CBS1 as close to BST1/2 pin and SW1/2 pin as possible. Likewise, place CBS2 as close to BST2 pin and SW2 pins as possible. Power Supply Bypass Capacitors CBYP1 and CBYP2 carry the transient current for the switching power stage. To avoid overstressing the MP7770 and excessive output noise, place CBYP1 as close to the VDD1 pins and PGND1 pins as possible, and place CBYP2 as close to the VDD2 pins and PGND2 pins as possible. Integral Capacitors CINT sets the amplifier switching frequencies and are typically on the order of a few nF. Place the integral capacitor CINT as close to the corresponding input as possible to reduce distortion and noise. For example, place CINT1 as close to pins 2 and 3 as possible at SE output configuration. Reference Bypass Capacitors for SE Output When used with SE output, CR1 and CR2 filter the ½ VDD reference voltages. Place CR1 and CR2 as close to the IC as possible to improve power supply rejection and reduce distortion and noise at the output. 2) The Inductor-Capacitor (LC) filter converts the pulse train at SW to the output voltage that drives the speaker. Please keep the filter capacitor close to the inductor. 3) Keep the sensitive feedback signal trace on the input side and shield the trace with the AGND plane. Make sure that any traces carrying the switch node (SW) voltages are routed far from any input signal traces. If the trace must run near the SW trace near the input, shield the input with a ground plane between the traces. Physically separate each channel to 1) Place the following components as close to the MP7770 as possible: MP7770 Rev.1.0 12/4/2012 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2012 MPS. All Rights Reserved. 18 MP7770 –2 X 45W STEREO SE OR 90W MONO BTL CLASS D AUDIO AMPLIFIER prevent crosstalk. Make sure that all inductors used on a single circuit board have the same orientation. Route each power supply from the source to each channel individually, not serially. This prevents channel-to-channel coupling through the power supply input. Electro-Magnetic Interference (EMI) Considerations Due to the switching nature of Class D amplifiers, care must be taken to minimize the effects of electromagnetic interference from the amplifier. However, proper component selection and careful attention to circuit layout can minimize the effects of the EMI due to the amplifier switching. The power inductors are a potential source of radiated emissions. For the best EMI performance, use toroidal inductors, since the magnetic field is well-contained inside the core. However toroidal inductors can be expensive to wind. For a more economical solution, use shielded-gapped–ferrite or shielded-ferritebobbin-core inductors. These inductors typically do not contain the EM field as well toroidal inductors, but can achieve a better balance between good EMI performance with low cost. The size of high-current loops that carry rapidly changing currents must be minimized: Make sure that the VDD bypass capacitors are as close to the MP7770 as possible. Nodes that carry rapidly changing voltage, such as SW, need to be made as small as possible. If sensitive traces run near a trace connected to SW, place a ground shield between the traces. MP7770 Rev.1.0 12/4/2012 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2012 MPS. All Rights Reserved. 19 MP7770 –2 X 45W STEREO SE OR 90W MONO BTL CLASS D AUDIO AMPLIFIER TYPICAL APPLICATION CIRCUITS CFB1 RFB1 CIN1 6 CR1 REF1 CINT1 RIN1 CH1 INPUT 5 4 BST1 28 IN1 C TIMER1 SW1 24,25 11 CF1 TIMER2 MP7770 CIN2 9 REF2 CR2 10 CH2 INPUT 13 FAULT SW2 IN2 VDD1 FAULT PGND1 14 OTW 1 EN OTW EN VDD2 7,8 AGND2 2 BST2 C CINT2 RIN2 PGND2 CH1 OUTPUT 15 LF2 COUT2 18,19 22,23 CF2 VDD CBYP1 26,27 CVDDBYP 1000 CH2 OUTPUT 20,21 CBYP2 16,17 UVP RFB2 CFB2 Figure 6: 24V VDD Stereo SE Typical Application Circuit CFB1 22pF 5 6 4 IN1 14 OTW 22, 23 U1 BST1 28 REF1 SW1 24, 25 TIMER1 1 EN1 EN PGND1 26, 27 MP7770 OTW 2 UVP 11 BST2 9 REF2 INPUT- 10 IN2 CFBX2 2pF 7 SW1 SP- 15 SP+ SW2 TIMER2 SW2 AGND2 VCC RSN1 10 CSN1 390pF 50V 13 FAULT FAULT AGND1 CINT 2.2nF VDD2 SW2 CFBX1 2pF INPUT+ VDD1 20, 21 VCC 8 PGND2 18, 19 16, 17 RSN2 10 CSN2 390pF 50V SW1 CFB2 22pF Figure 7: 24V VDD Mono BTL Typical Application Circuit MP7770 Rev.1.0 12/4/2012 www.MonolithicPower.com MPS Proprietary Information. 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All Rights Reserved. 20 MP7770 –2 X 45W STEREO SE OR 90W MONO BTL CLASS D AUDIO AMPLIFIER COUT1 CF1 CFB1 RIN1 RFB1 CINT1 CR1 CR2 RIN2 CINT2 1 EN BST1 28 2 UVP PGND1 27 3 NC PGND1 26 4 TIMER1 SW1 25 5 IN1 SW1 24 REF1 VDD1 23 7 AGND1 VDD1 22 8 AGND2 VDD2 21 9 REF2 VDD2 20 10 IN2 SW2 11 TIMER2 SW2 19 18 12 NC PGND2 17 13 FAULT PGND2 16 14 OTW BST2 15 6 CBS1 LF1 CBYP1 FB1 CVDDBYP FB2 CBYP2 LF2 CBS2 MP7770 RFB2 CFB2 CF2 AGND PGND AGND COUT2 Top PGND Bottom Figure 8: Stereo SE Reference PCB Layout CFB1 RFB1 CFBX1 CIN2 RIN2 CINT2 28 PGND1 27 3 NC PGND1 26 4 TIMER1 SW1 25 5 IN1 SW1 24 6 REF1 VDD1 23 7 AGND1 VDD1 22 8 AGND2 VDD2 21 9 REF2 VDD2 20 10 IN2 SW2 11 TIMER2 SW2 19 18 12 NC PGND2 17 13 FAULT PGND2 16 14 OTW BST2 15 CFBX2 CBS1 CBYP1 LF1 FB1 CY1 BST1 UVP CX RIN1 EN 2 FB2 LF2 CBYP2 CY2 CINT1 CIN1 1 CBS2 MP7770 CVDDBYP RFB2 CVDDBYP CFB2 AGND PGND Top Bottom Figure 9: Mono BTL Reference PCB Layout MP7770 Rev.1.0 12/4/2012 www.MonolithicPower.com MPS Proprietary Information. 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All Rights Reserved. 21 MP7770 –2 X 45W STEREO SE OR 90W MONO BTL CLASS D AUDIO AMPLIFIER PACKAGE INFORMATION TSSOP28-EP PACKAGE OUTLINE DRAWING FOR 28-TSSOP w/ EXPOSED PADDLE MF-PO-D-0055 revision 2.0 6.00 TYP 9.60 9.80 0.65 BSC 0.40 TYP 28 15 1.60 TYP 4.30 4.50 PIN 1 ID 3.20 TYP 6.20 6.60 14 1 TOP VIEW RECOMMENDED LAND PATTERN 0.80 1.05 1.20 MAX SEATING PLANE 0.19 0.30 0.65 BSC 0.00 0.15 0.09 0.20 SEE DETAIL " " FRONT VIEW SIDE VIEW GAUGE PLANE 0.25 BSC 5.40 5.90 0o-8o 2.60 3.10 BOTTOM VIEW MP7770 Rev.1.0 12/4/2012 5.80 TYP 0.45 0.75 NOTE : 1) ALL DIMENSIONS ARE IN MILLIMETERS. 2) PACKAGE LENGTH DOES NOT INCLUDE MOLD FLASH , PROTRUSION OR GATE BURR. 3) PACKAGE WIDTH DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. 4) LEAD COPLANARITY(BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.10 MILLIMETERS MAX. 5) DRAWING CONFORMS TO JEDEC MO-153, VARIATION AET. 6) DRAWING IS NOT TO SCALE. www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2012 MPS. All Rights Reserved. 22 MP7770 –2 X 45W STEREO SE OR 90W MONO BTL CLASS D AUDIO AMPLIFIER TSSOP28-EPR PACKAGE OUTLINE DRAWING FOR 28-TSSOP w/ REVERSE EXPOSED PADDLE MF-PO-D-0XXX preliminary 9.60 9.80 5.40 5.90 28 0.65 BSC 0.40 TYP 15 2.60 3.10 PIN 1 ID 1 1.60 TYP 4.30 4.50 5.80 TYP 6.20 6.60 14 TOP VIEW RECOMMENDED LAND PATTERN 0.80 1.05 1.20 MAX SEATING PLANE 0.19 0.30 0.65 BSC 0.00 0.15 0.09 0.20 SEE DETAIL " " FRONT VIEW SIDE VIEW GAUGE PLANE 0.25 BSC 0o-8o 0.45 0.75 NOTE : BOTTOM VIEW 1) ALL DIMENSIONS ARE IN MILLIMETERS. 2) PACKAGE LENGTH DOES NOT INCLUDE MOLD FLASH , PROTRUSION OR GATE BURR. 3) PACKAGE WIDTH DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. 4) LEAD COPLANARITY(BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.10 MILLIMETERS MAX. 5) JEDEC REFERENCE IS MO-153. 6) DRAWING IS NOT TO SCALE. NOTICE: The information in this document is subject to change without notice. Please contact MPS for current specifications. Users should warrant and guarantee that third party Intellectual Property rights are not infringed upon when integrating MPS products into any application. MPS will not assume any legal responsibility for any said applications. MP7770 Rev. 1.0 12/4/2012 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2012 MPS. All Rights Reserved. 23