HUF76013P3, HUF76013D3S
TM
Data Sheet
April 2000
File Number
4849
20A, 20V, 0.022 Ohm, N-Channel, Logic
Level Power MOSFETs
The HUF76013 is an application-specific MOSFET
optimized for switching when used as the upper switch in
synchronous buck applications. The low gate charge and low
input capacitance results in lower driver and lower switching
losses thereby increasing the overall system efficiency.
Symbol
D
Features
• 20A, 20V
- rDS(ON) = 0.022Ω, VGS = 10V
- rDS(ON) = 0.030Ω, VGS = 5V
• PWM Optimized for Synchronous Buck Applications
• Fast Switching
• Low Gate Charge
- Qg Total 14nC (Typ)
G
S
Packaging
HUF76013D3S
JEDEC TO-252AA
HUF76013P3
JEDEC TO-220AB
SOURCE
DRAIN
GATE
DRAIN (FLANGE)
GATE
SOURCE
DRAIN
(FLANGE)
Absolute Maximum Ratings
• Low Capacitance
- CISS 624pF (Typ)
- CRSS 71pF (Typ)
Ordering Information
PART NUMBER
PACKAGE
BRAND
HUF76013P3
TO-220AB
76013P
HUF76013D3S
TO-252AA
76013D
NOTE: When ordering, use the entire part number. Add the suffix T to
obtain the HUF76013D3S in tape and reel, e.g., HUF76013D3ST.
TC = 25oC, Unless Otherwise Specified
SYMBOL
PARAMETER
HUF76013P3,
HUF76013D3S
UNITS
VDSS
Drain to Source Voltage (Note 1)
20
V
VDGR
Drain to Gate Voltage (RGS = 20kΩ) (Note 1)
20
V
Gate to Source Voltage
±16
V
20
20
Figure 4
A
A
A
50
0.4
W
W/oC
-55 to 150
oC
300
260
oC
oC
VGS
ID
ID
IDM
PD
TJ, TSTG
TL
Tpkg
Drain Current
Continuous (TC = 25oC, VGS = 10V) (Figure 2)
Continuous (TC = 100oC, VGS = 5V)
Pulsed Drain Current
Power Dissipation
Derate Above 25oC
Operating and Storage Temperature
Maximum Temperature for Soldering
Leads at 0.063in (1.6mm) from Case for 10s
Package Body for 10s, See Techbrief TB334
THERMAL SPECIFICATIONS
RθJC
Thermal Resistance Junction to Case, TO-220, TO-252
2.5
oC/W
RθJA
Thermal Resistance Junction to Ambient TO-220
62
oC/W
Thermal Resistance Junction to Ambient TO-252
100
oC/W
NOTE:
1. TJ = 25oC to 125oC.
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil and Design is a trademark of Intersil Corporation. | Copyright © Intersil Corporation 2000
UltraFET® is a registered trademark of Intersil Corporation.
HUF76013P3, HUF76013D3S
TC = 25oC, Unless Otherwise Specified
Electrical Specifications
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
OFF STATE SPECIFICATIONS
Drain to Source Breakdown Voltage
Zero Gate Voltage Drain Current
BVDSS
IDSS
Gate to Source Leakage Current
IGSS
ID = 250µA, VGS = 0V (Figure 11)
VDS = 20V, VGS = 0V
20
-
-
V
-
-
1
µA
VDS = 20V, VGS = 0V, TC = 150oC
-
-
250
µA
VGS = ±16V
-
-
±100
nA
ON STATE SPECIFICATIONS
Gate to Source Threshold Voltage
VGS(TH)
VGS = VDS, ID = 250µA (Figure 10)
1
-
3
V
Drain to Source ON Resistance
rDS(ON)
ID = 20A, VGS = 10V (Figures 8, 9)
-
0.018
0.022
W
ID = 20A, VGS = 5V (Figure 8)
-
0.025
0.030
W
VDD = 10V, ID = 20A
VGS = 5V, RGS = 19Ω
(Figures 14, 18, 19)
-
-
197
ns
-
11
-
ns
SWITCHING SPECIFICATIONS (VGS = 5V)
Turn-On Time
tON
Turn-On Delay Time
td(ON)
Rise Time
Turn-Off Delay Time
Fall Time
Turn-Off Time
tr
-
120
-
ns
td(OFF)
-
19
-
ns
tf
-
30
-
ns
tOFF
-
-
72
ns
-
-
151
ns
-
7
-
ns
-
93
-
ns
td(OFF)
-
37
-
ns
tf
-
29
-
ns
tOFF
-
-
100
ns
-
14.4
17
nC
-
7.8
9
nC
SWITCHING SPECIFICATIONS (VGS = 10V)
Turn-On Time
tON
Turn-On Delay Time
td(ON)
Rise Time
tr
Turn-Off Delay Time
Fall Time
Turn-Off Time
VDD = 10V, ID = 20A
VGS = 10V,
RGS = 19Ω
(Figures 15, 18, 19)
GATE CHARGE SPECIFICATIONS
Total Gate Charge at 10V
Qg(TOT)
VGS = 0V to 10V
Total Gate Charge at 5V
Qg(TOT)
VGS = 0V to 5V
Threshold Gate Charge
Qg(TH)
VGS = 0V to 1V
VDD = 10V,
ID = 20A,
Ig(REF) = 1.0mA
(Figures 13, 16, 17)
-
0.9
1
nC
Gate to Source Gate Charge
Qgs
-
3.5
-
nC
Gate to Drain “Miller” Charge
Qgd
-
3.2
-
nC
-
624
-
pF
-
444
-
pF
-
71
-
pF
MIN
TYP
MAX
UNITS
ISD = 20A
-
-
1.25
V
ISD = 10A
-
-
1.0
V
trr
ISD = 20A, dISD/dt = 100A/µs
-
-
55
ns
QRR
ISD = 20A, dISD/dt = 100A/µs
-
-
82
nC
CAPACITANCE SPECIFICATIONS
Input Capacitance
CISS
Output Capacitance
COSS
Reverse Transfer Capacitance
CRSS
VDS = 20V, VGS = 0V,
f = 1MHz
(Figure 12)
Source to Drain Diode Specifications
PARAMETER
SYMBOL
Source to Drain Diode Voltage
VSD
Reverse Recovery Time
Reverse Recovered Charge
2
TEST CONDITIONS
HUF76013P3, HUF76013D3S
Typical Performance Curves
POWER DISSIPATION MULTIPLIER
1.2
25
ID, DRAIN CURRENT (A)
1.0
0.8
0.6
0.4
VGS = 10V
20
VGS = 5.0V
15
10
5
0.2
0
0
0
25
50
75
100
125
150
25
TA , AMBIENT TEMPERATURE (oC)
50
75
100
125
150
TC, CASE TEMPERATURE (oC)
FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE
TEMPERATURE
FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs
CASE TEMPERATURE
2
ZθJC, NORMALIZED
THERMAL IMPEDANCE
1
DUTY CYCLE - DESCENDING ORDER
0.5
0.2
0.1
0.05
0.02
0.01
PDM
0.1
t1
t2
NOTES:
DUTY FACTOR: D = t1/t2
PEAK TJ = PDM x ZθJC x RθJC + TC
SINGLE PULSE
0.01
10-5
10-4
10-3
10-2
10-1
100
101
t, RECTANGULAR PULSE DURATION (s)
FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
IDM, PEAK CURRENT (A)
1000
TC = 25oC
FOR TEMPERATURES
ABOVE 25oC DERATE PEAK
CURRENT AS FOLLOWS:
100
150 - TC
125
I = I25
VGS = 10V
VGS = 5V
TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION
10
10-5
10-4
10-3
10-2
t, PULSE WIDTH (s)
FIGURE 4. PEAK CURRENT CAPABILITY
3
10-1
100
101
HUF76013P3, HUF76013D3S
Typical Performance Curves
(Continued)
40
100
ID , DRAIN CURRENT (A)
ID, DRAIN CURRENT (A)
300
100µs
10
OPERATION IN THIS
AREA MAY BE
LIMITED BY rDS(ON)
1ms
1
30
20
TJ = 150oC
10
TJ = 25oC
10ms
SINGLE PULSE
TJ = MAX RATED TC = 25oC
1
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
VDD = 15V
0
10
2
50
3
VDS , DRAIN TO SOURCE VOLTAGE (V)
rDS(ON) , DRAIN TO SOURCE
ON RESISTANCE (mΩ)
ID, DRAIN CURRENT (A)
50
30
VGS = 5V
5
FIGURE 6. TRANSFER CHARACTERISTICS
TC = 25oC
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
VGS = 10V
4
VGS , GATE TO SOURCE VOLTAGE (V)
FIGURE 5. FORWARD BIAS SAFE OPERATING AREA
40
TJ = -55oC
VGS = 4V
20
VGS = 3.5V
10
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
TC = 25oC
ID = 20A
40
ID = 5A
ID = 10A
30
20
VGS = 3V
0
10
0
1
2
3
4
2
VDS , DRAIN TO SOURCE VOLTAGE (V)
FIGURE 7. SATURATION CHARACTERISTICS
6
8
10
FIGURE 8. DRAIN TO SOURCE ON RESISTANCE vs GATE
VOLTAGE AND DRAIN CURRENT
1.6
1.2
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
VGS = VDS, ID = 250µA
1.4
NORMALIZED GATE
THRESHOLD VOLTAGE
NORMALIZED DRAIN TO SOURCE
ON RESISTANCE
4
VGS , GATE TO SOURCE VOLTAGE (V)
1.2
1.0
0.8
1.0
0.8
VGS = 10V, ID = 20A
0.6
-80
-40
0
40
80
120
TJ, JUNCTION TEMPERATURE (oC)
FIGURE 9. NORMALIZED DRAIN TO SOURCE ON
RESISTANCE vs JUNCTION TEMPERATURE
4
160
0.6
-80
-40
0
40
80
120
160
TJ, JUNCTION TEMPERATURE (oC)
FIGURE 10. NORMALIZED GATE THRESHOLD VOLTAGE vs
JUNCTION TEMPERATURE
HUF76013P3, HUF76013D3S
Typical Performance Curves
(Continued)
1.2
2500
NORMALIZED DRAIN TO SOURCE
BREAKDOWN VOLTAGE
ID = 250µA
C, CAPACITANCE (pF)
1.1
1.0
0.9
COSS ≅ CDS + CGD
1000
CISS = CGS + CGD
CRSS = CGD
100
0.8
-80
VGS = 0V, f = 1MHz
-40
0
40
80
120
50
0.1
160
1
TJ , JUNCTION TEMPERATURE (oC)
10
20
VDS , DRAIN TO SOURCE VOLTAGE (V)
FIGURE 11. NORMALIZED DRAIN TO SOURCE BREAKDOWN
VOLTAGE vs JUNCTION TEMPERATURE
FIGURE 12. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
VDD = 10V
180
VGS = 5V, VDD = 10V, ID = 20A
8
150
SWITCHING TIME (ns)
VGS , GATE TO SOURCE VOLTAGE (V)
10
6
4
WAVEFORMS IN
DESCENDING ORDER:
ID = 20A
ID = 10A
ID = 5A
2
0
tr
120
90
tf
60
td(OFF)
30
td(ON)
0
3
6
9
0
15
12
0
Qg, GATE CHARGE (nC)
10
20
FIGURE 13. GATE CHARGE WAVEFORMS FOR CONSTANT
GATE CURRENT
FIGURE 14. SWITCHING TIME vs GATE RESISTANCE
120
VGS = 10V, VDD = 10V, ID = 20A
tr
SWITCHING TIME (ns)
100
80
td(OFF)
60
40
tf
20
td(ON)
0
10
20
30
40
RGS, GATE TO SOURCE RESISTANCE (Ω)
FIGURE 15. SWITCHING TIME vs GATE RESISTANCE
5
40
RGS , GATE TO SOURCE RESISTANCE (Ω)
NOTE: Refer to Intersil Application Notes AN7254 and AN7260.
0
30
50
50
HUF76013P3, HUF76013D3S
Test Circuits and Waveforms
VDS
VDD
RL
Qg(TOT)
VDS
VGS = 10V
VGS
Qg(TOT)
+
-
VDD
VGS = 5V
VGS
DUT
VGS = 1V
Ig(REF)
0
Qg(TH)
Qgs
Qgd
Ig(REF)
0
FIGURE 16. GATE CHARGE TEST CIRCUIT
FIGURE 17. GATE CHARGE WAVEFORMS
VDS
tON
tOFF
td(ON)
td(OFF)
tf
tr
RL
VDS
90%
90%
+
VGS
-
VDD
10%
10%
0
DUT
90%
RGS
VGS
VGS
0
FIGURE 18. SWITCHING TIME TEST CIRCUIT
6
10%
50%
50%
PULSE WIDTH
FIGURE 19. SWITCHING TIME WAVEFORM
HUF76013P3, HUF76013D3S
PSPICE Electrical Model
.SUBCKT HUF76013P3 2 1 3 ;
rev 23March 2000
CA 12 8 6.5e-10
CB 15 14 7.0e-10
CIN 6 8 5.6e-10
DBODY 7 5 DBODYMOD
DBREAK 5 11 DBREAKMOD
DPLCAP 10 5 DPLCAPMOD
LDRAIN
DPLCAP
DRAIN
2
5
10
5
51
ESLC
11
-
RDRAIN
6
8
EVTHRES
+ 19 8
+
LGATE
GATE
1
EVTEMP
RGATE +
18 22
9
20
21
DBODY
-
16
MWEAK
6
MMED
MSTRO
RLGATE
MMED 16 6 8 8 MMEDMOD
MSTRO 16 6 8 8 MSTROMOD
MWEAK 16 21 8 8 MWEAKMOD
+
17
EBREAK 18
50
-
IT 8 17 1
LSOURCE
CIN
8
SOURCE
3
7
RSOURCE
RBREAK 17 18 RBREAKMOD 1
RDRAIN 50 16 RDRAINMOD 1e-3
RGATE 9 20 3.0
RLDRAIN 2 5 10
RLGATE 1 9 49
RLSOURCE 3 7 49
RSLC1 5 51 RSLCMOD 1e-6
RSLC2 5 50 1e3
RSOURCE 8 7 RSOURCEMOD 12.5e-3
RVTHRES 22 8 RVTHRESMOD 1
RVTEMP 18 19 RVTEMPMOD 1
S1A
S1B
S2A
S2B
DBREAK
+
RSLC2
ESG
LDRAIN 2 5 1.00e-9
LGATE 1 9 4.9e-9
LSOURCE 3 7 4.9e-9
RLDRAIN
RSLC1
51
EBREAK 11 7 17 18 26
EDS 14 8 5 8 1
EGS 13 8 6 8 1
ESG 6 10 6 8 1
EVTHRES 6 21 19 8 1
EVTEMP 20 6 18 22 1
RLSOURCE
S2A
S1A
12
S1B
CA
17
18
RVTEMP
S2B
13
CB
6
8
EGS
19
VBAT
5
8
EDS
-
-
IT
14
+
+
6 12 13 8 S1AMOD
13 12 13 8 S1BMOD
6 15 14 13 S2AMOD
13 15 14 13 S2BMOD
RBREAK
15
14
13
13
8
-
+
8
22
RVTHRES
VBAT 22 19 DC 1
ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*175),2.5))}
.MODEL DBODYMOD D (IS = 5.4e-13 RS = 1.15e-2 TRS1 = 7.0e-5 TRS2 = -1.0e-6 CJO = 12.3e-10 TT = 2.93e-8 M = 0.40)
.MODEL DBREAKMOD D (RS = 3.50e-1 TRS1 = 1e-3 TRS2 = -6.5e-6)
.MODEL DPLCAPMOD D (CJO = 4.6e-10 IS = 1e-30 N = 10 M = 0.6)
.MODEL MMEDMOD NMOS (VTO = 2.2 KP = 2.0 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 3.0)
.MODEL MSTROMOD NMOS (VTO = 2.66 KP = 40 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u LAMBDA=.01)
.MODEL MWEAKMOD NMOS (VTO = 1.90 KP = 0.03 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 30 RS = 0.1)
.MODEL RBREAKMOD RES (TC1 = 1.0e-3 TC2 = -1.0e-6)
.MODEL RDRAINMOD RES (TC1 = 2.1e-2 TC2 = 6.5e-5)
.MODEL RSLCMOD RES (TC1 = 3.5e-3 TC2 = 2e-6)
.MODEL RSOURCEMOD RES (TC1 = 1e-3 TC2 = 1e-6)
.MODEL RVTHRESMOD RES (TC1 = -1.9e-3 TC2 = -6.0e-6)
.MODEL RVTEMPMOD RES (TC1 = -1.8e-3 TC2 = 0)
.MODEL S1AMOD VSWITCH (RON = 1e-5
.MODEL S1BMOD VSWITCH (RON = 1e-5
.MODEL S2AMOD VSWITCH (RON = 1e-5
.MODEL S2BMOD VSWITCH (RON = 1e-5
ROFF = 0.1
ROFF = 0.1
ROFF = 0.1
ROFF = 0.1
VON = -4.5 VOFF= -1.5)
VON = -1.5 VOFF= -4.5)
VON = -0.5 VOFF= 0)
VON = 0 VOFF= -0.5)
.ENDS
NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global
Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley.
7
HUF76013P3, HUF76013D3S
SABER Electrical Model
REV 23March2000
template huf76013p3 n2,n1,n3
electrical n2,n1,n3
{
var i iscl
dp..model dbodymod = (isl = 5.4e-13, rs = 1.15e-2, trs1 = 7.0e-5, trs2 = -1e-6, cjo = 12.3e-10, tt = 2.93e-8, m = 0.40)
dp..model dbreakmod = (rs = 3.50e-1, trs1 = 1e-3, trs2 = -6.5e-6)
dp..model dplcapmod = (cjo = 4.60e-10, isl = 10e-30,nl=10, m = 0.6)
m..model mmedmod = (type=_n, vto = 2.2, kp = 2.0, is = 1e-30, tox = 1)
m..model mstrongmod = (type=_n, vto = 2.66, kp = 40, lamda=0.01, is = 1e-30, tox = 1)
m..model mweakmod = (type=_n, vto = 1.90, kp = 0.03, is = 1e-30, tox = 1, rs=0.1)
sw_vcsp..model s1amod = (ron = 1e-5, roff = 0.1, von = -4.5, voff = -1.5)
DPLCAP 5
sw_vcsp..model s1bmod = (ron =1e-5, roff = 0.1, von = -1.5, voff = -4.5)
sw_vcsp..model s2amod = (ron = 1e-5, roff = 0.1, von = -0.5, voff = 0)
10
sw_vcsp..model s2bmod = (ron = 1e-5, roff = 0.1, von = 0, voff = -0.5)
LDRAIN
DRAIN
2
RLDRAIN
RSLC1
51
c.ca n12 n8 = 6.50e-10
c.cb n15 n14 = 7.0e-10
c.cin n6 n8 = 5.60e-10
RSLC2
ISCL
dp.dbody n7 n5 = model=dbodymod
dp.dbreak n5 n11 = model=dbreakmod
dp.dplcap n10 n5 = model=dplcapmod
RDRAIN
6
8
ESG
EVTHRES
+ 19 8
+
i.it n8 n17 = 1
LGATE
GATE
1
l.ldrain n2 n5 = 1.00e-9
l.lgate n1 n9 = 4.9e-9
l.lsource n3 n7 = 4.9e-9
EVTEMP
RGATE + 18 22
9
20
21
11
DBODY
16
MWEAK
6
EBREAK
+
17
18
MMED
MSTRO
RLGATE
CIN
m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u
m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u
m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u
res.rbreak n17 n18 = 1, tc1 = 1.0e-3, tc2 = -1.00e-6
res.rdrain n50 n16 = 1e-3, tc1 = 2.1e-2, tc2 = 6.5e-5
res.rgate n9 n20 = 3.0
res.rldrain n2 n5 = 10
res.rlgate n1 n9 = 49
res.rlsource n3 n7 = 49
res.rslc1 n5 n51= 1e-6, tc1 = 3.5e-3, tc2 = 2.0e-6
res.rslc2 n5 n50 = 1e3
res.rsource n8 n7 = 12.5e-3, tc1 = 1.0e-3, tc2 =1e-6
res.rvtemp n18 n19 = 1, tc1 = -1.8e-3, tc2 = 0
res.rvthres n22 n8 = 1, tc1 = -1.9e-3, tc2 = -6.00e-6
DBREAK
50
-
-
8
LSOURCE
7
RSOURCE
RLSOURCE
S1A
12
S2A
13
8
S1B
CA
RBREAK
15
14
13
17
18
RVTEMP
S2B
13
CB
6
8
EGS
19
-
-
IT
14
+
+
VBAT
5
8
EDS
-
+
8
22
RVTHRES
spe.ebreak n11 n7 n17 n18 = 26
spe.eds n14 n8 n5 n8 = 1
spe.egs n13 n8 n6 n8 = 1
spe.esg n6 n10 n6 n8 = 1
spe.evtemp n20 n6 n18 n22 = 1
spe.evthres n6 n21 n19 n8 = 1
sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod
sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod
sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod
sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod
v.vbat n22 n19 = dc=1
equations {
i (n51->n50) +=iscl
iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/175))** 2.5))
}
}
8
SOURCE
3
HUF76013P3, HUF76013D3S
SPICE Thermal Model
th
REV 23March 2000
JUNCTION
HUF76013T
CTHERM1 th 6 1.0e-3
CTHERM2 6 5 2.80e-3
CTHERM3 5 4 3.00e-3
CTHERM4 4 3 3.40e-3
CTHERM5 3 2 6.40e-3
CTHERM6 2 tl 9.50e-2
RTHERM1
CTHERM1
6
RTHERM1 th 6 1.85e-2
RTHERM2 6 5 4.61e-2
RTHERM3 5 4 1.30e-1
RTHERM4 4 3 7.29e-1
RTHERM5 3 2 1.10
RTHERM6 2 tl 1.46e-1
RTHERM2
CTHERM2
5
SABER Thermal Model
RTHERM3
CTHERM3
SABER thermal model HUF76013T
template thermal_model th tl
thermal_c th, tl
{
ctherm.ctherm1 th 6 = 1.0e-3
ctherm.ctherm2 6 5 = 2.80e-3
ctherm.ctherm3 5 4 = 3.00e-3
ctherm.ctherm4 4 3 = 3.40e-3
ctherm.ctherm5 3 2 = 6.40e-3
ctherm.ctherm6 2 tl = 9.50e-2
4
RTHERM4
CTHERM4
3
rtherm.rtherm1 th 6 =1.85e-2
rtherm.rtherm2 6 5 = 4.61e-2
rtherm.rtherm3 5 4 = 1.30e-1
rtherm.rtherm4 4 3 = 7.29e-1
rtherm.rtherm5 3 2 = 1.10
rtherm.rtherm6 2 tl = 1.46e-1
}
RTHERM5
CTHERM5
2
RTHERM6
CTHERM6
tl
9
CASE
HUF76013P3, HUF76013D3S
TO-252AA
SURFACE MOUNT JEDEC TO-252AA PLASTIC PACKAGE
E
H1
A
b2
SYMBOL
A
A1
b
b1
b2
b3
c
D
E
e
e1
H1
J1
L
L1
A1
SEATING
PLANE
D
L2
1
L
3
b1
b
L1
e
c
e1
J1
0.265
(6.7)
TERM. 4
b3
L3
L2
L3
0.265 (6.7)
0.070 (1.8)
0.118 (3.0)
BACK VIEW
0.063 (1.6) TYP
0.090 (2.3) TYP
MINIMUM PAD SIZE RECOMMENDED FOR
SURFACE-MOUNTED APPLICATIONS
1.5mm
DIA. HOLE
INCHES
MIN
MAX
0.086
0.094
0.018
0.022
0.028
0.032
0.033
0.045
0.205
0.215
0.190
0.018
0.022
0.270
0.295
0.250
0.265
0.090 TYP
0.180 BSC
0.035
0.045
0.040
0.045
0.100
0.115
MILLIMETERS
MIN
MAX
2.19
2.38
0.46
0.55
0.72
0.81
0.84
1.14
5.21
5.46
4.83
0.46
0.55
6.86
7.49
6.35
6.73
2.28 TYP
4.57 BSC
0.89
1.14
1.02
1.14
2.54
2.92
0.020
0.025
0.170
0.51
0.64
4.32
0.040
-
NOTES
4, 5
4, 5
4
4, 5
2
4, 5
7
7
-
1.01
-
4, 6
3
2
NOTES:
1. These dimensions are within allowable dimensions of Rev. B of
JEDEC TO-252AA outline dated 9-88.
2. L3 and b3 dimensions establish a minimum mounting surface for
terminal 4.
3. Solder finish uncontrolled in this area.
4. Dimension (without solder).
5. Add typically 0.002 inches (0.05mm) for solder plating.
6. L1 is the terminal length for soldering.
7. Position of lead to be measured 0.090 inches (2.28mm) from bottom
of dimension D.
8. Controlling dimension: Inch.
9. Revision 11 dated 1-00.
4.0mm
USER DIRECTION OF FEED
2.0mm
TO-252AA
1.75mm
C
L
16mm TAPE AND REEL
16mm
8.0mm
22.4mm
COVER TAPE
13mm
330mm
50mm
GENERAL INFORMATION
1. 2500 PIECES PER REEL.
2. ORDER IN MULTIPLES OF FULL REELS ONLY.
3. MEETS EIA-481 REVISION "A" SPECIFICATIONS.
10
16.4mm
HUF76013P3, HUF76013D3S
TO-220AB
3 LEAD JEDEC TO-220AB PLASTIC PACKAGE
A
INCHES
E
ØP
A1
Q
H1
TERM. 4
D
45o
E1
D1
L1
b1
L
b
c
MIN
MAX
MIN
MAX
NOTES
A
0.170
0.180
4.32
4.57
-
A1
0.048
0.052
1.22
1.32
-
b
0.030
0.034
0.77
0.86
3, 4
b1
0.045
0.055
1.15
1.39
2, 3
c
0.014
0.019
0.36
0.48
2, 3, 4
D
0.590
0.610
14.99
15.49
-
4.06
-
10.41
-
D1
-
0.160
E
0.395
0.410
E1
-
0.030
e
60o
1
2
e1
3
e
J1
e1
MILLIMETERS
SYMBOL
H1
0.100 TYP
0.200 BSC
0.235
0.255
10.04
-
0.76
-
2.54 TYP
5
5.08 BSC
5
5.97
6.47
-
J1
0.100
0.110
2.54
2.79
6
L
0.530
0.550
13.47
13.97
-
L1
0.130
0.150
3.31
3.81
2
ØP
0.149
0.153
3.79
3.88
-
Q
0.102
0.112
2.60
2.84
-
NOTES:
1. These dimensions are within allowable dimensions of Rev. J of
JEDEC TO-220AB outline dated 3-24-87.
2. Lead dimension and finish uncontrolled in L1.
3. Lead dimension (without solder).
4. Add typically 0.002 inches (0.05mm) for solder coating.
5. Position of lead to be measured 0.250 inches (6.35mm) from bottom of dimension D.
6. Position of lead to be measured 0.100 inches (2.54mm) from bottom of dimension D.
7. Controlling dimension: Inch.
8. Revision 2 dated 7-97.
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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Intersil Corporation
P. O. Box 883, Mail Stop 53-204
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TEL: (321) 724-7000
FAX: (321) 724-7240
11
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