AD AD S83 S8 17 317 ADS8317 www.ti.com .................................................................................................................................................... SBAS356D – JUNE 2007 – REVISED OCTOBER 2009 16-Bit, High-Speed, 2.7V to 5.5V microPower Sampling ANALOG-TO-DIGITAL CONVERTER Check for Samples: ADS8317 FEATURES DESCRIPTION • The ADS8317 is a 16-bit, sampling, analog-to-digital (A/D) converter specified for a supply voltage range from 2.7V to 5.5V. It requires very little power, even when operating at the full data rate. At lower data rates, the high speed of the device enables it to spend most of its time in the power-down mode. For example, the average power dissipation is less than 0.2mW at a 10kHz data rate. 1 23 • • • • • • 16 Bits No Missing Codes (Full-Supply Range, High or Low Grade) Very Low Noise: 5LSBPP Excellent Linearity: ±0.8LSB typ, ±1.5LSB max INL +0.7LSB typ, +1.25LSB max DNL ±1mV max Offset ±16LSB typ Gain Error microPower: 10mW at 5V, 250kHz 4mW at 2.7V, 200kHz 2mW at 2.7V, 100kHz 0.2mW at 2.7V, 10kHz Packages: MSOP-8, SON-8 Pin-Compatible with the ADS8321 Serial ( SPI™/SSI) Interface The ADS8317 offers excellent linearity and very low noise and distortion. It also features a synchronous serial (SPI/SSI-compatible) interface and a differential input. The reference voltage can be set to any level within the range of 0.1V to VDD/2. Low power and small size make the ADS8317 ideal for portable and battery-operated systems. It is also an excellent fit for remote data-acquisition modules, simultaneous multichannel systems, and isolated data acquisition. The ADS8317 is available in MSOP-8 and SON-8 packages. The SON package size is the same as a 3x3 QFN package. APPLICATIONS • • • • • • • Battery-Operated Systems Remote Data Acquisition Isolated Data Acquisition Simultaneous Sampling, Multichannel Systems Industrial Controls Robotics Vibration Analysis SAR REF ADS8317 DOUT +IN Serial Interface CDAC −IN DCLOCK S/H Amp Comparator CS/SHDN 1 2 3 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. SPI is a trademark of Motorola, Inc. All other trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2007–2009, Texas Instruments Incorporated ADS8317 SBAS356D – JUNE 2007 – REVISED OCTOBER 2009 .................................................................................................................................................... www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ORDERING INFORMATION (1) PRODUCT MAXIMUM INTEGRAL LINEARITY ERROR (LSB) (2) NO MISSING CODES ERROR (LSB) PACKAGELEAD PACKAGE DESIGNATOR SPECIFIED TEMPERATURE RANGE PACKAGE MARKING ADS8317I ±2 16 MSOP-8 DGK –40°C to +85°C D17 ADS8317IB ±1.5 16 MSOP-8 DGK –40°C to +85°C D17 ADS8317I ±2 16 SON-8 DRB –40°C to +85°C D17 ADS8317IB ±1.5 16 SON-8 DRB –40°C to +85°C D17 (1) (2) ORDERING NUMBER TRANSPORT MEDIA, QUANTITY ADS8317IDGKT Tape and Reel, 250 ADS8317IDGKR Tape and Reel, 2500 ADS8317IBDGKT Tape and Reel, 250 ADS8317IBDGKR Tape and Reel, 2500 ADS8317IDRBT Tape and Reel, 250 ADS8317IDRBR Tape and Reel, 2500 ADS8317IBDRBT Tape and Reel, 250 ADS8317IBDRBR Tape and Reel, 2500 For the most current package and ordering information, see the Package Option Addendum located at the end of this data sheet, or see the TI website at www.ti.com. Maximum Integral Linearity Error specifies a 5V power supply and 2.5V reference voltage. ABSOLUTE MAXIMUM RATINGS (1) Over operating free-air temperature range (unless otherwise noted). ADS8317 UNIT –0.3 to +7 V –0.3 to VDD + 0.3 V –0.3 to VDD + 0.3 V Supply voltage, VDD to GND Analog input voltage (2) Reference input voltage (2) Digital input voltage (2) –0.3 to VDD + 0.3 V –20 to +20 mA Input current to any pin except supply Power dissipation See Dissipation Ratings Table Operating virtual junction temperature range, TJ –40 to +150 °C Operating free-air temperature range, TA –40 to +85 °C Storage temperature range, TSTG –65 to +150 °C (1) (2) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum rated conditions for extended periods may affect device reliability. All voltage values are with respect to ground terminal. DISSIPATION RATINGS 2 PACKAGE R θ JC R θ JA DERATING FACTOR ABOVE TA = +25°C DGK +39.1°C/W +206.3°C/W 4.847mW/°C 606mW 388mW 315mW DRB +5°C/W +45.8°C/W 3.7mW/°C 370mW 204mW 148mW TA ≤ +25°C POWER RATING TA = +70°C POWER RATING TA = +85°C POWER RATING Submit Documentation Feedback Copyright © 2007–2009, Texas Instruments Incorporated Product Folder Link(s): ADS8317 ADS8317 www.ti.com .................................................................................................................................................... SBAS356D – JUNE 2007 – REVISED OCTOBER 2009 RECOMMENDED OPERATING CONDITIONS MIN Supply voltage, GND to VDD MAX UNIT 3.6 V 5.5 V 1 VDD/2 V –IN to GND –0.2 VDD + 0.2 V +IN to GND –0.2 VDD + 0.2 V +IN – (–IN) –VREF +VREF V –40 +125 °C Low-voltage levels 2.7 5V logic levels 4.5 Reference input voltage Analog input voltage Operating junction temperature, TJ TYP 5.0 ELECTRICAL CHARACTERISTICS: VDD = +5V At –40°C to +85°C, VREF = +2.5V, –IN = +2.5V, fSAMPLE = 250kHz, and fCLK = 24 × fSAMPLE, unless otherwise noted. ADS8317I PARAMETER TEST CONDITIONS MIN TYP ADS8317IB MAX MIN VREF –VREF VDD + 0.1 –0.1 TYP MAX UNIT VREF V ANALOG INPUT Full-scale range FSR +IN – (–IN) Absolute input range Input resistance –VREF +IN RON Input capacitance –0.1 Hold 5 V 100 50 GΩ Ω Sampling 50 During sampling 24 24 pF nA Input leakage current 100 ±50 ±50 +IN to –IN, during sampling 20 20 pF FSBW fS sinewave, SINAD = 60dB 500 500 kHz Differential input capacitance Full-power bandwidth VDD + 0.1 5 DC ACCURACY Resolution No missing codes Integral linearity error 16 NMC 16 16 16 ±1.5 +2 Bits 16 16 Bits –1.5 ±0.8 +1.5 LSB LSB INL –2 Differential linearity error DNL –1 ±1 +2 –1 +0.7,–0.5 +1.25 Offset error VOS –2 ±0.75 +2 –1 ±0.5 +1 Offset error drift Gain error Gain error drift TCVOS GERR ±3 Positive –32 ±16 +32 –32 ±16 +32 Negative –32 ±16 +32 –32 ±16 +32 TCGERR ±0.1 Bipolar zero error –2 ±0.75 mV μV/°C ±3 ±0.1 +2 –1 ±0.5 LSB LSB ppm/°C +1 mV Bipolar zero error drift ±3 ±3 μV/°C Noise 50 50 μVRMS 1 1 LSB Power-supply rejection PSRR 4.75V ≤ VDD ≤ 5.25V SAMPLING DYNAMICS Conversion time (16 DCLOCKs) Acquisition time (4.5 DCLOCKs) tCONV 24kHz ≤ fCLK ≤ 6.0MHz tAQ fCLK = 6.0MHz 2.667 0.75 Throughput rate (22 DCLOCKs) Clock frequency 666.7 2.667 6.0 0.024 250 kSPS 6.0 MHz Submit Documentation Feedback Copyright © 2007–2009, Texas Instruments Incorporated Product Folder Link(s): ADS8317 μs μs 0.75 250 0.024 666.7 3 ADS8317 SBAS356D – JUNE 2007 – REVISED OCTOBER 2009 .................................................................................................................................................... www.ti.com ELECTRICAL CHARACTERISTICS: VDD = +5V (continued) At –40°C to +85°C, VREF = +2.5V, –IN = +2.5V, fSAMPLE = 250kHz, and fCLK = 24 × fSAMPLE, unless otherwise noted. ADS8317I PARAMETER TEST CONDITIONS MIN TYP ADS8317IB MAX MIN TYP MAX UNIT AC ACCURACY Total harmonic distortion Spurious-free dynamic range Signal-to-noise ratio Signal-to-noise + distortion Effective number of bits THD SFDR SNR SINAD ENOB 5VPP sinewave at 2kHz –102 –106 dB 5VPP sinewave at 10kHz –100 –104 dB 5VPP sinewave at 2kHz 106 110 dB 5VPP sinewave at 10kHz 104 109 dB 5VPP sinewave at 2kHz 89.6 90 dB 5VPP sinewave at 10kHz 89.6 90 dB 5VPP sinewave at 2kHz 89.5 89.9 dB 5VPP sinewave at 10kHz 89.4 89.8 dB 5VPP sinewave at 2kHz 14.57 14.65 Bits 5VPP sinewave at 10kHz 14.56 14.63 Bits VOLTAGE REFERENCE INPUT Reference voltage 0.5 CS = GND, fSAMPLE = 0Hz Reference input resistance CS = VDD Reference input capacitance Reference input current VDD/2 0.5 5 VDD/2 V 5 GΩ 5 5 GΩ 24 24 pF fS = 250kHz 35 52 35 52 μA fS = 200kHz 25 38 25 38 μA fS = 100kHz 10 15 10 15 μA fS = 10kHz 1 2 1 2 μA CS = VDD 0.1 μA 0.1 DIGITAL INPUTS (1) Logic family CMOS CMOS High-level input voltage VIH 0.7 × VDD VDD + 0.3 0.7 × VDD VDD + 0.3 Low-level input voltage VIL –0.3 0.3 × VDD –0.3 0.3 × VDD V Input current IIN VI = VDD or GND –50 +50 –50 +50 nA Input capacitance CI 5 5 V pF DIGITAL OUTPUTS (1) Logic family CMOS High-level output voltage VOH VDD = 4.5V, IOH = –100μA Low-level output voltage VOL VDD = 4.5V, IOL = 100μA High-impedance state output current IOZ CS = VDD, VI = VDD or GND Output capacitance CO Load capacitance CL Data format (1) 4 CMOS 4.44 4.44 V 0.5 –50 +50 5 –50 0.5 V +50 nA 5 30 Binary twos complement pF 30 pF Binary twos complement Applies for 5.0V nominal supply: VDD (min) = 4.5V and VDD (max) = 5.5V. Submit Documentation Feedback Copyright © 2007–2009, Texas Instruments Incorporated Product Folder Link(s): ADS8317 ADS8317 www.ti.com .................................................................................................................................................... SBAS356D – JUNE 2007 – REVISED OCTOBER 2009 ELECTRICAL CHARACTERISTICS: VDD = +2.7V At –40°C to +85°C, VREF = +1.25V, –IN = 1.25V, fSAMPLE = 200kHz, and fCLK = 24 × fSAMPLE, unless otherwise noted. ADS8317I PARAMETER TEST CONDITIONS MIN TYP ADS8317IB MAX MIN –VREF VREF –0.1 VDD + 0.1 TYP MAX UNIT –VREF VREF V –0.1 VDD + 0.1 ANALOG INPUT Full-scale range FSR +IN – (–IN) Absolute input range Input resistance +IN RON Input capacitance Hold 5 Sampling 100 During sampling Input leakage current 150 100 GΩ Ω 150 24 24 pF nA ±50 ±50 +IN to –IN, during sampling 20 20 pF FSBW fS sinewave, SINAD = 60dB 1000 1000 kHz Differential input capacitance Full-power bandwidth V 5 DC ACCURACY Resolution No missing codes Integral linearity error Differential linearity error Offset error Offset error drift Gain error Gain error drift 16 NMC INL 16 ±2 +3 –2 –1 +1.5,–1 +2.5 +2 –3 DNL VOS –2 TCVOS GERR ±1 Positive –32 Negative –32 TCGERR 16 Bits ±1.5 +2 LSB –1 ±1 +2 LSB –1 ±0.5 +1 –2 ±16 +32 –32 ±16 +32 –32 Noise PSRR 2.7V ≤ VDD ≤ 3.6V ±0.8 mV μV/°C ±0.4 ±0.15 Bipolar zero error drift Bits 16 ±0.4 Bipolar zero error Power-supply rejection 16 16 ±16 +32 ±16 +32 ±0.15 +2 –1 ±0.4 LSB LSB ppm/°C +1 mV μV/°C ±0.2 ±0.2 50 50 μVRMS 1 1 LSB SAMPLING DYNAMICS Conversion time (16 DCLOCKs) Acquisition time (4.5 DCLOCKs) tCONV 24kHz ≤ fCLK ≤ 4.8MHz tAQ fCLK = 4.8MHz 3.333 666.7 0.9375 3.333 666.7 Throughput rate (22 DCLOCKs) 200 Clock frequency 0.024 4.8 μs μs 0.9375 0.024 200 kSPS 4.8 MHz AC ACCURACY Total harmonic distortion Spurious-free dynamic range Signal-to-noise ratio THD SFDR SNR Signal-to-noise + distortion SINAD Effective number of bits ENOB 2.5VPP sinewave at 2kHz –104 –107 dB 2.5VPP sinewave at 10kHz –101 –106 dB 2.5VPP sinewave at 2kHz 106 108 dB 2.5VPP sinewave at 10kHz 104 107 dB 2.5VPP sinewave at 2kHz 84.8 85 dB 2.5VPP sinewave at 10kHz 84.8 85 dB 2.5VPP sinewave at 2kHz 84.7 84.9 dB 2.5VPP sinewave at 10kHz 84.7 84.8 dB 2.5VPP sinewave at 2kHz 13.77 13.8 Bits 2.5VPP sinewave at 10kHz 13.77 13.79 Bits VOLTAGE REFERENCE INPUT Reference voltage Reference input resistance 1 CS = GND, fSAMPLE = 0Hz CS = VDD Reference input capacitance fS = 200kHz Reference input current VDD/2 5 1 VDD/2 V 5 kΩ 5 5 GΩ 20 20 9 14 pF 9 14 μA 3 5 3 5 μA fS = 10kHz 0.5 1 0.5 1 μA CS = VDD 0.1 fS = 100kHz 0.1 Submit Documentation Feedback Copyright © 2007–2009, Texas Instruments Incorporated Product Folder Link(s): ADS8317 μA 5 ADS8317 SBAS356D – JUNE 2007 – REVISED OCTOBER 2009 .................................................................................................................................................... www.ti.com ELECTRICAL CHARACTERISTICS: VDD = +2.7V (continued) At –40°C to +85°C, VREF = +1.25V, –IN = 1.25V, fSAMPLE = 200kHz, and fCLK = 24 × fSAMPLE, unless otherwise noted. ADS8317I PARAMETER TEST CONDITIONS MIN ADS8317IB TYP MAX MIN TYP MAX UNIT DIGITAL INPUTS (1) Logic family LVCMOS LVCMOS High-level input voltage VIH VDD = 3.6V 2 VDD + 0.3 2 VDD + 0.3 Low-level input voltage VIL VDD = 2.7V –0.3 0.8 –0.3 0.3 × VDD V Input current IIN VI = VDD or GND –50 +50 –50 +50 nA Input capacitance CI 5 5 V pF DIGITAL OUTPUTS (1) Logic family LVCMOS High-level output voltage VOH VDD = 2.7V, IOH = –100μA Low-level output voltage VOL VDD = 2.7V, IOL = 100μA High-impedance state output current IOZ CS = VDD, VI = VDD or GND Output capacitance CO Load capacitance CL VDD – 0.2 V 0.2 –50 +50 –50 5 0.2 V +50 nA 5 pF 30 Data format (1) LVCMOS VDD – 0.2 Binary twos complement 30 pF Binary twos complement Applies for 5.0V nominal supply: VDD (min) = 2.7V and VDD (max) = 3.6V. ELECTRICAL CHARACTERISTICS: GENERAL At –40°C to +85°C, –IN = GND, and fDCLOCK = 24 × fSAMPLE, unless otherwise noted. ADS8317I PARAMETER TEST CONDITIONS MIN TYP ADS8317IB MAX MIN TYP MAX UNIT ANALOG INPUT Power supply VDD Low-voltage levels 2.7 3.6 2.7 3.6 V 5V logic levels 4.5 5.5 4.5 5.5 V VDD = 2.7V, fS = 10kHz, fDCLOCK = 4.8MHz Operating supply current Power-down supply current Power dissipation Power dissipation in power-down 6 IDD IDD 0.065 0.085 0.065 0.085 mA VDD = 2.7V, fS = 100kHz, fDCLOCK = 4.8MHz 0.7 1.0 0.7 1.0 mA VDD = 2.7V, fS = 200kHz, fDCLOCK = 4.8MHz 1.4 2.0 1.4 2.0 mA VDD = 5V, fS = 200kHz, fDCLOCK = 6MHz 1.5 2.5 1.5 2.5 mA VDD = 5V, fS = 250kHz, fDCLOCK = 6MHz 2.0 3.0 2.0 3.0 mA VDD = 2.7V 0.1 0.1 μA VDD = 5V 0.2 0.2 μA VDD = 2.7V, fS = 10kHz, fDCLOCK = 4.8MHz 0.18 0.23 0.18 0.23 mW VDD = 2.7V, fS = 100kHz, fDCLOCK = 4.8MHz 1.9 2.7 1.9 2.7 mW VDD = 2.7V, fS = 200kHz, fDCLOCK = 4.8MHz 3.8 5.4 3.8 5.4 mW VDD = 5V, fS = 200kHz, fDCLOCK = 6MHz 7.5 12.5 7.5 12.5 mW VDD = 5V, fS = 250kHz, fDCLOCK = 6MHz 10 15 10 15 mW VDD = 2.7V, CS = VDD 0.3 0.3 μW VDD = 5V, CS = VDD 0.6 0.6 μW Submit Documentation Feedback Copyright © 2007–2009, Texas Instruments Incorporated Product Folder Link(s): ADS8317 ADS8317 www.ti.com .................................................................................................................................................... SBAS356D – JUNE 2007 – REVISED OCTOBER 2009 PIN CONFIGURATION DGK PACKAGE MSOP-8 (TOP VIEW) REF 1 +IN 2 8 VDD 7 DCLOCK ADS8317 -IN 3 6 DOUT GND 4 5 CS/SHDN DRB PACKAGE SON-8 (TOP VIEW) REF 1 +IN 2 8 VDD 7 DCLOCK 6 DOUT 5 CS/SHDN ADS8317 (1) -IN 3 GND 4 (Thermal Pad) The DRB package thermal pad must be soldered to the printed circuit board for proper thermal and mechanical performance. TERMINAL FUNCTIONS TERMINAL NAME NO. I/O DESCRIPTION REF 1 Analog input Reference input +IN 2 Analog input Noninverting analog input –IN 3 Analog input Inverting analog input GND 4 Power-supply connection CS/SHDN 5 Digital input DOUT 6 Digital output DCLOCK 7 Digital input VDD 8 Power-supply connection Ground Chip select when low; Shutdown mode when high. Serial output data word Data clock synchronizes the serial data transfer and determines conversion speed. Power supply Equivalent Input Circuits (VDD = 5.0V) VDD VDD RON 50W C(SAMPLE) 24pF ANALOG IN GND Diode Turn-On Voltage: 0.35V Equivalent Analog Input Circuit VDD RON 50W REF GND Equivalent Reference Input Circuit 24pF I/O GND Equivalent Digital Input/Output Circuit Submit Documentation Feedback Copyright © 2007–2009, Texas Instruments Incorporated Product Folder Link(s): ADS8317 7 ADS8317 SBAS356D – JUNE 2007 – REVISED OCTOBER 2009 .................................................................................................................................................... www.ti.com TIMING INFORMATION tCYC CS/SHDN Sample Power Down Conversion tSUCS DCLOCK tCSD Use positive clock edge for data transfer Hi-Z DOUT 0 tSMPL B7 B15 B14 B13 B12 B11 B10 B9 B8 (MSB) tCONV B6 B5 B4 B3 B2 Hi-Z (1) B1 B0 (LSB) NOTE: (1) A minimum of 22 clock cycles are required for 16-bit conversion; 24 clock cycles are shown. If CS remains low at the end of conversion, a new data stream is shifted out with LSB-first data followed by zeroes indefinitely. tCYC CS/SHDN tSUCS Power Down DCLOCK tCSD Hi-Z DOUT 0 tSMPL B15 B14 B6 (MSB) B5 B4 B3 tCONV B2 B1 B0 B1 B2 B3 B4 B5 (LSB) B0 (2) Hi-Z B11 B12 B13 B14 B15 (MSB) NOTE: (2) After completing the data transfer, if further clocks are applied with CS low, the A/D converter will output zeroes indefinitely. 1.4V 3kW DOUT 90% DOUT 10% Test Point tr 100pF CLOAD tf Voltage Waveforms for DOUT Rise and Fall Times, tr, tf Load Circuit for tdDO, tr, and tf Test Point DCLOCK VDD DOUT tdDO tdis Waveform 2, ten 3kW tdis Waveform 1 100pF CLOAD DOUT thDO Load Circuit for tdis and ten Voltage Waveforms for DOUT Delay Times, tdDO 90% CS/SHDN DOUT Waveform 1(3) CS/SHDN 90% DCLOCK 1 4 5 tdis DOUT Waveform 2(4) 10% DOUT B15 ten Voltage Waveforms for tdis Voltage Waveforms for ten NOTES: (3) Waveform 1 is for an output with internal conditions such that the output is high unless disabled by the output control. (4) Waveform 2 is for an output with internal conditions such that the output is low unless disabled by the output control. Figure 1. Timing Diagrams 8 Submit Documentation Feedback Copyright © 2007–2009, Texas Instruments Incorporated Product Folder Link(s): ADS8317 ADS8317 www.ti.com .................................................................................................................................................... SBAS356D – JUNE 2007 – REVISED OCTOBER 2009 TIMING INFORMATION (continued) Timing Characteristics SYMBOL DESCRIPTION MIN TYP 4.5 MAX 5.0 UNIT tSMPL Analog input sample time tCONV Conversion time tCYC Complete cycle time tCSD CS falling to DCLOCK low tSUCS CS falling to DCLOCK rising tHDO DCLOCK falling to current DOUT not valid tDIS CS rising to DOUT 3-state 70 100 ns tEN DCLOCK falling to DOUT enabled 20 50 ns tF DOUT fall time 5 25 ns tR DOUT rise time 7 25 ns 16 DCLOCKs 22 DCLOCKs 0 20 5 DCLOCKs ns ns 15 ns Submit Documentation Feedback Copyright © 2007–2009, Texas Instruments Incorporated Product Folder Link(s): ADS8317 9 ADS8317 SBAS356D – JUNE 2007 – REVISED OCTOBER 2009 .................................................................................................................................................... www.ti.com TYPICAL CHARACTERISTICS: VDD = +5V At TA = 25°C, VREF = 2.5V, fSAMPLE = 250kHz, fCLK = 24 × fSAMPLE, unless otherwise noted. DIFFERENTIAL LINEARITY ERROR vs CODE 3 2 2 1 1 DLE (LSB) ILE (LSB) INTEGRAL LINEARITY ERROR vs CODE 3 0 0 -1 -1 -2 -2 -3 8000h C000h 0000h 4000h -3 8000h 7FFFh C000h 0000h Output Code Figure 2. 7FFFh Figure 3. SUPPLY CURRENT vs TEMPERATURE CHANGE IN OFFSET vs TEMPERATURE 3.0 1.745 2.5 Delta from +25°C (LSB) 1.750 1.740 Supply Current (mA) 4000h Output Code 1.735 1.730 1.725 1.720 1.715 2.0 1.5 1.0 0.5 0 -0.5 -1.0 -1.5 1.710 -2.0 -50 -25 0 25 50 75 100 -50 -25 0 Temperature (°C) 25 50 75 100 75 100 Temperature (°C) Figure 4. Figure 5. CHANGE IN BIPOLAR ZERO ERROR vs TEMPERATURE CHANGE IN GAIN vs TEMPERATURE 3.0 0.50 2.0 Delta from +25°C (LSB) Delta from +25°C (LSB) 2.5 1.5 1.0 0.5 0 -0.5 -1.0 0.25 0 -0.25 -0.50 -1.5 -2.0 -0.75 -50 -25 0 25 50 75 100 -50 Temperature (°C) 0 25 50 Temperature (°C) Figure 6. 10 -25 Figure 7. Submit Documentation Feedback Copyright © 2007–2009, Texas Instruments Incorporated Product Folder Link(s): ADS8317 ADS8317 www.ti.com .................................................................................................................................................... SBAS356D – JUNE 2007 – REVISED OCTOBER 2009 TYPICAL CHARACTERISTICS: VDD = +5V (continued) At TA = 25°C, VREF = 2.5V, fSAMPLE = 250kHz, fCLK = 24 × fSAMPLE, unless otherwise noted. SUPPLY CURRENT vs SAMPLING RATE 10 1 Supply Current (mA) Power-Down Current (nA) POWER-DOWN CURRENT vs TEMPERATURE 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 0.1 0.01 0.001 -50 -25 0 25 50 75 100 1 10 100 250 Sampling Rate (kHz) Temperature (°C) Figure 8. Figure 9. REFERENCE CURRENT vs SAMPLING RATE FREQUENCY SPECTRUM (8192 point FFT, fIN = 1.9836kHz, –0.2dB) 0 100 10 -40 Amplitude (dB) Supply Current (mA) -20 1 0.1 -60 -80 -100 -120 -140 0.01 -160 1 10 100 250 0 Sampling Rate (kHz) 25 50 75 125 Figure 10. Figure 11. FREQUENCY SPECTRUM (8192 Point FFT, fIN = 9.9792kHz, –0.2dB) SIGNAL-TO-NOISE RATIO AND SIGNAL-TO-NOISE + DISTORTION vs INPUT FREQUENCY 0 95 -20 SNR and SINAD (dB) SNR -40 Amplitude (dB) 100 Frequency (kHz) -60 -80 -100 -120 90 SINAD 85 80 -140 75 -160 0 25 50 75 100 125 1 10 100 200 Frequency (kHz) Frequency (kHz) Figure 12. Figure 13. Submit Documentation Feedback Copyright © 2007–2009, Texas Instruments Incorporated Product Folder Link(s): ADS8317 11 ADS8317 SBAS356D – JUNE 2007 – REVISED OCTOBER 2009 .................................................................................................................................................... www.ti.com TYPICAL CHARACTERISTICS: VDD = +5V (continued) At TA = 25°C, VREF = 2.5V, fSAMPLE = 250kHz, fCLK = 24 × fSAMPLE, unless otherwise noted. SPURIOUS-FREE DYNAMIC RANGE AND TOTAL HARMONIC DISTORTION vs INPUT FREQUENCY 120 -120 115 -115 SFDR 15.0 14.5 -105 100 -100 95 -95 THD(1) 90 -90 85 -85 80 -80 75 -75 70 10 100 13.5 13.0 12.5 12.0 -65 1 14.0 -70 NOTE: (1) First nine harmonics of the input frequency. 65 ENOB (Bits) -110 105 THD (dB) SFDR (dB) 110 EFFECTIVE NUMBER OF BITS vs INPUT FREQUENCY 200 1 10 Frequency (kHz) 100 200 Frequency (kHz) Figure 14. Figure 15. CHANGE IN SIGNAL-TO-NOISE + DISTORTION vs TEMPERATURE CHANGE IN SIGNAL-TO-NOISE + DISTORTION vs INPUT LEVEL 100 0.7 fIN = 1.98364kHz, -0.2dB 0.6 90 fIN = 1.98364kHz 80 0.4 0.3 SINAD (dB) Delta from +25°C (LSB) 0.5 0.2 0.1 0 70 60 50 -0.1 40 -0.2 30 -0.3 20 -0.4 10 -0.5 -50 -25 0 25 75 50 100 -80 -70 -60 Temperature (°C) -50 -40 -30 -20 -10 0 Input Level (dB) Figure 16. Figure 17. PEAK-TO-PEAK NOISE FOR A DC INPUT vs REFERENCE VOLTAGE OUTPUT CODE HISTOGRAM FOR A DC INPUT (8192 Conversions) 100 Peak-to-Peak Noise (LSB) VDD = 5V 4835 10 1673 1608 34 42 1 1 0.1 2 2.5 FFFE Figure 18. 12 FFFF 0000 0001 0002 Code (Hex) Reference Voltage (V) Figure 19. Submit Documentation Feedback Copyright © 2007–2009, Texas Instruments Incorporated Product Folder Link(s): ADS8317 ADS8317 www.ti.com .................................................................................................................................................... SBAS356D – JUNE 2007 – REVISED OCTOBER 2009 TYPICAL CHARACTERISTICS: VDD = +2.7V At TA = 25°C, VREF = 1.25V, fSAMPLE = 200kHz, fCLK = 24 × fSAMPLE, unless otherwise noted. DIFFERENTIAL LINEARITY ERROR vs CODE 3 2 2 1 1 DLE (LSB) ILE (LSB) INTEGRAL LINEARITY ERROR vs CODE 3 0 0 -1 -1 -2 -2 -3 8000h C000h 0000h 4000h -3 8000h 7FFFh C000h 0000h Output Code Figure 20. 7FFFh Figure 21. SUPPLY CURRENT vs TEMPERATURE CHANGE IN OFFSET vs TEMPERATURE 1.310 1.00 1.305 0.75 Delta from +25°C (LSB) 1.300 Supply Current (mA) 4000h Output Code 1.295 1.290 1.285 1.280 1.275 1.270 0.50 0.25 0 -0.25 -0.50 -0.75 1.265 1.260 -1.00 -50 -25 0 25 75 50 100 -50 -25 0 Temperature (°C) 25 50 75 100 75 100 Temperature (°C) Figure 22. Figure 23. CHANGE IN BIPOLAR ZERO ERROR vs TEMPERATURE CHANGE IN GAIN vs TEMPERATURE 0.50 0.50 Delta from +25°C (LSB) Delta from +25°C (LSB) 0.25 0.25 0 -0.25 0 -0.25 -0.50 -0.75 -0.50 -1.00 -50 -25 0 25 50 75 100 -50 Temperature (°C) -25 0 25 50 Temperature (°C) Figure 24. Figure 25. Submit Documentation Feedback Copyright © 2007–2009, Texas Instruments Incorporated Product Folder Link(s): ADS8317 13 ADS8317 SBAS356D – JUNE 2007 – REVISED OCTOBER 2009 .................................................................................................................................................... www.ti.com TYPICAL CHARACTERISTICS: VDD = +2.7V (continued) At TA = 25°C, VREF = 1.25V, fSAMPLE = 200kHz, fCLK = 24 × fSAMPLE, unless otherwise noted. POWER-DOWN CURRENT vs TEMPERATURE SUPPLY CURRENT vs SAMPLING RATE 10 25 1 23 Supply Current (mA) Power-Down Current (nA) 24 22 21 20 19 0.1 0.01 18 0.001 17 0.0001 16 -50 -25 0 25 75 50 100 10 1 100 200 Sampling Rate (kHz) Temperature (°C) Figure 26. Figure 27. REFERENCE CURRENT vs SAMPLING RATE FREQUENCY SPECTRUM (8192 Point FFT, fIN = 1.9775kHz, –0.2dB) 0 100 10 -40 Amplitude (dB) Reference Current (mA) -20 1 0.1 -60 -80 -100 -120 -140 0.01 -160 10 1 100 200 0 20 30 40 50 60 70 80 90 100 Figure 28. Figure 29. FREQUENCY SPECTRUM (8192 Point FFT, fIN = 9.9854kHz, –0.2dB) SIGNAL-TO-NOISE RATIO AND SIGNAL-TO-NOISE + DISTORTION vs INPUT FREQUENCY 0 86 -20 85 -40 84 -60 -80 -100 -120 SNR 83 82 81 SINAD 80 79 -140 78 -160 0 10 20 30 40 50 60 70 80 90 100 1 10 100 200 Frequency (kHz) Frequency (kHz) Figure 30. 14 10 Frequency (kHz) SNR and SINAD (dB) Amplitude (dB) Sampling Rate (kHz) Figure 31. Submit Documentation Feedback Copyright © 2007–2009, Texas Instruments Incorporated Product Folder Link(s): ADS8317 ADS8317 www.ti.com .................................................................................................................................................... SBAS356D – JUNE 2007 – REVISED OCTOBER 2009 TYPICAL CHARACTERISTICS: VDD = +2.7V (continued) At TA = 25°C, VREF = 1.25V, fSAMPLE = 200kHz, fCLK = 24 × fSAMPLE, unless otherwise noted. SPURIOUS-FREE DYNAMIC RANGE AND TOTAL HARMONIC DISTORTION vs INPUT FREQUENCY 110 EFFECTIVE NUMBER OF BITS vs INPUT FREQUENCY -110 15.0 -105 14.5 -100 14.0 SFDR (dB) 100 THD(1) ENOB (Bits) 105 THD (dB) SFDR 95 -95 90 -90 13.0 -85 12.5 -80 12.0 85 13.5 NOTE: (1) First nine harmonics of the input frequency. 80 1 10 100 200 1 10 Frequency (kHz) Figure 32. 200 Figure 33. CHANGE IN SIGNAL-TO-NOISE + DISTORTION vs TEMPERATURE SIGNAL-TO-NOISE + DISTORTION vs INPUT LEVEL 0.6 100 fIN = 1.97754kHz, -0.2dB 0.5 fIN = 1.97754kHz 90 0.4 80 0.3 70 0.2 SINAD (dB) Delta from +25°C (LSB) 100 Frequency (kHz) 0.1 0 -0.1 -0.2 60 50 40 30 -0.3 20 -0.4 10 -0.5 0 -0.6 -50 -25 0 25 75 50 100 -80 -70 -60 Temperature (°C) -50 -40 -30 -20 -10 0 Input Level (dB) Figure 34. Figure 35. OUTPUT CODE HISTOGRAM FOR A DC INPUT (8192 Conversions) 3920 1596 1504 581 2 497 50 41 1 FFFC FFFD FFFE FFFF 0000 0001 0002 0003 0004 Code (Hex) Figure 36. Submit Documentation Feedback Copyright © 2007–2009, Texas Instruments Incorporated Product Folder Link(s): ADS8317 15 ADS8317 SBAS356D – JUNE 2007 – REVISED OCTOBER 2009 .................................................................................................................................................... www.ti.com THEORY OF OPERATION The ADS8317 is a classic Successive Approximation Register (SAR) analog-to-digital (A/D) converter. The architecture is based on capacitive redistribution that inherently includes a sample-and-hold function. The converter is fabricated on a 0.6μ CMOS process. The architecture and fabrication process allow the ADS8317 to acquire and convert an analog signal at up to 250,000 conversions per second while consuming less than 10mW from VDD. Differential linearity for the ADS8317 is factory-adjusted via a package-level trim procedure. The state of the trim elements is stored in non-volatile memory and is continuously updated after each acquisition cycle, just prior to the start of the successive approximation operation. This process ensures that one complete conversion cycle always returns the part to its factory-adjusted state in the event of a power interruption. The ADS8317 requires an external reference, an external clock, and a single power source (VDD). The external reference can be any voltage between 0.1V and VDD/2. The value of the reference voltage directly sets the range of the analog input. The reference input current depends on the conversion rate of the ADS8317. The external clock can vary between 24kHz (1kHz throughput) and 6.0MHz (250kHz throughput). The duty cycle of the clock is not significant, as long as the minimum high and low times are at least 200ns (VDD = 4.75V or greater). The minimum clock frequency is set by the leakage on the internal capacitors to the ADS8317. The analog input is provided to two input pins: +IN and –IN. When a conversion is initiated, the differential input on these pins is sampled on the internal capacitor array. While a conversion is in progress, both inputs are disconnected from any internal function. The digital data that are provided on the DOUT pin are for the conversion currently in progress—there is no pipeline delay. It is possible to continue to clock the ADS8317 after the conversion is complete and to obtain the serial data least significant bit first. See the Digital Timing section for more information. ANALOG INPUT The analog input is bipolar and fully differential. There are two general methods of driving the analog input of the ADS8317: single-ended or differential, as shown in Figure 37. When the input is single-ended, the –IN input is held at a fixed voltage. The +IN input swings around the same voltage and the peak-to-peak amplitude is 2 × VREF. The value of VREF determines the range over which the common voltage may vary, as shown in Figure 38 and Figure 39. Single-Ended Input 2 ´ VREF Peak-to-Peak ADS8317 Common Voltage Differential Input VREF Peak-to-Peak ADS8317 Common Voltage VREF Peak-to-Peak Figure 37. Methods of Driving the ADS8317—Single-Ended or Differential The digital result of the conversion is clocked out by the DCLOCK input and is provided serially (most significant bit first) on the DOUT pin. 16 Submit Documentation Feedback Copyright © 2007–2009, Texas Instruments Incorporated Product Folder Link(s): ADS8317 ADS8317 www.ti.com .................................................................................................................................................... SBAS356D – JUNE 2007 – REVISED OCTOBER 2009 5 5 4 3.8 2.8 3 Single-Ended Input 2 2.2 1 0.2 0 VDD = 5V Common Voltage Range (V) Common Voltage Range (V) VDD = 5V 4 3.8 2.75 3 2 Differential Input 1 0.95 0 -0.3 -0.3 -1 -1 0 0.5 1.0 1.5 2.0 2.5 0 0.5 VREF (V) 1.0 1.5 Figure 38. Single-Ended 5V Input, Common Voltage Range vs VREF 3.0 2.5 2.0 1.5 1.5 1.0 Single-Ended Input 1.05 0.2 0 -0.5 -0.2 2.5 2.0 1.5 1.5 1.5 1.0 Differential Input 0.5 0.5 0 -0.3 -0.5 0.5 -1.0 0.10 VDD = 2.7V Common Voltage Range (V) Common Voltage Range (V) VDD = 2.7V 0.5 2.5 Figure 40. Differential 5V Input, Common Voltage Range vs VREF 3.0 1.5 2.0 VREF (V) -1.0 0.35 0.60 0.85 1.10 1.35 0 VREF (V) 0.25 0.50 0.75 1.00 1.25 VREF (V) Figure 39. Single-Ended 2.7V Input, Common Voltage Range vs VREF Figure 41. Differential 2.7V Input, Common Voltage Range vs VREF When the input is differential, the amplitude of the input is the difference between the +IN and –IN input, or +IN – (–IN). A voltage or signal is common to both of these inputs. The peak-to-peak amplitude of each input is VREF about this common voltage. However, since the inputs are 180° out-of-phase, the peak-to-peak amplitude of the difference voltage is 2 × VREF. The value of VREF also determines the range of the voltage that may be common to both inputs, as shown in Figure 41 and Figure 40. In each case, care should be taken to ensure that the output impedance of the sources driving the +IN and –IN inputs are matched. If this matching is not observed, the two inputs could have different settling times. This difference may result in offset error, gain error, and linearity error that change with both temperature and input voltage. If the impedance cannot be matched, the errors can be lessened by giving the ADS8317 additional acquisition time. Submit Documentation Feedback Copyright © 2007–2009, Texas Instruments Incorporated Product Folder Link(s): ADS8317 17 ADS8317 SBAS356D – JUNE 2007 – REVISED OCTOBER 2009 .................................................................................................................................................... www.ti.com The input current on the analog inputs depends on a number of factors: sample rate, input voltage, and source impedance. Essentially, the current into the ADS8317 charges the internal capacitor array during the sample period. After this capacitance has been fully charged, there is no further input current. The source of the analog input voltage must be able to charge the input capacitance (24pF) to 16-bit settling level within 4.5 clock cycles. When the converter goes into the hold mode, or while it is in the power-down mode, the input impedance is greater than 1GΩ. Care must be taken regarding the absolute analog input voltage. The +IN input should always remain within the range of GND – 300mV to VDD + 300mW. The –IN input should always remain within the range of GND – 300mV to 4V. Outside of these ranges, the converter linearity may not meet specifications. To obtain maximum performance from the ADS8317, an input circuit such as that shown in Figure 42 is recommended. Single-Ended 10W +IN OPA365 50W 24pF 1000pF ADS8317 -IN VCM 50W 24pF + 10W +IN 50W 24pF 1000pF ADS8317 1nF 10W -IN OPA365 The external reference sets the analog input range. The ADS8317 operates with a reference in the range of 0.1V to VDD/2. There are several important implications to this specification. As the reference voltage is reduced, the analog voltage weight of each digital output code is reduced. This reduction is often referred to as the least significant bit (LSB) size and is equal to the reference voltage divided by 65,536. This relationship means that any offset or gain error inherent in the A/D converter appears to increase (in terms of LSB size) as the reference voltage is reduced. For a reference voltage of 2.5V, the value of the LSB is 76.3μV, and for a reference voltage of 1.25V, the LSB is 38.15μV. The noise inherent in the converter also appears to increase with a lower LSB size. With a 2.5V reference, the internal noise of the converter typically contributes only 5LSB peak-to-peak of potential error to the output code. When the external reference is 1.25V, the potential error contribution from the internal noise is almost two times larger (9LSB). The errors arising from the internal noise are Gaussian in nature and can be reduced by averaging consecutive conversion results. For more information regarding noise, consult Figure 18, Peak-to-Peak Noise for a DC Input vs Reference Voltage. Note that the Effective Number Of Bits (ENOB) figure is calculated based on the converter signal-to-(noise + distortion) ratio with a 2kHz, 0dB input signal. SINAD is related to ENOB as follows: SINAD = 6.02 × ENOB + 1.76 Differential OPA365 REFERENCE INPUT 50W 24pF With lower reference voltages, extra care should be taken to provide a clean layout including adequate bypassing, a clean power supply, a low-noise reference, and a low-noise input signal. Due to the lower LSB size, the converter is also more sensitive to external sources of error, such as nearby digital signals and electromagnetic interference. 1000pF Figure 42. Single-Ended and Differential Methods of Interfacing the ADS8317 18 Submit Documentation Feedback Copyright © 2007–2009, Texas Instruments Incorporated Product Folder Link(s): ADS8317 ADS8317 www.ti.com .................................................................................................................................................... SBAS356D – JUNE 2007 – REVISED OCTOBER 2009 The equivalent input circuit for the reference voltage is presented in Figure 43. At the same time, an equivalent capacitor of 24pF is switched. To obtain optimum performance from the ADS8317, special care must be taken in designing the interface circuit to the reference input pin. To ensure a stable reference voltage, a 47μF tantalum capacitor with low ESR should be connected as close as possible to the input pin. If a high output impedance reference source is used, an additional operational amplifier with a current-limiting resistor must be placed in front of the capacitors. ADS8317 VREF 50W 24pF OPA350 47mF Figure 43. Input Reference Circuit and Interface When the ADS8317 is in power-down mode, the input resistance of the reference pin has a value of 5GΩ. Because the input capacitors must be recharged before the next conversion starts, an operational amplifier with good dynamic characteristics, such as the OPA350, should be used to buffer the reference input. Noise The transition noise of the ADS8317 itself is extremely low, as shown in Figure 19 and Figure 36; it is much lower than competing A/D converters. These histograms were generated by applying a low-noise DC input and initiating 8192 conversions. The digital output of the A/D converter varies in output code because of the internal noise of the ADS8317. This variance is true for all 16-bit, SAR-type A/D converters. Using a histogram to plot the output codes, the distribution should appear bell-shaped with the peak of the bell curve representing the nominal code for the input value. The ±1σ, ±2σ, and ±3σ distributions represent 68.3%, 95.5%, and 99.7%, respectively, of all codes. The transition noise can be calculated by dividing the number of codes measured by 6, which yields the ±3σ distribution, or 99.7%, of all codes. Statistically, up to three codes could fall outside the distribution when executing 1000 conversions. The ADS8317, with five output codes for the ±3σ distribution, yields less than ±0.8LSB of transition noise. Remember that to achieve this low-noise performance, the peak-to-peak noise of the input signal and reference must be less than 50μV. Averaging The noise of the A/D converter can be compensated by averaging the digital codes. By averaging conversion results, transition noise is reduced by a factor of 1/√n , where n is the number of averages. For example, averaging four conversion results reduces the transition noise from ±0.8LSB to ±0.4LSB. Averaging should only be used for input signals with frequencies near DC. For AC signals, a digital filter can be used to low-pass filter and decimate the output codes. This configuration works in a similar manner to averaging; for every decimation by 2, the signal-to-noise ratio improves by 3dB. Submit Documentation Feedback Copyright © 2007–2009, Texas Instruments Incorporated Product Folder Link(s): ADS8317 19 ADS8317 SBAS356D – JUNE 2007 – REVISED OCTOBER 2009 .................................................................................................................................................... www.ti.com DIGITAL INTERFACE Signal Levels The ADS8317 has a wide range of power-supply voltage. The A/D converter, as well as the digital interface circuit, is designed to accept and operate from 2.7V up to 5.5V. This voltage range accommodates different logic levels. When the ADS8317 power-supply voltage is in the range of 4.5V to 5.5V (5V logic level), the ADS8317 can be connected directly to another 5V, CMOS-integrated circuit. When the ADS8317 power-supply voltage is in the range of 2.7V to 3.6V (3V logic level), the ADS8317 can be connected directly to another 3.3V LVCMOS integrated circuit. Serial Interface The ADS8317 communicates with microprocessors and other digital systems via a synchronous 3-wire serial interface, as illustrated in the Timing Information section and Timing Characteristics . The DCLOCK signal synchronizes the data transfer, with each bit being transmitted on the falling edge of DCLOCK. Most receiving systems capture the bitstream on the rising edge of DCLOCK. However, if the minimum hold time for DOUT is acceptable, the system can use the falling edge of DCLOCK to capture each bit. A falling CS signal initiates the conversion and data transfer. The first 4.5 to 5.0 clock periods of the conversion cycle are used to sample the input signal. 20 After the fifth falling DCLOCK edge, DOUT is enabled and outputs a low value for one clock period. For the next 16 DCLOCK periods, DOUT outputs the conversion result, most significant bit first. After the least significant bit (B0) has been output, subsequent clocks repeat the output data, but in a least significant bit first format. After the most significant bit (B15) has been repeated, DOUT will 3-state. Subsequent clocks have no effect on the converter. A new conversion is initiated only when CS has been taken high and returned low. Data Format The output data from the ADS8317 are in binary twos complement format, as shown in Table 1 and Figure 44. The table and figure represent the ideal output code for the given input voltage and do not include the effects of offset, gain error, or noise. Table 1. Ideal Input Voltages and Output Codes DESCRIPTION ANALOG VALUE Full-scale range 2 × VREF Least significant bit (LSB) 2 × VREF/65536 Binary Code Hex Code +Full scale +VREF – 1 LSB 0111 1111 1111 1111 7FFF 0V 0000 0000 0000 0000 0000 0V – 1 LSB 1111 1111 1111 1111 FFFF –VREF 1000 0000 0000 0000 8000 Midscale Midscale – 1 LSB –Full scale Submit Documentation Feedback DIGITAL OUTPUT BINARY TWOS COMPLEMENT Copyright © 2007–2009, Texas Instruments Incorporated Product Folder Link(s): ADS8317 ADS8317 www.ti.com .................................................................................................................................................... SBAS356D – JUNE 2007 – REVISED OCTOBER 2009 0111 1111 1111 1111 65535 0111 1111 1111 1110 65534 0111 1111 1111 1101 65533 0000 0000 0000 0001 32769 0000 0000 0000 0000 32768 1111 1111 1111 1111 32767 1000 0000 0000 0010 2 1000 0000 0000 0001 1 1000 0000 0000 0000 Step Digital Output Code Binary Twos Complement 0 +38.15mV -38.15mV V-FS = -2.5V V+FS = VREF = 2.5V V+FS - 1LSB = 2.499992V 0V -2.49996V 2.499985V -2.49992V Bipolar Analog Input Voltage = V(+IN) - V(-IN) -2.49985V 1LSB = 76.29mV VCM = 2.5V 16-BIT -Full-Scale Code Midscale Code +Full-Scale Code Twos Complement Output V-FS = 8000h VMS = 0000h V+FS = 7FFFh Bipolar Analog Input VCODE = -VREF VCODE = 0V VCODE = VREF - 1LSB VREF = 2.5V Figure 44. Ideal Conversion Characteristics (Conditions: VCM = 2.5V, VREF = 2.5V) Submit Documentation Feedback Copyright © 2007–2009, Texas Instruments Incorporated Product Folder Link(s): ADS8317 21 ADS8317 SBAS356D – JUNE 2007 – REVISED OCTOBER 2009 .................................................................................................................................................... www.ti.com POWER DISSIPATION Short Cycling The architecture of the converter, the semiconductor fabrication process, and a careful design allow the ADS8317 to convert at up to a 250kHz rate while requiring very little power. However, for the absolute lowest power dissipation, there are several things to keep in mind. Another way to save power is to use the CS signal to short-cycle the conversion. The ADS8317 places the latest data bit on the DOUT line as it is generated; therefore, the converter can easily be short-cycled. This term means that the conversion can be terminated at any time. For example, if only 14 bits of the conversion result are needed, then the conversion can be terminated (by pulling CS high) after the 14th bit has been clocked out. The power dissipation of the ADS8317 scales directly with conversion rate. Therefore, the first step to achieving the lowest power dissipation is to find the lowest conversion rate that satisfies the system requirements. In addition, the ADS8317 goes into Power-Down mode under two conditions: when the conversion is complete and whenever CS is high (see the Timing Characteristics section). Ideally, each conversion should occur as quickly as possible, preferably at a 6.0MHz clock rate. This way, the converter spends the longest possible time in power-down mode. This is very important because the converter not only uses power on each DCLOCK transition (as is typical for digital CMOS components), but also uses some current for the analog circuitry, such as the comparator. The analog section dissipates power continuously until power-down mode is entered. Figure 9 and Figure 27 illustrate the current consumption of the ADS8317 versus sample rate. For these graphs, the converter is clocked at maximum speed regardless of the sample rate. CS is held high during the remaining sample period. This technique can also be used to lower the power dissipation (or to increase the conversion rate) in those applications where an analog signal is being monitored until some condition becomes true. For example, if the signal is outside a predetermined range, the full 16-bit conversion result may not be needed. If so, the conversion can be terminated after the first n bits, where n might be as low as 3 or 4. This technique results in lower power dissipation in both the converter and the rest of the system because they spend more time in power-down mode. POWER-ON RESET The ADS8317 bias circuit is self-starting. There may be a static current (approximately 1.5mA with VDD = 5V) after power-on, unless the circuit is powered down. It is recommended to run a single test conversion (configured the same as any regular conversion) after the power supply reaches at least 2.4V to ensure the device is put into power-down mode. There is an important distinction between the power-down mode that is entered after a conversion is complete and the full power-down mode that is enabled when CS is high. CS low only shuts down the analog section. The digital section completely shuts down only when CS is high. Thus, if CS is left low at the end of a conversion, and the converter is continually clocked, the power consumption is not as low as when CS is high. 22 Submit Documentation Feedback Copyright © 2007–2009, Texas Instruments Incorporated Product Folder Link(s): ADS8317 ADS8317 www.ti.com .................................................................................................................................................... SBAS356D – JUNE 2007 – REVISED OCTOBER 2009 LAYOUT For optimum performance, care should be taken with the physical layout of the ADS8317 circuitry. This caution is particularly true if the reference voltage is low and/or the conversion rate is high. At a 250kHz conversion rate, the ADS8317 makes a bit decision every 167ns. That is, for each subsequent bit decision, the digital output must be updated with the results of the last bit decision, the capacitor array appropriately switched and charged, and the input to the comparator settled to a 16-bit level, all within one clock cycle. The basic SAR architecture is sensitive to spikes on the power supply, reference, and ground connections that occur just prior to latching the comparator output. Thus, during any single conversion for an n-bit SAR converter, there are n windows in which large external transient voltages can easily affect the conversion result. Such spikes might originate from switching power supplies, digital logic, and high-power devices, to name a few potential sources. This particular source of error can be very difficult to track down if the glitch is almost synchronous to the converter DCLOCK signal because the phase difference between the glitch and DCLOCK changes with time and temperature, causing sporadic misoperation. With these considerations in mind, power to the ADS8317 should be clean and well-bypassed. A 0.1μF ceramic bypass capacitor should be placed as close as possible to the ADS8317 package. In addition, a 1μF to 10μF capacitor and a 5Ω or 10Ω series resistor may be used to low-pass filter a noisy supply. The reference should be similarly bypassed with a 47μF capacitor. Again, a series resistor and large capacitor can be used to low-pass filter the reference voltage. If the reference voltage originates from an op amp, make sure that the op amp can drive the bypass capacitor without oscillation (the series resistor can help in this case). Keep in mind that while the ADS8317 draws very little current from the reference on average, there are still instantaneous current demands placed on the external input and reference circuitry. Texas Instruments' OPA365 op amp provides optimum performance for buffering the signal inputs; the OPA350 can be used to effectively buffer the reference input. Also, keep in mind that the ADS8317 offers no inherent rejection of noise or voltage variation in regards to the reference input. This characteristic is of particular concern when the reference input is tied to the power supply. Any noise and ripple from the supply appears directly in the digital results. While high-frequency noise can be filtered out, as described in the previous paragraph, voltage variation resulting from the line frequency (50Hz or 60Hz) can be difficult to remove. The GND pin on the ADS8317 should be placed on a clean ground point. In many cases, this point is the analog ground. Avoid connecting the GND pin too close to the grounding point for a microprocessor, microcontroller, or digital signal processor. If needed, run a ground trace directly from the converter to the power-supply connection point. The ideal layout includes an analog ground plane for the converter and associated analog circuitry. Submit Documentation Feedback Copyright © 2007–2009, Texas Instruments Incorporated Product Folder Link(s): ADS8317 23 ADS8317 SBAS356D – JUNE 2007 – REVISED OCTOBER 2009 .................................................................................................................................................... www.ti.com APPLICATION CIRCUITS Figure 45 shows an example of a basic data acquisition system. The ADS8317 input range is connected to 2.5V or 4.096V. The 5Ω resistor and 1μF to 10μF capacitor filters the microcontroller noise on the supply, as well as any high-frequency noise from the supply itself. The exact values should be picked such that the filter provides adequate rejection of noise. Operational amplifiers and voltage reference are connected to the analog power supply, AVDD. DVDD 2.7V to 3.6V 0.1mF AVDD 2.7V to 5V 10mF 5W REF3225 REF OPA350 10W IN OUT VDD 47mF 2.2mF 0.47mF + 0.1mF GND + 10mF ADS8317 DSP 10W VCM + (0V to 2.5V) 1000pF CS 1nF DOUT DCLOCK 10W -IN OPA365 VCM TMS320C6xx or TMS320C5xx or TMS320C2xx +IN OPA365 GND GND 1000pF Figure 45. Example of a Basic Data Acquisition System 24 Submit Documentation Feedback Copyright © 2007–2009, Texas Instruments Incorporated Product Folder Link(s): ADS8317 ADS8317 www.ti.com .................................................................................................................................................... SBAS356D – JUNE 2007 – REVISED OCTOBER 2009 REVISION HISTORY NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision C (June 2008) to Revision D .................................................................................................... Page • Changed SON-8 (DRB) package availability ........................................................................................................................ 1 • Deleted lead temperature specification ................................................................................................................................ 2 • Added missing mu symbol to High-level output voltage test condition ................................................................................. 4 • Added missing mu symbol to Low-level output voltage test condition ................................................................................. 4 • Changed X-axis unit from mA to μA in Figure 10 ............................................................................................................... 11 • Changed Figure 38 ............................................................................................................................................................. 17 • Changed Figure 39 ............................................................................................................................................................. 17 • Changed Figure 40 title (typo) ............................................................................................................................................ 17 • Added missing mu symbol to the value of the LSB, 76.3V ................................................................................................ 18 Changes from Revision B (May 2008) to Revision C ...................................................................................................... Page • Changed 2nd timing diagram from the top in Figure 1 ......................................................................................................... 8 Submit Documentation Feedback Copyright © 2007–2009, Texas Instruments Incorporated Product Folder Link(s): ADS8317 25 PACKAGE OPTION ADDENDUM www.ti.com 18-Oct-2013 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) ADS8317IBDGKR ACTIVE VSSOP DGK 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU | CU NIPDAUAG Level-2-260C-1 YEAR -40 to 85 D17 ADS8317IBDGKRG4 ACTIVE VSSOP DGK 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 D17 ADS8317IBDGKT ACTIVE VSSOP DGK 8 250 Green (RoHS & no Sb/Br) CU NIPDAU | CU NIPDAUAG Level-2-260C-1 YEAR -40 to 85 D17 ADS8317IBDGKTG4 ACTIVE VSSOP DGK 8 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 D17 ADS8317IBDRBR ACTIVE SON DRB 8 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 D17 ADS8317IBDRBT ACTIVE SON DRB 8 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 D17 ADS8317IDGKR ACTIVE VSSOP DGK 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU | CU NIPDAUAG Level-2-260C-1 YEAR -40 to 85 D17 ADS8317IDGKRG4 ACTIVE VSSOP DGK 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 D17 ADS8317IDGKT ACTIVE VSSOP DGK 8 250 Green (RoHS & no Sb/Br) CU NIPDAU | CU NIPDAUAG Level-2-260C-1 YEAR -40 to 85 D17 ADS8317IDGKTG4 ACTIVE VSSOP DGK 8 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 D17 ADS8317IDRBR ACTIVE SON DRB 8 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 D17 ADS8317IDRBT ACTIVE SON DRB 8 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 D17 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 18-Oct-2013 Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. 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Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 6-Nov-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing ADS8317IBDGKR VSSOP DGK 8 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 ADS8317IBDGKT VSSOP DGK 8 250 180.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 ADS8317IBDRBR SON DRB 8 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2 ADS8317IBDRBT SON DRB 8 250 180.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2 ADS8317IDGKR VSSOP DGK 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 ADS8317IDGKT VSSOP DGK 8 250 180.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 ADS8317IDRBR SON DRB 8 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2 ADS8317IDRBT SON DRB 8 250 180.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 6-Nov-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) ADS8317IBDGKR VSSOP DGK 8 2500 367.0 367.0 35.0 ADS8317IBDGKT VSSOP DGK 8 250 210.0 185.0 35.0 ADS8317IBDRBR SON DRB 8 3000 338.1 338.1 20.6 ADS8317IBDRBT SON DRB 8 250 210.0 185.0 35.0 ADS8317IDGKR VSSOP DGK 8 2500 367.0 367.0 35.0 ADS8317IDGKT VSSOP DGK 8 250 210.0 185.0 35.0 ADS8317IDRBR SON DRB 8 3000 338.1 338.1 20.6 ADS8317IDRBT SON DRB 8 250 210.0 185.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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