Dual, 256-Position, SPI Digital Potentiometer AD5162 2-channel, 256-position potentiometer End-to-end resistance: 2.5 kΩ, 10 kΩ, 50 kΩ, and 100 kΩ Compact 10-lead MSOP (3 mm × 4.9 mm) package Fast settling time: tS = 5 µs typical on power-up Full read/write of wiper register Power-on preset to midscale Computer software replaces microcontroller in factory programming applications Single supply: 2.7 V to 5.5 V Low temperature coefficient: 35 ppm/°C Low power: IDD = 6 µA maximum Wide operating temperature: −40°C to +125°C Evaluation board available Qualified for automotive applications FUNCTIONAL BLOCK DIAGRAM A1 W1 B1 W2 B2 VDD WIPER REGISTER 1 WIPER REGISTER 2 A=0 A=1 GND AD5162 CLK SDI CS SPI INTERFACE 04108-0-001 FEATURES Figure 1. APPLICATIONS Systems calibrations Electronics level settings Mechanical trimmers replacement in new designs Permanent factory PCB setting Transducer adjustment of pressure, temperature, position, chemical, and optical sensors RF amplifier biasing Automotive electronics adjustment Gain control and offset adjustment GENERAL DESCRIPTION The AD5162 provides a compact 3 mm × 4.9 mm packaged solution for dual, 256-position adjustment applications. This device performs the same electronic adjustment function as a 3-terminal mechanical potentiometer. Available in four end-toend resistance values (2.5 kΩ, 10 kΩ, 50 kΩ, 100 kΩ), this low temperature coefficient device is ideal for high accuracy and stability-variable resistance adjustments. The wiper settings are controllable through an SPI digital interface. The resistance between the wiper and either endpoint of the fixed resistor varies linearly with respect to the digital code transferred into the RDAC latch.1 Operating from a 2.7 V to 5.5 V power supply and consuming less than 6 µA allows the AD5162 to be used in portable batteryoperated applications. For applications that program the AD5162 at the factory, Analog Devices offers device programming software running on Windows® NT/2000/XP operating systems. This software effectively replaces the need for external SPI controllers, which in turn enhances the time to market of systems. An AD5162 evaluation kit and software are available. The kit includes a cable and instruction manual. 1 The terms digital potentiometer, VR, and RDAC are used interchangeably. Rev. C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. www.analog.com Tel: 781.329.4700 Fax: 781.461.3113 ©2003–2010 Analog Devices, Inc. All rights reserved. AD5162 TABLE OF CONTENTS Features .............................................................................................. 1 Theory of Operation ...................................................................... 13 Applications ....................................................................................... 1 Programming the Variable Resistor and Voltage ................... 13 Functional Block Diagram .............................................................. 1 Programming the Potentiometer Divider ............................... 14 General Description ......................................................................... 1 ESD Protection ........................................................................... 14 Revision History ............................................................................... 2 Terminal Voltage Operating Range ......................................... 14 Specifications..................................................................................... 3 Power-Up Sequence ................................................................... 14 Electrical Characteristics: 2.5 kΩ Version ................................. 3 Layout and Power Supply Bypassing ....................................... 15 Electrical Characteristics: 10 kΩ, 50 kΩ, and 100 kΩ Versions ......................................................................................................... 4 Constant Bias to Retain Resistance Setting............................. 15 Timing Characteristics: All Versions ......................................... 5 SPI Interface .................................................................................... 16 Absolute Maximum Ratings ............................................................ 6 SPI-Compatible, 3-Wire Serial Bus.......................................... 16 ESD Caution .................................................................................. 6 Outline Dimensions ....................................................................... 17 Pin Configuration and Function Descriptions ............................. 7 Ordering Guide .......................................................................... 17 Typical Performance Characteristics ............................................. 8 Automotive Products ................................................................. 17 Evaluation Board ........................................................................ 15 Test Circuits ..................................................................................... 12 REVISION HISTORY 12/10—Rev. B to Rev.C Added Automotive Parts to Features Section ............................... 1 Added Automotive Products Paragraph...................................... 17 4/09—Rev. A to Rev. B Changes to Features Section............................................................ 1 Changes to DC Characteristics—Rheostat Mode Parameter and to DC Characteristics—Potentiometer Divider Mode Parameter, Table 1 ................................................................................................ 3 Updated Outline Dimensions ....................................................... 17 Changes to Ordering Guide .......................................................... 17 11/03—Rev. 0 to Rev. A Changes to Electrical Characteristics ............................................ 3 11/03—Revision 0: Initial Version Rev. C | Page 2 of 20 AD5162 SPECIFICATIONS ELECTRICAL CHARACTERISTICS: 2.5 kΩ VERSION VDD = 5 V ± 10%, or 3 V ± 10%; VA = VDD; VB = 0 V; −40°C < TA < +125°C; unless otherwise noted. Table 1. Parameter DC CHARACTERISTICS—RHEOSTAT MODE Resistor Differential Nonlinearity2 Resistor Integral Nonlinearity2 Nominal Resistor Tolerance3 Resistance Temperature Coefficient Wiper Resistance DC CHARACTERISTICS—POTENTIOMETER DIVIDER MODE4 Differential Nonlinearity5 Integral Nonlinearity5 Voltage Divider Temperature Coefficient Full-Scale Error Zero-Scale Error RESISTOR TERMINALS Voltage Range6 Capacitance A, B7 Capacitance W7 Common-Mode Leakage DIGITAL INPUTS AND OUTPUTS Input Logic High Input Logic Low Input Logic High Input Logic Low Input Current Input Capacitance7 POWER SUPPLIES Power Supply Range Supply Current Power Dissipation8 Power Supply Sensitivity DYNAMIC CHARACTERISTICS9 Bandwidth, −3 dB Total Harmonic Distortion VW Settling Time Resistor Noise Voltage Density Symbol Conditions Min Typ 1 Max Unit R-DNL R-INL ∆RAB (∆RAB/RAB )/∆T RWB RWB, VA = no connect RWB, VA = no connect TA = 25°C VAB = VDD, wiper = no connect Code = 0x00, VDD = 5 V −2 −14 −20 ±0.1 ±2 +2 +14 +55 LSB LSB % ppm/°C Ω DNL INL (∆VW/VW)/∆T Code = 0x80 VWFSE VWZSE Code = 0xFF Code = 0x00 VA, VB, VW CA, CB CW ICM VIH VIL VIH VIL IIL CIL 35 160 −1.5 −2 ±0.1 ±0.6 15 +1.5 +2 LSB LSB ppm/°C −14 0 −5.5 4.5 0 12 LSB LSB VDD 45 V pF 60 pF 1 nA GND f = 1 MHz, measured to GND, code = 0x80 f = 1 MHz, measured to GND, code = 0x80 VA = VB = VDD/2 VDD = 5 V VDD = 5 V VDD = 3 V VDD = 3 V VIN = 0 V or 5 V 200 2.4 0.8 2.1 0.6 ±1 5 VDD RANGE IDD PDISS PSS VIH = 5 V or VIL = 0 V VIH = 5 V or VIL = 0 V, VDD = 5 V VDD = 5 V ± 10%, code = midscale 2.7 3.5 BW THDW tS eN_WB Code = 0x80 VA = 1 V rms, VB = 0 V, f = 1 kHz VA = 5 V, VB = 0 V, ±1 LSB error band RWB = 1.25 kΩ, RS = 0 4.8 0.1 1 3.2 1 ±0.02 5.5 6 30 ±0.08 V V V V µA pF V µA µW %/% MHz % µs nV/√Hz Typical specifications represent average readings at 25°C and VDD = 5 V. Resistor position nonlinearity error, R-INL, is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. R-DNL measures the relative step change from the ideal between successive tap positions. Parts are guaranteed monotonic. 3 VA = VDD, VB = 0 V, wiper (VW) = no connect. 4 Specifications apply to all VRs. 5 INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output DAC. VA = VDD and VB = 0 V. DNL specification limits of ±1 LSB maximum are guaranteed monotonic operating conditions. 6 Resistor Terminal A, Resistor Terminal B, and Resistor Terminal W have no limitations on polarity with respect to each other. 7 Guaranteed by design, but not subject to production test. 8 PDISS is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation. 9 All dynamic characteristics use VDD = 5 V. 2 Rev. C | Page 3 of 20 AD5162 ELECTRICAL CHARACTERISTICS: 10 kΩ, 50 kΩ, AND 100 kΩ VERSIONS VDD = 5 V ± 10%, or 3 V ± 10%; VA = VDD; VB = 0 V; −40°C < TA < 125°C; unless otherwise noted. Table 2. Parameter DC CHARACTERISTICS—RHEOSTAT MODE Resistor Differential Nonlinearity2 Resistor Integral Nonlinearity2 Nominal Resistor Tolerance3 Resistance Temperature Coefficient Wiper Resistance DC CHARACTERISTICS—POTENTIOMETER DIVIDER MODE4 Differential Nonlinearity5 Integral Nonlinearity5 Voltage Divider Temperature Coefficient Full-Scale Error Zero-Scale Error RESISTOR TERMINALS Voltage Range6 Capacitance A, B7 Capacitance W7 Common-Mode Leakage DIGITAL INPUTS AND OUTPUTS Input Logic High Input Logic Low Input Logic High Input Logic Low Input Current Input Capacitance POWER SUPPLIES Power Supply Range Supply Current Power Dissipation Power Supply Sensitivity DYNAMIC CHARACTERISTICS Bandwidth, −3 dB Symbol Conditions Min Typ1 Max Unit R-DNL R-INL ∆RAB (∆RAB/RAB )/∆T RWB RWB, VA = no connect RWB, VA = no connect TA = 25°C VAB = VDD, wiper = no connect Code = 0x00, VDD = 5 V −1 −2.5 −20 ±0.1 ±0.25 +1 +2.5 +20 LSB LSB % ppm/°C Ω DNL INL (∆VW/VW)/∆T VWFSE VWZSE VA, VB, VW CA, CB CW ICM VIH VIL VIH VIL IIL CIL VDD RANGE IDD PDISS PSS BW Total Harmonic Distortion THDW VW Settling Time tS Resistor Noise Voltage Density eN_WB 35 160 −1 −1 Code = 0x80 Code = 0xFF Code = 0x00 −2.5 0 ±0.1 ±0.3 15 −1 1 GND f = 1 MHz, measured to GND, code = 0x80 f = 1 MHz, measured to GND, code = 0x80 VA = VB = VDD/2 VDD = 5 V VDD = 5 V VDD = 3 V VDD = 3 V VIN = 0 V or 5 V 200 +1 +1 0 2.5 VDD LSB LSB ppm/°C LSB LSB 45 V pF 60 pF 1 nA 2.4 0.8 2.1 0.6 ±1 5 2.7 5.5 6 30 ±0.08 V V V V µA pF V µA µW %/% VIH = 5 V or VIL = 0 V VIH = 5 V or VIL = 0 V, VDD = 5 V VDD = 5 V ± 10%, code = midscale 3.5 RAB = 10 kΩ/50 kΩ/100 kΩ, code = 0x80 VA = 1 V rms, VB = 0 V, f = 1 kHz, RAB = 10 kΩ VA = 5 V, VB = 0 V, ±1 LSB error band RWB = 5 kΩ, RS = 0 600/100/40 kHz 0.1 % 2 µs 9 nV/√Hz 1 ±0.02 Typical specifications represent average readings at 25°C and VDD = 5 V. Resistor position nonlinearity error, R-INL, is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. R-DNL measures the relative step change from the ideal between successive tap positions. Parts are guaranteed monotonic. 3 VA = VDD, VB = 0 V, wiper (VW) = no connect. 4 Specifications apply to all VRs. 5 INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output DAC. VA = VDD and VB = 0 V. DNL specification limits of ±1 LSB maximum are guaranteed monotonic operating conditions. 6 Resistor Terminal A, Resistor Terminal B, and Resistor Terminal W have no limitations on polarity with respect to each other. 7 Guaranteed by design, but not subject to production test. 2 Rev. C | Page 4 of 20 AD5162 TIMING CHARACTERISTICS: ALL VERSIONS VDD = 5 V ± 10%, or 3 V ± 10%; VA = VDD; VB = 0 V; −40°C < TA < +125°C; unless otherwise noted. Table 3. Parameter SPI INTERFACE TIMING CHARACTERISTICS1 Clock Frequency Input Clock Pulse Width Data Setup Time Data Hold Time CS Setup Time CS High Pulse Width CLK Fall to CS Fall Hold Time CLK Fall to CS Rise Hold Time CS Rise to Clock Rise Setup 1 Symbol fCLK tCH, tCL tDS tDH tCSS tCSW tCSH0 tCSH1 tCS1 Conditions Min Clock level high or low 20 5 5 15 40 0 0 10 See the timing diagrams for the locations of measured values (that is, see Figure 42 and Figure 43). Rev. C | Page 5 of 20 Typ Max Unit 25 MHz ns ns ns ns ns ns ns ns AD5162 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 4. Parameter VDD to GND VA, VB, VW to GND Terminal Current, Ax to Bx, Ax to Wx, Bx to Wx1 Pulsed Continuous Digital Inputs and Output Voltage to GND Operating Temperature Range Maximum Junction Temperature (TJMAX) Storage Temperature Lead Temperature (Soldering, 10 sec) Thermal Resistance, θJA for 10-Lead MSOP2 Rating –0.3 V to +7 V VDD ±20 mA ±5 mA 0 V to 7 V –40°C to +125°C 150°C –65°C to +150°C 300°C 230°C/W Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION 1 The maximum terminal current is bound by the maximum current handling of the switches, the maximum power dissipation of the package, and the maximum applied voltage across any two of the A, B, and W terminals at a given resistance. 2 The package power dissipation is (TJMAX − TA)/θJA. Rev. C | Page 6 of 20 AD5162 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS B1 1 10 W1 9 B2 W2 3 AD5162 GND 4 TOP VIEW VDD 5 8 CS 7 SDI 6 CLK 04108-0-002 A1 2 Figure 2. Table 5. Pin Function Descriptions Pin No. 1 2 3 4 5 6 7 8 9 10 Mnemonic B1 A1 W2 GND VDD CLK SDI CS B2 W1 Description B1 Terminal. A1 Terminal. W2 Terminal. Digital Ground. Positive Power Supply. Serial Clock Input. Positive-edge triggered. Serial Data Input. Chip Select Input, Active Low. When CS returns high, data is loaded into the DAC register. B2 Terminal. W1 Terminal. Rev. C | Page 7 of 20 AD5162 TYPICAL PERFORMANCE CHARACTERISTICS 2.0 0.5 TA = 25°C RAB = 10kΩ 1.0 VDD = 2.7V 0.5 0 VDD = 5.5V –0.5 RAB = 10kΩ 0.4 POTENTIOMETER MODE DNL (LSB) –1.0 –1.5 0.3 0.2 0.1 VDD = 2.7V; TA = –40°C, +25°C, +85°C, +125°C 0 –0.1 –0.2 –0.3 32 64 96 128 160 192 224 256 CODE (DECIMAL) –0.5 04108-0-003 0 0 32 128 160 192 224 256 Figure 6. DNL vs. Code vs. Temperature 1.0 0.5 TA = 25°C RAB = 10kΩ 0.3 0.2 VDD = 2.7V 0.1 0 –0.1 –0.2 VDD = 5.5V –0.3 TA = 25°C RAB = 10kΩ 0.8 POTENTIOMETER MODE INL (LSB) 0.4 0.6 0.4 VDD = 5.5V 0.2 0 VDD = 2.7V –0.2 –0.4 –0.6 –0.8 –0.4 0 32 64 96 128 160 192 224 256 CODE (DECIMAL) –1.0 04108-0-004 –0.5 0 32 64 96 128 160 192 224 256 CODE (DECIMAL) 04108-0-007 RHEOSTAT MODE DNL (LSB) 96 CODE (DECIMAL) Figure 3. R-INL vs. Code vs. Supply Voltages Figure 7. INL vs. Code vs. Supply Voltages Figure 4. R-DNL vs. Code vs. Supply Voltages 0.5 0.5 RAB = 10kΩ 0.3 VDD = 5.5V TA = –40°C, +25°C, +85°C, +125°C 0.2 0.1 0 –0.1 VDD = 2.7V TA = –40°C, +25°C, +85°C, +125°C –0.2 TA = 25°C RAB = 10kΩ 0.4 POTENTIOMETER MODE DNL (LSB) 0.4 –0.3 0.3 0.2 0.1 VDD = 2.7V 0 –0.1 VDD = 5.5V –0.2 –0.3 –0.4 –0.4 –0.5 0 32 64 96 128 160 192 CODE (DECIMAL) 224 256 04108-0-005 POTENTIOMETER MODE INL (LSB) 64 04108-0-006 –0.4 –2.0 –0.5 0 32 64 96 128 160 192 224 CODE (DECIMAL) Figure 8. DNL vs. Code vs. Supply Voltages Figure 5. INL vs. Code vs. Temperature Rev. C | Page 8 of 20 256 04108-0-008 RHEOSTAT MODE INL (LSB) 1.5 AD5162 2.0 4.50 RAB = 10kΩ RAB = 10kΩ 1.0 0.5 0 VDD = 5.5V TA = –40°C, +25°C, +85°C, +125°C –0.5 –1.0 –1.5 0 32 64 96 128 160 192 224 256 CODE (DECIMAL) 3.00 2.25 VDD = 2.7V, VA = 2.7V 1.50 VDD = 5.5V, VA = 5.0V 0.75 0 –40 04108-0-009 –2.0 3.75 –10 5 20 35 50 65 80 95 110 125 TEMPERATURE (°C) Figure 9. R-INL vs. Code vs. Temperature Figure 12. Zero-Scale Error vs. Temperature 10 0.5 RAB = 10kΩ 0.4 0.3 0.2 IDD, SUPPLY CURRENT (µA) RHEOSTAT MODE DNL (LSB) –25 04108-0-012 VDD = 2.7V TA = –40°C, +25°C, +85°C, +125°C ZSE, ZERO-SCALE ERROR (LSB) RHEOSTAT MODE INL (LSB) 1.5 VDD = 2.7V, 5.5V; TA = –40°C, +25°C, +85°C, +125°C 0.1 0 –0.1 –0.2 VDD = 5V 1 VDD = 3V –0.3 32 64 96 128 160 192 224 256 CODE (DECIMAL) 0.1 –40 –7 26 59 92 Figure 10. R-DNL vs. Code vs. Temperature Figure 13. Supply Current vs. Temperature 120 2.0 RAB = 10kΩ RAB = 10kΩ RHEOSTAT MODE TEMPCO (ppm/°C) 1.0 0.5 0 VDD = 5.5V, VA = 5.0V –0.5 VDD = 2.7V, VA = 2.7V –1.0 –1.5 –25 –10 5 20 35 50 65 80 95 TEMPERATURE (°C) 110 125 04108-0-011 FSE, FULL-SCALE ERROR (LSB) 1.5 –2.0 –40 125 TEMPERATURE (°C) 100 80 VDD = 2.7V TA = –40°C TO +85°C, –40°C TO +125°C 60 40 VDD = 5.5V TA = –40°C TO +85°C, –40°C TO +125°C 20 0 –20 0 32 64 96 128 160 192 224 CODE (DECIMAL) Figure 14. Rheostat Mode Tempco ΔRWB/ΔT vs. Code Figure 11. Full-Scale Error vs. Temperature Rev. C | Page 9 of 20 256 04108-0-014 0 04108-0-010 –0.5 04108-0-013 –0.4 AD5162 0 RAB = 10kΩ 0x80 –6 40 0x40 –12 30 GAIN (dB) 20 0x20 –18 VDD = 2.7V TA = –40°C TO +85°C, –40°C TO +125°C 10 0 0x10 –24 0x08 –30 0x04 –36 0x02 –42 –10 0x01 VDD = 5.5V TA = –40°C TO +85°C, –40°C TO +125°C –48 –20 0 32 64 96 128 160 192 224 256 CODE (DECIMAL) –60 1k 10k Figure 15. Potentiometer Mode Tempco ΔVWB/ΔT vs. Code 1M Figure 18. Gain vs. Frequency vs. Code, RAB = 50 kΩ 0 0 0x80 –6 0x80 –6 0x40 –12 0x40 –12 0x20 –18 0x20 –18 –24 GAIN (dB) 0x10 GAIN (dB) 100k FREQUENCY (Hz) 04108-0-018 –54 –30 04108-0-015 POTENTIOMETER MODE TEMPCO (ppm/°C) 50 0x08 0x04 –30 –36 0x02 0x01 –42 0x10 –24 0x08 –30 0x04 –36 0x02 –42 –48 –54 –54 100k 1M 10M FREQUENCY (Hz) –60 04108-0-016 –60 10k 1k 100k 1M FREQUENCY (Hz) Figure 16. Gain vs. Frequency vs. Code, RAB = 2.5 kΩ Figure 19. Gain vs. Frequency vs. Code, RAB = 100 kΩ 0 0 0x80 –12 0x40 –18 0x20 –6 –12 GAIN (dB) 0x10 –24 0x08 –30 0x04 –36 0x02 0x01 –42 10kΩ 570kHz 2.5kΩ 2.2MHz –30 –36 –42 –54 –60 100k FREQUENCY (Hz) 1M 04108-0-017 –48 –54 10k 50kΩ 120kHz –24 –48 1k 100kΩ 60kHz –18 Figure 17. Gain vs. Frequency vs. Code, RAB = 10 kΩ –60 1k 10k 100k 1M FREQUENCY (Hz) Figure 20. −3 dB Bandwidth at Code = 0x80 Rev. C | Page 10 of 20 10M 04108-0-020 –6 GAIN (dB) 10k 04108-0-019 0x01 –48 AD5162 10 1 VDD = 5.5V VW2 0.1 VDD = 2.7V 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 DIGITAL INPUT VOLTAGE (V) 5.0 04108-0-025 0.01 04108-0-024 VW1 Figure 24. Analog Crosstalk Figure 21. Supply Current vs. Digital Input Voltage VW VW 04108-0-021 04108-0-026 CLK VW2 VW VW1 CS Figure 23. Digital Crosstalk 04108-0-023 Figure 25. Midscale Glitch, Code 0x80 to Code 0x7F Figure 22. Digital Feedthrough 04108-0-022 IDD, SUPPLY CURRENT (mA) TA = 25°C Figure 26. Large-Signal Settling Time Rev. C | Page 11 of 20 AD5162 TEST CIRCUITS Figure 27 through Figure 32 illustrate the test circuits that define the test conditions used in the product specification tables (see Table 1 and Table 2). VA VMS ( W V+ B ∆VMS PSRR (dB) = 20 LOG ∆VDD ∆VMS% PSS (%/%) = ∆VDD% A B Figure 27. Test Circuit for Potentiometer Divider Nonlinearity Error (INL, DNL) VMS Figure 30. Test Circuit for Power Supply Sensitivity (PSS, PSSR) NO CONNECT DUT DUT A IW A W +15V W VIN AD8610 B OFFSET GND 04108-0-028 B VMS ) –15V 2.5V Figure 28. Test Circuit for Resistor Position Nonlinearity Error (Rheostat Operation: R-INL, R-DNL) VOUT 04108-0-031 V+ ∆VDD W 04108-0-027 A V+ = VDD ± 10% DUT 04108-0-030 V+ = VDD 1LSB = V+/2N DUT Figure 31. Test Circuit for Gain vs. Frequency NC W VMS2 IW = VDD/RNOMINAL B RW = [VMS1 – VMS2]/IW VMS1 A VDD VW GND 04108-0-029 A DUT B NC Figure 29. Test Circuit for Wiper Resistance ICM W VCM NC = NO CONNECT 04108-0-033 DUT Figure 32. Test Circuit for Common-Mode Leakage Current Rev. C | Page 12 of 20 AD5162 THEORY OF OPERATION The AD5162 is a 256-position, digitally controlled variable resistor (VR) device. The general equation determining the digitally programmed output resistance between W and B is An internal power-on preset places the wiper at midscale during power-on, which simplifies the fault condition recovery at power-up. PROGRAMMING THE VARIABLE RESISTOR AND VOLTAGE Rheostat Operation The nominal resistance of the RDAC between Terminal A and Terminal B is available in 2.5 kΩ, 10 kΩ, 50 kΩ, and 100 kΩ. The nominal resistance (RAB) of the VR has 256 contact points accessed by the wiper terminal and the B terminal contact. The 8-bit data in the RDAC latch is decoded to select one of the 256 possible settings. A A B B W 04108-0-034 W B Figure 33. Rheostat Mode Configuration Assuming that a 10 kΩ part is used, the first connection of the wiper starts at the B terminal for Data 0x00. Because there is a 50 Ω wiper contact resistance, such a connection yields a minimum of 100 Ω (2 × 50 Ω) resistance between Terminal W and Terminal B. The second connection is the first tap point, which corresponds to 139 Ω (RWB = RAB/256 + 2 × RW = 39 Ω + 2 × 50 Ω) for Data 0x01. The third connection is the next tap point, representing 178 Ω (2 × 39 Ω + 2 × 50 Ω) for Data 0x02, and so on. Each LSB data value increase moves the wiper up the resistor ladder until the last tap point is reached at 10,100 Ω (RAB + 2 × RW). A RS (1) In summary, if RAB is 10 kΩ and the A terminal is open circuited, the output resistance, RWB, is set according to the RDAC latch codes, as listed in Table 6. Table 6. Codes and Corresponding RWB Resistance RWB (Ω) 9961 5060 139 100 Output State Full scale (RAB − 1 LSB + RW) Midscale 1 LSB Zero scale (wiper contact resistance) Note that in the zero-scale condition, a finite wiper resistance of 100 Ω is present. Care should be taken to limit the current flow between W and B in this state to a maximum pulse current of no more than 20 mA. Otherwise, degradation or possible destruction of the internal switch contact may occur. Similar to the mechanical potentiometer, the resistance of the RDAC between Wiper W and Terminal A also produces a digitally controlled complementary resistance, RWA. When these terminals are used, the B terminal can be opened. Setting the resistance value for RWA starts at a maximum value of resistance and decreases as the data loaded in the latch increases in value. The general equation for this operation is RWA (D) = D7 D6 D5 D4 D3 D2 D1 D0 D × RAB + 2 × RW 256 where: D is the decimal equivalent of the binary code loaded in the 8-bit RDAC register. RAB is the end-to-end resistance. RW is the wiper resistance contributed by the on resistance of the internal switch. D (Dec) 255 128 1 0 A W RWB (D) = RS 256 − D × RAB + 2 × RW 256 (2) When RAB is 10 kΩ and the B terminal is open circuited, the output resistance, RWA, is set according to the RDAC latch codes, as listed in Table 7. RS W Table 7. Codes and Corresponding RWA Resistance RDAC RS B 04108-0-035 LATCH AND DECODER Figure 34. AD5162 Equivalent RDAC Circuit D (Dec) 255 128 1 0 RWA (Ω) 139 5060 9961 10,060 Output State Full scale Midscale 1 LSB Zero scale Typical device-to-device matching is process-lot dependent and may vary by up to ±30%. Because the resistance element is processed in thin-film technology, the change in RAB with temperature has a very low temperature coefficient of 35 ppm/°C. Rev. C | Page 13 of 20 AD5162 PROGRAMMING THE POTENTIOMETER DIVIDER ESD PROTECTION Voltage Output Operation All digital inputs are protected with a series of input resistors and parallel Zener ESD structures, as shown in Figure 36 and Figure 37. This applies to the SDI, CLK, and CS digital input pins. 340Ω LOGIC GND VI Figure 36. ESD Protection of Digital Pins A GND Figure 35. Potentiometer Mode Configuration Figure 37. ESD Protection of Resistor Terminals If ignoring the effect of the wiper resistance for approximation, connecting the A terminal to 5 V and the B terminal to ground produces an output voltage at the wiper to B, starting at 0 V up to 1 LSB less than 5 V. Each LSB of voltage is equal to the voltage applied across the A and B terminals divided by the 256 positions of the potentiometer divider. The general equation defining the output voltage at VW with respect to ground for any valid input voltage applied to Terminal A and Terminal B is 256 − D D VA + VB 256 256 TERMINAL VOLTAGE OPERATING RANGE The AD5162 VDD and GND power supply defines the boundary conditions for proper 3-terminal digital potentiometer operation. Supply signals present on the A, B, and W terminals that exceed VDD or GND are clamped by the internal forward-biased diodes (see Figure 38). VDD (3) A W A more accurate calculation, which includes the effect of wiper resistance, VW, is VW (D) = R (D ) RWB (D) VA + WA VB RAB RAB B GND (4) Operation of the digital potentiometer in the divider mode results in more accurate operation over temperature. Unlike in the rheostat mode, the output voltage is dependent mainly on the ratio of the internal resistors RWA and RWB, not on the absolute values. Therefore, the temperature drift reduces to 15 ppm/°C. 04108-0-039 B 04108-0-038 A, B, W VO 04108-0-036 W VW (D) = 04108-0-037 The digital potentiometer easily generates a voltage divider at wiper to B and wiper to A, proportional to the input voltage at A to B. Unlike the polarity of VDD to GND, which must be positive, voltage across A to B, W to A, and W to B can be at either polarity. Figure 38. Maximum Terminal Voltages Set by VDD and GND POWER-UP SEQUENCE Because the ESD protection diodes limit the voltage compliance at the A, B, and W terminals (see Figure 38), it is important to power VDD/GND before applying voltage to the A, B, and W terminals; otherwise, the diode is forward-biased such that VDD is powered unintentionally and may affect the rest of the user’s circuit. The ideal power-up sequence is in the following order: GND, VDD, digital inputs, and then VA, VB, VW. The relative order of powering VA, VB, VW, and the digital inputs is not important, as long as they are powered after VDD/GND. Rev. C | Page 14 of 20 AD5162 110 LAYOUT AND POWER SUPPLY BYPASSING TA = 25°C 106 104 102 100 98 96 94 92 90 0 5 10 15 DAYS 20 25 30 04108-0-041 Similarly, it is also good practice to bypass the power supplies with quality capacitors for optimum stability. Supply leads to the device should be bypassed with disc or chip ceramic capacitors of 0.01 μF to 0.1 μF. Low ESR 1 μF to 10 μF tantalum or electrolytic capacitors should also be applied at the supplies to minimize any transient disturbance and low frequency ripple (see Figure 39). In addition, note that the digital ground should be joined remotely to the analog ground at one point to minimize the ground bounce. 108 BATTERY LIFE DEPLETED (%) It is good practice to employ compact, minimum lead length layout design. The leads to the inputs should be as direct as possible with a minimum conductor length. Ground paths should have low resistance and low inductance. Figure 40. Battery Operating Life Depletion VDD C3 10F + EVALUATION BOARD VDD C1 0.1F An evaluation board, along with all necessary software, is available to program the AD5162 from any PC running Windows® 98/2000/XP. The graphical user interface, as shown in Figure 41, is straightforward and easy to use. More detailed information is available in the user manual, which is supplied with the board. AD5162 04108-0-040 GND Figure 39. Power Supply Bypassing For users who desire nonvolatility but cannot justify the additional cost of the EEMEM, the AD5162 can be considered a low cost alternative by maintaining a constant bias to retain the wiper setting. The AD5162 is designed specifically for low power applications, allowing low power consumption even in batteryoperated systems. The graph in Figure 40 demonstrates the power consumption from a 3.4 V, 450 mAhr Li-Ion cell phone battery connected to the AD5162. The measurement over time shows that the device draws approximately 1.3 μA and consumes negligible power. Over a course of 30 days, the battery is depleted by less than 2%, the majority of which is due to the intrinsic leakage current of the battery itself. This demonstrates that constantly biasing the potentiometer can be a practical approach. Most portable devices do not require the removal of batteries for the purpose of charging. Although the resistance setting of the AD5162 is lost when the battery needs replacement, such events occur rather infrequently such that this inconvenience is justified by the lower cost and smaller size offered by the AD5162. If total power is lost, the user should be provided with a means to adjust the setting accordingly. 04108-0-044 CONSTANT BIAS TO RETAIN RESISTANCE SETTING Figure 41. AD5162 Evaluation Board Software The AD5162 starts at midscale upon power-up. To increment or decrement the resistance, simply move the scrollbars in the left of the software window (see Figure 41). To write a specific value, use the bit pattern in the upper part of the SDI Write Bit Control (Hit Run) box and then click Run. The format of writing data to the device is shown in Table 8. Rev. C | Page 15 of 20 AD5162 SPI INTERFACE SPI-COMPATIBLE, 3-WIRE SERIAL BUS Table 8. Serial Data-Word Format1 The AD5162 contains a 3-wire, SPI-compatible digital interface (SDI, CS, and CLK). The 9-bit serial word must be loaded MSB first. The format of the word is shown in Table 8. MSB B8 A0 (28) The positive-edge sensitive CLK input requires clean transitions to avoid clocking incorrect data into the serial input register. Standard logic families work well. If mechanical switches are used for product evaluation, they should be debounced by a flip-flop or another suitable means. When CS is low, the clock loads data into the serial register on each positive clock edge (see Figure 42). 1 B6 D6 B5 D5 B4 D4 B3 D3 Dx A0 D7 D6 D5 D4 D3 D2 D1 D0 CLK 0 1 RDAC REGISTER LOAD CS VOUT 04108-0-042 0 1 0 Figure 42. SPI Interface Timing Diagram (VA = 5 V, VB = 0 V, VW = VOUT) tDS tCS1 tCH CLK 0 tCL tCSH0 LSB B0 D0 (20) 0 1 Dx tCH 1 B1 D1 1 1 0 B2 D2 The values of bits are shown in parentheses. SDI The data setup and data hold times in Table 3 determine the valid timing requirements. The AD5162 uses a 9-bit serial input data register word that is transferred to the internal RDAC register when the CS line returns to logic high. Extra MSB bits are ignored. SDI (DATA IN) B7 D7 (27) tCSH1 tCSS 1 CS tCSW 0 ±1LSB VOUT 0 Figure 43. SPI Interface Detailed Timing Diagram (VA = 5 V, VB = 0 V, VW = VOUT) Rev. C | Page 16 of 20 04108-0-043 tS VDD AD5162 OUTLINE DIMENSIONS 3.10 3.00 2.90 10 3.10 3.00 2.90 1 5.15 4.90 4.65 6 5 PIN 1 IDENTIFIER 0.50 BSC 0.95 0.85 0.75 15° MAX 1.10 MAX 0.30 0.15 6° 0° 0.23 0.13 0.70 0.55 0.40 COMPLIANT TO JEDEC STANDARDS MO-187-BA 091709-A 0.15 0.05 COPLANARITY 0.10 Figure 44. 10-Lead Mini Small Outline Package [MSOP] (RM-10) Dimensions shown in millimeters ORDERING GUIDE Model1, 2, 3 AD5162BRM2.5 AD5162BRM2.5-RL7 AD5162BRM10 AD5162BRM50 AD5162BRM50-RL7 AD5162BRM100 AD5162BRM100-RL7 AD5162BRMZ2.5 AD5162BRMZ2.5-RL7 AD5162BRMZ10 AD5162BRMZ10-RL7 AD5162BRMZ50 AD5162BRMZ50-RL7 AD5162BRMZ100 AD5162BRMZ100-RL7 AD5162WBRMZ100-RL7 AD5162EVAL RAB (kΩ) 2.5 2.5 10 50 50 100 100 2.5 2.5 10 10 50 50 100 100 100 Temperature –40°C to +125°C –40°C to +125°C –40°C to +125°C –40°C to +125°C –40°C to +125°C –40°C to +125°C –40°C to +125°C –40°C to +125°C –40°C to +125°C –40°C to +125°C –40°C to +125°C –40°C to +125°C –40°C to +125°C –40°C to +125°C –40°C to +125°C –40°C to +125°C Package Description 10-Lead MSOP 10-Lead MSOP 10-Lead MSOP 10-Lead MSOP 10-Lead MSOP 10-Lead MSOP 10-Lead MSOP 10-Lead MSOP 10-Lead MSOP 10-Lead MSOP 10-Lead MSOP 10-Lead MSOP 10-Lead MSOP 10-Lead MSOP 10-Lead MSOP 10-Lead MSOP Evaluation Board Package Option RM-10 RM-10 RM-10 RM-10 RM-10 RM-10 RM-10 RM-10 RM-10 RM-10 RM-10 RM-10 RM-10 RM-10 RM-10 RM-10 Branding D0Q D0Q D0R D0S D0S D0T D0T D74 D74 D9K D9K D0S# D0S# D0T# D0T# D0T# 1 Z = RoHS Compliant Part. W = Qualified for Automotive Applications. 3 The evaluation board is shipped with the 10 k Ω RAB resistor option; however, the board is compatible with all available resistor value options. 2 AUTOMOTIVE PRODUCTS The AD5162W model is available with controlled manufacturing to support the quality and reliability requirements of automotive applications. Note that these automotive models may have specifications that differ from the commercial models; therefore, designers should review the Specifications section of this data sheet carefully. Only the automotive grade products shown are available for use in automotive applications. Contact your local Analog Devices account representative for specific product ordering information and to obtain the specific Automotive Reliability reports for these models. Rev. C | Page 17 of 20 AD5162 NOTES Rev. C | Page 18 of 20 AD5162 NOTES Rev. C | Page 19 of 20 AD5162 NOTES ©2003–2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D04108-0-12/10(C) Rev. C | Page 20 of 20