FEDL610Q426-01 Issue Date: Mar. 17, 2015 ML610Q426/ ML610426 8-bit Microcontroller with a Built-in LCD driver GENERAL DESCRIPTION This LSI is a high performance CMOS 8-bit microcontroller equipped with an 8-bit CPU nX-U8/100 and integrated with peripheral functions such as the synchronous serial port, UART, melody driver, RC oscillation type A/D converter, and LCD driver. The CPU nX-U8/100 is capable of efficient instruction execution in 1-instruction 1-clock mode by 3-stage pipe line architecture parallel procesing. Additionally, it adopts the low-/high-speed dual clock system, standby mode, and process that prohibits leak current at high temperatures, and is most suitable for battery-driven applications. Flash version can rewrite programs on-board, which can contribute to reduction in product development TAT. The flash memory incorporated into this Flash version implements the mask ROM-equivalent low-voltage operation and low-power consumption, enabling volume production by the Flash version. FEATURES • CPU − 8-bit RISC CPU (CPU name: nX-U8/100) − Instruction system: 16-bit instructions − Instruction set: Transfer, arithmetic operations, comparison, logic operations, multiplication/division, bit manipulations, bit logic operations, jump, conditional jump, call return stack manipulations, arithmetic shift, and so on − On-Chip debug function − Minimum instruction execution time 30.5 µs (@32.768 kHz system clock) 1.0 µs (@1 MHz system clock) • Internal memory ML610Q426 : − Internal 40KByte Flash ROM (20K×16 bits) (including unusable 1KByte TEST area) − Internal 2KByte Data RAM (2048×8 bits) − Internal 124-byte RAM for display ML610426 : − Internal 40KByte MASK ROM (20K×16 bits) (including unusable 1KByte TEST area) − Internal 2KByte Data RAM (2048×8 bits) − Internal 124-byte RAM for display • Interrupt controller ML610426, ML610Q426 : − 1 non-maskable interrupt sources (Internal source: 1) − 24 maskable interrupt sources (Internal sources: 19, External sources: 5) : ML610426/ML610Q426 − 27 maskable interrupt sources (Internal sources: 19, External sources: 8) : ML610Q426C • Time base counter − Low-speed time base counter ×1 channel Frequency compensation (Compensation range: Approx. −488ppm to +488ppm. Compensation accuracy: Approx. 0.48ppm) − High-speed time base counter ×1 channel 1/34 FEDL610Q426-01 ML610Q426/426 • Watchdog timer − Non-maskable interrupt and reset − Free running − Overflow period: 4 types selectable (125ms, 500ms, 2s, and 8s) • Timers − 8 bits × 4 channels (Timer0-3: 16-bit x 2 configuration available by using Timer0-1 or TimerI-J) − Clock frequency measurement mode (in one channel of 16-bit configuration using TimerI-J) − Continuous timer mode/One shot timer mode − Timer count start/stop by software and external trigger • 1 kHz timer − 10 Hz/1 Hz interrupt function • PWM − Resolution 16 bits × 1 channel − Continuous PWM mode/One shot PWM mode − PWM start/stop by software and external trigger • Synchronous serial port − Master/slave selectable × 2 channel − LSB first/MSB first selectable − 8-bit length/16-bit length selectable • UART − Half-Duplex Communication − TXD/RXD × 1 channel − Bit length, parity/no parity, odd parity/even parity, 1 stop bit/2 stop bits − Positive logic/negative logic selectable − Built-in baud rate generator • I2C bus interface − Master function only − Standard mode (50 kbps@1MHｚ, 100kbps@1MHz) • Melody driver − Scale: 29 types (Melody sound frequency: 508 Hz to 32.768 kHz) − Tone length: 63 types − Tempo: 15 types − Buzzer output mode (4 output modes, 8 frequencies, 16 duty levels) • RC oscillation type A/D converter − 16-bit counter − Time division x 1.5 channels • General-purpose ports ML610Q426, ML610426 : - Input-only port: 5 channels - Input/output port: 7 channels (including secondary functions) ML610Q426C : - Input-only port: 7 channels - Input/output port: 13 channels (including secondary functions) 2/34 FEDL610Q426-01 ML610Q426/426 • LCD driver − Number of segments (*) and duty ML610Q426/426: Up to 800 dots (select among 50seg x 16com, 51seg x 15com, 52seg x 14com, 53seg x 13com, 54seg x 12com, 55seg x 11com, 56seg x 10com, 57seg x 9com, 58seg x 8com, 59seg x 7com, 60seg x 6com, 61seg x 5com, and 62seg x 4com), 1/1 to 1/16 duty ML610Q426C: Up to 672 dots (select among 42seg x 16com, 43seg x 15com, 44seg x 14com, 45seg x 13com, 46seg x 12com, 47seg x 11com, 48seg x 10com, 49seg x 9com, 50seg x 8com, 51seg x 7com, 52seg x 6com, 53seg x 5com, and 54seg x 4com), 1/1 to 1/16 duty − 1/2, 1/3, 1/4 bias (built-in bias generation circuit) − 1/1 bias (LED mode) − Frame frequency selecable: approx. 64Hz, 73Hz, 85Hz, and 102Hz − Bias voltage multiplying clock selectable (8 types) − Contrast adjustment (1/1 bias, 1/2 bias, 1/3 bias: 16 steps, 1/4 bias: 10 steps) − LCD drive stop mode, LCD display mode, all LCDs on mode, and all LCDs off mode selectable (*) 8 segment pins are changed to general purpose port by mask option. • EL driver − pumping clock signal and discharge pulse signal output for the back light of LCD pannel and minimum external components • Reset − Reset by the RESET_N pin − Reset by power-on detection − Reset by the watchdog timer (WDT) 2nd overflow • Power supply voltage detect function − Judgment voltages: One of 16 levels − Judgment accuracy: ±2% (Typ.) − Input channels: Operating voltage(VDD) or 1 external input • Clock − Low-speed clock: (This LSI can not guarantee the operation withoug low-speed clock) Crystal oscillation (32.768 kHz) − High-speed clock: Built-in RC oscillation (1MHz) • Power management − HALT mode: Instruction execution by CPU is suspended (peripheral circuits are in operating states). − STOP mode: Stop of low-speed oscillation and high-speed oscillation (Operations of CPU and peripheral circuits are stopped.) − Clock gear: The frequency of high-speed system clock can be changed by software (1/1, 1/2, 1/4, or 1/8 of the oscillation clock) − Block Control Function: Power down (reset registers and stop clock supply) the circuits of unused peripherals. • Guaranteed operating range − Operating temperature: −20°C to 70°C − Operating voltage: VDD = 1.1V to 3.6V 3/34 FEDL610Q426-01 ML610Q426/426 • Product name – Supported Function The line-up of the ML610Q426 and the ML610426 is below. - Chip (Die) ML610Q426-xxxWA ROM type Operating temperature LCD driver Number of segment Product availability Flash ROM -20°C to +70°C Up to 800 dots Yes Yes ML610Q426P-xxxWA Flash ROM -40°C to +85°C Up to 800 dots ML610Q426C-xxxWA Flash ROM -20°C to +70°C Up to 672 dots ML610Q426PC-xxxWA Flash ROM -40°C to +85°C Up to 672 dots - ML610426-xxxWA Mask ROM -20°C to +70°C Up to 800 dots Yes ML610426P-xxxWA Mask ROM -40°C to +85°C Up to 800 dots - ML610426C-xxxWA Mask ROM -20°C to +70°C Up to 672 dots - ML610426PC-xxxWA Mask ROM -40°C to +85°C Up to 672 dots -100-pin plastic TQFP - ROM type Operating temperature LCD driver Number of segment Product availability ML610Q426-xxxTB Flash ROM -20°C to +70°C Up to 800 dots - ML610Q426P-xxxTB Flash ROM -40°C to +85°C Up to 800 dots - ML610Q426C-xxxTB Flash ROM -20°C to +70°C Up to 672 dots ML610Q426PC-xxxTB Flash ROM -40°C to +85°C Up to 672 dots - ML610426-xxxTB Mask ROM -20°C to +70°C Up to 800 dots ML610426P-xxxTB Mask ROM -40°C to +85°C Up to 800 dots - ML610426C-xxxTB Mask ROM -20°C to +70°C Up to 672 dots ML610426PC-xxxTB Mask ROM -40°C to +85°C Up to 672 dots xxx: ROM code number (xxx of the blank product is NNN) Q: Flash ROM version P: Wide range temperature version (P version) C: larger I/O and less LCD segment pin version by mask option (C version) WA: Chip (Die), TB: TQFP 4/34 FEDL610Q426-01 ML610Q426/426 BLOCK DIAGRAM ML610Q426/ML610426 Block Diagram Figure 1 shows the block diagram of the ML610Q426. "*" indicates the secondary function of each port. CPU (nX-U8/100) EPSW1～3 GREG 0～15 PSW Timing Controller On-Chip ICE Instruction Decoder DSR/CSR EA PC Instruction Register Data-bus RESET & TEST RAM 2048byte Interrupt Controller OSC LSCLK* OUTCLK* INT 1 Power Program Memory (Flash/Mask)(*3) 40Kbyte WDT Bus Controller INT 1 INT 1 INT 4 TBC SCK1* SIN1* SOUT1* UART RXD1* TXD1* I2C SDA* SCL* INT 1 INT 1 INT 1 PWM8* INT 1 Melody INT 5/8 (*2) MD0* P00 to P04 8bit Timer ×4 RC-ADC ×1 GPIO INT 1 VPP SSIO PWM INT 8 IN0* CS0* RS0* RT0* RCT0* RCM* LR SP XT0 XT1 VDDL VDDX ECSR1～3 ALU VDD VSS RESET_N TEST ELR1～3 P05 to P06 (*1) P50 to P53 (*1) P63 to P64 (*1) P65 to P66 P70 to P74 1kHz Timer LCD Driver COM0 to COM15 SEG0 to SEG61 Display register BLDI BLD Figure 1 EL Driver ELC* (*1) LCD BIAS VL1, VL2, VL3, VL4 ELP* (*1) C1, C2 ML610Q426 Block Diagram (*1) SEG0-7 are changed to these pins by mask option (only ML610Q426) SEG0-7 to I/O change by mask option increases from 5 interrupts to 8 interrupts (only ML610Q426) (*3) Flash ROM version : ML610Q426, Mask ROM version : ML610426. (*2) 5/34 FEDL610Q426-01 ML610Q426/426 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 SEG40 SEG41 SEG42 SEG43 SEG44 SEG45 ML610Q426 Chip Dimension SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 71 72 73 74 75 76 77 78 79 80 81 82 83 84 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 SEG0 85 86 87 88 89 90 91 92 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 SEG46 SEG47 SEG48 SEG49 COM15/SEG50 COM14/SEG51 COM13/SEG52 COM12/SEG53 COM11/SEG54 COM10/SEG55 COM9/SEG56 COM8/SEG57 COM7/SEG58 COM6/SEG59 COM5/SEG60 COM4/SEG61 COM3 COM2 COM1 COM0 2.50 mm 26 VPP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 P01 P02 P03 P04 P70 P71 P72 P73 P74 P65 P66 V DDL V SS XT0 XT1 V DDX V DD RESET_N TEST V L1 V L2 V L3 V L4 C1 C2 P00 93 2.50 mm Chip size: PAD count: Minimum PAD pitch: PAD aperture: Chip thickness: Voltage of the rear side of chip: Figure 2 Y X 2.50mm × 2.50mm 93 pins 80 µm 70 µm × 70 µm 350 µm VSS level ML610Q426 Chip Dimension 6/34 FEDL610Q426-01 ML610Q426/426 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 SEG40 SEG41 SEG42 SEG43 SEG44 SEG45 ML610Q426C Chip Dimension SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 71 72 73 74 75 76 77 78 79 80 81 82 83 84 P06 P05 P64 P63 P53 P52 P51 P50 85 86 87 88 89 90 91 92 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 SEG46 SEG47 SEG48 SEG49 COM15/SEG50 COM14/SEG51 COM13/SEG52 COM12/SEG53 COM11/SEG54 COM10/SEG55 COM9/SEG56 COM8/SEG57 COM7/SEG58 COM6/SEG59 COM5/SEG60 COM4/SEG61 COM3 COM2 COM1 COM0 2.50 mm 26 VPP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 P01 P02 P03 P04 P70 P71 P72 P73 P74 P65 P66 V DDL V SS XT0 XT1 V DDX V DD RESET_N TEST V L1 V L2 V L3 V L4 C1 C2 P00 93 2.50 mm Chip size: PAD count: Minimum PAD pitch: PAD aperture: Chip thickness: Voltage of the rear side of chip: Figure 3 Y X 2.50 mm × 2.50 mm 93 pins 80 µm 70 µm × 70 µm 350 µm VSS level ML610Q426C Chip Dimension 7/34 FEDL610Q426-01 ML610Q426/426 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 SEG40 SEG41 SEG42 SEG43 SEG44 SEG45 ML610426 Chip Dimension 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 P65 P66 V DDL V SS XT0 XT1 V DDX V DD RESET_N TEST V L1 V L2 V L3 V L4 C1 C2 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 P01 P02 P03 P04 P70 P71 P72 P73 P74 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 SEG0 P00 SEG46 SEG47 SEG48 SEG49 COM15/SEG50 COM14/SEG51 COM13/SEG52 COM12/SEG53 COM11/SEG54 COM10/SEG55 COM9/SEG56 COM8/SEG57 COM7/SEG58 COM6/SEG59 COM5/SEG60 COM4/SEG61 COM3 COM2 COM1 COM0 2.42 mm Chip size: PAD count: Minimum PAD pitch: PAD aperture: Chip thickness: Voltage of the rear side of chip: Figure 4 2.38mm Y X 2.42mm × 2.38mm 92 pins 80 µm 70 µm × 70 µm 350 µm VSS level ML610426 Chip Dimension 8/34 FEDL610Q426-01 ML610Q426/426 ML610Q426/ML610Q426C Pad Coordinates Table 1 Pad Coordinates of ML610Q426/ML610Q426C Chip Center: X=0,Y=0 PAD No. Pad Name 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 X (μm) P01 P02 P03 P04 P70 P71 P72 P73 P74 P65 P66 VDDL VSS XT0 XT1 VDDX VDD RESET_N TEST VL1 VL2 VL3 VL4 C1 C2 VPP COM0 COM1 COM2 COM3 COM4/SEG61 COM5/SEG60 COM6/SEG59 COM7/SEG58 COM8/SEG57 COM9/SEG56 COM10/SEG55 COM11/SEG54 COM12/SEG53 COM13/SEG52 COM14/SEG51 COM15/SEG50 SEG49 SEG48 SEG47 SEG46 SEG45 SEG44 SEG43 SEG42 -1055 -975 -895 -815 -735 -655 -575 -495 -415 -310 -230 -140 -60 20 180 260 340 420 500 620 700 780 860 940 1020 1144 1144 1144 1144 1144 1144 1144 1144 1144 1144 1144 1144 1144 1144 1144 1144 1144 1144 1144 1144 1144 880 800 720 640 Y (μm) -1144 -1144 -1144 -1144 -1144 -1144 -1144 -1144 -1144 -1144 -1144 -1144 -1144 -1144 -1144 -1144 -1144 -1144 -1144 -1144 -1144 -1144 -1144 -1144 -1144 -700 -550 -470 -390 -310 -230 -150 -70 10 90 170 250 330 410 490 570 650 730 810 890 970 1144 1144 1144 1144 PAD No. 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 (*1) Pad for ML610Q426 (*2) Pad Name SEG41 SEG40 SEG39 SEG38 SEG37 SEG36 SEG35 SEG34 SEG33 SEG32 SEG31 SEG30 SEG29 SEG28 SEG27 SEG26 SEG25 SEG24 SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 (1) SEG7 (2) P06 (1) SEG6 (2) P05 (1) SEG5 (2) P64 (1) SEG4 (2) P63 (1) SEG3 (2) P53 (1) SEG2 (2) P52 (1) SEG1 (2) P51 (1) SEG0 (2) P50 p00 X (μm) Y (μm) 560 480 400 320 240 160 80 0 -80 -160 -240 -320 -400 -480 -560 -640 -720 -800 -880 -960 -1144 -1144 -1144 -1144 -1144 -1144 -1144 -1144 -1144 -1144 -1144 -1144 -1144 -1144 1144 1144 1144 1144 1144 1144 1144 1144 1144 1144 1144 1144 1144 1144 1144 1144 1144 1144 1144 1144 970 890 810 730 650 570 490 410 330 250 170 90 10 -70 -1144 -187 -1144 -267 -1144 -347 -1144 -427 -1144 -507 -1144 -587 -1144 -667 -1144 -747 -1144 -847 Pad for ML610Q426C 9/34 FEDL610Q426-01 ML610Q426/426 ML610426 Pad Coordinates Table 2 Pad Coordinates of ML610426 Chip Center: X=0,Y=0 PAD No. Pad Name 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 P01 P02 P03 P04 P70 P71 P72 P73 P74 P65 P66 VDDL VSS XT0 XT1 VDDX VDD RESET_N TEST VL1 VL2 VL3 VL4 C1 C2 (No pin) COM0 COM1 COM2 COM3 COM4/SEG61 COM5/SEG60 COM6/SEG59 COM7/SEG58 COM8/SEG57 COM9/SEG56 COM10/SEG55 COM11/SEG54 COM12/SEG53 COM13/SEG52 COM14/SEG51 COM15/SEG50 SEG49 SEG48 SEG47 SEG46 SEG45 SEG44 SEG43 SEG42 X (μm) -1055 -975 -895 -815 -735 -655 -575 -495 -415 -310 -230 -140 -60 20 180 260 340 420 500 620 700 780 860 940 1020 1104 1104 1104 1104 1104 1104 1104 1104 1104 1104 1104 1104 1104 1104 1104 1104 1104 1104 1104 1104 938 858 778 698 Y (μm) -1084 -1084 -1084 -1084 -1084 -1084 -1084 -1084 -1084 -1084 -1084 -1084 -1084 -1084 -1084 -1084 -1084 -1084 -1084 -1084 -1084 -1084 -1084 -1084 -1084 -630 -550 -470 -390 -310 -230 -150 -70 10 90 170 250 330 410 490 570 650 730 810 890 1084 1084 1084 1084 PAD No. 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 Pad Name SEG41 SEG40 SEG39 SEG38 SEG37 SEG36 SEG35 SEG34 SEG33 SEG32 SEG31 SEG30 SEG29 SEG28 SEG27 SEG26 SEG25 SEG24 SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 X (μm) Y (μm) 618 538 458 378 298 218 138 58 -22 -102 -182 -262 -342 -422 -502 -582 -662 -742 -822 -902 -1104 -1104 -1104 -1104 -1104 -1104 -1104 -1104 -1104 -1104 -1104 -1104 -1104 -1104 1084 1084 1084 1084 1084 1084 1084 1084 1084 1084 1084 1084 1084 1084 1084 1084 1084 1084 1084 1084 980 900 820 740 660 580 500 420 340 260 180 100 20 -60 85 SEG7 -1104 -177 SEG6 P05 -1104 -257 87 SEG5 -1104 -337 88 SEG4 -1104 -417 89 SEG3 -1104 -497 90 SEG2 -1104 -577 91 SEG1 -1104 -657 92 SEG0 -1104 -737 93 p00 -1104 837 86 Note: No pin for PAD No. 26 10/34 FEDL610Q426-01 ML610Q426/426 PIN LIST ML610Q426/426 Pin List Primary function PAD No. 13 17 12 16 26 20 21 22 23 24 25 I/O Function Vss VDD VDDL VDDX (1) Negative power supply pin Positive power supply pin Power supply pin for internal logic (internally generated) Power supply pin for low-speed oscillator (internally generated) Power supply pin for Flash ROM Power supply pin for LCD bias (internally generated) Power supply pin for LCD bias (internally generated) Power supply pin for LCD bias (internally generated) Power supply pin for LCD bias (internally generated) Capacitor connection pin for LCD bias generation Capacitor connection pin for LCD bias generation Test pin VPP (2) VL1 VL2 VL3 VL4 C1 C2 19 TEST I/O 18 14 15 RESET_N XT0 XT1 I I O 93 P00/EXI0/ TPRUN0 I 1 P01/EXI1/ TPRUN1 I 2 P02/EXI2/ TPRUN2 I 3 P03/EXI3/ RXD1/ TPRUN3 I 4 P04/EXI4/ T0IP8CK I 10 P65 I/O Input/output port 11 P66 I/O Input/output port, P8RUN, BLDI 5 P70 I/O Input/output port, TIJRUN I/O Input/output port, T0IP8CK 6 (*1) Pin name P71 Reset input pin Low-speed clock oscillation pin Low-speed clock oscillation pin Input port, External interrupt, Timer and PWM common external trigger input Input port, External interrupt, Timer and PWM common external trigger input Input port, External interrupt, Timer and PWM common external trigger input Input port, External interrupt, UART1 data input, Timer and PWM common external trigger input Input port, External interrupt, Timer 0/Timer I/PWM8 external clock input 7 P72 I/O Input/output port, T1JCK 8 P73 I/O Input/output port 9 P74 I/O Input/output port Pin for ML610426 and ML610Q426 (*2) Secondary, Tertiary, or Quaternary function Secondary/ Tertiary/ Quaternary Pin name I/O Function Secondary Tertiary Quaternary Secondary Tertiary Quaternary LSCLK RCM SDA OUTCLK MD0 SCL O O O O O O Secondary IN0 I Tertiary Quaternary SIN1 ELP I I/O Secondary CS0 O Tertiary SCK1 I/O Quaternary ELC I/O Secondary RCT0 O Tertiary Quaternary SOUT1 RXD1 Low-speed clock output RC type ADC oscillation monitor I2C data input/output High-speed clock output Melody 0 output I2C clock input/output RC type ADC0 oscillation input pin SSIO1 data input Pumping clock output RC type ADC0 reference capacitor connection pin SSIO1 synchronous clock input/output Discharge pulse signal output RC type ADC0 reference resistor connection pin SSIO1 data output UART1 data input RC type ADC0 measurement resistor sensor connection pin Melody 0 output UART1 data output RC type ADC0 resistor/capacitor sensor connection pin PWM8 output Secondary RS0 O Tertiary Quaternary MD0 TXD1 O O Secondary RT0 O Tertiary PWM8 O Pin for ML610Q426 11/34 FEDL610Q426-01 ML610Q426/426 Primary function PAD No. 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 Pin name I/O SEG0 O P50/EXI8 I/O SEG1 O P51/EXI8 I/O Function LCD segment pin Input/output port, External interrupt LCD segment pin Input/output port, External interrupt SEG2 O P52/EXI8 I/O SEG3 O P53/EXI8 I/O SEG4 O LCD segment pin Input/output port, External interrupt LCD segment pin Input/output port, External interrupt LCD segment pin P63 I/O Input/output port SEG5 O LCD segment pin P64 I/O Input/output port SEG6 O P05/EXI5/ T1JCK I SEG7 P06/EXI6 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 O I O O O O O O O O O O O O O O O O O O O O O O O O O O O O LCD segment pin Input port, External interrupt, Timer 1/Timer B external clock input LCD segment pin Input port, External interrupt LCD segment pin LCD segment pin LCD segment pin LCD segment pin LCD segment pin LCD segment pin LCD segment pin LCD segment pin LCD segment pin LCD segment pin LCD segment pin LCD segment pin LCD segment pin LCD segment pin LCD segment pin LCD segment pin LCD segment pin LCD segment pin LCD segment pin LCD segment pin LCD segment pin LCD segment pin LCD segment pin LCD segment pin LCD segment pin LCD segment pin LCD segment pin LCD segment pin Secondary function or Tertiary function Secondary/ Tertiary/ Quaternary Secondary Tertiary Secondary Pin name I/O Function MD0 SIN1 O I Tertiary SCK1 I/O Secondary Tertiary RXD1 SOUT1 I O Melody 0 output SSIO1 data input SSIO1 synchronous clock input/output UART1 data input SSIO1 data output Secondary TXD1 O UART1 data output Secondary Tertiary Quaternary Secondary Tertiary ELP PWM8 ELC O O O Pumping clock output PWM8 output Discharge pulse signal output 12/34 FEDL610Q426-01 ML610Q426/426 ML610Q426/426 Pin List Primary function PAD No. 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 Secondary function or Tertiary function Pin name I/O Function SEG36 SEG37 SEG38 SEG39 SEG40 SEG41 SEG42 SEG43 SEG44 SEG45 SEG46 SEG47 SEG48 SEG49 COM15/ SEG50 COM14/ SEG51 COM13/ SEG52 COM12/ SEG53 COM11/ SEG54 COM10/ SEG55 COM9/ SEG56 COM8/ SEG57 COM7/ SEG58 COM6/ SEG59 COM5/ SEG60 COM4/ SEG61 COM3 COM2 COM1 COM0 O O O O O O O O O O O O O O LCD segment pin LCD segment pin LCD segment pin LCD segment pin LCD segment pin LCD segment pin LCD segment pin LCD segment pin LCD segment pin LCD segment pin LCD segment pin LCD segment pin LCD segment pin LCD segment pin O LCD common/segment pin Secondary/ Tertiary/ Quaternary O LCD common/segment pin O Pin name I/O Function LCD common/segment pin O LCD common/segment pin O LCD common/segment pin O LCD common/segment pin O LCD common/segment pin O LCD common/segment pin O LCD common/segment pin O LCD common/segment pin O LCD common/segment pin O LCD common/segment pin O O O O LCD common pin LCD common pin LCD common pin LCD common pin 13/34 FEDL610Q426-01 ML610Q426/426 PIN DESCRIPTION Primary/ Secondary/ Tertiary/ Quaternary Logic — Negative — — — — Secondary — Secondary — General-purpose input port. General-purpose input port. These pins are available in case SEG0-SEG7 pins are changed by mask option. General-purpose input/output port P50-P53 I/O General-purpose input/output port. Since these pins have secondary functions, the pins cannot be used as a port when the secondary functions are used. These pins are available in case SEG0-SEG7 pins are changed by mask option. P63-P64 I/O General-purpose input/output port. Since these pins have secondary functions, the pins cannot be used as a port when the secondary functions are used. These pins are available in case SEG0-SEG7 pins are changed by mask option. P65-P66 I/O General-purpose input/output port. Since these pins have secondary functions, the pins cannot be used as a port when the secondary functions are used. Primary Primary Positive Positive Primary Positive Primary Positive Primary Positive I/O General-purpose input/output port. Since these pins have secondary functions, the pins cannot be used as a port when the secondary functions are used. Primary Positive Pin name I/O Description System Reset input pin. When this pin is set to a “L” level, system reset mode is set and the internal section is initialized. When this pin is set to a “H” level subsequently, program execution starts. A pull-up resistor is internally connected. XT0 I Crystal connection pin for low-speed clock. XT1 O A 32.768 kHz crystal oscillator (see measuring circuit 1) is connected to this pin. Capacitors CDL and CGL are connected across this pin and VSS as required. LSCLK O Low-speed clock output pin. This pin is used as the secondary function of the P65 pin. OUTCLK O High-speed clock output pin. This pin is used as the secondary function of the P66 pin. General-purpose input port RESET_N P00-P04 P05-P06 P70-P74 I I I 14/34 FEDL610Q426-01 ML610Q426/426 Pin name I/O UART TXD1 O RXD1 I Description UART data output pin. This pin is used as the quaternary function of the P73 pin or tertiary function of P53 pin. UART data input pin. This pin is used as the quaternary function of the P72 pin or tertiary function of P52 pin or the primary function of the P03 pin. Primary/ Secondary/ Tertiary/ Quaternary Logic Positive Tertiary/ Quaternary Positive Primary/ Tertiary/ Quaternary 2 I C bus interface 2 SDA I/O I C data input/output pin. This pin is used as the quaternary function of the Quaternary Positive P65 pin. This pin has an NMOS open drain output. When using this pin as 2 a function of the I C, externally connect a pull-up resistor. 2 SCL O I C clock output pin. This pin is used as the quaternary function of the P66 Quaternary Positive pin. This pin has an NMOS open drain output. When using this pin as a 2 function of the I C, externally connect a pull-up resistor. Synchronous serial (SSIO) SCK1 SIN1 SOUT1 I/O Synchronous serial clock input/output pin. This pin is used as the tertiary function of the P71 pin or P51 pin. I Synchronous serial data input pin. This pin is used as the tertiary function of the P70 pin or P50 pin. O Synchronous serial data output pin. This pin is used as the tertiary function of the P72 pin or P52 pin. Tertiary — Tertiary Positive Tertiary Positive PWM PWM8 O PWM8 output pin. This pin is used as the tertiary function of the P74 or the quaternary function P63 pin. T0IP8CK I P8RUN I PWM8 external clock input pin. This pin is used as the primary function of the P04 pin or P71 pin. PWM8 external trigger input pin. This pin is used as the primary function of the P66 pin and the primary function of the P66 pin. TPRUN0, I TPRUN1, TPRUN2, TPRUN3 External interrupt EXI0-4 I EXI5-6 I EXI8 I Timer T0IP8CK I T1JCK I TIJRUN I TPRUN0, TPRUN1, TPRUN2, TPRUN3 I Secondary/ Positive Tertiary Primary — Primary Positive/ negative Positive/ negative PWM8 common external trigger input pin. This pin is used as the primary function of the P00, P01, P02 and P03 pin. Primary External maskable interrupt input pins. Interrupt enable and edge selection can be performed for each bit by software. These pins are used as the primary functions of the P00-P04 pins. External maskable interrupt input pins. Interrupt enable and edge selection can be performed for each bit by software. These pins are used as the primary functions of the P05-P06 pins. These pins are available in case SEG0-SEG7 pins are changed by mask option. External maskable interrupt input pins. Interrupt enable and edge selection can be performed for each bit by software. These pins are used as the primary functions of the P50-P53 pins. These pins are available in case SEG0-SEG7 pins are changed by mask option. Primary Positive/ negative Primary Positive/ negative Primary Positive/ negative External clock input pin used for Timer 0 and Timer I. This pin is used as the primary function of the P04 pin or P71 pin External clock input pin used for Timer 1 and Timer B. This pin is used as the primary function of the P72 pin or P05 pin. TimerI/TimerJ external trigger input. This pin is used as the primary function of the P70 pin. TimerI/TimerJ common external trigger input. These pins are used as the primary functions of the P00, P01, P02 and P03 pins. Primary Primary Primary — — Positive/ negative Primary Positive/ negative 15/34 FEDL610Q426-01 ML610Q426/426 Melody MD0 Melody/buzzer signal output pin. This pin is used as the tertiary function of the P66 pin or tertiary function of P73 pin or secondary function of the P50 pin. RC oscillation type A/D converter IN0 I Channel 0 oscillation input pin. This pin is used as the secondary function of the P70 pin. CS0 O Channel 0 reference capacitor connection pin. This pin is used as the secondary function of the P71 pin. RCT0 O Resistor/capacitor sensor connection pin of Channel 0 for measurement. This pin is used as the secondary function of the P72 pin. RS0 O This pin is used as the secondary function of the P73 pin which is the reference resistor connection pin of Channel 0. RT0 O Resistor sensor connection pin of Channel 0 for measurement. This pin is used as the secondary function of the P74 pin. RCM O RC oscillation monitor pin. This pin is used as the tertiary function of the P65 pin. BLD BLDI I Battery level detection input. This pin is used as the primary function of the P66 pin. O Secondary/ Positive/ negative Tertiary Secondary Secondary Secondary Secondary Secondary Tertiary Primary — — — — — — — 16/34 FEDL610Q426-01 ML610Q426/426 Pin name I/O LCD drive signal COM0-7 O COM8-15 O SEG0-7 O SEG8-39 O SEG40-53 O SEG54-61 O EL driver signal ELP O Description Common output pins. Common output pins. Segment output pins. These pins are available in case P05-P06, P50-P53, and P63-P64 pins are changed by mask option. Segment output pins. Segment output pins. Segment output pins. Pumping clock output pin. This pin is used as the quaternary function of the P70 pin or tertiary function of the P63 pin. ELC O Discharge pulse signal output pin. This pin is used as the quaternary function of the P71 pin or tertiary function of the P64 pin. LCD driver power supply VL1 — Power supply pins for LCD bias (internally generated). Capacitors Ca, Cb, VL2 — Cc, and Cd (see measuring circuit 1) are connected between VSS and VL3 — VL1,VL2, VL3,and VL4 respectively. VL4 — Power supply pins for LCD bias (internally generated). Capacitors C12 is C1 — connected between C1 and C2. C2 — For testing TEST I/O Input/output pin for testing. A pull-down resistor is internally connected. Power supply VSS — VDD — VDDL — VDDX — VPP — Negative power supply pin. Positive power supply pin. Positive power supply pin (internally generated) for internal logic. Capacitors CL (see measuring circuit 1) are connected between this pin and VSS. Plus-side power supply pin (internally generated) for low-speed oscillation. Capacitor CX (see measuring circuit 1) is connected between this pin and VSS. Power supply pin for programming Flash ROM.A pull up resistor is internally connected. Primary/ Secondary/ Tertiary/ Quaternary Logic — — — — — — — — — — — — Tertiary — Tertiary Positive — — — — — — — — — — — — — — — — — — — — — — — — 17/34 FEDL610Q426-01 ML610Q426/426 TERMINATION OF UNUSED PINS Table 5 shows methods of terminating the unused pins. Table 5 Pin VPP Termination of Unused Pins Recommended pin termination Open VL1, VL2, VL3, VL4 Open C1, C2 RESET_N TEST P00 to P06 P50 to P53 P63 to P66 P70 to P74 COM0 to COM15 SEG0 to SEG61 Open Open Open VDD or VSS Open Open Open Open Open Note: It is recommended to set the unused input ports and input/output ports to the inputs with pull-down resistors/pull-up resistors or the output mode since the supply current may become excessively large if the pins are left open in the high impedance input setting. 18/34 FEDL610Q426-01 ML610Q426/426 ELECTRICAL CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS (VSS = 0V) Parameter Symbol Condition Rating Unit Power supply voltage 1 VDD Ta = 25°C −0.3 to +4.6 V Power supply voltage 2 VPP Ta = 25°C −0.3 to +9.5 V Power supply voltage 3 VDDL Ta = 25°C −0.3 to +3.6 V Power supply voltage 4 VDDX Ta = 25°C −0.3 to +3.6 V Power supply voltage 5 VL1 Ta = 25°C −0.3 to +1.75 V Power supply voltage 6 VL2 Ta = 25°C −0.3 to +3.5 V Power supply voltage 7 VL3 Ta = 25°C −0.3 to +5.25 V Power supply voltage 8 VL4 Ta = 25°C −0.3 to +7.0 V Input voltage VIN Ta = 25°C −0.3 to VDD+0.3 V Output voltage VOUT Ta = 25°C −0.3 to VDD+0.3 V Output current 1 IOUT1 Port5–7, Ta = 25°C −12 to +11 mA Power dissipation PD Ta = 25°C 1.0 mW Storage temperature TSTG −55 to +150 °C RECOMMENDED OPERATING CONDITIONS (VSS = 0V) Parameter Symbol Condition Range Unit Operating temperature TOP ML610426, ML610Q426 -20 to+70 °C Operating voltage VDD fOP 1.1 to 3.6 30k to 157k 30k to 1.25M V Operating frequency (CPU) VDD = 1.1 to 3.6V VDD = 1.3 to 3.6V CV 1.0±30% µF CL 1.0±30% µF CX ML610426/Q426 0.1±30% µF Ca，b，c，d 1.0±30% µF C12 1.0±30% µF Capacitor externally connected to VDD pin Capacitor externally connected to VDDL pin Capacitor externally connected to VDDLX pin Capacitors externally connected to VL1, 2, 3, 4 pins Capacitors externally connected across C1 and C2 pins Hz CLOCK GENERATION CIRCUIT OPERATING CONDITIONS (VSS = 0V) Parameter Low-speed crystal oscillation frequency Recommended equivalent series resistance value of low-speed crystal oscillation Low-speed crystal oscillation external capacitor Symbol Rating Condition Unit Min. Typ. Max. fXTL 32.768k Hz RL 40k Ω 12 CDL/CGL CL=6pF of crystal oscillation CL=9pF of crystal oscillation pF 18 19/34 FEDL610Q426-01 ML610Q426/426 OPERATING CONDITIONS OF FLASH ROM (VSS = 0V) Parameter Operating temperature Operating voltage Rewrite counts Data retention Symbol Condition Rating Unit TOP VDD VDDL VPP CEP YDR Flash ROM, At write/erase 0 to +40 2.75 to 3.6 2.5 to 2.75 7.7 to 8.3 80 10 °C At write/erase (*1) V cycles years (*1) : In addition the power supply to VDD pin and VPP pin, within the range 2.5V to 2.75V has to be supplied to VDDL pin when programming and eraseing Flash ROM 20/34 FEDL610Q426-01 ML610Q426/426 DC CHARACTERISTICS (1/5) Parameter Symbol 1MHz RC oscillation frequency Low-speed crystal oscillation start 2 time* 1MHz RC oscillation start time Reset pulse width Reset noise elimination pulse width Power-on reset generated power rise time fRC (VDD = 1.1 to 3.6V, VSS = 0V, Ta = -20 to +70°C, unless otherwise specified) Rating Measuring Condition Unit circuit Min. Typ. Max. Typ. Typ. Ta = 25°C 1.0 MHz −10% +10% VDD = 1.3 to 3.6V Typ. Typ. 1 * 1.0 MHz −25% +25% TXTL 0.6 2 s TRC PRST 200 10 µs PNRST 0.3 TPOR 10 1 µs ms *1: Recommended operating temperature (Ta = −20 to +70°C) *2 : Use 32.768kHz crystal resonator DT-26 (Load capacitance 6pF) (made by KDS:DAISHINKU CORP.) is used (CGL=CDL=12pF). [Reset pulse width] VIL1 RESET_N VIL1 PRST Reset pulse width (PRST) [Power-on reset activation power rise time] 0.9xVDD VDD 0.1xVDD TPOR Power-on reset activation power rise time (TPOR ) 21/34 FEDL610Q426-01 ML610Q426/426 DC CHARACTERISTICS (2/5) (VDD = 1.1 to 3.6V, VSS = 0V, Ta = -20 to +70°C, unless otherwise specified) Rating Measuring Condition Unit circuit Min. Min. Min. CN4-0 = 00H 0.89 0.94 0.99 CN4-0 = 02H 0.93 0.98 1.03 CN4-0 = 04H 0.97 1.02 1.07 CN4-0 = 06H 1.01 1.06 1.11 CN4-0 = 08H 1.05 1.10 1.15 CN4-0 = 0AH 1.09 1.14 1.19 CN4-0 = 0CH 1.13 1.18 1.23 CN4-0 = 0EH 1.17 1.22 1.27 VDD = 3.0V, Tj = 25°C V CN4-0 = 10H 1.21 1.26 1.31 CN4-0 = 12H 1.25 1.30 1.35 1 CN4-0 = 14H* 1.29 1.34 1.39 1 CN4-0 = 16H* 1.33 1.38 1.43 1 CN4-0 = 18H* 1.37 1.42 1.47 1 CN4-0 = 1AH* 1.41 1.46 1.51 1 CN4-0 = 1CH* 1.45 1.50 1.55 1 1 CN4-0 = 1EH* 1.49 1.54 1.59 Parameter Symbol VL1 voltage VL1 VL1 temperature deviation ΔVL1 VDD = 3.0V ― -1.5 ― mV/°C VL1 voltage dependency ΔVL1 VDD = 1.3 to 3.6V ― 5 20 mV/V VL2 VL1 Typ. -10% VL1 TYP. -10% VL1 VL2 voltage VL1 Typ. +4% VL1 TYP. +4% VL3 voltage VL3 VL4 voltage VL4 VDD = 3.0V, Tj = 25°C, 1MΩ load (VL4−VSS) 1/2bias 1/3bias, 1/1bias 1/4bias 1/2bias 1/3bias, 1/1bias 1/4bias 1/2bias 1/3bias,1/1bias 1/4bias Typ. -10% VL1×2 VL1 VL1×2 VL1×3 VL1×2 VL1×3 VL1×4 V Typ. +4% LCD bias voltage TBIAS ― ― ― 600 generation time *1: When using 1/4 bias, the VL1 voltage is set to typ. 1.30 V (same voltage as in CN4–0 = 12H). ms 22/34 FEDL610Q426-01 ML610Q426/426 DC CHARACTERISTICS (3/5) Parameter BLD threshold voltage BLD input voltage from I/O ports BLD threshold voltage temperature deviation Symbol VBLD (VDD = 1.1 to 3.6V, VSS = 0V, Ta = -20 to +70°C, unless otherwise specified) Rating Measuring Condition Unit circuit Min. Typ. Max. LD3–0 = 0H 1.16 LD3–0 = 1H 1.18 LD3–0 = 2H 1.20 LD3–0 = 3H 1.22 LD3–0 = 4H 1.24 LD3–0 = 5H 1.26 LD3–0 = 6H 1.28 LD3–0 = 7H 1.30 VDD, VBLDI= 1.1 to Typ. Typ. V 3.6V −6% +6% LD3–0 = 8H 2.35 LD3–0 = 9H 2.40 LD3–0 = 0AH 2.45 LD3–0 = 0BH 2.50 LD3–0 = 0CH 2.55 LD3–0 = 0DH 2.60 LD3–0 = 0EH 2.65 LD3–0 = 0FH 2.70 VBLDI ∆VBLD 1.1 VDD 0 V %/°C 1 0.25 Ta = 25°C Supply current 1 IDD1 CPU: In STOP state. Low-speed/high-speed oscillation: stopped. µA Ta = -20 to 70°C Supply current 2 Supply current 3 0.65 IDD2 CPU: In HALT state LTBC: Operating *3*4 High-speed oscillation: Stopped LCD/BIAS circuits: Stopped Ta = 25°C IDD3 CPU: In 32.768kHz operating state.*1*3 High-speed oscillation: Stopped. LCD/BIAS circuits: Operating.*2 Ta = 25°C 0.5 5 6 1.4 µA 7.5 µA CPU: In 1MHz CR operating state. Supply current 4 Ta = 25°C IDD4 140 170 µA LCD/BIAS circuits: 2 3 Operating.* * *1 : CPU operating rate is 100% (No HALT state). *2 : All SEGs: off waveform, No LCD panel load, 1/3 bias, 1/3 duty, Frame frequency: Approx. 64 Hz, Bias voltage multiplying clock: 1/128 LSCLK (256Hz) *3 : Use 32.768kHz crystal resonator DT-26 (Load capacitance 6pF) (made by KDS:DAISHINKU CORP.) is used (CGL=CDL=12pF). *4 : Significant bits of BLKCON0 to BLKCON4 registers are all “1” 23/34 FEDL610Q426-01 ML610Q426/426 DC CHARACTERISTICS (4/5) Parameter Symbol Output voltage 1 (P50–P53) (P63-P66) (P70-P74) VOH1 VOL1 Output voltage 1 (P65–P66) VOL2 VOH3 IOH3 = −0.03mA, VL1=1.2V VL4−0.2 VOMH3 IOMH3 = +0.03mA, VL1=1.2V VL3+0.2 VOMH3S IOMH3S = −0.03mA, VL1=1.2V VL3−0.2 IOM3 = +0.03mA, VL1=1.2V VL2+0.2 IOM3S = −0.03mA, VL1=1.2V VL2−0.2 VOML3 IOML3 = +0.03mA, VL1=1.2V VL1+0.2 VOML3S IOML3S = −0.03mA, VL1=1.2V VL1−0.2 VOL3 IOL3 = +0.03mA, VL1=1.2V 0.2 VL4−0.2 VL123+0.2 VL123−0.2 0.2 1 −1 −600 −600 −600 20 10 2 -1 2 0.2 0.01 −200 −200 −200 −1 −300 −300 −300 300 300 300 30 30 30 −30 −30 −30 1 −20 -10 -2 600 600 600 200 200 200 −2 -0.2 -0.01 1 VOM3 VOM3S Output voltage 3 (COM0–COM15) (SEG0–SEG61) (VDD = 1.1 to 3.6V, VSS = 0V, Ta = -20 to +70°C, unless otherwise specified) Rating Measuring Condition Unit circuit Min. Typ. Max. IOH1 = −0.5mA, VDD = 1.8 to 3.6V VDD−0.5 IOH1 = -0.1mA, VDD = 1.3 to 3.6V VDD−0.3 P65-P66, IOH1 = -0.03mA, P70-P74 VDD = 1.1 to 3.6V VDD−0.3 P50-P53, IOH1 = -0.015mA, P63-P64 VDD = 1.1 to 3.6V IOL1 = +0.5mA, VDD = 1.8 to 3.6V 0.5 IOL1 = +0.1mA, VDD = 1.3 to 3.6V 0.5 IOL1 = +0.03mA, VDD = 1.1 to 3.6V 0.3 IOL2 = +3mA, VDD = 2.0 to 3.6V 0.4 (when I2C mode is selected) 1/4,1/3,1/1 bias IOH3 = −1µA, VOH3 CN4-0=1AH,1CH,1EH IOMH3 = +1µA, VOMH3 1/2bias VOML3S VOL3 Output leakage (P50–P53) (P63-P66) (P70-P74) Input current 1 (RESET_N) Input current 1 (TEST) IOOH IOOL IIH1 IIL1 IIH1 IIL1 Input current 2 (P00-P06) (P50–P53) (P63-P66) (P70-P74) IIH2 IIL2 IIH2Z IIL2Z CN4-0=1AH,1CH,1EH IOML3S = −1µA, CN4-0=1AH,1CH,1EH IOL3 = +1µA, CN4-0=1AH,1CH,1EH VOH = VDD (in high-impedance state) VOL = VSS (in high-impedance state) VIH1 = VDD VDD = 1.8 to 3.6V VIL1 = VSS VDD = 1.3 to 3.6V VDD = 1.1 to 3.6V VDD = 1.8 to 3.6V VDD = 1.3 to 3.6V VIH1 = VDD VDD = 1.1 to 3.6V VIL1 = Vss VDD = 1.8 to 3.6V VIH2 = VDD VDD = 1.3 to 3.6V (when pulled-down) VDD = 1.1 to 3.6V VDD = 1.8 to 3.6V VIL2 = VSS VDD = 1.3 to 3.6V (when pulled-up) VDD = 1.1 to 3.6V VIH2 = VDD (in high-impedance state) VIL2 = VSS (in high-impedance state) V 2 µA 3 µA 4 24/34 FEDL610Q426-01 ML610Q426/426 DC CHARACTERISTICS (5/5) Parameter Input voltage 1 (RESET_N) (TEST) (P00-P06) (P50–P53) (P63-P66) (P70–P74) Input pin capacitance (P00-P06) (P50–P53) (P63-P66) (P70–P74) Symbol (VDD = 1.1 to 3.6V, VSS = 0V, Ta = -20 to +70°C, unless otherwise specified) Rating Measuring Condition Unit circuit Min. Typ. Max. VDD = 1.3 to 3.6V 0.7 ×VDD VDD VDD = 1.1 to 3.6V 0.7 ×VDD VDD VIH1 VDD = 1.3 to 3.6V 0 0.3 ×VDD VDD = 1.1 to 3.6V 0 0.2 ×VDD f = 10kHz Vrms = 50mV Ta = 25°C 5 VIL1 CIN V 5 pF 25/34 FEDL610Q426-01 ML610Q426/426 MEASURING CIRCUITS MEASURING CIRCUIT 1 CGL XT0 CDL XT1 C2 32.768kHz crystal C12 C1 VDD VDDL VDDX VL1 VL2 VL3 VL4 VSS CL CX : 1.0µF : 1.0µF : 0.1µF : 1.0µF : 1.0µF : 12pF 32.768kHz crystal resonator DT-26 (Load capacitance 6pF) (Made by KDS:DAISHINKU CORP.) A CV CV CL CX Ca,Cb, Cc,Cd C12 CGL,CDL Ca Cb Cc MEASURING CIRCUIT 2 (*2) VIL Input pins (*1) Output pins VIH VDD VDDL VDDX VL1 VL2 VL3 VL4 V VSS (*1) Input logic circuit to determine the specified measuring conditions. (*2) Measured at the specified output pins. 26/34 FEDL610Q426-01 ML610Q426/426 MEASURING CIRCUIT 3 (*2) (*1) VIL Output pins Input pins VIH VDD VDDL VDDX VL1 VL2 VL3 VL4 A VSS *1: Input logic circuit to determine the specified measuring conditions. *2: Measured at the specified output pins. MEASURING CIRCUIT 4 Input pins Output pins (*3) A VDD VDDL VDDX VL1 VL2 VL3 VL4 VSS *3: Measured at the specified output pins. MEASURING CIRCUIT 5 VDD VDDL VDDX VL1 VL2 VL3 VL4 VSS Waveform monitoring VIL Output pins (*1) Input pins VIH *1: Input logic circuit to determine the specified measuring conditions. 27/34 FEDL610Q426-01 ML610Q426/426 AC CHARACTERISTICS (External Interrupt) (VDD = 1.1 to 3.6V, VSS = 0V, Ta = -20 to +70°C, unless otherwise specified) Rating Symbol Condition Unit Min. Typ. Max. Parameter External interrupt disable period TNUL Interrupt: Enabled (MIE = 1), CPU: NOP operation System clock: 32.768kHz 76.8 106.8 µs P00–P06 (Rising-edge interrupt) tNUL P00–P06 (Falling-edge interrupt) tNUL P00–P06 (Both-edge interrupt) tNUL AC CHARACTERISTICS (UART) Parameter Transmit baud rate (VDD = 1.1 to 3.6V, VSS = 0V, Ta = -20 to +70°C, unless otherwise specified) Rating Symbol Condition Unit Min. Typ. Max. tTBRT 1 BRT* 1 s 1 BRT* BRT* 1 BRT* s −3% +3% *1: Baud rate period (including the error of the clock frequency selected) set with the UART baud rate register (UA1BRTL,H) and the UART mode register 0 (UA1MOD0). Receive baud rate tRBRT tTBRT TXD1* tRBRT RXD1* *: Indicates the secondary function of the port. 28/34 FEDL610Q426-01 ML610Q426/426 AC CHARACTERISTICS (Synchronous Serial Port) Parameter Symbol SCLKn input cycle (slave mode) SCLKn output cycle (master mode) SCLKn input pulse width (slave mode) SCLKn output pulse width (master mode) (VDD = 1.3 to 3.6V, VSS = 0V, Ta = -20 to +70°C, unless otherwise specified) Rating Condition Unit Min. Typ. Max. tSCYC 10 tSCYC tSW 4 tSD output load 10pF SOUTn output delay time (master mode) tSD output load 10pF SINn input setup time (slave mode) SINn input setup time (master mode) SINn input hold time SCLKn* s 1 µs 1 P72/SOUT1 P52/SOUT1 P72/SOUT1 SCLKn* ×0.4 SCLKn* ×0.5 SCLKn* ×0.6 500 850 500 P52/SOUT1 650 SOUTn output delay time (slave mode) µs 1 1 tSW s ns ns tSS 80 ns tSS P70/SIN1 P50/SIN1 500 850 ns tSH 300 ns n= 1 *1: Clock period selected with SnCK3–0 of the serial port n mode register (SIOnMOD1) tSCYC tSW tSW SCLKn* tSD tSD SOUTn* tSS tSH SINn* *: Indicates the secondary function of the port. 29/34 FEDL610Q426-01 ML610Q426/426 AC CHARACTERISTICS (I2C Bus Interface: Standard Mode) (VDD = 1.8 to 3.6V, VSS = 0V, Ta = -20 to +70°C, unless otherwise specified) Rating Symbol Condition Unit Min. Typ. Max. fSCL 0 100 kHz Parameter SCL clock frequency SCL hold time (start/restart condition) SCL ”L” level time SCL ”H” level time SCL setup time (restart condition) SDA hold time SDA setup time SDA setup time (stop condition) Bus-free time tHD:STA 4.0 µs tLOW tHIGH 4.7 4.0 µs µs tSU:STA 4.7 µs tHD:DAT tSU:DAT 0 0.25 3.45 µs µs tSU:STO 4.0 µs tBUF 4.7 µs Start condition Restart condition Stop condition P70/SDA P71/SCL tHD:STA tLOW tHIGH tSU:STA tHD:STA tSU:DAT tHD:DAT tSU:STO tBUF 30/34 FEDL610Q426-01 ML610Q426/426 AC Characteristics (RC Oscillation A/D Converter) Condition for VDD=1.8 to 3.6V Parameter (VDD=1.8 to 3.6V, VSS=0V, Ta=-20 to +70°C, unless otherwise specified) Rating Condition Unit Min. Typ. Max. Symbol RS0,RT0, RT0-1 fOSC1 fOSC2 fOSC3 Kf1 Kf2 Kf3 Oscillation resistor Oscillation frequency VDD = 3.0V RS to RT oscillation *1 frequency ratio VDD = 3.0V CS0, CT0 ≥740pF 1 ― ― kΩ Resistor for oscillation=1kΩ Resistor for oscillation=10kΩ Resistor for oscillation=100kΩ RT0, RT0-1=1kΩ RT0, RT0-1=10kΩ RT0, RT0-1=100kΩ 457.3 53.48 5.43 7.972 0.981 0.099 525.2 58.18 5.89 9.028 1 0.101 575.1 62.43 6.32 9.782 1.019 0.104 kHz kHz kHz *1: Kfx is the ratio of the oscillation frequency by the sensor resistor to the oscillation frequency by the reference resistor on the same conditions. Kfx = fOSCX(RT0-CS0 oscillation) fOSCX(RS0-CS0 oscillation) ( x = 1, 2, 3 ) fOSCX(RT0-1-CS0 oscillation) fOSCX(RS0-CS0 oscillation) , IN0 CS0 RCT0 (Note 1) RT0 RS0 RT0, RT0-1: 1kΩ/10kΩ/100kΩ RS0: 10kΩ CS0, CT0: 560pF CVR0: 820pF RS0 RT0 RCM Input pin VIH RT0-1 CT0 CS0 CVR0 VIL VDD CV VDDL VDDX Frequency measurement (fOSCX) VSS CL *1: Input logic circuit to determine the specified measuring conditions. 31/34 FEDL610Q426-01 ML610Q426/426 Condition for VDD=1.1 to 3.6V Parameter Oscillation resistor Oscillation frequency VDD = 1.5V RS to RT oscillation *1 frequency ratio VDD = 1.5V Oscillation frequency VDD = 3.0V RS to RT oscillation *1 frequency ratio VDD = 3.0V (VDD = 1.1 to 3.6V, VSS = 0V, Ta = -20 to +70°C, unless otherwise specified) Rating Symbol Condition Unit Min. Typ. Max. RS0, 1 ― ― CS0, CT0 ≥740pF kΩ RT0,RT0-1 fOSC1 81.93 93.16 101.2 kHz Resistor for oscillation=6kΩ fOSC2 35.32 38.75 41.48 kHz Resistor for oscillation=15kΩ fOSC3 5.22 5.65 6.03 kHz Resistor for oscillation=105kΩ Kf1 2.139 2.381 2.632 RT0, RT0-1=1kΩ Kf2 0.973 1 1.028 RT0, RT0-1=10kΩ Kf3 0.142 0.147 0.152 RT0, RT0-1=100kΩ fOSC1 85.28 94.58 103.3 kHz Resistor for oscillation=6kΩ fOSC2 35.72 38.87 41.78 kHz Resistor for oscillation=15kΩ fOSC3 5.189 5.622 6.012 kHz Resistor for oscillation=105kΩ Kf1 2.227 2.432 2.626 RT0, RT0-1=1kΩ Kf2 0.982 1 1.018 RT0, RT0-1=10kΩ Kf3 0.141 0.145 0.149 RT0, RT0-1=100kΩ *1: Kfx is the ratio of the oscillation frequency by the sensor resistor to the oscillation frequency by the reference resistor on the same conditions. Kfx = fOSCX(RT0-CS0 oscillation) fOSCX(RS0-CS0 oscillation) ( x = 1, 2, 3 ) fOSCX(RT0-1-CS0 oscillation) fOSCX(RS0-CS0 oscillation) , , IN0 CS0 RCT0 VIH RA0 RT0, RT0-1: 1kΩ/10kΩ/100kΩ RA0, RA0-1: 5kΩ RS0: 15kΩ CS0, CT0: 560pF CVR0: 820pF RT0 RS0 RT0-1 RA0-1 CT0 CS0 CVR0 RS0 RT0 (Note 1) Frequency measurement (fOSCX) Input pin RCM VIL VDD CV VDDL CL VDDX VSS CX *1: Input logic circuit to determine the specified measuring conditions. Note: ･Please have the shortest layout for the common node (wiring patterns which are connected to the external capacitors, resistors and IN0 pin), including CVR0. Especially, do not have long wiring between IN0 and RS0. The coupling capacitance on the wires may occur incorrect A/D conversion. Also, please do not have signals which may be a source of noise around the node. ･When RT0 (Thermistor and etc.) requires long wiring due to the restricted placement, please have VSS(GND) trace next to the signal. ･Please make wiring to components (capacitor, resistor, and so on) necessary for objective measurement. Wiring to reserved components may affect to the A/D conversion operation by noise the components itself may have. 32/34 FEDL610Q426-01 ML610Q426/426 Revision History Document No. FEDL610Q426-01 Date Mar.17, 2015 Page Previous Current Edition Edition – – Description Final edition 1 33/34 FEDL610Q426-01 ML610Q426/426 Notes 1) The information contained herein is subject to change without notice. 2) Although LAPIS Semiconductor is continuously working to improve product reliability and quality, semiconductors can break down and malfunction due to various factors. Therefore, in order to prevent personal injury or fire arising from failure, please take safety measures such as complying with the derating characteristics, implementing redundant and fire prevention designs, and utilizing backups and fail-safe procedures. LAPIS Semiconductor shall have no responsibility for any damages arising out of the use of our Products beyond the rating specified by LAPIS Semiconductor. 3) Examples of application circuits, circuit constants and any other information contained herein are provided only to illustrate the standard usage and operations of the Products.The peripheral conditions must be taken into account when designing circuits for mass production. 4) The technical information specified herein is intended only to show the typical functions of the Products and examples of application circuits for the Products. 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