IXYS IX21844N Programmable dead-time Datasheet

IX21844
High Voltage Half-Bridge
Gate Driver
INTEGRATED CIRCUITS DIVISION
Driver Characteristics
Parameter
VOFFSET
IO +/- (Source/Sink)
VBIAS
Description
Rating
Units
600
V
1.4 / 1.8
A
10-20
V
The IX21844 is a high voltage IC that can drive high
speed MOSFETs and IGBTs that operate up to
+600V. The IX21844 is configured with dependent
high-side and low side referenced output channels
which can source 1.4A and sink 1.8A. The floating
high-side channel can drive an N-channel power
MOSFET or IGBT 600V from the common reference.
Features
• Floating Channel for Bootstrap Operation to +600V
with an Absolute Maximum Rating of +700V
• Programmable Dead-Time
• Outputs Can Source 1.4A and Sink 1.8A
• Gate Drive Supply Range From 10V to 20V
• Tolerant to Negative Voltage Transients:
dV/dt Immune
• 3.3V and 5V Logic Compatible
• Undervoltage Lockout for Both High-side and
Low-Side Outputs
• Matched Propagation Delays
Manufactured on IXYS Integrated Circuits Division's
proprietary high-voltage BCDMOS on SOI (silicon on
isolator) process, the IX21844 is extremely robust and
virtually immune to negative transients. The UVLO
circuit prevents the turn-on of the MOSFET or IGBT
until there is sufficient VBS or VCC supply voltage. A
programmable dead-time can be set between 400ns
and 5us to insure that both the high-side and low-side
power MOSFET or IGBT are not enabled at the same
time. Propagation delays are matched for use in high
frequency applications.
Applications
The IX21844 is available in 14-pin DIP and 14-pin
SOIC (narrow body) packages. The 14-pin SOIC
(narrow body) package is also available in tape & reel.
•
•
•
•
Switch Mode Power Supply
Motor Driver Inverter
DC/DC Converter
Uninterruptible Power Supplies (UPS)
Ordering Information
Part
Description
IX21844G
14-Pin DIP (25/Tube)
IX21844N
14-Pin SOIC (Narrow Body) (50/Tube)
IX21844NTR 14-Pin SOIC (Narrow Body) (2000/Reel)
IX21844 Functional Block Diagram
VB
IN
DT
+5V
Input
&
Dead-Time
Control Logic
Level
Shift
VSS / COM
High
Voltage
Level
Shift
Pulse
Generator
R
S
R
Q
Buffer
Level
Shift
VSS / COM
LS Delay
Control
HO
VS
VCC
UVLO
SD
VSS
UVLO
Buffer
LO
COM
DS-IX21844-R01
www.ixysic.com
1
IX21844
INTEGRATED CIRCUITS DIVISION
1. Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.1 Package Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.2 Pin Description (DIP & SOIC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.3 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.4 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.5 Static Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.6 Dynamic Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.7 Test Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3
3
3
4
4
5
5
6
2. Performance Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3. Manufacturing Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1 Moisture Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2 ESD Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.3 Reflow Profile. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.4 Board Wash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.5 Mechanical Dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2
www.ixysic.com
12
12
12
12
12
13
R01
IX21844
INTEGRATED CIRCUITS DIVISION
1 Specifications
1.1 Package Pinout
IN 1
14 N/C
SD 2
13 VB
VSS 3
12 HO
DT 4
11 VS
10 N/C
COM 5
LO 6
9
N/C
VCC 7
8
N/C
1.2 Pin Description (DIP & SOIC)
Pin#
Name
Description
1
IN
Logic input for both high-side gate
drive output (HO) and low-side gate
drive output (LO). In phase with HO.
2
SD
Shut-down logic input. Active low.
3
VSS
Logic ground
4
DT
Programmable Dead-Time input
5
COM
6
LO
Low-side gate drive output
7
VCC
Low-side and logic supply
8
N/C
No connection
9
N/C
No connection
10
N/C
No connection
11
VS
High-side floating supply return
12
HO
High-side gate drive output
13
VB
High-side floating supply
14
N/C
No connection
R01
Low-side return
www.ixysic.com
3
IX21844
INTEGRATED CIRCUITS DIVISION
1.3 Absolute Maximum Ratings
Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage
parameters are absolute voltages referenced to COM.
Parameter
High-Side Floating Absolute Voltage
High-Side Floating Supply Offset Voltage
High-Side Floating Output Voltage
Low-Side and Logic Fixed Supply Voltage
Low-Side Output Voltage
Programmable Dead-Time Pin Voltage
Logic Input Voltage
Logic ground
Allowable Offset Supply Voltage Transient
Package Power Dissipation @ TA  25°C
Thermal Resistance, Junction to Ambient
Junction Temperature
Storage Temperature
Lead Temperature (Soldering, 10 Seconds)
Symbol
VB
VS
VHO
VCC
VLO
DT
VIN, VSD
VSS
dVS/dt
14-Pin PDIP
14-Pin SOIC
14-Pin PDIP
14-Pin SOIC
Min
Max
Units
-0.3
VB-20
700
VB+0.3
VS-0.3
VB+0.3
-0.3
20
VCC+0.3
-0.3
VSS-0.3
VCC+0.3
VSS-0.3
VCC+0.3
VCC-20
VCC+0.3
-50
-
50
1.6
1
75
120
150
150
300
PD
RJA
TJ
TS
TL
V
V/ns
W
°C/W
°C
1.4 Recommended Operating Conditions
For proper operation, the device should be used within the recommended conditions. The VS and VSS offset ratings
are tested with all supplies biased at a 15V differential.
Parameter
High-Side Floating Supply Absolute Voltage
High-Side Floating Supply Offset Voltage
High-Side Floating Output Voltage
Low-Side and Logic Fixed Supply Voltage
Low-Side Output Voltage
Logic Input Voltage
Programmable Dead-Time Pin Voltage
Logic Ground
Ambient Temperature
4
Symbol
VB
VS
VHO
VCC
VLO
VIN, VSD
DT
VSS
TA
www.ixysic.com
Min
Max
VS+10
VS+20
-5
VS
600
VB
10
20
VCC
0
VSS
VSS + 5
VSS
VCC
-5
-40
5
+125
Units
V
°C
R01
IX21844
INTEGRATED CIRCUITS DIVISION
1.5 Static Electrical Characteristics
VBIAS (VCC, VBS)=15V, VSS=COM, DT=VSS, and TA=25°C unless otherwise specified. The VIL, VIH, and IIN
parameters are referenced to VSS/COM and are applicable to the respective input leads: IN and SD. VO and IO are
referenced to COM and are applicable to the respective output leads: HO and LO.
Symbol
Min
Typ
Max
Logic “1” Input Voltage
Parameter
Conditions
VIH
2
-
-
Logic “0” Input Voltage
SD Input Positive Going Threshold
SD Input Negative Going Threshold
High Level Output Voltage, VBIAS - VO
VIL
-
0.8
0.8
2.5
IO=0A
VOH
2
-
Low Level Output Voltage, VO
IO=20mA
VOL
-
-
0.2
Offset Supply Leakage Current
Quiescent VBS Supply Current
VB=VS=600V
VCC=10V to 20V
VSD,TH+
VSD,TH-
VIN=0V or 5V
Quiescent VCC Supply Current
Units
V
ILK
-
33
60
IQBS
20
87
150
IQCC
0.4
1.8
2.2
mA
A
A
Logic “1” Input Bias Current
IN=5V
IIN+
-
35
60
Logic “0” Input Bias Current
IIN-
-
-
1
SD Logic “1” Input Bias Current
IN=0V
VSD=5V
ISD+
-
-
30
A
SD Logic “0” Input Bias Current
VSD=0V
A
VCC and VBS Supply
Under-voltage Positive Going Threshold
VCC and VBS Supply
Under-voltage Negative Going Threshold
-
Hysteresis
ISD-
-
15
60
VCCUV+
VBSUV+
8
8.6
9.8
VCCUVVBSUV-
7.4
7.9
9
VCCUVH
VBSUVH
0.3
0.7
-
Output High Short Circuit Pulsed Current
VO=0V, PW<10s
IO+
1.4
2.2
-
Output Low Short Circuit Pulsed Current
VO=15V, PW<10s
IO-
1.8
2.5
-
V
A
1.6 Dynamic Electrical Characteristics
VBIAS (VCC, VBS)=15V, CL=1000pF, TA=25°C, DT=VSS, and VSS=COM unless otherwise specified.
Parameter
Turn-On Propagation Delay
Turn-Off Propagation Delay
Shutdown propagation Delay
Delay Matching, HS & LS Turn-on
Delay Matching, HS & LS Turn-off
Turn-On Rise Time
Turn-Off Fall Time
Dead-Time: LO Turn-off to HO Turn-on (DTLO-HO)
& HO Turn-off to LO Turn-on (DTHO-LO)
Dead-Time Matching: (DTLO-HO) - (DTHO-LO)
R01
Conditions
VS=0V
VS=0V or 600V
Symbol
Min
Typ
Max
ton
-
560
900
toff
-
200
400
-
tSD
-
225
0
0
23
400
90
40
60
VS=0V
MTon
MToff
tr
RDT=0
RDT=200k
RDT=0
RDT=200k
www.ixysic.com
tf
DT
MDT
Units
ns
-
14
35
280
355
520
4
5
6
s
-
0
0
50
600
ns
5
IX21844
INTEGRATED CIRCUITS DIVISION
1.7 Test Waveforms
1.7.1 Switching Time Test Circuit
IN
1
14
SD
2
13
3 VSS
12
4 DT
5 COM
LO
CL
VB=15V
HO
10μF
VS 11
CL
0.1μF
10
6
9
7 VCC
8
VCC=15V
10μF
1.7.2 Input/Output Timing Diagram
0.1μF
1.7.5 Delay Matching Waveform Definitions
IN(LO)
IN
IN(HO)
50%
SD
50%
LO
HO
10%
HO
MT
MT
LO
90%
LO
1.7.3 Shutdown Waveform Definition
HO
1.7.6 Switching Time Waveform Definitions
IN(LO)
SD
50%
50%
IN(HO)
ton
tsd
HO
LO
90%
LO
HO
IN
90%
HO
LO
DTLO-HO
10%
90%
tf
90%
10%
10%
1.7.7 Truth Table
50%
50%
toff
tr
90%
1.7.4 Dead-Time Waveform Definition
50%
DTHO-LO
IN
SD
HO
LO
1
1
H
L
0
1
L
H
X
0
L
L
10%
MDT= DTLO-HO - DTHO-LO
6
www.ixysic.com
R01
IX21844
INTEGRATED CIRCUITS DIVISION
2 Performance Characteristics
Turn-On Propagation Delay
vs. VBIAS Supply Voltage
800
700
600
700
600
500
500
400
400
300
400
Delay (ns)
900
800
12
14
16
Supply Voltage (V)
18
20
300
200
-50
-25
0
25
50
75 100
Temperature (ºC)
125
20
0
12
14
16
Supply Voltage (V)
18
20
-50
30
20
10
0
14
16
Supply Voltage (V)
18
20
600
-25
0
25
50
75 100
Temperature (ºC)
125
200
3
2
0
25
50
75 100
Temperature (ºC)
125
150
18
20
SD Propagation Delay
vs. VBIAS Supply Voltage
250
200
150
100
0
0
14
16
Supply Voltage (V)
300
1
-25
12
350
4
100
-50
200
400
Delay (ns)
Deadtime (μs)
300
300
10
5
400
150
400
150
Deadtime
vs. RDT
6
500
125
0
-50
Deadtime
vs. Temperature
(RDT=0Ω)
25
50
75 100
Temperature (ºC)
100
0
12
0
500
Deadtime (ns)
Fall Time (ns)
10
-25
Deadtime
vs. VBIAS Supply Voltage
(RDT=0Ω)
600
40
10
20
10
50
20
20
30
Turn-Off Fall Time
vs. Temperature
30
18
40
10
40
14
16
Supply Voltage (V)
50
30
150
12
Turn-On Rise Time
vs. Temperature
Turn-On Rise Time
vs. VBIAS Supply Voltage
Turn-Off Fall Time
vs. VBIAS Supply Voltage
50
Fall Time (ns)
10
150
0
0
Deadtime (ns)
125
10
100
R01
50
25
75 100
Temperature (ºC)
Rise Time (ns)
40
Rise Time (ns)
Delay (ns)
400
0
-25
Turn-Off Propagation Delay
vs. Temperature
50
200
0
-50
500
300
100
300
10
Turn-Off Propagation Delay
vs. VBIAS Supply Voltage
500
1000
900
Delay (ns)
Delay (ns)
1000
Turn-On Propagation Delay
vs. Temperature
50
0
0
50
100
RDT (kΩ)
150
www.ixysic.com
200
10
12
14
16
Supply Voltage (V)
18
20
7
IX21844
INTEGRATED CIRCUITS DIVISION
SD Propagation Delay
vs. Temperature
400
5
SD Input Positive Going Threshold
vs. Temperature
SD Input Positive Going Threshold
vs. VBIAS Supply Voltage
5
350
250
200
150
Threshold (V)
Threshold (V)
Delay (ns)
4
4
300
3
2
100
3
2
1
1
50
0
-25
0
25
50
75 100
Temperature (ºC)
125
150
10
SD Input Negative Going Threshold
vs. VBIAS Supply Voltage
Threshold (V)
Threshold (V)
2
15
4
12
14
16
Supply Voltage (V)
18
20
-50
Supply Current (μA)
9
6
3
0
25
50
75 100
Temperature (ºC)
125
0
25
50
75 100
Temperature (ºC)
125
150
100
50
VCC Supply Current
vs. VCC Supply Voltage
12
4
3
2
1
0
14
16
Supply Voltage (V)
18
12
14
16
Supply Voltage (V)
18
20
25
50
75 100
Temperature (ºC)
125
150
125
150
150
100
50
-50
3
2
1
-25
0
25
50
75 100
Temperature (ºC)
www.ixysic.com
0
25
50
75 100
Temperature (ºC)
100
4
-50
-25
Offset Supply Leakage Current
vs. Temperature
0
10
0
200
20
VCC Supply Current
vs. Temperature
(VCC=15V)
5
Supply Current (mA)
5
-25
0
10
150
3
250
Leakage Current (μA)
-25
150
6
-50
0
-50
125
VBS Supply Current
vs. Temperature
200
0
25
50
75 100
Temperature (ºC)
9
150
Supply Current (μA)
250
12
-25
VBS Floating Supply Current
vs. VBS Floating Supply Voltage
VCC and VBS Undervoltage Threshold (+)
vs Temperature
15
0
0
0
12
-25
VCC and VBS Undervoltage Threshold (-)
vs. Temperature
5
1
10
UV Threshold (+) (V)
-50
20
2
0
Supply Current (mA)
18
3
1
8
14
16
Supply Voltage (V)
SD Input Negative Going Threshold
vs. Temperature
4
3
12
UV Threshold (-) (V)
5
0
0
-50
125
150
75
50
25
0
-50
-25
0
25
50
75 100
Temperature (ºC)
125
150
R01
IX21844
INTEGRATED CIRCUITS DIVISION
5
80
4
Bias Current (μA)
80
100
60
40
20
Bias Current (μA)
100
Bias Current (μA)
Logic "1" Input Bias Current
vs. Temperature
Logic "1" Input Bias Current
vs. VCC Supply Voltage
60
40
20
10
12
14
16
Supply Voltage (V)
18
-50
20
-25
4
5
2
0
25
50
75 100
Temperature (ºC)
125
14
16
Supply Voltage (V)
18
-50
20
4
3
2
0
0
18
-50
20
High Level Output Voltage (VBIAS - VO)
vs. Temperature
4
0.8
3
2
1
0
0
25
50
75 100
Temperature (ºC)
125
-25
0
25
50
75 100
Temperature (ºC)
125
150
25
50
75 100
Temperature (ºC)
125
150
4
3
2
1
10
12
14
16
Supply Voltage (V)
18
20
Low Level Output Voltage (VO)
vs. Temperature
Low Level Output Voltage (VO)
vs. VBIAS Supply Voltage
1.0
0.6
0.4
0.2
0.8
0.6
0.4
0.2
0.0
0
-50
0
0
150
Output Voltage (V)
1.0
Output Voltage (V)
5
-25
-25
High Level Output (VBIAS-VO)
vs. VBIAS Supply Voltage
5
Output Voltage (V)
Input Voltage (V)
Input Voltage (V)
12
1
1
14
16
Supply Voltage (V)
2
0
10
5
12
3
1
6
2
20
4
Logic "0" Input Voltage
vs. Temperature
3
18
5
150
4
14
16
Supply Voltage (V)
6
2
5
12
Logic "1" Input Voltage
vs. Temperature
3
Logic "0" Input Voltage
vs. VCC Supply Voltage
10
1
10
0
-25
2
150
1
6
Output Voltage (V)
125
4
1
0
-50
R01
25
50
75 100
Temperature (ºC)
Input Voltage (V)
6
Input Voltage (V)
Bias Current (μA)
5
0
Logic "1" Input Voltage
vs. VCC Supply Voltage
Logic "0" Input Bias Current
vs. Temperature
3
3
0
0
0
Logic "0" Input Bias Current
vs. VCC Supply Voltage
10
12
14
16
Supply Voltage (V)
www.ixysic.com
18
20
-50
-25
0
50
25
75 100
Temperature (ºC)
125
150
9
IX21844
INTEGRATED CIRCUITS DIVISION
5
Output Source Current (A)
5
Output Source Current (A)
Output Source Current
vs. Temperature
Output Source Current
vs. VBIAS Supply Voltage
4
3
2
1
10
2
1
12
14
16
Supply Voltage (V)
18
-50
20
-25
Output Sink Current
vs. VBIAS Supply Voltage
5
0
25
50
75 100
Temperature (ºC)
125
150
125
150
Output Sink Current
vs. Temperature
5
Output Source Current (A)
Output Sink Current (A)
3
0
0
4
3
2
1
0
10
10
4
12
14
16
Supply Voltage (V)
18
20
4
3
2
1
0
-50
-25
www.ixysic.com
0
25
50
75 100
Temperature (ºC)
R01
IX21844
INTEGRATED CIRCUITS DIVISION
Figure 1. Typical Connection Diagram
up to 600V
VCC
HO
IN
IN
VS
SD
SD
VCC
VB
LOAD
DT
RDT
VSS
R01
COM
VSS
LO
www.ixysic.com
11
IX21844
INTEGRATED CIRCUITS DIVISION
3 Manufacturing Information
3.1 Moisture Sensitivity
All plastic encapsulated semiconductor packages are susceptible to moisture ingression. IXYS Integrated
Circuits Division classified all of its plastic encapsulated devices for moisture sensitivity according to the
latest version of the joint industry standard, IPC/JEDEC J-STD-020, in force at the time of product
evaluation. We test all of our products to the maximum conditions set forth in the standard, and guarantee
proper operation of our devices when handled according to the limitations and information in that standard as well as
to any limitations set forth in the information or standards referenced below.
Failure to adhere to the warnings or limitations as established by the listed specifications could result in reduced
product performance, reduction of operable life, and/or reduction of overall reliability.
This product carries a Moisture Sensitivity Level (MSL) rating as shown below, and should be handled according to
the requirements of the latest version of the joint industry standard IPC/JEDEC J-STD-033.
Device
Moisture Sensitivity Level (MSL) Rating
IX21844G / IX21844N
MSL 1
3.2 ESD Sensitivity
This product is ESD Sensitive, and should be handled according to the industry standard
JESD-625.
3.3 Reflow Profile
This product has a maximum body temperature and time rating as shown below. All other guidelines of
J-STD-020 must be observed.
Device
Maximum Temperature x Time
IX21844G (DIP)
IX21844N (SOIC)
245°C for 30 seconds
260°C for 30 seconds
3.4 Board Wash
IXYS Integrated Circuits Division recommends the use of no-clean flux formulations. However, board washing to
remove flux residue is acceptable, and the use of a short drying bake may be necessary. Chlorine-based or
Fluorine-based solvents or fluxes should not be used. Cleaning methods that employ ultrasonic energy should not be
used.
12
www.ixysic.com
R01
IX21844
INTEGRATED CIRCUITS DIVISION
3.5 Mechanical Dimensions
3.5.1 IX21844G 14-Pin DIP Package
18.542 / 19.050
(0.730 / 0.750)
See Note 2
PCB Hole Pattern
0º / 15º
8.509 / 9.525
(0.335 / 0.375)
See Note 3
7.62 BSC
(0.300 BSC)
Pin 1
2.542
(0.100)
7.62
(0.300)
1.35
(0.053)
2.54
(0.100)
1.524 typ
(0.06 typ)
Hole Size =
6.223 / 6.477
(0.245 / 0.255)
See Note 2
5.334 max
(0.210 max)
3.175 / 3.429
(0.125 / 0.135)
NOTES:
1. JEDEC outline: MS-001 AA.
2. This dimension does not include mold flash or
protrusions. Mold flash or protrusions shall not
exceed 0.254 (0.010).
3. Measured at the lead tips with the leads
unconstrained.
4. Pointed or rounded lead tips are preferred to
ease insertion.
5. Distance between leads including dam bar
protrusions to be 0.127 (0.005).
6. Datum plane H coincident with the bottom of
lead where lead exits body.
H
Seating Plane
0.457 typ
(0.018 typ)
2.921 / 3.810
(0.115 / 0.150)
0.381 min
(0.015 min)
0.85
(0.0335)
DIMENSIONS
(min / max)
mm
(inches)
3.5.2 IX21844N 14-Pin SOIC (Narrow Body) Package
8.65 BSC
(0.341 BSC)
See Note 2
3.90 BSC
(0.154 BSC)
See Note 3
0.31 / 0.51
(0.012 / 0.020)
1.25 min
(0.049 min)
1.27 TYP
(0.05 TYP)
0.10 / 0.25
(0.004 / 0.010)
R01
0.37 x 45º
(0.015 x 45º)
PCB Pattern
DIMENSIONS
min / max
mm
(inches)
0º / 8º
1.75 max
(0.069 max)
5.98 / 6.02
(0.235 / 0.237)
0.15 / 0.25
(0.006 / 0.010)
0.4 / 0.95
(0.016 / 0.037)
5.30
(0.209)
1.50
(0.059)
0.60
(0.024)
1.27
(0.05)
NOTES:
1. JEDEC outline: MS-012 AB Rev F. (reference)
2. Molded package dimension do not include mold flash,
protrusions, or gate burrs. Mold flash, protrusions, and
gate burrs shall not exceed 0.15 (0.006) per side.
3. Lead dimensions do not include inter-lead flash or
protrusions. Inter-lead flash and protrusions shall not
exceed 0.25 (0.010) per side.
www.ixysic.com
13
IX21844
INTEGRATED CIRCUITS DIVISION
3.5.3 IX21844NTR Tape & Reel Packaging
1.75 ± 0.10
330.2 DIA.
(13.00 DIA.)
4.00 ± 0.10
8.00 ± 0.10
2.00 ± 0.10
Top Cover
Tape Thickness
0.102 MAX.
(0.004 MAX.)
1.20
7.50 ± 0.10
Ø1.50
+0.1, -0
6.50 9.65 ± 0.10
16.00 ± 0.30
Embossed Carrier
3.50
6.55 ± 0.10
Ø1.50 MIN
Embossment
2.35 ± 0.10
NOTES:
1. All dimensions in millimeters
2. 10 sprocket hole pitch cumulative tolerance ± 0.20.
3. Carrier camber is within 1mm in 250mm.
2.85 ± 0.10
4. Tape material : Black Conductive Polystyrene Alloy.
5. All dimensions meet EIA-481-C requirements.
6. Thickness : 0.30 ± 0.05mm.
For additional information please visit our website at: www.ixysic.com
IXYS Integrated Circuits Division makes no representations or warranties with respect to the accuracy or completeness of the contents of this publication and reserves the right to make
changes to specifications and product descriptions at any time without notice. Neither circuit patent licenses nor indemnity are expressed or implied. Except as set forth in IXYS Integrated
Circuits Division’s Standard Terms and Conditions of Sale, IXYS Integrated Circuits Division assumes no liability whatsoever, and disclaims any express or implied warranty, relating to its
products including, but not limited to, the implied warranty of merchantability, fitness for a particular purpose, or infringement of any intellectual property right.
The products described in this document are not designed, intended, authorized or warranted for use as components in systems intended for surgical implant into the body, or in other
applications intended to support or sustain life, or where malfunction of IXYS Integrated Circuits Division’s product may result in direct physical harm, injury, or death to a person or severe
property or environmental damage. IXYS Integrated Circuits Division reserves the right to discontinue or make changes to its products at any time without notice.
Specification: DS-IX21844-R01
©Copyright 2013, IXYS Integrated Circuits Division
All rights reserved. Printed in USA.
12/19/2013
14
www.ixysic.com
R01