ON NCV4279A50D2R2G Micropower 150 ma ldo linear regulator Datasheet

NCV4279A
5.0 V Micropower 150 mA
LDO Linear Regulator with
DELAY, Adjustable RESET,
and Sense Output
The NCV4279A is a 5.0 V precision micropower voltage regulator
with an output current capability of 150 mA.
The output voltage is accurate within ±2.0% with a maximum
dropout voltage of 0.5 V at 100 mA. Low quiescent current is a feature
drawing only 150 mA with a 1.0 mA load. This part is ideal for any and
all battery operated microprocessor equipment.
Microprocessor control logic includes an active reset output RO
with delay and a SI/SO monitor which can be used to provide an early
warning signal to the microprocessor of a potential impending reset
signal. The use of the SI/SO monitor allows the microprocessor to
finish any signal processing before the reset shuts the microprocessor
down.
The active Reset circuit operates correctly at an output voltage as
low as 1.0 V. The Reset function is activated during the power up
sequence or during normal operation if the output voltage drops
outside the regulation limits.
The reset threshold voltage can be decreased by the connection of an
external resistor divider to the RADJ lead. The regulator is protected
against reverse battery, short circuit, and thermal overload conditions.
The device can withstand load dump transients making it suitable for
use in automotive environments. The device has also been optimized
for EMC conditions.
If the application requires pullup resistors at the logic outputs Reset
and Sense Out, the NCV4269A with integrated resistors can be used.
Features
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May, 2013 − Rev. 4
MARKING
DIAGRAMS
8
8
1
SO−8
D1 SUFFIX
CASE 751
1
4279A5
ALYW
G
1
14
14
1
SO−14
D2 SUFFIX
CASE 751A
NCV4279A5G
AWLYWW
1
A
WL, L
YY, Y
WW, W
G, G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Lead Free Indicators
PIN CONNECTIONS
I
1
8
SI
Q
SO
RO
RADJ
5.0 V ± 2.0% Output
Low 150 mA Quiescent Current
Active Reset Output Low Down to VQ = 1.0 V
Adjustable Reset Threshold
150 mA Output Current Capability
Fault Protection
♦ +60 V Peak Transient Voltage
♦ −40 V Reverse Voltage
♦ Short Circuit
♦ Thermal Overload
Early Warning through SI/SO Leads
Internally Fused Leads in SO−14 Package
Very Low Dropout Voltage
Electrical Parameters Guaranteed Over Entire Temperature Range
These are Pb−Free Devices
NCV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
© Semiconductor Components Industries, LLC, 2013
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D
GND
SO−8
RADJ
D
GND
GND
GND
GND
RO
1
14
SI
I
GND
GND
GND
Q
SO
SO−14
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 13 of this data sheet.
Publication Order Number:
NCV4279A/D
NCV4279A
I
Q
Error
Amplifier
Current and
Saturation
Control
Reference
and Trim
RO
D
or
Reference
SO
RADJ
+
SI
−
GND
Figure 1. Block Diagram
PACKAGE PIN DESCRIPTION
Package Pin Number
SO−8
SO−14
Pin Symbol
3
1
RADJ
4
2
D
5
3, 4, 5, 6,
10, 11, 12
GND
6
7
RO
Reset Output; This is an Open−Collector Output. Leave Open if Not Used.
7
8
SO
Sense Output; This is an Open−Collector Output. If not used, keep open.
8
9
Q
5 V Output; Connect to GND with a 10 mF Capacitor, ESR < 10 W.
1
13
I
Input; Connect to GND Directly at the IC with a Ceramic Capacitor.
2
14
SI
Function
Reset Threshold Adjust; if not used to connect to GND.
Reset Delay; To Set Time Delay, Connect to GND with a Capacitor
Ground
Sense Input; If not used, Connect to Q.
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2
NCV4279A
MAXIMUM RATINGS (TJ = −40°C to 150°C)
Parameter
Symbol
Min
Max
Unit
Input to Regulator
VI
II
−40
Internally Limited
45
Internally Limited
V
Input Peak Transient Voltage
VI
−
60
V
Sense Input
VSI
ISI
−40
−1
45
1
V
mA
VRADJ
IRADJ
−0.3
−10
7
10
V
mA
Reset Delay
VD
ID
−0.3
Internally Limited
7
Internally Limited
V
Ground
Iq
50
−
mA
Reset Output
VRO
IRO
−0.3
Internally Limited
7
Internally Limited
V
Sense Output
VSO
ISO
−0.3
Internally Limited
7
Internally Limited
V
Regulated Output
VQ
IQ
−0.5
−10
7.0
−
V
mA
TJ
TSTG
−
−50
150
150
°C
°C
VI
TJ
−
−40
45
150
V
°C
Reset Threshold Adjust
Junction Temperature
Storage Temperature
Input Voltage Operating Range
Junction Temperature Operating Range
LEAD TEMPERATURE SOLDERING AND MSL
Parameter
MSL, 8−Lead, 14−Lead, LS Temperature 260°C Peak (Notes 3)
Symbol
Value
Unit
MSL
1
−
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. This device series incorporates ESD protection and exceeds the following ratings:
Human Body Model (HBM) ≤ 4.0 kV per AEC−Q100−002.
Machine Model (MM) ≤ 200 V per AEC−Q100−003.
2. Latchup Current Maximum Rating: ≤ 150 mA per AEC−Q100−004.
3. Lead free: 60−150 Sec above 217°C, 40 Sec Max at Peak, 265°C Peak.
THERMAL CHARACTERISTICS
Characteristic
Test Conditions (Typical Values)
Unit
Junction−to−Pin 4 ( Y − JL4, YL4)
53.8
°C/W
Junction−to−Ambient Thermal Resistance (RqJA, qJA)
170.9
°C/W
Junction−to−Pin 4 ( Y − JL4, YL4)
18.4
°C/W
Junction−to−Ambient Thermal Resistance (RqJA, qJA)
111.6
°C/W
SO−8 Package (Note 4)
SO−14 Package (Note 4)
4. 2 oz copper, 50
mm2
copper area, 1.5 mm thick FR4
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NCV4279A
ELECTRICAL CHARACTERISTICS (−40°C ≤ TJ ≤ 150°C, VI = 13.5 V unless otherwise specified)
Characteristic
Symbol
Test Conditions
Min
Typ
Max
Unit
Output Voltage
VQ
1 mA v IQ v 100 mA; 6 V v VI v 16 V
4.90
5.00
5.10
V
Current Limit
IQ
−
150
200
500
mA
Current Consumption; Iq = II – IQ
Iq
IQ = 1 mA, RO, SO High
−
190
250
mA
Current Consumption; Iq = II – IQ
Iq
IQ = 1 mA, RO High, SO Low (Note 5)
−
560
650
mA
Current Consumption; Iq = II – IQ
Iq
IQ = 10 mA, RO, SO High
−
250
450
mA
Current Consumption; Iq = II – IQ
Iq
IQ = 50 mA, RO, SO High
−
2.0
3.0
mA
Dropout Voltage
Vdr
IQ = 100 mA (Note 6)
−
0.25
0.5
V
Load Regulation
DVQ
IQ = 5 mA to 100 mA
−
10
20
mV
Line Regulation
DVQ
VI = 6 V to 26 V; IQ = 1 mA
−
10
30
mV
VRT
−
4.50
4.65
4.80
V
Reset Adjust Switching Threshold
VRADJ,TH
VQ > 3.5 V
1.26
1.35
1.44
V
Reset Output Saturation Voltage
VRO,SAT
VQ < VRT, RRO = 20 kW
−
0.1
0.4
V
Upper Delay Switching Threshold
VUD
−
1.4
1.8
2.2
V
Lower Delay Switching Threshold
VLD
−
0.3
0.45
0.60
V
VD,SAT
VQ < VRT
−
−
0.1
V
ID,C
VD = 1 V
3.0
6.5
9.5
mA
Delay Time L ³ H
td
CD = 100 nF
17
28
−
ms
Delay Time H ³ L
tRR
CD = 100 nF
−
3.15
−
ms
Sense Threshold High
VSI,High
−
1.24
1.31
1.38
V
Sense Threshold Low
VSI,Low
−
1.16
1.20
1.28
V
Sense Output Saturation Voltage
VSO,Low
VSI < 1.20 V; VQ > 3 V; RSO = 20 kW
−
0.1
0.4
V
ISI
−
−1.0
0.1
1.0
mA
REGULATOR
RESET GENERATOR
Reset Switching Threshold
Saturation Voltage on Delay Capacitor
Charge Current
INPUT VOLTAGE SENSE
Sense Input Current
5. Including 20 kW external SO pull−up resistor current.
6. Dropout voltage = VI − VQ measured when the output voltage has dropped 100 mV from the nominal value obtained at 13.5 V input.
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4
NCV4279A
II
I
CI
470 nF
1000 mF
IQ
Q
RADJ1
ISI
VI
SI
D
GND
ID
VSI
RADJ
SO
RO
Iq
VRO
VSO
IRADJ
RSO
RRO
VQ
VRADJ
VD
CD
100 nF
CQ
22 mF
RADJ2
Figure 2. Measuring Circuit
VI
t
< tRR
VQ
VRT
t
dV
I
+ D
dt
CD
VD
VUD
VLD
td
t
tRR
VRO
VRO,SAT
Power−on−Reset
t
Thermal
Shutdown
Voltage Dip
at Input
Undervoltage
Figure 3. Reset Timing Diagram
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5
Secondary
Spike
Overload
at Output
NCV4279A
Sense Input Voltage
VSI,High
VSI,Low
t
Sense Output Voltage
High
Low
t
Figure 4. Sense Timing Diagram
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NCV4279A
TYPICAL PERFORMANCE CHARACTERISTICS
3.2
16
VI = 13.5 V
VD = 1.0 V
VI = 13.5 V
2.8
12
2.4
10
2.0
VD, (V)
ID,C. (mA)
14
8
6
VUD
1.6
1.2
4
0.8
2
0.4
0
−40
0
40
80
120
VLD
0
−40
160
0
40
80
120
TJ (°C)
TJ (°C)
Figure 5. Charge Current ID,C vs. Temperature TJ
Figure 6. Switching Voltage VUD and VLD vs.
Temperature TJ
500
160
1.7
1.6
400
1.5
300
VDRADJ,TH, (V)
Vdr (mV)
TJ = 125°C
TJ = 25°C
200
TJ = −40°C
1.4
1.3
1.2
1.1
100
1.0
0
0
30
60
90
IQ (mA)
120
150
0.9
−40
180
12
30
10
120
160
8
RL = 33 W
VQ, (V)
Iq (mA)
25
15
6
RL = 50 W
4
10
0
0
80
Figure 8. Reset Adjust Switching Threshold
VRADJ,TH vs. Temperature TJ
35
5
40
TJ (°C)
Figure 7. Drop Voltage Vdr vs. Output Current IQ
20
0
RL = 50 W
10
2
RL = 200 W
RL = 100 W
20
30
40
0
50
0
2
4
6
8
VI (V)
VI (V)
Figure 9. Current Consumption Iq vs.
Input Voltage VI
Figure 10. Output Voltage VQ vs.
Input Voltage VI
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10
NCV4279A
TYPICAL PERFORMANCE CHARACTERISTICS
5.2
1.6
VI = 13.5 V
VI = 13.5 V
5.1
1.5
5.0
1.3
VQ, (V)
Sense Output High
Sense Output Low
4.9
1.2
4.8
1.1
4.7
1.0
−40
0
40
80
120
4.6
−40
160
0
40
80
120
160
TJ (°C)
TJ (°C)
Figure 11. Sense Threshold VSI vs. Temperature TJ
Figure 12. Output Voltage VQ vs. Temperature TJ
350
300
250
IQ (mV)
VSI, (V)
1.4
200
150
TJ = 25°C
TJ = 125°C
100
50
0
0
10
20
30
40
50
VI (V)
Figure 13. Output Current IQ vs. Input Voltage VI
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NCV4279A
TYPICAL PERFORMANCE CHARACTERISTICS
12
1.6
10
1.4
1.2
6
Iq, (mA)
Iq, (mA)
8
VI = 13.5 V
TJ = 25°C
1.0
VI = 13.5 V
TJ = 25°C
0.8
0.6
4
0.4
2
0
0.2
0
20
40
60
80
100
0
0
120
10
20
IQ (mA)
Figure 14. Current Consumption Iq vs.
Output Current IQ
7
250
6
200
Iq, (mA)
Iq, (mA)
50
TJ = 25°C
IQ = 100 mA
IQ = 100 mA
4
3
2
IQ = 50 mA
1
IQ = 10 mA
0
40
Figure 15. Current Consumption Iq vs.
Output Current IQ
TJ = 25°C
5
30
IQ (mA)
150
100
50
6
8
10
12
14
16
18
20
22
24
0
26
6
VI (V)
8
10
12
14
16
18
20
22
24
VI (V)
Figure 16. Current Consumption Iq vs.
Input Voltage VI
Figure 17. Current Consumption Iq vs.
Input Voltage VI
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26
NCV4279A
TYPICAL THERMAL CHARACTERISTICS
200
180
160
qJA (°C/W)
140
120
100
80
60
40
20
0
0
100
200
300
400
500
600
700
COPPER HEAT−SPREADER AREA (mm2)
SO−8 Std Package NCV4279, 1.0 oz
SO−8 Std Package NCV4279, 2.0 oz
SO−14 w/6 Thermal Leads NCV4279, 1.0 oz
SO−14 w/6 Thermal Leads NCV4279, 2.0 oz
Figure 18. Junction−to−Ambient Thermal Resistance (qJA) vs. Heat Spreader Area
1000
R(t) (°C/W)
100
10
1
0.1
0.000001
0.00001
0.0001
0.001
0.01
0.1
PULSE TIME (s)
Single Pulse (SO−8 Std Package) PCB = 50 mm2, 2.0 oz
Single Pulse (SO−14 w/6 Thermal Leads) PCB = 50 mm2, 2.0 oz
YLA (SO−8)
YLA (SO−14)
Figure 19. R(t) vs. Pulse Time
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10
1
10
100
1000
NCV4279A
APPLICATION DESCRIPTION
OUTPUT REGULATOR
If the reset adjust option is not needed, the RADJ pin
should be connected to GND causing the reset threshold to
go to its default value (typically 4.65 V).
The output is controlled by a precision trimmed reference.
The PNP output has drive quiescent current control for
regulation while the input voltage is low, preventing over
saturation. Current limit and voltage monitors complement
the regulator design to give safe operating signals to the
processor and control circuits.
RESET DELAY (D)
The reset delay circuit provides a delay (programmable by
capacitor CD) on the reset output lead RO. The delay lead D
provides charge current ID,C (typically 6.5 mA) to the
external delay capacitor CD during the following times:
1. During Powerup (once the regulation threshold has
been exceeded).
2. After a reset event has occurred and the device is
back in regulation. The delay capacitor is set to
discharge when the regulation (VRT, reset
threshold voltage) has been violated. When the
delay capacitor discharges to VLD, the reset signal
RO pulls low.
RESET OUTPUT (RO)
A reset signal, Reset Output, RO, (low voltage) is
generated as the IC powers up. After the output voltage VQ
increases above the reset threshold voltage VRT, the delay
timer D is started. When the voltage on the delay timer VD
passes VUD, the reset signal RO goes high. A discharge of
the delay timer VD is started when VQ drops and stays below
the reset threshold voltage VRT. When the voltage of the
delay timer VD drops below the lower threshold voltage VLD
the reset output voltage VRO is brought low to reset the
processor.
The reset output RO is an open collector NPN transistor,
controlled by a low voltage detection circuit. The circuit is
functionally independent of the rest of the IC, thereby
guaranteeing that RO is valid for VQ as low as 1.0 V.
SETTING THE DELAY TIME
The delay time is set by the delay capacitor CD and the
charge current ID. The time is measured by the delay
capacitor voltage charging from the low level of VDSAT to
the higher level VUD. The time delay follows the equation:
td + [CD (VUD * VD, SAT)]ńID
RESET ADJUST (RADJ)
Example:
Using CD = 100 nF.
Use the typical value for VD,SAT = 0.1 V.
Use the typical value for VUD = 1.8 V.
Use the typical value for Delay Charge Current ID = 6.5 mA.
The reset threshold VRT can be decreased from a typical
value of 4.65 V to as low as 3.5 V by using an external
voltage divider connected from the Q lead to the pin RADJ,
as shown in Figure 20. The resistor divider keeps the voltage
above the VRADJ,TH (typical 1.35 V) for the desired input
voltages, and overrides the internal threshold detector.
Adjust the voltage divider according to the following
relationship:
I
CI*
Q
VDD
RADJ1
0.1 mF
CQ**
10 mF
(2.2 mF)
RADJ
RADJ2
NCV4279A
D
RSI1
RRO
SI
RSI2
CD
SO
RO
Microprocessor
VBAT
td + [100 nF (1.8 * 0.1 V)] ń 6.5 mA + 26.2 ms
(eq. 1)
VRT + VRADJ, TH @ (RADJ1 ) RADJ2) ń RADJ2
(eq. 2)
RSO
I/O
GND
I/O
*CI required if regulator is located far from the power supply filter.
** CQ − minimum cap required for stability is 2.2 mF while higher over/under−shoots may be expected. Cap must operate at required temperature range.
Figure 20. Application Diagram
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(eq. 3)
NCV4279A
SENSE INPUT (SI) / SENSE OUTPUT (SO) VOLTAGE
MONITOR
solution, but, if the circuit operates at low temperatures
(−25°C to −40°C), both the value and ESR of the capacitor
will vary considerably. The capacitor manufacturer’s data
sheet usually provides this information.
The 10 mF output capacitor CQ shown in Figure 20 should
work for most applications; however, it is not necessarily the
optimized solution. Stability is guaranteed at CQ is min
2.2 mF and max ESR is 10 W. There is no min ESR limit
which was proved with MURATA’s ceramic caps
GRM31MR71A225KA01 (2.2 mF, 10 V, X7R, 1206) and
GRM31CR71A106KA01 (10 mF, 10 V, X7R, 1206) directly
soldered between output and ground pins.
An on−chip comparator is available to provide early
warning to the microprocessor of a possible reset signal. The
output is from an open collector driver. The reset signal
typically turns the microprocessor off instantaneously. This
can cause unpredictable results with the microprocessor.
The signal received from the SO pin will allow the
microprocessor time to complete its present task before
shutting down. This function is performed by a comparator
referenced to the band gap voltage. The actual trip point can
be programmed externally using a resistor divider to the
input monitor SI (Figure 20). The values for RSI1 and RSI2
are selected for a typical threshold of 1.20 V on the SI Pin.
CALCULATING POWER DISSIPATION IN A SINGLE
OUTPUT LINEAR REGULATOR
SIGNAL OUTPUT
The maximum power dissipation for a single output
regulator (Figure 20) is:
Figure 21 shows the SO Monitor timing waveforms as a
result of the circuit depicted in Figure 20. As the output
voltage (VQ) falls, the monitor threshold (VSILOW), is
crossed. This causes the voltage on the SO output to go low
sending a warning signal to the microprocessor that a reset
signal may occur in a short period of time. TWARNING is the
time the microprocessor has to complete the function it is
currently working on and get ready for the reset
shutdown signal. When the voltage on the SO goes low and
the RO stays high the current consumption is typically
560 mA at 1 mA load current.
PD(max) + [VI(max) * VQ(min)] IQ(max) ) VI(max) Iq (eq. 4)
where:
VI(max) is the maximum input voltage,
VQ(min) is the minimum output voltage,
IQ(max) is the maximum output current for the application,
and Iq is the quiescent current the regulator consumes at
IQ(max).
Once the value of PD(max) is known, the maximum
permissible value of RqJA can be calculated:
RqJA = (150°C – TA) / PD
VQ
(eq. 5)
The value of RqJA can then be compared with those in the
package section of the data sheet. Those packages with RqJA’s
less than the calculated value in equation 2 will keep the die
temperature below 150°C. In some cases, none of the packages
will be sufficient to dissipate the heat generated by the IC, and
an external heatsink will be required. The current flow and
voltages are shown in the Measurement Circuit Diagram.
SI
VSI,Low
VRO
HEATSINKS
A heatsink effectively increases the surface area of the
package to improve the flow of heat away from the IC and
into the surrounding air.
Each material in the heat flow path between the IC and the
outside environment will have a thermal resistance. Like
series electrical resistances, these resistances are summed to
determine the value of RqJA:
SO
TWARNING
Figure 21. SO Warning Waveform Time Diagram
RqJA + RqJC ) RqCS ) RqSA
STABILITY CONSIDERATIONS
(eq. 6)
where:
RqJC = the junction−to−case thermal resistance,
RqCS = the case−to−heat sink thermal resistance, and
RqSA = the heat sink−to−ambient thermal resistance.
RqJC appears in the package section of the data sheet. Like
RqJA, it too is a function of package type. RqCS and RqSA are
functions of the package type, heatsink and the interface
between them. These values appear in data sheets of
heatsink manufacturers. Thermal, mounting, and
heatsinking considerations are discussed in the
ON Semiconductor application note AN1040/D, available
on the ON Semiconductor website.
The input capacitor CI in Figure 20 is necessary for
compensating input line reactance. Possible oscillations
caused by input inductance and input capacitance can be
damped by using a resistor of approximately 1.0 W in series
with CI.
The output or compensation capacitor helps determine
three main characteristics of a linear regulator: startup delay,
load transient response and loop stability.
The capacitor value and type should be based on cost,
availability, size and temperature constraints. The
aluminum electrolytic capacitor is the least expensive
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NCV4279A
ORDERING INFORMATION
Package
Shipping†
NCV4279A50D1G
SO−8
(Pb−Free)
98 Units/Rail
NCV4279A50D1R2G
SO−8
(Pb−Free)
2500 Tape & Reel
SO−14
(Pb−Free)
55 Units/Rail
SO−14
(Pb−Free)
2500 Tape & Reel
Device
NCV4279A50D2G
Output Voltage
5.0 V
NCV4279A50D2R2G
†For information on tape and reel specifications,including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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NCV4279A
PACKAGE DIMENSIONS
SOIC−8
CASE 751−07
ISSUE AK
−X−
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
A
8
5
S
B
0.25 (0.010)
Y
M
M
1
4
−Y−
K
G
C
N
DIM
A
B
C
D
G
H
J
K
M
N
S
X 45 _
SEATING
PLANE
−Z−
0.10 (0.004)
H
D
0.25 (0.010)
M
Z Y
S
X
M
J
S
SOLDERING FOOTPRINT*
1.52
0.060
7.0
0.275
4.0
0.155
0.6
0.024
1.270
0.050
SCALE 6:1
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
http://onsemi.com
14
MILLIMETERS
MIN
MAX
4.80
5.00
3.80
4.00
1.35
1.75
0.33
0.51
1.27 BSC
0.10
0.25
0.19
0.25
0.40
1.27
0_
8_
0.25
0.50
5.80
6.20
INCHES
MIN
MAX
0.189
0.197
0.150
0.157
0.053
0.069
0.013
0.020
0.050 BSC
0.004
0.010
0.007
0.010
0.016
0.050
0 _
8 _
0.010
0.020
0.228
0.244
NCV4279A
PACKAGE DIMENSIONS
SOIC−14
CASE 751A−03
ISSUE J
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.127
(0.005) TOTAL IN EXCESS OF THE D
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
−A−
14
8
−B−
P 7 PL
0.25 (0.010)
M
7
1
G
−T−
0.25 (0.010)
M
T B
S
A
DIM
A
B
C
D
F
G
J
K
M
P
R
J
M
K
D 14 PL
F
R X 45 _
C
SEATING
PLANE
B
M
S
SOLDERING FOOTPRINT*
MILLIMETERS
MIN
MAX
8.55
8.75
3.80
4.00
1.35
1.75
0.35
0.49
0.40
1.25
1.27 BSC
0.19
0.25
0.10
0.25
0_
7_
5.80
6.20
0.25
0.50
INCHES
MIN
MAX
0.337 0.344
0.150 0.157
0.054 0.068
0.014 0.019
0.016 0.049
0.050 BSC
0.008 0.009
0.004 0.009
0_
7_
0.228 0.244
0.010 0.019
7X
7.04
14X
1.52
1
14X
0.58
1.27
PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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NCV4279A/D