Dallas DS21348 3.3v e1/t1/j1 line interface Datasheet

DS21348/Q348
3.3V E1/T1/J1 Line Interface
www.maxim-ic.com
FEATURES
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Complete E1, T1, or J1 line interface unit
(LIU)
Supports both long-haul and short-haul
trunks
Internal software-selectable receive-side
termination for 75Ω/100Ω/120W
3.3V power supply
32-bit or 128-bit crystal-less jitter attenuator
requires only a 2.048MHz master clock for
both E1 and T1 with option to use 1.544MHz
for T1
Generates the appropriate line build-outs,
with and without return loss, for E1 and
DSX-1 and CSU line build-outs for T1
AMI, HDB3, and B8ZS, encoding/decoding
16.384MHz, 8.192MHz, 4.096MHz, or
2.048MHz clock output synthesized to
recovered clock
Programmable monitor mode for receiver
Loopbacks and PRBS pattern generation/
detection with output for received errors
Generates/detects in-band loop codes, 1 to 16
bits including CSU loop codes
8-bit parallel or serial interface with optional
hardware mode
Muxed and nonmuxed parallel bus supports
Intel or Motorola
Detects/generates blue (AIS) alarms
NRZ/bipolar interface for TX/RX data I/O
Transmit open-circuit detection
Receive Carrier Loss (RCL) indication
(G.775)
High-Z State for TTIP and TRING
50mA (rms) current limiter
PIN DESCRIPTION
44
1
44 TQFP
7 mm
CABGA
ORDERING INFORMATION
DS21348TN
DS21348T
DS21348GN
DS21348G
DS21Q348N
DS21Q348
1 of 73
44-Pin TQFP (-40°C to +85°C)
44-Pin TQFP
(0o C to +70oC)
7mm CABGA (-40°C to +85°C)
7mm CABGA (0o C to +70oC)
(Quad) BGA
(-40°C to +85°C)
(Quad) BGA
(0o C to +70o C)
111501
DS21348/Q348
DESCRIPTION
The DS21348 is a complete selectable E1 or T1 LIU for short-haul and long-haul applications.
Throughout the data sheet, J1 is represented wherever T1 exists. Receive sensitivity adjusts automatically
to the incoming signal and can be programmed for 0dB to 12 dB or 0dB to 43dB for E1 applications and
0dB to 30dB or 0dB to 36dB for T1 applications. The device can generate the necessary G.703 E1
waveshapes in 75Ω or 120Ω applications and DSX-1 line build outs or CSU line build outs of 0dB,
-7.5dB, -15dB, and -22.5dB for T1 applications. The crystal-less onboard jitter attenuator requires only a
2.048MHz MCLK for both E1 and T1 applications (with the option of using a 1.544MHz MCLK in T1
applications). The jitter attenuator FIFO is selectable to either 32 bits or 128 bits in depth and can be
placed in either the transmit or receive data paths. An X 2.048MHz output clock synthesized to RCLK is
available for use as a backplane system clock (where n = 1, 2, 4, or 8). The DS21348 has diagnostic
capabilities such as loopbacks and PRBS pattern generation/detection. 16-bit loop-up and loop-down
codes can be generated and detected. The device can be controlled via an 8-bit parallel muxed or
nonmuxed port, serial port, or used in hardware mode. The device fully meets all of the latest E1 and T1
specifications including ANSI T1.403-1999, ANSI T1.408, AT&T TR 62411, ITU G.703, G.704, G.706,
G.736, G.775, G.823, I.431, O.151, O.161, ETSI ETS 300 166, JTG.703, JTI.431, JJ-20.1, TBR12,
TBR13, and CTR4.
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DS21348/Q348
TABLE OF CONTENTS
1.
2.
3.
LIST OF FIGURES............................................................................................................................... 4
LIST OF TABLES ................................................................................................................................ 5
INTRODUCTION................................................................................................................................. 6
3.1 DOCUMENT REVISION HISTORY ............................................................................................ 6
4. PIN DESCRIPTION ............................................................................................................................. 9
5. HARDWARE MODE ......................................................................................................................... 22
5.1 REGISTER MAP .......................................................................................................................... 23
5.2 PARALLEL PORT OPERATION................................................................................................ 23
5.3 SERIAL PORT OPERATION ...................................................................................................... 24
6. CONTROL REGISTERS.................................................................................................................... 24
6.1 DEVICE POWER-UP AND RESET ............................................................................................ 31
7 STATUS REGISTERS ....................................................................................................................... 34
8. DIAGNOSTICS .................................................................................................................................. 39
8.1 IN-BAND LOOP CODE GENERATION AND DETECTION ................................................... 39
8.2 LOOPBACKS ............................................................................................................................... 43
8.2.1 Remote Loopback (RLB)......................................................................................................... 43
8.2.2 Local Loopback (LLB)............................................................................................................ 43
8.2.3 Analog Loopback (LLB).......................................................................................................... 44
8.2.4 Dual Loopback (DLB) ............................................................................................................ 44
8.3 PRBS GENERATION & DETECTION ....................................................................................... 44
8.4 ERROR COUNTER...................................................................................................................... 44
8.4.1 Error Counter Update ............................................................................................................ 45
8.5 ERROR INSERTION.................................................................................................................... 45
9. ANALOG INTERFACE ..................................................................................................................... 46
9.1 RECEIVER..................................................................................................................................... 46
9.2 TRANSMITTER ........................................................................................................................... 47
9.3 JITTER ATTENUATOR .............................................................................................................. 47
9.4 G.703 SYNCHRONIZATION SIGNAL ...................................................................................... 48
10. DS21Q348 QUAD LIU....................................................................................................................... 55
11. DC CHARACTERISTICS.................................................................................................................. 59
12. AC CHARACTERISTICS.................................................................................................................. 61
13. MECHANICAL DIMENSIONS......................................................................................................... 70
13.1 MECHANICAL DIMENSIONS—QUAD VERSION................................................................. 72
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DS21348/Q348
1. LIST OF FIGURES
Figure 3-1 DS21348 BLOCK DIAGRAM................................................................................................... 7
Figure 3-2 RECEIVE LOGIC....................................................................................................................... 8
Figure 3-3 TRANSMIT LOGIC ................................................................................................................... 9
Figure 4-1 PARALLEL PORT MODE PINOUT (BIS1 = 0, BIS0 = 1 or 0)............................................. 22
Figure 4-2 SERIAL PORT MODE PINOUT (BIS1 = 1, BIS0 = 0) .......................................................... 22
Figure 4-3 HARDWARE MODE PINOUT (BIS1 = 1, BIS0 = 1) ............................................................ 22
Figure 5-1 SERIAL PORT OPERATION FOR READ ACCESS (R=1) MODE 1.................................. 25
Figure 5-2 SERIAL PORT OPERATION FOR READ ACCESS MODE 2 ............................................. 25
Figure 5-3 SERIAL PORT OPERATION FOR READ ACCESS MODE 3 ............................................. 26
Figure 5-4 SERIAL PORT OPERATION FOR READ ACCESS MODE 4 ............................................. 26
Figure 5-5 SERIAL PORT OPERATION FOR WRITE ACCESS (R=0) MODES 1&2 ...……………27
Figure 5-6 SERIAL PORT OPERATION FOR WRITE ACCESS MODES 3& 4 …………...…………27
Figure 9-1 BASIC INTERFACE…………………………………………………………………………49
Figure 9-2 PROTECTED INTERFACE USING INTERNAL RECEIVE TERMINATION.................... 50
Figure 9-3 PROTECTED INTERFACE USING EXTERNAL RECEIVE TERMINATION................... 51
Figure 9-4 E1 TRANSMIT PULSE TEMPLATE...................................................................................... 52
Figure 9-5 T1 TRANSMIT PULSE TEMPLATE...................................................................................... 53
Figure 9-6 JITTER TOLERANCE ............................................................................................................. 54
Figure 9-7 JITTER ATTENUATION ........................................................................................................ 54
Figure 10-1 BGA 12 x 12 PIN LAYOUT .................................................................................................. 58
Figure 12-1 INTEL BUS READ TIMING (PBTS = 0, BIS1 = 0, BIS0 = 0)............................................. 62
Figure 12-2 INTEL BUS WRITE TIMING (PBTS = 0, BIS1 = 0, BIS0 = 0)........................................... 62
Figure 12-3 MOTOROLA BUS TIMING (PBTS = 1, BIS1 = 0, BIS0 = 0) ............................................ 63
Figure 12-4 INTEL BUS READ TIMING (PBTS = 0, BIS1 = 0, BIS0 = 1)............................................. 65
Figure 12-5 INTEL BUS WRITE TIMING (PBTS = 0, BIS1 = 0, BIS0 = 1)........................................... 65
Figure 12-6 MOTOROLA BUS READ TIMING (PBTS = 1, BIS1 = 0, BIS0 = 1) ................................. 66
Figure 12-7 MOTOROLA BUS WRITE TIMING (PBTS = 1, BIS1 = 0, BIS0 = 1)................................ 66
Figure 12-8 SERIAL BUS TIMING (BIS1 = 1, BIS0 = 0)........................................................................ 67
Figure 12-9 RECEIVE SIDE TIMING ...................................................................................................... 68
Figure 12-10 TRANSMIT SIDE TIMING................................................................................................. 69
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DS21348/Q348
2. LIST OF TABLES
Table 4-1 BUS INTERFACE SELECTION ................................................................................................ 9
Table 4-2a PIN ASSIGNMENT IN PARALLEL PORT MODE .............................................................. 10
Table 4-2b PIN DESCRIPTIONS IN PARALLEL PORT MODE (Sorted by Pin Name, DS21348T Pin
Numbering) .......................................................................................................................................... 11
Table 4-3a PIN ASSIGNMENT IN SERIAL PORT MODE..................................................................... 13
Table 4-3b PIN DESCRIPTIONS IN SERIAL PORT MODE (Sorted by Pin Name, DS21348T Pin
Numbering) .......................................................................................................................................... 14
Table 4-4a PIN ASSIGNMENT IN HARDWARE MODE....................................................................... 16
Table 4-4b PIN DESCRIPTIONS IN HARDWARE MODE (Sorted by Pin Name, DS21348T Pin
Numbering) .......................................................................................................................................... 17
Table 4-5 LOOPBACK CONTROL IN HARDWARE MODE ................................................................ 20
Table 4-6 TRANSMIT DATA CONTROL IN HARDWARE MODE ..................................................... 20
Table 4-7 RECEIVE SENSITIVITY SETTINGS...................................................................................... 20
Table 4-8 MONITOR GAIN SETTINGS .................................................................................................. 20
Table 4-9 INTERNAL RX TERMINATION SELECT ............................................................................. 20
Table 4-10 MCLK SELECTION................................................................................................................ 20
Table 5-1 REGISTER MAP ....................................................................................................................... 23
Table 6-1 MCLK SELECTION.................................................................................................................. 29
Table 6-2 RECEIVE SENSITIVITY SETTINGS...................................................................................... 31
Table 6-3 BACK PLANE CLOCK SELECT............................................................................................. 32
Table 6-4 MONITOR GAIN SETTINGS .................................................................................................. 32
Table 6-5 INTERNAL RX TERMINATION SELECT ............................................................................. 33
Table 7-1 RECEIVED ALARM CRITERIA ............................................................................................. 35
Table 7-2 RECEIVE LEVEL INDICATION............................................................................................. 38
Table 8-1 TRANSMIT CODE LENGTH................................................................................................... 40
Table 8-2 RECEIVE CODE LENGTH ...................................................................................................... 40
Table 8-3 DEFINITION OF RECEIVED ERRORS.................................................................................. 44
Table 8-4 FUNCTION OF ECRS BITS AND RNEG PIN ........................................................................ 45
Table 9-1 LINE BUILD OUT SELECT FOR E1 IN REGISTER CCR4 (ETS = 0) ................................. 48
Table 9-2 LINE BUILD OUT SELECT FOR T1 IN REGISTER CCR4 (ETS = 1) ................................. 48
Table 9-3 TRANSFORMER SPECIFICATIONS FOR 3.3V OPERATION ............................................ 48
Table 10-1 DS21Q348 PIN ASSIGNMENT.............................................................................................. 55
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DS21348/Q348
3. INTRODUCTION
The analog AMI/HDB3 waveform off of the E1 line or the AMI/B8ZS waveform off of the T1 line is
transformer coupled into the RTIP and RRING pins of the DS21348. The user has the option to use
internal termination, software selectable for 75Ω/100Ω/120W applications, or external termination. The
device recovers clock and data from the analog signal and passes it through the jitter attenuation MUX
outputting the received line clock at RCLK and bipolar or NRZ data at RPOS and RNEG. The DS21348
contains an active filter that reconstructs the analog received signal for the nonlinear losses that occur in
transmission. The receive circuitry is also configurable for various monitor applications. The device has a
usable receive sensitivity of 0dB to -43dB for E1 and 0dB to -36dB for T1, which allows the device to
operate on 0.63mm (22AWG) cables up to 2.5km (E1) and 6k feet (T1) in length. Data input at TPOS and
TNEG is sent via the jitter attenuation mux to the waveshaping circuitry and line driver. The DS21348
will drive the E1 or T1 line from the TTIP and TRING pins via a coupling transformer. The line driver
can handle both CEPT 30/ISDN-PRI lines for E1 and long haul (CSU) or short haul (DSX-1) lines for T1.
3.1
DOCUMENT REVISION HISTORY
1) Datasheet for 3.3V only, 011801.
2) Added supply current measurements; added thermal characteristics of quad package, 092101.
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DS21348/Q348
MCLK
VSM
VSS
VDD
DS21348 BLOCK DIAGRAM Figure 3-1
2
2
JACLK
Jitter
Attenuator
MUX
Power Connections
2.048MHz to
1.544MHz PLL
16.384MHz or
8.192MHz or
4.096MHz or
2.048MHz
Synthesizer
TTIP
MUX
Local Loopback
Wave Shaping
TRING
CSU Filters
Line Drivers
See Figure 3-2
Remote Loopback
Unframed
All Ones
Insertion
Jitter Attenuation
(can be placed in either transmit or receive path)
Clock / Data
Recovery
Peak Detect
Remote Loopback (Dual Mode)
Analog Loopback
RTIP
Filter
RRING
Optional
Termination
VCO / PLL
See Figure 3-3
Control and
Interrupt
Control and Test Port
(routed to all blocks)
A0 to A4
Hardware
Interface
21
INT*
8
CS*
5
D0 to D7 /
AD0 to AD7
ALE(AS)
RD*(DS*)
WR*(R/W*)
Parallel Interface
PBTS
SDO
SDI
SCLK
RCL/LOTC
TPOS
TCLK
TNEG
MUX (the Serial, Parallel, and Hardware Interfaces share device pins)
Serial Interface
RPOS
RCLK
RNEG
PBEO
MUX
BIS1
BIS0
BPCLK
7 of 73
HRST*
TEST
DS21348/Q348
RECEIVE LOGIC Figure 3-2
Clock
Invert
From
Remote
Loopback
Routed to
All Blocks
RCLK
CCR2.0
RPOS
mux
B8ZS/HDB3
Decoder
NRZ Data
RNEG
BPV/CV/EXZ
CCR1.6
4 or 8 Zero Detect
16 Zero Detect
CCR2.3
CCR6.2/ RIR1.5
CCR6.0/
CCR6.1
All Ones
Detector
SR.4 RIR1.3
RIR1.7
Loop Code
Detector
SR.6
SR.7
PBEO
PRBS
Detector
SR.0
mux
CCR6.0
RIR1.6
CCR1.4
8 of 73
16-Bit Error
Counter (ECR)
rx bd
DS21348/Q348
TRANSMIT LOGIC Figure 3-3
CCR3.3
CCR1.6
CCR3.4
CCR2.2
CCR3.1
PRBS Generator
CCR3.0
OR
Gate
mux
1
To
Remote
Loopback
BPV
Insert
Loop Code Generator
Logic
Error
Insert
B8ZS/
HDB3
Coder
TPOS
OR
Gate
TNEG
mux
0
0
0
Clock
Invert
mux
Routed to
All Blocks
JACLK
(derived
from
MCLK)
1
mux
1
RCLK
OR
Gate
TCLK
CCR2.1
AND
Gate
CCR1.1
Loss Of Transmit
Clock Detect
CCR1.2
CCR1.0
tx bd
To LOTC Output Pin
SR.5
4. PIN DESCRIPTION
The DS21348 can be controlled in a parallel port mode, a serial port mode, or a hardware mode (Table
4-1, 4-2, and 4-3). The parallel and serial port modes are described in Section 3, and the Hardware Mode
is described below.
BUS INTERFACE SELECTION Table 4-1
BIS1
0
0
0
0
1
1
BIS0
0
0
1
1
0
1
PBTS
0
1
0
1
-
MODE
Muxed Intel
Muxed Motorola
Nonmuxed Intel
Nonmuxed Motorola
Serial Port
Hardware
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DS21348/Q348
PIN ASSIGNMENT IN PARALLEL PORT MODE Table 4-2a
DS21348T
PIN #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
DS21348G
PIN#
C3
C2
B1
D2
C1
D3
D1
E1
F2
F1
G1
E3
F3
G2
F4
G3
E4
G4
F5
G5
F6
G6
E5
E6
F7
D6
D5
D7
C6
C7
B6
B7
A7
C5
B5
A6
B4
C4
A4
B3
A3
B2
A2
A1
I/O
I
I
I
I
I
I
I/O
I
I
I
I
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
I/O
O
O
I
I
I
I
I
O
I
I
O
O
O
O
O
I
I
I
I
Parallel
Port Mode
CS*
RD*(DS*)
WR*(R/W*)
ALE(AS)
NA
NA
A4
A3
A2
A1
A0
D7/AD7
D6/AD6
D5/AD5
D4/AD4
D3/AD3
D2/AD2
D1/AD1
D0/AD0
VSM
VDD
VSS
INT*
PBEO
RCL/LOTC
TEST
RTIP
RRING
HRST*
MCLK
BPCLK
BIS0
BIS1
TTIP
VSS
VDD
TRING
RPOS
RNEG
RCLK
TPOS
TNEG
TCLK
PBTS
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DS21348/Q348
PIN DESCRIPTIONS IN PARALLEL PORT MODE (Sorted by Pin Name,
DS21348T Pin Numbering) Table 4-2b
ACRONYM
PIN
I/O
A0 to A4
I
ALE(AS)
11
to
7
4
I
BIS0/BIS1
32/33
I
BPCLK
31
O
CS*
1
I
D0 / AD0
to
D7 / AD7
19
to
12
I/O
HRST*
29
I
INT*
23
O
MCLK
30
I
NA
PBEO
24
I
O
PBTS
44
I
DESCRIPTION
Address Bus. In nonmultiplexed bus operation (BIS1 = 0, BIS0 =
1), serves as the address bus. In multiplexed bus operation (BIS1 =
0, BIS0 = 0), these pins are not used and should be tied low.
Address Latch Enable (Address Strobe). When using the parallel
port (BIS1 = 0) in multiplexed bus mode (BIS0 = 0), serves to
demultiplex the bus on a positive-going edge. In nonmultiplexed bus
mode (BIS0 = 1), should be tied low.
Bus Interface Select Bits 0 & 1. Used to select bus interface option.
See Table 4-1 for details.
Back Plane Clock. A 16.384MHz, 8.192MHz, 4.096MHz, or
2.048MHz clock output that is referenced to RCLK selectable via
CCR5.7 and CCR5.6. In hardware mode, defaults to 16.384MHz
output.
Chip Select. Must be low to read or write to the device. CS* is an
active low signal.
Data Bus/Address/Data Bus. In nonmultiplexed bus operation
(BIS1 = 0, BIS0 = 1), serves as the data bus. In multiplexed bus
operation (BIS1 = 0, BIS0 = 0), serves as an 8-bit multiplexed
address/data bus.
Hardware Reset. Bringing HRST* low will reset the DS21348
setting all control bits to their default state of all zeros.
Interrupt [INT*] Pin 23. Flags host controller during conditions
and change of conditions defined in the Status Register. Active low,
open drain output.
Master Clock. A 2.048MHz (±50ppm) clock source with TTL
levels is applied at this pin. This clock is used internally for both
clock/data recovery and for jitter attenuation. Use of a T1 1.544
MHz clock source is optional.
See Note 2.
Not Assigned. Should be tied low.
PRBS Bit Error Output. The receiver will constantly search for a
215-1 or a 220-1 PRBS depending on the ETS bit setting (CCR1.7).
Remains high if out of synchronization with the PRBS pattern. Goes
low when synchronized to the PRBS pattern. Any errors in the
received pattern after synchronization will cause a positive going
pulse (with same period as E1 or T1 clock) synchronous with
RCLK. PRBS bit errors can also be reported to the ECR1 and ECR2
registers by setting CCR6.2 to a logic 1.
Parallel Bus Type Select. When using the parallel port (BIS1 = 0),
set high to select Motorola bus timing, set low to select Intel bus
timing. This pin controls the function of the RD*(DS*), ALE(AS),
and WR*(R/W*) pins. If PBTS = 1 and BIS1 = 0, then these pins
assume the Motorola function listed in parenthesis (). In serial port
mode, this pin should be tied low.
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DS21348/Q348
ACRONYM
PIN
I/O
RCLK
40
O
RD*
(DS*)
2
I
RCL/
LOTC
25
O
RNEG
39
O
RPOS
38
O
RTIP/
RRING
27/
28
I
TCLK
43
I
TEST
26
I
TNEG
42
I
TPOS
41
I
TTIP/
TRING
34/
37
O
VDD
21/
36
20
22/
35
-
Receive Clock. Buffered recovered clock from the line.
Synchronous to MCLK in absence of signal at RTIP and RRING.
Read Input (Data Strobe). RD* and DS* are active low signals.
DS active low when in nonmultiplexed, Motorola mode. See the Bus
Timing Diagrams in Section 12.
Receive Carrier Loss/Loss of Transmit Clock. An output which
will toggle high during a receive carrier loss (CCR2.7 = 0) or will
toggle high if the TCLK pin has not been toggled for 5 msec ± 2
msec (CCR2.7 = 1). CCR2.7 defaults to logic 0 when in hardware
mode.
Receive Negative Data. Updated on the rising edge (CCR2.0 = 0)
or the falling edge (CCR2.0 = 1) of RCLK with the bipolar data out
of the line interface. Set NRZE (CCR1.6) to a one for NRZ
applications. In NRZ mode, data will be output on RPOS while a
received error will cause a positive-going pulse synchronous with
RCLK at RNEG. See Section 8.4 for details.
Receive Positive Data. Updated on the rising edge (CCR2.0 = 0) or
the falling edge (CCR2.0 = 1) of RCLK with bipolar data out of the
line interface. Set NRZE (CCR1.6) to a one for NRZ applications. In
NRZ mode, data will be output on RPOS while a received error will
cause a positive-going pulse synchronous with RCLK at RNEG. See
Section 8.4 for details.
Receive Tip and Ring. Analog inputs for clock recovery circuitry.
These pins connect via a 1:1 transformer to the line. See Section 7
for details.
Transmit Clock. A 2.048MHz or 1.544MHz primary clock. Used to
clock data through the transmit side formatter. Can be sourced
internally by MCLK or RCLK. See Common Control Register 1 and
Figure 3-3.
3-State Control. Set high to 3-state all outputs and I/O pins
(including the parallel control port). Set low for normal operation.
Useful in board level testing.
Transmit Negative Data. Sampled on the falling edge (CCR2.1 =
0) or the rising edge (CCR2.1 = 1) of TCLK for data to be
transmitted out onto the line.
Transmit Positive Data. Sampled on the falling edge (CCR2.1 = 0)
or the rising edge (CCR2.1 = 1) of TCLK for data to be transmitted
out onto the line.
Transmit Tip and Ring [TTIP & TRING]. Analog line driver
outputs. These pins connect via a step-up transformer to the line. See
Section 7 for details.
Positive Supply. 5.0V ±5%
I
-
Voltage Supply Mode. Should be tied high for 5V operation.
Signal Ground.
VSM
VSS
DESCRIPTION
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DS21348/Q348
ACRONYM
PIN
I/O
WR*
(R/W*)
3
I
DESCRIPTION
Write Input (Read/Write). WR* is an active low signal. See the
Bus Timing Diagrams in section 12.
PIN ASSIGNMENT IN SERIAL PORT MODE Table 4-3a
DS21348T
PIN #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
DS21348G
PIN#
C3
C2
B1
D2
C1
D3
D1
E1
F2
F1
G1
E3
F3
G2
F4
G3
E4
G4
F5
G5
F6
G6
E5
E6
F7
D6
D5
D7
C6
C7
B6
B7
A7
C5
B5
A6
B4
C4
A4
I/O
I
I
I
I
I
I
I/O
I
I
I
I
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
I/O
O
O
I
I
I
I
I
O
I
I
O
O
O
O
Serial
Port Mode
CS*
NA
NA
NA
SCLK
SDI
SDO
ICES
OCES
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
VSM
VDD
VSS
INT*
PBEO
RCL/LOTC
TEST
RTIP
RRING
HRST*
MCLK
BPCLK
BIS0
BIS1
TTIP
VSS
VDD
TRING
RPOS
RNEG
13 of 73
DS21348/Q348
DS21348T
PIN #
40
41
42
43
44
DS21348G
PIN#
B3
A3
B2
A2
A1
I/O
Serial
Port Mode
RCLK
TPOS
TNEG
TCLK
NA
O
I
I
I
I
PIN DESCRIPTIONS IN SERIAL PORT MODE (Sorted by Pin Name, DS21348T
Pin Numbering) Table 4-3b
ACRONYM
PIN
I/O
BIS0/
BIS1
BPCLK
32/
33
31
I
O
CS*
1
I
HRST*
29
I
ICES
8
I
INT*
23
O
MCLK
30
I
NA
OCES
9
I
I
PBEO
24
O
RCLK
40
O
DESCRIPTION
Bus Interface Select Bits 0 & 1. Used to select bus interface option.
See Table 4-1 for details.
Back Plane Clock. A 16.384MHz, 8.192MHz, 4.096MHz, or
2.048MHz clock output that is referenced to RCLK selectable via
CCR5.7 and CCR5.6. In hardware mode, defaults to 16.384 MHz
output.
Chip Select. Must be low to read or write to the device. CS* is an
active low signal.
Hardware Reset. Bringing HRST* low will reset the DS21348
setting all control bits to their default state of all zeros.
Input Clock Edge Select. Selects whether the serial port data input
(SDI) is sampled on rising (ICES =0) or falling edge (ICES = 1) of
SCLK.
Interrupt [INT*] Pin 23. Flags host controller during conditions
and change of conditions defined in the Status Register. Active low,
open drain output.
Master Clock. A 2.048MHz (±50ppm) clock source with TTL
levels is applied at this pin. This clock is used internally for both
clock/data recovery and for jitter attenuation. Use of a T1 1.544
MHz clock source is optional.
See Note 2.
Not Assigned. Should be tied low.
Output Clock Edge Select. Selects whether the serial port data
output (SDO) is valid on the rising (OCES = 1) or falling edge
(OCES = 0) of SCLK.
PRBS Bit Error Output. The receiver will constantly search for a
215-1 or a 220-1 PRBS depending on the ETS bit setting (CCR1.7).
Remains high if out of synchronization with the PRBS pattern. Goes
low when synchronized to the PRBS pattern. Any errors in the
received pattern after synchronization will cause a positive going
pulse (with same period as E1 or T1 clock) synchronous with
RCLK. PRBS bit errors can also be reported to the ECR1 and ECR2
registers by setting CCR6.2 to a logic 1.
Receive Clock. Buffered recovered clock from the line.
Synchronous to MCLK in absence of signal at RTIP and RRING.
14 of 73
DS21348/Q348
ACRONYM
PIN
I/O
RCL/
LOTC
25
O
RNEG
39
O
RPOS
38
O
RTIP/
RRING
27/
28
I
SCLK
SDI
5
6
I
I
SDO
7
O
TCLK
43
I
TEST
26
I
TNEG
42
I
TPOS
41
I
TTIP/
TRING
34/
37
O
VDD
21/
36
20
22/
35
-
Receive Carrier Loss/Loss of Transmit Clock. An output which
will toggle high during a receive carrier loss (CCR2.7 = 0) or will
toggle high if the TCLK pin has not been toggled for 5 msec ± 2
msec (CCR2.7 = 1). CCR2.7 defaults to logic 0 when in hardware
mode.
Receive Negative Data. Updated on the rising edge (CCR2.0 = 0)
or the falling edge (CCR2.0 = 1) of RCLK with the bipolar data out
of the line interface. Set NRZE (CCR1.6) to a one for NRZ
applications. In NRZ mode, data will be output on RPOS while a
received error will cause a positive-going pulse synchronous with
RCLK at RNEG. See section 8.4 for details.
Receive Positive Data. Updated on the rising edge (CCR2.0 = 0) or
the falling edge (CCR2.0 = 1) of RCLK with bipolar data out of the
line interface. Set NRZE (CCR1.6) to a one for NRZ applications. In
NRZ mode, data will be output on RPOS while a received error will
cause a positive-going pulse synchronous with RCLK at RNEG. See
section 8.4 for details.
Receive Tip and Ring. Analog inputs for clock recovery circuitry.
These pins connect via a 1:1 transformer to the line. See Section 7
for details.
Serial Clock. Serial bus clock input.
Serial Data Input. Sampled on rising edge (ICES = 0) or the falling
edge (ICES = 1) of SCLK.
Serial Data Output. Valid on the falling edge (OCES = 0) or the
rising edge (OCES = 1) of SCLK.
Transmit Clock. A 2.048MHz or 1.544MHz primary clock. Used to
clock data through the transmit side formatter. Can be sourced
internally by MCLK or RCLK. See Common Control Register 1 and
Figure 3-3.
3-State Control. Set high to 3-state all outputs and I/O pins
(including the parallel control port). Set low for normal operation.
Useful in board level testing.
Transmit Negative Data. Sampled on the falling edge (CCR2.1 =
0) or the rising edge (CCR2.1 = 1) of TCLK for data to be
transmitted out onto the line.
Transmit Positive Data. Sampled on the falling edge (CCR2.1 = 0)
or the rising edge (CCR2.1 = 1) of TCLK for data to be transmitted
out onto the line.
Transmit Tip and Ring [TTIP & TRING]. Analog line driver
outputs. These pins connect via a step-up transformer to the line.
See Section 7 for details.
Positive Supply. 5.0V ±5%
I
-
Voltage Supply Mode. Should be tied high for 5V operation.
Signal Ground.
VSM
VSS
DESCRIPTION
15 of 73
DS21348/Q348
PIN ASSIGNMENT IN HARDWARE MODE Table 4-4a
DS21348T
PIN #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
DS21348G
PIN#
C3
C2
B1
D2
C1
D3
D1
E1
F2
F1
G1
E3
F3
G2
F4
G3
E4
G4
F5
G5
F6
G6
E5
E6
F7
D6
D5
D7
C6
C7
B6
B7
A7
C5
B5
A6
B4
C4
A4
B3
A3
B2
A2
A1
I/O
I
I
I
I
I
I
I/O
I
I
I
I
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
I/O
O
O
I
I
I
I
I
O
I
I
O
O
O
O
O
I
I
I
I
Hardware
Mode
EGL
ETS
NRZE
SCLKE
L2
L1
L0
DJA
JAMUX
JAS
HBE
CES
TPD
TX0
TX1
LOOP0
LOOP1
MM0
MM1
VSM
VDD
VSS
RT1
PBEO
RCL
TEST
RTIP
RRING
HRST*
MCLK
BPCLK
BIS0
BIS1
TTIP
VSS
VDD
TRING
RPOS
RNEG
RCLK
TPOS
TNEG
TCLK
RT0
16 of 73
DS21348/Q348
PIN DESCRIPTIONS IN HARDWARE MODE (Sorted by Pin Name, DS21348T Pin
Numbering) Table 4-4b
ACRONYM
PIN
I/O
BIS0/
BIS1
BPCLK
32/
33
31
I
O
CES
12
I
DJA
8
I
EGL
1
I
ETS
2
I
HBE
11
I
HRST*
29
I
JAMUX
9
I
JAS
10
I
L0/L1/L2
7/
6/
5
16/
17
I
LOOP0/
LOOP1
I
DESCRIPTION
Bus Interface Select Bits 0 & 1. Used to select bus interface option.
See Table 4-1 for details.
Back Plane Clock. A 16.384MHz, 8.192MHz, 4.096MHz, or
2.048MHz clock output that is referenced to RCLK selectable via
CCR5.7 and CCR5.6. In hardware mode, defaults to 16.384MHz
output.
Receive & Transmit Clock Edge Select. Selects which RCLK
edge to update RPOS and RNEG and which TCLK edge to sample
TPOS and TNEG. CES combines TCES (CCR2.1) and RCES
(CCR2.0).
0 = update RNEG/RPOS on rising edge of RCLK; sample
TPOS/TNEG on falling edge of TCLK
1 = update RNEG/RPOS on falling edge of RCLK; sample
TPOS/TNEG on rising edge of TCLK
Disable Jitter Attenuator.
0 = jitter attenuator enabled
1 = jitter attenuator disabled
Receive Equalizer Gain Limit. This bit controls the sensitivity of
the receive equalizer. See Table 4-7.
E1/T1 Select.
0 = E1
1 = T1
Receive & Transmit HDB3/B8ZS Enable. HBE combines RHBE
(CCR2.3) and THBE (CCR2.2).
0 = enable HDB3 (E1)/B8ZS (T1)
1 = disable HDB3 (E1)/B8ZS (T1)
Hardware Reset. Bringing HRST* low will reset the DS21348
setting all control bits to their default state of all zeros.
Jitter Attenuator MUX. Controls the source for JACLK. See
Figure 3-1 and Table 4-10.
0 = JACLK sourced from MCLK (2.048MHz or 1.544MHz at
MCLK)
1 = JACLK sourced from internal PLL (2.048MHz at MCLK)
Jitter Attenuator Select.
0 = place the jitter attenuator on the receive side
1 = place the jitter attenuator on the transmit side
Transmit LIU Waveshape Select Bits 0 & 1 [H/W Mode]. These
inputs determine the waveshape of the transmitter. See Table 9-1
and Table 9-2.
Loopback Select Bits 0 & 1 [H/W Mode]. These inputs determine
the active loopback mode (if any). See Table 4-5.
17 of 73
DS21348/Q348
ACRONYM
PIN
I/O
MCLK
30
I
MM0/
MM1
18/
19
I
NA
NRZE
3
I
I
PBEO
24
O
RCLK
40
O
RCL
25
O
RNEG
39
O
RPOS
38
O
RT0/
RT1
RTIP/
RRING
44/
23
27/
28
I
I
DESCRIPTION
Master Clock. A 2.048MHz (±50ppm) clock source with TTL
levels is applied at this pin. This clock is used internally for both
clock/data recovery and for jitter attenuation. Use of a T1 1.544MHz
clock source is optional.
See Note 2.
Monitor Mode Select Bits 0 & 1 [H/W Mode]. These inputs
determine if the receive equalizer is in a monitor mode.
See Table 4-8.
Not Assigned. Should be tied low.
NRZ Enable [H/W Mode].
0 = Bipolar data at RPOS/RNEG and TPOS/TNEG
1 = NRZ data at RPOS and TPOS or TNEG; RNEG outputs a
positive going pulse when device receives a BPV, CV, or EXZ.
PRBS Bit Error Output. The receiver will constantly search for a
215-1 or a 220-1 PRBS depending on the ETS bit setting (CCR1.7).
Remains high if out of synchronization with the PRBS pattern.
Goes low when synchronized to the PRBS pattern. Any errors in the
received pattern after synchronization will cause a positive going
pulse (with same period as E1 or T1 clock) synchronous with
RCLK. PRBS bit errors can also be reported to the ECR1 and
ECR2 registers by setting CCR6.2 to a logic 1.
Receive Clock. Buffered recovered clock from the line.
Synchronous to MCLK in absence of signal at RTIP and RRING.
Receive Carrier Loss. An output which will toggle high during a
receive carrier loss (CCR2.7 = 0) or will toggle high if the TCLK
pin has not been toggled for 5 msec ± 2 msec (CCR2.7 = 1). CCR2.7
defaults to logic 0 when in hardware mode.
Receive Negative Data. Updated on the rising edge (CCR2.0 = 0)
or the falling edge (CCR2.0 = 1) of RCLK with the bipolar data out
of the line interface. Set NRZE (CCR1.6) to a one for NRZ
applications. In NRZ mode, data will be output on RPOS while a
received error will cause a positive-going pulse synchronous with
RCLK at RNEG. See section 8.4 for details.
Receive Positive Data. Updated on the rising edge (CCR2.0 = 0) or
the falling edge (CCR2.0 = 1) of RCLK with bipolar data out of the
line interface. Set NRZE (CCR1.6) to a one for NRZ applications.
In NRZ mode, data will be output on RPOS while a received error
will cause a positive-going pulse synchronous with RCLK at RNEG.
See section 8.4 for details.
Receive LIU Termination Select Bits 0 & 1 [H/W Mode]. These
inputs determine the receive termination. See Table 4-9.
Receive Tip and Ring. Analog inputs for clock recovery circuitry.
These pins connect via a 1:1 transformer to the line. See Section 7
for details.
18 of 73
DS21348/Q348
ACRONYM
PIN
I/O
SCLKE
4
I
TCLK
43
I
TEST
26
I
TNEG
42
I
TPD
13
I
TPOS
41
I
TTIP/
TRING
34/
37
O
TX0/
TX1
VDD
14/
15
21/
36
20
22/
35
I
VSM
VSS
DESCRIPTION
-
Receive & Transmit Synchronization Clock Enable. SCLKE
combines RSCLKE (CCR5.3) and TSCLKE (CCR5.2).
0 = disable 2.048 MHz synchronization transmit and receive mode
1 = enable 2.048 MHz synchronization transmit and receive mode
Transmit Clock. A 2.048MHz or 1.544MHz primary clock. Used to
clock data through the transmit side formatter. Can be sourced
internally by MCLK or RCLK. See Common Control Register 1 and
Figure 3-3.
3-State Control. Set high to 3-state all outputs and I/O pins
(including the parallel control port). Set low for normal operation.
Useful in board level testing.
Transmit Negative Data. Sampled on the falling edge (CCR2.1 =
0) or the rising edge (CCR2.1 = 1) of TCLK for data to be
transmitted out onto the line.
Transmit Power-Down.
0 = normal transmitter operation
1 = powers down the transmitter and 3-states the TTIP and TRING
pins
Transmit Positive Data. Sampled on the falling edge (CCR2.1 = 0)
or the rising edge (CCR2.1 = 1) of TCLK for data to be transmitted
out onto the line.
Transmit Tip and Ring [TTIP & TRING]. Analog line driver
outputs. These pins connect via a step-up transformer to the line.
See Section 7 for details.
Transmit Data Source Select Bits 0 & 1 [H/W Mode]. These
inputs determine the source of the transmit data. See Table 4-6.
Positive Supply. 5.0V ±5%
I
-
Voltage Supply Mode. Should be tied high for 5V operation.
Signal Ground.
NOTES:
1) G.703 requires an accuracy of ±50ppm for both T1 and E1. TR62411 and ANSI specs require an
accuracy of ±32ppm for T1 interfaces.
2) * Denotes active low.
19 of 73
DS21348/Q348
LOOP BACK CONTROL IN HARDWARE MODE Table 4-5
LOOPBACK
Remote Loop Back
Local Loop Back
Analog Loop Back
No Loop Back
SYMBOL
RLB
LLB
ALB
-
CONTROL BIT
CCR6.6
CCR6.7
CCR6.4
-
LOOP1
1
1
0
0
LOOP0
1
0
1
0
TRANSMIT DATA CONTROL IN HARDWARE MODE Table 4-6
TRANSMIT DATA
Transmit Unframed All Ones
Transmit Alternating Ones and Zeros
Transmit PRBS
TPOS and TNEG
SYMBOL
TUA1
TAOZ
TPRBSE
-
CONTROL BIT
CCR3.7
CCR3.5
CCR3.4
-
TX1
1
1
0
0
TX0
1
0
1
0
RECEIVE SENSITIVITY SETTINGS Table 4-7
EGL
(CCR4.4)
0
1
1
0
ETS
(CCR1.7)
0 (E1)
0 (E1)
1 (T1)
1 (T1)
RECEIVE SENSITIVITY
-12 dB (short haul)
-43 dB (long haul)
-30 dB (limited long haul)
-36 dB (long haul)
MONITOR GAIN SETTINGS Table 4-8
MM1
(CCR5.5)
0
0
1
1
MM0
(CCR5.4)
0
1
0
1
INTERNAL LINEAR GAIN
BOOST (dB)
Normal operation (no boost)
20
26
32
INTERNAL RX TERMINATION SELECT Table 4-9
RT1
(CCR5.1)
0
0
1
1
RT0
(CCR5.0)
0
1
0
1
INTERNAL RECEIVE
TERMINATION CONFIGURATION
Internal receive-side termination disabled
Internal receive-side 120W enabled
Internal receive-side 100W enabled
Internal receive-side 75W enabled
MCLK SELECTION Table 4-10
MCLK
2.048MHz
2.048MHz
1.544MHz
JAMUX
(CCR1.3)
0
1
0
ETS
(CCR1.7)
0
1
1
20 of 73
DS21348/Q348
PARALLEL PORT MODE PINOUT (BIS1 = 0, BIS0 = 1 or 0) Figure 4-1
34 TTIP
35 VSS
36 VDD
37 TRING
38 RPOS
39 RNEG
40 RCLK
41 TPOS
42 TNEG
43 TCLK
44 PBTS
1 CS*
BIS1 33
tie low
2 RD (DS)
BIS0 32
tie low (MUX) or high (non-MUX)
3 WR* (R/W*)
BPCLK 31
MCLK 30
4 ALE (AS)
DS21348
Parallel Port
Operation
5 NA
6 NA
7 A4
HRST* 29
RRING 28
RTIP 27
(Note: tie all NA pins low)
8 A3
TEST 26
9 A2
RCL/LOTC 25
PBEO 24
10 A1
AD0/D0 19
INT* 23
VSS 22
VDD 21
VSM 20
AD1/D1 18
AD2/D2 17
AD3/D3 16
AD4/D4 15
AD5/D5 14
AD6/D6 13
AD7/D7 12
11 A0
tie lo w
SERIAL PORT MODE PINOUT (BIS1 = 1, BIS0 = 0) Figure 4-2
35 VSS
36 VDD
37 TRING
38 RPOS
39 RNEG
40 RCLK
41 TPOS
42 TNEG
43 TCLK
tie low 44 PBTS
34
TT
IP
1 CS*
BIS1 33 tie high
2 NA
BIS0 32 tie low
3 NA
BPCLK 31
4 NA
MCLK 30
DS21348
Serial Port
Operation
5 SCLK
6 SDI
7 SDO
HRST* 29
RRING 28
RTIP 27
(Note: tie all NA pins low)
TEST 26
8 ICES
RCL/LOTC 25
9 OCES
10 NA
PBEO 24
11 NA
INT* 23
VSS 22
VDD 21
VSM 20
NA 19
NA 18
NA 17
NA 16
NA 15
NA 14
NA 13
NA 12
tie low
21 of 73
DS21348/Q348
HARDWARE MODE PINOUT (BIS1 = 1, BIS0 = 1) Figure 4-3
34 TTIP
35 VSS
36 VDD
37 TRING
38 RPOS
39 RNEG
40 RCLK
41 TPOS
42 TNEG
43 TCLK
44 RT0
1 EGL
BIS1 33
tie high
2 ETS
BIS0 32
tie high
3 NRZE
BPCLK 31
4 SCLKE
MCLK 30
DS21348
Hardware
Operation
5 L2
6 L1
HRST* 29
RRING 28
7 L0
RTIP 27
8 DJA
TEST 26
RCL 25
9 JAMUX
11 HBE
RT1 23
VSS 22
VDD 21
VSM 20
MM1 19
MM0 18
TX1 15
TX0 14
TPD 13
CES 12
LOOP1 17
PBEO 24
LOOP0 16
10 JAS
tie low
5. HARDWARE MODE
In hardware mode (BIS1 = 1, BIS0 = 1), pins 1-19, 23, 25, 31, and 44 are redefined to be used for
initializing the DS21348. BPCLK (pin 31) defaults to a 16.384MHz output when in hardware mode. The
RCL/LOTC (pin 25) is designated to RCL when in hardware mode. JABDS (CCR4.2) defaults to logic 0.
The RHBE (CCR2.3) and THBE (CCR2.2) control bits are combined and controlled by HBE at pin 11
while the RSCLKE (CCR5.3) and TSCLKE (CCR5.2) bits are combined and controlled by SCLKE at
pin 4. TCES (CCR2.1) and RCES (CCR2.0) are combined and controlled by CES at pin 12. The
transmitter functions are combined and controlled by TX1 (pin 15) and TX0 (pin 14). The loopback
functions are controlled by LOOP1 (pin 17) and LOOP0 (pin 16). All other control bits default to the
logic 0 setting.
22 of 73
DS21348/Q348
5.1
Register Map
Table 5-1 REGISTER MAP
ACRONYM
REGISTER NAME
R/W
PARALLEL
PORT
MODE
CCR1
CCR2
CCR3
CCR4
CCR5
CCR6
SR
IMR
RIR1
RIR2
IBCC
TCD1
Common Control Register 1
Common Control Register 2
Common Control Register 3
Common Control Register 4
Common Control Register 5
Common Control Register 6
Status Register
Interrupt Mask Register
Receive Information Register 1
Receive Information Register 2
In-Band Code Control Register
Transmit Code Definition
Register 1
Transmit Code Definition
Register 2
Receive Up Code Definition
Register 1
Receive Up Code Definition
Register 2
Receive Down Code Definition
Register 1
Receive Down Code Definition
Register 2
Error Count Register 1
Error Count Register 2
Test 1
Test 2
Test 3
-
R/W
R/W
R/W
R/W
R/W
R/W
R
R/W
R
R
R/W
R/W
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
SERIAL
PORT
MODE
See Notes 2 - 5
(msb)
(lsb)
B000 000A
B000 001A
B000 010A
B000 011A
B000 100A
B000 101A
B000 110A
B000 111A
B001 000A
B001 001A
B001 010A
B001 011A
R/W
0Ch
B001 100A
R/W
0Dh
B001 101A
R/W
0Eh
B001 110A
R/W
0Fh
B001 111A
R/W
10h
B010 000A
R
R
R/W
R/W
R/W
-
11h
12h
13h
14h
15h
Note 1
B010 001A
B010 010A
B010 011A
B010 100A
B010 101A
-
TCD2
RUPCD1
RUPCD2
RDNCD1
RDNCD2
ECR1
ECR2
TEST1
TEST2
TEST2
-
NOTES:
1)
2)
3)
4)
Register addresses 16h to 1Fh do not exist.
In the Serial Port Mode, the LSB is on the right hand side.
In the Serial Port Mode, data is read and written LSB first.
In the Serial Port Mode, the A bit (the LSB) determines whether the access is a read (A = 1) or a write
(A = 0).
5) In the Serial Port Mode, the B bit (the MSB) determines whether the access is a burst access (B = 1)
or a single register access (B = 0).
23 of 73
DS21348/Q348
5.2
Parallel Port Operation
When using the parallel interface on the DS21348 (BIS1 = 0) the user has the option for either
multiplexed bus operation (BIS1 = 0, BIS0 = 0) or non-multiplexed bus operation (BIS1 = 0, BIS0 = 1).
The DS21348 can operate with either Intel or Motorola bus timing configurations. If the PBTS pin is tied
low, Intel timing will be selected; if tied high, Motorola timing will be selected. All Motorola bus signals
are listed in parenthesis (). See the timing diagrams in Section 12 for more details.
5.3
Serial Port Operation
Setting BIS1 = 1 and BIS0 = 0 enables the serial bus interface on the DS21348. Port read/write timing is
unrelated to the system transmit and receive timing, allowing asynchronous reads or writes by the host.
See Section 12 for the AC timing of the serial port. All serial port accesses are LSB first. See Figure 5-1,
Figure 5-2, Figure 5-3, and Figure 5-4 for more details.
Reading or writing to the internal registers requires writing one address/command byte prior to
transferring register data. The first bit written (LSB) of the address/command byte specifies whether the
access is a read (1) or a write (0). The next 5 bits identify the register address. Bit 7 is reserved and must
be set to 0 for proper operation.
The last bit (MSB) of the address/command byte is the burst mode bit. When the burst bit is enabled
(B = 0) and a READ operation is performed, addresses 0 through 15h are read sequentially, starting at
address 0h. And when the burst bit is enabled and a WRITE operation is performed, addresses 0 through
16h are written sequentially, starting at address 0h. Burst operation is stopped once address 15h is read.
See Figure 5-5 and Figure 5-6 for more details.
All data transfers are initiated by driving the CS* input low. When Input Clock-Edge Select (ICES) is
low, input data is latched on the rising edge of SCLK and when ICES is high, input data is latched on the
falling edge of SCLK. When Output Clock-Edge Select (OCES) is low, data is output on the falling edge
of SCLK and when OCES is high, data is output on the rising edge of SCLK. Data is held until the next
falling or rising edge. All data transfers are terminated if the CS* input transitions high. Port control logic
is disabled and SDO is 3-stated when CS* is high.
24 of 73
DS21348/Q348
SERIAL PORT OPERATION FOR READ ACCESS (R=1) MODE 1 Figure 5-1
ICES = 1 (sample SDI on the falling edge of SCLK)
OCES = 1 (update SDO on rising edge of SCLK)
SCLK
1
2
3
4
5
6
A0
A1
A2
A3
A4
7
8
9
10
11
12
13
14
15
D0
D1
D2
D3
D4
D5
D6
16
CS*
SDI
1
0
(lsb)
B
(msb)
READ ACCESS ENABLED
SDO
(lsb)
D7
(msb)
SERIAL PORT OPERATION FOR READ ACCESS MODE 2 Figure 5-2
ICES = 1 (sample SDI on the falling edge of SCLK)
OCES = 0 (update SDO on falling edge of SCLK)
SCLK
1
2
3
4
5
6
A0
A1
A2
A3
A4
7
8
9
10
11
12
13
14
15
16
CS*
SDI
1
(lsb)
SDO
0
B
(msb)
D0
(lsb)
25 of 73
D1
D2
D3
D4
D5
D6
D7
(msb)
DS21348/Q348
SERIAL PORT OPERATION FOR READ ACCESS MODE 3 Figure 5-3
ICES = 0 (sample SDI on the rising edge of SCLK)
OCES = 0 (update SDO on falling edge of SCLK)
SCLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
CS*
SDI
A0
1
A1
A2
A3
A4
0
B
(lsb)
(msb)
SDO
D0
D1
D2
D3
D4
D5
D6
D7
(lsb)
(msb)
SERIAL PORT OPERATION FOR READ ACCESS MODE 4 Figure 5-4
ICES = 0 (sample SDI on the rising edge of SCLK)
OCES = 1 (update SDO on rising edge of SCLK)
SCLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
CS*
SDI
1
(lsb)
A0
A1
A2
A3
A4
0
B
(msb)
SDO
D0
D1
(lsb)
D2
D3
D4
D5
D6
D7
(msb)
D0
26 of 73
DS21348/Q348
SERIAL PORT OPERATION FOR WRITE ACCESS (R=0) MODES 1 & 2 Figure
5-5
ICES = 1 (sample SDI on the falling edge of SCLK)
SCLK
1
2
3
4
5
6
A0
A1
A2
A3
A4
7
8
9
10
11
12
13
14
15
B
DO
D1
D2
D3
D4
D5
D6
(msb)
(lsb)
16
CS*
SDI
0
0
(lsb)
D7
(msb)
WRITE ACCESS ENABLED
SDO
SERIAL PORT OPERATION FOR WRITE ACCESS (R=0) MODES 3 & 4
Figure 5-6
ICES = 0 (sample SDI on the rising edge of SCLK)
SCLK
1
2
3
4
5
6
0
A0
A1
A2
A3
A4
7
8
9
10
11
12
13
14
15
16
CS*
SDI
(lsb)
0
B
DO
(msb)
(lsb)
D1
D2
D3
D4
D5
D6
D7
(msb)
WRITE ACCESS ENABLED
SDO
27 of 73
DS21348/Q348
6. CONTROL REGISTERS
CCR1 (00H): COMMON CONTROL REGISTER 1
(MSB)
ETS
NRZE
RCLA
SYMBOL
POSITION
ETS
CCR1.7
NRZE
CCR1.6
RCLA
CCR1.5
ECUE
CCR1.4
JAMUX
CCR1.3
TTOJ
CCR1.2
TTOR
CCR1.1
LOTCMC
CCR1.0
ECUE
JAMUX
TTOJ
TTOR
(LSB)
LOTCMC
DESCRIPTION
E1/T1 Select.
0 = E1
1 = T1
NRZ Enable.
0 = Bipolar data at RPOS/RNEG and TPOS/TNEG
1 = NRZ data at RPOS and TPOS or TNEG; RNEG outputs a
positive going pulse when device receives a BPV, CV, or EXZ.
Receive Carrier Loss Alternate Criteria.
0 = RCL declared upon 255 (E1) or 192 (T1) consecutive zeros
1 = RCL declared upon 2048 (E1) or 1544 (T1) consecutive
zeros
Error Counter Update Enable. A 0 to 1 transition forces the
next clock cycle to load the error counter registers with the
latest counts and reset the counters. The user must wait a
minimum of two clocks cycles (976ns for E1 and 1296ns for
T1) before reading the error count registers to allow for a proper
update. See Section 6 for details.
Jitter Attenuator MUX. Controls the source for JACLK. See .
0 = JACLK sourced from MCLK (2.048MHz or 1.544MHz at
MCLK)
1 = JACLK sourced from internal PLL (2.048MHz at MCLK)
TCLK to JACLK. Internally connects TCLK to JACLK. See .
0 = disabled
1 = enabled
TCLK to RCLK. Internally connects TCLK to RCLK. See .
0 = disabled
1 = enabled
Loss Of Transmit Clock Mux Control. Determines whether
the transmit logic should switch to JACLK if the TCLK input
should fail to transition. See .
0 = do not switch to JACLK if TCLK stops
1 = switch to JACLK if TCLK stops
28 of 73
DS21348/Q348
MCLK SELECTION Table 6-1
MCLK
JAMUX
(CCR1.3)
0
1
0
2.048MHz
2.048MHz
1.544MHz
ETS
(CCR1.7)
0
1
1
CCR2 (01H): COMMON CONTROL REGISTER 2
(MSB)
P25S
n/a
SCLD
SYMBOL
POSITION
P25S
CCR2.7
SCLD
CCR2.6
CCR2.5
CLDS
CCR2.4
RHBE
CCR2.3
THBE
CCR2.2
TCES
CCR2.1
RCES
CCR2.0
CLDS
RHBE
THBE
TCES
(LSB)
RCES
DESCRIPTION
Pin 25 Select. Forced to logic 0 in hardware mode.
0 = toggles high during a Receive Carrier Loss condition
1 = toggles high if TCLK does not transition for at least 5ms
Not Assigned. Should be set to zero when written to.
Short Circuit Limit Disable (ETS = 0). Controls the 50 mA
(rms) current limiter.
0 = enable 50 mA current limiter
1 = disable 50 mA current limiter
Custom Line Driver Select. Setting this bit to a one will
redefine the operation of the transmit line driver. When this bit
is set to a one and CCR4.5 = CCR4.6 = CCR4.7 = 0, then the
device will generate a square wave at the TTIP and TRING
outputs instead of a normal waveform. When this bit is set to a
one and CCR4.5 = CCR4.6 = CCR4.7 ¹ 0, then the device will
force TTIP and TRING outputs to become open drain drivers
instead of their normal push-pull operation. This bit should be
set to zero for normal operation of the device. Contact the
factory for more details on how to use this bit.
Receive HDB3/B8ZS Enable.
0 = enable HDB3 (E1)/B8ZS (T1)
1 = disable HDB3 (E1)/B8ZS (T1)
Transmit HDB3/B8ZS Enable.
0 = enable HDB3 (E1)/B8ZS (T1)
1 = disable HDB3 (E1)/B8ZS (T1)
Transmit Clock Edge Select. Selects which TCLK edge to
sample TPOS and TNEG.
0 = sample TPOS and TNEG on falling edge of TCLK
1 = sample TPOS and TNEG on rising edge of TCLK
Receive Clock Edge Select. Selects which RCLK edge to
update RPOS and RNEG.
0 = update RPOS and RNEG on rising edge of RCLK
1 = update RPOS and RNEG on falling edge of RCLK
29 of 73
DS21348/Q348
CCR3 (02H): COMMON CONTROL REGISTER 3
(MSB)
TUA1
ATUA1
TAOZ
SYMBOL
POSITION
TUA1
CCR3.7
ATUA1
CCR3.6
TAOZ
CCR3.5
TPRBSE
CCR3.4
TLCE
CCR3.3
LIRST
CCR3.2
IBPV
CCR3.1
IBE
CCR3.0
TPRBSE
TLCE
LIRST
IBPV
(LSB)
IBE
DESCRIPTION
Transmit Unframed All Ones. The polarity of this bit is set
such that the device will transmit an all ones pattern on powerup or device reset. This bit must be set to a one to allow the
device to transmit data. The transmission of this data pattern is
always timed off of the JACLK (See Figure 3-1).
0 = transmit all ones at TTIP and TRING
1 = transmit data normally
Automatic Transmit Unframed All Ones. Automatically
transmit an unframed all ones pattern at TTIP and TRING
during a receive carrier loss (RCL) condition or receive all ones
condition.
0 = disabled
1 = enabled
Transmit Alternate Ones and Zeros. Transmit a …101010…
pattern at TTIP and TRING. The transmission of this data
pattern is always timed off of TCLK (See Figure 3-1).
0 = disabled
1 = enabled
Transmit PRBS Enable. Transmit a 215 - 1 (E1) or a 220 - 1
(T1) PRBS at TTIP and TRING.
0 = disabled
1 = enabled
Transmit Loop Code Enable. Enables the transmit side to
transmit the loop up code in the Transmit Code Definition
registers (TCD1 and TCD2). See Section 6 for details.
0 = disabled
1 = enabled
Line Interface Reset. Setting this bit from a zero to a one will
initiate an internal reset that resets the clock recovery state
machine and re-centers the jitter attenuator. Normally this bit is
only toggled on power-up. Must be cleared and set again for a
subsequent reset.
Insert BPV. A 0 to 1 transition on this bit will cause a single
BiPolar Violation (BPV) to be inserted into the transmit data
stream. Once this bit has been toggled from a 0 to a 1, the
device waits for the next occurrence of three consecutive ones
to insert the BPV. This bit must be cleared and set again for a
subsequent error to be inserted. See .
Insert Bit Error. A 0 to 1 transition on this bit will cause a
single logic error to be inserted into the transmit data stream.
This bit must be cleared and set again for a subsequent error to
be inserted. See Figure 3-3.
30 of 73
DS21348/Q348
6.1
Device Power-Up and Reset
The DS21348 will reset itself upon power-up setting all writeable registers to 00h and clear the status and
information registers. CCR3.7 (TUA1) = 0 results in the LIU transmitting unframed all ones. After the
power supplies have settled following power-up, initialize all control registers to the desired settings, then
toggle the LIRST bit (CCR3.2). At anytime, the DS21348 can be reset to the default settings by bringing
HRST* (pin 29) low (level triggered) or by powering down and powering up again.
CCR4 (03H): COMMON CONTROL REGISTER 4
(MSB)
L2
L1
L0
SYMBOL
POSITION
L2
CCR4.7
L1
CCR4.6
L0
CCR4.5
EGL
CCR4.4
JAS
CCR4.3
JABDS
CCR4.2
DJA
CCR4.1
TPD
CCR4.0
EGL
JAS
JABDS
DJA
DESCRIPTION
Line Build Out Select Bit 2. Sets the transmitter build out; see
Table 9-1 for E1 and Table 9-2 for T1.
Line Build Out Select Bit 1. Sets the transmitter build out; see
Table 9-1 for E1 and Table 9-2 for T1.
Line Build Out Select Bit 0. Sets the transmitter build out; see
Table 9-1 for E1 and Table 9-2 for T1.
Receive Equalizer Gain Limit. This bit controls the sensitivity
of the receive equalizer. See Table 6-2.
Jitter Attenuator Select.
0 = place the jitter attenuator on the receive side
1 = place the jitter attenuator on the transmit side
Jitter Attenuator Buffer Depth Select.
0 = 128 bits
1 = 32 bits (use for delay sensitive applications)
Disable Jitter Attenuator.
0 = jitter attenuator enabled
1 = jitter attenuator disabled
Transmit Power-Down.
0 = normal transmitter operation
1 = powers down the transmitter and 3-states the TTIP and
TRING pins
RECEIVE SENSITIVITY SETTINGS Table 6-2
EGL
(CCR4.4)
0
1
1
0
(LSB)
TPD
ETS
(CCR1.7)
0 (E1)
0 (E1)
1 (T1)
1 (T1)
RECEIVE SENSITIVITY
-12dB (short haul)
-43dB (long haul)
-30dB (limited long haul)
-36dB (long haul)
31 of 73
DS21348/Q348
CCR5 (04H): COMMON CONTROL REGISTER 5
(MSB)
BPCS1
BPCS0
MM1
MM0
RSCLKE
TSCLKE
RT1
SYMBOL
POSITION
DESCRIPTION
BPCS1
CCR5.7
Back Plane Clock Select 1. See Table 6-3 for details.
BPCS0
CCR5.6
Back Plane Clock Select 0. See Table 6-3 for details
MM1
CCR5.5
Monitor Mode 1. See Table 6-4.
MM0
CCR5.4
Monitor Mode 0. See Table 6-4.
RSCLKE
CCR5.3
TSCLKE
CCR5.2
RT1
CCR5.1
Receive Synchronization Clock Enable.
0 = disable 2.048MHz synchronization receive mode
1 = enable 2.048MHz synchronization receive mode
Transmit Synchronization Clock Enable.
0 = disable 2.048MHz transmit synchronization clock
1 = enable 2.048MHz transmit synchronization clock
Receive Termination 1. See Table 6-5 for details.
RT0
CCR5.0
Receive Termination 0. See Table 6-5 for details.
BACK PLANE CLOCK SELECT Table 6-3
BPCS1
(CCR5.7)
0
0
1
1
BPCS0
(CCR5.6)
0
1
0
1
BPCLK FREQUENCY
16.384MHz
8.192MHz
4.096MHz
2.048 MHz
MONITOR GAIN SETTINGS Table 6-4
MM1
(CCR5.5)
0
0
1
1
MM0
(CCR5.4)
0
1
0
1
INTERNAL LINEAR
GAIN BOOST (dB)
Normal operation (no boost)
20
26
32
32 of 73
(LSB)
RT0
DS21348/Q348
INTERNAL RX TERMINATION SELECT Table 6-5
RT1
(CCR5.1)
0
0
1
1
RT0
(CCR5.0)
0
1
0
1
INTERNAL RECEIVE
TERMINATION CONFIGURATION
Internal receive-side termination disabled
Internal receive-side 120W enabled
Internal receive-side 100W enabled
Internal receive-side 75W enabled
CCR6 (05H): COMMON CONTROL REGISTER 6
(MSB)
LLB
RLB
ARLBE
SYMBOL
POSITION
LLB
CCR6.7
RLB
CCR6.6
ARLBE
CCR6.5
ALB
CCR6.4
RJAB
CCR6.3
ALB
RJAB
ECRS2
ECRS1
(LSB)
ECRS0
DESCRIPTION
Local Loopback. In Local Loopback (LLB), transmit data will
be looped back to the receive path passing through the jitter
attenuator if it is enabled. Data in the transmit path will act as
normal. See for details.
0 = loopback disabled
1 = loopback enabled
Remote Loopback. In Remote Loopback (RLB), data output
from the clock/data recovery circuitry will be looped back to the
transmit path passing through the jitter attenuator if it is
enabled. Data in the receive path will act as normal while data
presented at TPOS and TNEG will be ignored. See for details.
0 = loopback disabled
1 = loopback enabled
Automatic Remote Loopback Enable & Reset. When this bit
is set high, the device will automatically go into remote
loopback when it detects loop up code programmed into the
Receive Loop Up Code Definition Registers (RUPCD1 and
RUPCD2) for a minimum of 5 seconds and it will also set the
RIR2.1 status bit. Once in a RLB state, it will remain in this
state until it has detected the loop code programmed into the
Receive Loop Down Code Definition Registers (RDNCD1 and
RDNCD2) for a minimum of 5 seconds at which point it will
force the device out of RLB and clear RIR2.1. The automatic
RLB circuitry can be reset by toggling this bit from a 1 to a 0.
The action of the automatic remote loopback circuitry is
logically OR’ed with the RLB (CCR6.6) control bit (i.e. either
one can cause a RLB to occur).
Analog Loopback. In Analog Loopback (ALB), signals at
TTIP and TRING will be internally connected to RTIP and
RRING. The incoming signals, from the line, at RTIP and
RRING will be ignored. The signals at TTIP and TRING will
be transmitted as normal. See for more details.
0 = loopback disabled
1 = loopback enabled
RCLK Jitter Attenuator Bypass. This control bit allows the
33 of 73
DS21348/Q348
SYMBOL
POSITION
DESCRIPTION
ECRS2
CCR6.2
receive recovered clock and data to bypass the jitter attenuation
while still allowing the BPCLK output to use the jitter
attenuator. See for details.
0 = disabled
1 = enabled
Error Count Register Select 2. See Section 8.4 for details.
ECRS1
CCR6.1
Error Count Register Select 1. See Section 8.4 for details.
ECRS0
CCR6.0
Error Count Register Select 0. See Section 8.4 for details.
7. STATUS REGISTERS
There are three registers that contain information on the current real time status of the device, Status
Register (SR) and Receive Information Registers 1 and 2 (RIR1/RIR2). When a particular event has
occurred (or is occurring), the appropriate bit in one of these three registers will be set to a one. Some of
the bits in SR, RIR1, and RIR2 are latched bits and some are real time bits. The register descriptions
below list which status bits are latched and which are real time bits. For latched status bits, when an event
or an alarm occurs the bit is set to a one and will remain set until the user reads that bit. The bit will be
cleared when it is read and it will not be set again until the event has occurred again. Two of the latched
status bits (RUA1 and RCL) will remain set after reading if the alarm is still present.
The user will always precede a read of any of the three status registers with a write. The byte written to
the register will inform the DS21348 which bits the user wishes to read and have cleared. The user will
write a byte to one of these registers with a one in the bit positions to be read and a zero in the other bit
positions. When a one is written to a bit location, that location will be updated with the latest information.
When a zero is written to a bit position, that bit position will not be updated and the previous value will
be held. A write to the status and information registers will be immediately followed by a read of the
same register. The read result should be logically AND’ed with the mask byte that was just written and
this value should be written back into the same register to insure that bit does indeed clear. This second
write step is necessary because the alarms and events in the status registers occur asynchronously with
respect to their access via the parallel port. This write-read-write scheme allows an external
microcontroller or microprocessor to individually poll certain bits without disturbing the other bits in the
register. This operation is key in controlling the DS21348 with higher-order software languages.
The bits in the SR register have the unique ability to initiate a hardware interrupt via the INT* output pin.
Each of the alarms and events in the SR can be either masked or unmasked from the interrupt pin via the
Interrupt Mask Register (IMR). The interrupts caused by the RCL, RUA1, and LOTC bits in SR act
differently than the interrupts caused by the other status bits in SR. The RCL, RUA1 and LOTC bits will
force the INT* pin low whenever they change state (i.e., go active or inactive). The INT* pin will be
allowed to return high (if no other interrupts are present) when the user reads the alarm bit that caused the
interrupt to occur even if the alarm is still present. The other status bits in SR can force the INT* pin low
when they are set. The INT* pin will be allowed to return high (if no other interrupts are present) when
the user reads the event bit that caused the interrupt to occur.
34 of 73
DS21348/Q348
RECEIVED ALARM CRITERIA Table 7-1
ALARM
RUA1
E1/T1
E1
RUA1
T1
RCL1
E1
RCL1
T1
SET CRITERIA
Less than 2 zeros in two frames
(512 bits)
Over a 3ms window, five or
fewer zeros are received
255 (or 2048)2 consecutive zeros
received (G.775)
192 (or 1544)2 consecutive zeros
are received
CLEAR CRITERIA
More than 2 zeros in two frames
(512 bits)
Over a 3ms window, six or more
zeros are received
In 255 bit times, at least 32 ones
are received
14 or more ones out of 112
possible bit positions are
received starting with the first
one received
NOTES:
1) Receive carrier loss (RCL) is also known as loss of signal (LOS) or Red Alarm in T1.
2) See CCR1.5 for details.
SR (06H): STATUS REGISTER
(MSB)
LUP
LDN
LOTC
SYMBOL
POSITION
LUP
(latched)
SR.7
LDN
(latched)
SR.6
LOTC
(real time)
RUA1
(latched)
RCL
(latched)
TCLE
(real time)
SR.5
TOCD
(real time)
PRBSD
(real time)
SR.1
SR.4
SR.3
SR.2
SR.0
RUA1
RCL
TCLE
TOCD
(LSB)
PRBSD
DESCRIPTION
Loop Up Code Detected. Set when the loop up code defined in
registers RUPCD1 and RUPCD2 is being received. See Section
6 for details.
Loop Down Code Detected. Set when the loop down code
defined in registers RDNCD1 and RDNCD2 is being received.
See Section 6 for details.
Loss of Transmit Clock. Set when the TCLK pin has not
transitioned for 5msec (±2msec). Will force the LOTC pin high.
Receive Unframed All Ones. Set when an unframed all ones
code is received at RRING and RTIP. See Table 7-1for details.
Receive Carrier Loss. Set when a receive carrier loss condition
exists at RRING and RTIP. See Table 7-1for details.
Transmit Current Limit Exceeded. Set when the 50 mA (rms)
current limiter is activated whether the current limiter is enabled
or not.
Transmit Open Circuit Detect. Set when the device detects
that the TTIP and TRING outputs are open circuited.
PRBS Detect. Set when the receive-side detects a 215 - 1 (E1)
or a 220 - 1 (T1) Pseudo Random Bit Sequence (PRBS).
35 of 73
DS21348/Q348
IMR (07H): INTERRUPT MASK REGISTER
(MSB)
LUP
LDN
LOTC
SYMBOL
POSITION
LUP
IMR.7
LDN
IMR.6
LOTC
IMR.5
RUA1
IMR.4
RCL
IMR.3
TCLE
IMR.2
TOCD
IMR.1
PRBSD
IMR.0
RUA1
RCL
TCLE
DESCRIPTION
Loop Up Code Detected.
0 = interrupt masked
1 = interrupt enabled
Loop Down Code Detected.
0 = interrupt masked
1 = interrupt enabled
Loss of Transmit Clock.
0 = interrupt masked
1 = interrupt enabled
Receive Unframed All Ones.
0 = interrupt masked
1 = interrupt enabled
Receive Carrier Loss.
0 = interrupt masked
1 = interrupt enabled
Transmit Current Limiter Exceeded.
0 = interrupt masked
1 = interrupt enabled
Transmit Open Circuit Detect.
0 = interrupt masked
1 = interrupt enabled
PRBS Detection.
0 = interrupt masked
1 = interrupt enabled
36 of 73
TOCD
(LSB)
PRBSD
DS21348/Q348
RIR1 (08H): RECEIVE INFORMATION REGISTER 1
(MSB)
ZD
16ZD
HBD
RCLC
RUA1C
JALT
n/a
(LSB)
n/a
SYMBOL
POSITION
DESCRIPTION
ZD
(latched)
RIR1.7
16ZD
(latched)
RIR1.6
HBD
(latched)
RIR1.5
RCLC
(latched)
RIR1.4
RUA1C
(latched)
RIR1.3
JALT
(latched)
RIR1.2
N/A
RIR1.1
Zero Detect. Set when a string of at least four (ETS = 0) or
eight (ETS = 1) consecutive zeros (regardless of the length of
the string) have been received. Will be cleared when read.
Sixteen Zero Detect. Set when at least 16 consecutive zeros
(regardless of the length of the string) have been received. Will
be cleared when read.
HDB3/B8ZS Word Detect. Set when an HDB3 (ETS = 0) or
B8ZS (ETS = 1) code word is detected independent of whether
the receive HDB3/B8ZS mode (CCR4.6) is enabled. Will be
cleared when read. Useful for automatically setting the line
coding.
Receive Carrier Loss Clear. Set when the RCL alarm has met
the clear criteria defined in Table 7-1. Will be cleared when
read.
Receive Unframed All Ones Clear. Set when the unframed all
ones signal is no longer detected. Will be cleared when read.
See Table 7-1.
Jitter Attenuator Limit Trip. Set when the jitter attenuator
FIFO reaches to within 4 bits of its useful limit. Will be cleared
when read. Useful for debugging jitter attenuation operation.
Not Assigned. Could be any value when read.
N/A
RIR1.0
Not Assigned. Could be any value when read.
37 of 73
DS21348/Q348
RIR2 (09H): RECEIVE INFORMAION REGISTER 2
(MSB)
RL3
RL2
RL1
RL0
N/A
N/A
ARLB
(LSB)
SEC
SYMBOL
POSITION
DESCRIPTION
RL3
(real time)
RL2
(real time)
RL1
(real time)
RL0
(real time)
N/A
RIR2.7
Receive Level Bit 3. See Table 7-2.
RIR2.6
Receive Level Bit 2. See Table 7-2.
RIR2.5
Receive Level Bit 1. See Table 7-2.
RIR2.4
Receive Level Bit 0. See Table 7-2.
RIR2.3
Not Assigned. Could be any value when read.
N/A
RIR2.2
Not Assigned. Could be any value when read.
ARLB
(real time)
RIR2.1
SEC
(latched)
RIR2.0
Automatic Remote LoopBack Detected. This bit will be set to
a one when the automatic Remote Loopback (RLB) circuitry
has detected the presence of a loop up code for 5 seconds. It
will remain set until the automatic RLB circuitry has detected
the loop down code for 5 seconds. See Section 6 for more
details. This bit will be forced low when the automatic RLB
circuitry is disabled (CCR6.5 = 0).
One-Second Timer. This bit will be set to a one on one-second
boundaries as timed by the device based on the RCLK. It will
be cleared when read.
RECEIVE LEVEL INDICATION Table 7-2
RL3
RL2
RL1
RL0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
38 of 73
Receive Level
(dB)
Greater than -2.5
-2.5 to -5.0
-5.0 to -7.5
-7.5 to -10.0
-10.0 to -12.5
-12.5 to -15.0
-15.0 to -17.5
-20.0 to -22.5
-22.5 to -25.0
-25.0 to -27.5
-27.5 to -30.0
-30.0 to -32.5
-32.5 to -35.0
-35.0 to -37.5
-37.5 to -40.0
-40.0 to -42.5
DS21348/Q348
8. DIAGNOSTICS
8.1
In-Band Loop Code Generation and Detection
The DS21348 has the ability to generate and detect a repeating bit pattern that is from one to eight or
sixteen bits in length. To transmit a pattern, the user will load the pattern to be sent into the Transmit
Code Definition (TCD1 and TCD2) registers and select the proper length of the pattern by setting the
TC0 and TC1 bits in the In-Band Code Control (IBCC) register. When generating a 1, 2, 4, 8, or 16 bit
pattern both the transmit code registers (TCD1 and TCD2) must be filled with the proper code.
Generation of a 1, 3, 5, or 7-bit pattern only requires TCD1 to be filled. Once this is accomplished, the
pattern will be transmitted as long as the TLCE control bit (CCR3.3) is enabled. As an example, if the
user wished to transmit the standard “loop up” code for Channel Service Units which is a repeating
pattern of ...10000100001... then 80h would be loaded into TCD1 and the length would set using TC1 and
TC0 in the IBCC register to 5 bits.
The DS21348 can detect two separate repeating patterns to allow for both a “loop up” code and a “loop
down” code to be detected. The user will program the codes to be detected in the Receive Up Code
Definition (RUPCD1 and RUPCD2) registers and the Receive Down Code Definition (RDNCD1 and
RDNCD2) registers and the length of each pattern will be selected via the IBCC register. The DS21348
will detect repeating pattern codes with bit error rates as high as 1x10-2. The code detector has a nominal
integration period of 48ms, hence, after about 48ms of receiving either code, the proper status bit (LUP at
SR.7 and LDN at SR.6) will be set to a one. Normally codes are sent for a period of 5 seconds. It is
recommended that the software poll the DS21348 every 100ms to 1000ms until 5 seconds has elapsed to
insure that the code is continuously present.
IBCC (0AH): IN-BAND CODE CONTROL REGISTER
(MSB)
TC1
TC0
RUP2
RUP1
RUP0
RDN2
RDN1
(LSB)
RDN0
SYMBOL
POSITION
DESCRIPTION
TC1
IBCC.7
Transmit Code Length Definition Bit 1. See Table 8-1
TC0
IBCC.6
Transmit Code Length Definition Bit 0. See Table 8-1
RUP2
IBCC.5
Receive Up Code Length Definition Bit 2. See Table 8-2
RUP1
IBCC.4
Receive Up Code Length Definition Bit 1. See Table 8-2
RUP0
IBCC.3
Receive Up Code Length Definition Bit 0. See Table 8-2
RDN2
IBCC.2
Receive Down Code Length Definition Bit 2. See Table 8-2
RDN1
IBCC.1
Receive Down Code Length Definition Bit 1. See Table 8-2
RDN0
IBCC.0
Receive Down Code Length Definition Bit 0. See Table 8-2
39 of 73
DS21348/Q348
TRANSMIT CODE LENGTH Table 8-1
TC1
0
0
1
1
TC0
0
1
0
1
LENGTH SELECTED
5 bits
6 bits/3 bits
7 bits
16 bits/8 bits/4 bits/2 bits/1 bits
RECEIVE CODE LENGTH Table 8-2
RUP2/ RDN2
RUP1/ RDN1
RUP0/ RDN0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
LENGTH
SELECTED
1 bits
2 bits
3 bits
4 bits
5 bits
6 bits
7 bits
16 bits/8 bits
TCD1 (0BH): TRANSMIT CODE DEFINITION REGISTER 1
(MSB)
C7
C6
C5
C4
C3
C2
C1
(LSB)
C0
SYMBOL
POSITION
DESCRIPTION
C7
TCD1.7
C6
TCD1.6
Transmit Code Definition Bit 7. First bit of the repeating
pattern.
Transmit Code Definition Bit 6.
C5
TCD1.5
Transmit Code Definition Bit 5.
C4
TCD1.4
Transmit Code Definition Bit 4.
C3
TCD1.3
Transmit Code Definition Bit 3.
C2
TCD1.2
C1
TCD1.1
C0
TCD1.0
Transmit Code Definition Bit 2. A Don’t Care if a 5-bit
length is selected.
Transmit Code Definition Bit 1. A Don’t Care if a 5-bit or 6bit length is selected.
Transmit Code Definition Bit 0. A Don’t Care if a 5-bit, 6bit, or 7-bit length is selected.
40 of 73
DS21348/Q348
TCD2 (0CH): TRANSMIT CODE DEFINITION REGISTER 2
(MSB)
C15
C14
C13
C12
C11
C10
SYMBOL
POSITION
C15
TCD2.7
Transmit Code Definition Bit 15
C14
TCD2.6
Transmit Code Definition Bit 14
C13
TCD2.5
Transmit Code Definition Bit 13
C12
TCD2.4
Transmit Code Definition Bit 12
C11
TCD2.3
Transmit Code Definition Bit 11
C10
TCD2.2
Transmit Code Definition Bit 10
C9
TCD2.1
Transmit Code Definition Bit 9
C8
TCD2.0
Transmit Code Definition Bit 8
C9
(LSB)
C8
DESCRIPTION
RUPCD1 (0DH): RECEIVE UP CODE DEFINITION REGISTER 1
(MSB)
C7
C6
C5
C4
C3
C2
C1
(LSB)
C0
SYMBOL
POSITION
DESCRIPTION
C7
RUPCD1.7
C6
RUPCD1.6
C5
RUPCD1.5
C4
RUPCD1.4
C3
RUPCD1.3
C2
RUPCD1.2
C1
RUPCD1.1
C0
RUPCD1.0
Receive Up Code Definition Bit 7. First bit of the repeating
pattern.
Receive Up Code Definition Bit 6. A Don’t Care if a 1-bit
length is selected.
Receive Up Code Definition Bit 5. A Don’t Care if a 1-bit or
2-bit length is selected.
Receive Up Code Definition Bit 4. A Don’t Care if a 1-bit to
3-bit length is selected.
Receive Up Code Definition Bit 3. A Don’t Care if a 1-bit to
4-bit length is selected.
Receive Up Code Definition Bit 2. A Don’t Care if a 1-bit to
5-bit length is selected.
Receive Up Code Definition Bit 1. A Don’t Care if a 1-bit to
6-bit length is selected.
Receive Up Code Definition Bit 0. A Don’t Care if a 1-bit to
7-bit length is selected.
41 of 73
DS21348/Q348
RUPCD2 (0EH): RECEIVE UP CODE DEFINITION REGISTER 2
(MSB)
C15
C14
C13
C12
C11
C10
SYMBOL
POSITION
DESCRIPTION
C15
RUPCD2.7
Receive Up Code Definition Bit 15
C14
RUPCD2.6
Receive Up Code Definition Bit 14
C13
RUPCD2.5
Receive Up Code Definition Bit 13
C12
RUPCD2.4
Receive Up Code Definition Bit 12
C11
RUPCD2.3
Receive Up Code Definition Bit 11
C10
RUPCD2.2
Receive Up Code Definition Bit 10
C9
RUPCD2.1
Receive Up Code Definition Bit 9
C8
RUPCD2.0
Receive Up Code Definition Bit 8
C9
(LSB)
C8
RDNCD1 (0FH): RECEIVE DOWN CODE DEFINITION REGISTER 1
(MSB)
C7
C6
C5
C4
C3
C2
C1
(LSB)
C0
SYMBOL
POSITION
DESCRIPTION
C7
RDNCD1.7
C6
RDNCD1.6
C5
RDNCD1.5
C4
RDNCD1.4
C3
RDNCD1.3
C2
RDNCD1.2
C1
RDNCD1.1
C0
RDNCD1.0
Receive Down Code Definition Bit 7. First bit of the
repeating pattern.
Receive Down Code Definition Bit 6. A Don’t Care if a 1-bit
length is selected.
Receive Down Code Definition Bit 5. A Don’t Care if a 1-bit
or 2-bit length is selected.
Receive Down Code Definition Bit 4. A Don’t Care if a 1-bit
to 3-bit length is selected.
Receive Down Code Definition Bit 3. A Don’t Care if a 1-bit
to 4-bit length is selected.
Receive Down Code Definition Bit 2. A Don’t Care if a 1-bit
to 5-bit length is selected.
Receive Down Code Definition Bit 1. A Don’t Care if a 1-bit
to 6-bit length is selected.
Receive Down Code Definition Bit 0. A Don’t Care if a 1-bit
to 7-bit length is selected.
42 of 73
DS21348/Q348
RDNCD2 (10H): RECEIVE DOWN CODE DEFINITION REGISTER 2
(MSB)
C15
C14
C13
C12
C11
C10
SYMBOL
POSITION
DESCRIPTION
C15
RDNCD2.7
Receive Down Code Definition Bit 15
C14
RDNCD2.6
Receive Down Code Definition Bit 14
C13
RDNCD2.5
Receive Down Code Definition Bit 13
C12
RDNCD2.4
Receive Down Code Definition Bit 12
C11
RDNCD2.3
Receive Down Code Definition Bit 11
C10
RDNCD2.2
Receive Down Code Definition Bit 10
C9
RDNCD2.1
Receive Down Code Definition Bit 9
C8
RDNCD2.0
Receive Down Code Definition Bit 8
8.2
C9
(LSB)
C8
Loopbacks
8.2.1 Remote Loopback (RLB)
When RLB (CCR6.6) is enabled, the DS21348 is placed into remote loopback. In this loopback, data
from the clock/data recovery state machine will be looped back to the transmit path passing through the
jitter attenuator if it is enabled. The data at the RPOS and RNEG pins will be valid while data presented
at TPOS and TNEG will be ignored. See for details.
If the Automatic Remote Loop Back Enable (CCR6.5) is set to a one, the DS21348 will automatically go
into remote loop back when it detects the loop up code programmed in the Receive Up Code Definition
Registers (RUPCD1 and RUPCD2) for a minimum of 5 seconds. When the DS21348 detects the loop
down code programmed in the Receive Loop Down Code Definition registers (RDNCD1 and RDNCD2)
for a minimum of 5 seconds, the DS21348 will come out of remote loop back. The ARLB can also be
disabled by setting ARLBE to a zero.
8.2.2 Local Loopback (LLB)
When LLB (CCR6.7) is set to a one, the DS21348 is placed into Local Loopback. In this loopback, data
on the transmit-side will continue to be transmitted as normal. TCLK and TPOS/TNEG will pass through
the jitter attenuator (if enabled) and be output at RCLK and RPOS/RNEG. Incoming data from the line at
RTIP and RRING will be ignored. If Transmit Unframed All Ones (CCR3.7) is set to a one while in LLB,
TTIP and TRING will transmit all ones while TCLK and TPOS/TNEG will be looped back to RCLK and
RPOS/RNEG. See for more details.
43 of 73
DS21348/Q348
8.2.3 Analog Loopback (LLB)
Setting ALB (CCR6.4) to a one puts the DS21348 in Analog Loopback. Signals at TTIP and TRING will
be internally connected to RTIP and RRING. The incoming signals at RTIP and RRING will be ignored.
The signals at TTIP and TRING will be transmitted as normal. See for more details.
8.2.4 Dual Loopback (DLB)
Setting both CCR6.7 and CCR6.6 to a one, LLB and RLB respectively, puts the DS21348 into Dual
Loopback operation. The TCLK and TPOS/TNEG signals will be looped back through the jitter
attenuator (if enabled) and output at RCLK and RPOS/RNEG. Clock and data recovered from RTIP and
RRING will be looped back to the transmit-side and output at TTIP and TRING. This mode of operation
is not available when implementing hardware operation. See for more details.
8.3
PRBS Generation and Detection
8.4
Error Counter
Setting TPRBSE (CCR3.4) = 1 enables the DS21348 to transmit a 215 - 1 (E1) or a 220 - 1 (T1) Pseudo
Random Bit Sequence (PRBS) depending on the ETS bit setting in CCR1.7. The receive-side of the
DS21348 will always search for these PRBS patterns independent of CCR3.4. The PRBS Bit Error
Output (PBEO) will remain high until the receiver has synchronized to one of the two patterns (64 bits
received without an error) at which time PBEO will go low and the PRBSD bit in the Status Register
(SR) will be set. Once synchronized, any bit errors received will cause a positive going pulse at PBEO,
synchronous with RCLK. This output can be used with external circuitry to keep track of bit error rates
during the PRBS testing. Setting CCR6.0 (ECRS) = 1 will allow the PRBS errors to be accumulated in
the 16-bit counter in registers ECR1 and ECR2. The PRBS synchronizer will remain in sync until it
experiences 6 bit errors or more within a 64 bit span. Both PRBS patterns comply with the ITU-T O.151
specifications.
Error Count Register 1 (ECR1) is the most significant word and ECR2 is the least significant word of a
user selectable 16-bit counter that records incoming errors including BiPolar Violations (BPV), Code
Violations (CV), Excessive Zero violations (EXZ) and/or PRBS Errors. See Table 8-3 and Table 8-4 and
Figure 3-2 for details.
DEFINITION OF RECEIVED ERRORS Table 8-3
ERROR
BPV
CV
EXZ
EXZ
PRBS
E1 OR T1
DEFINITION OF RECEIVED ERRORS
E1/T1
Two consecutive marks with the same polarity. Will ignore BPVs due to
HDB3 and B8ZS zero suppression when CCR2.3 = 0. Typically used with
AMI coding (CCR2.3 = 1). ITU-T O.161.
E1
When HDB3 is enabled (CCR2.3 = 0) and the receiver detects two
consecutive BPVs with the same polarity. ITU-T O.161.
E1
When four or more consecutive zeros are detected.
T1
When receiving AMI coded signals (CCR2.3 = 1), detection of 16 or more
zeros or a BPV. ANSI T1.403 1999.
When receiving B8ZS coded signals (CCR2.3 = 0), detection of 8 or more
zeros or a BPV. ANSI T1.403 1999.
E1/T1
A bit error in a received PRBS pattern. See section 8.3 for details.
ITU-T O.151.
44 of 73
DS21348/Q348
FUNCTION OF ECRS BITS AND RNEG PIN Table 8-4
E1 or T1
(CCR1.7)
0
0
0
0
1
1
1
1
X
ECRS2
(CCR6.2)
0
0
0
0
0
0
0
0
1
ECRS1
(CCR6.1)
0
0
1
1
X
X
X
X
X
ECRS0
(CCR6.0)
0
1
0
1
0
1
0
1
X
RHBE
(CCR2.3)
X
X
X
X
0
0
1
1
X
FUNCTION OF ECR
COUNTERS/RNEG1
CVs
BPVs (HDB3 code words not counted)
CVs + EXZs
BPVs + EXZs
BPVs (B8ZS code words not counted)
BPVs + 8 EXZs
BPVs
BPVs + 16 EXZs
PRBS Errors2
NOTES:
1. RNEG outputs error data only when in NRZ mode (CCR1.6 = 1)
2. PRBS errors will always be output at PBEO independent of ECR control bits and NRZ mode and will
not be present at RNEG.
8.4.1 Error Counter Update
A transition of the ECUE (CCR1.4) control bit from 0 to 1 will update the ECR registers with the current
values and reset the counters. ECUE must be set back to zero and another 0 to 1 transition must occur for
subsequent reads/resets of the ECR registers. Note that the DS21348 can report errors at RNEG when in
NRZ mode (CCR1.6 = 1) by outputting a pulse for each error occurrence. The counter saturates at 65,535
and will not rollover.
ECR1 (11H): UPPER ERROR COUNT REGISTER 1
ECR2 (12H): LOWER ERROR COUNT REGISTER 2
(MSB)
E15
E7
E14
E6
E13
E5
E12
E4
E11
E3
E10
E2
SYMBOL
POSITION
E15
ECR1.7
MSB of the 16-bit error count
E0
ECR2.0
LSB of the 16-bit error count
8.5
E9
E1
(LSB)
E8
E0
ECR1
ECR2
DESCRIPTION
Error Insertion
When IBPV (CCR3.1) is transitioned from a zero to a one, the device waits for the next occurrence of
three consecutive ones to insert a BPV. IBPV must be cleared and set again for another BPV error
insertion. See for details on the insertion of the BPV into the datastream.
When IBE (CCR3.0) is transitioned from a zero to a one, the device will insert a logic error. IBE must be
cleared and set again for another logic error insertion. See for details on the insertion of the logic error
into the datasteam.
45 of 73
DS21348/Q348
9. ANALOG INTERFACE
9.1
Receiver
The DS21348 contains a digital clock recovery system. The DS21348 couples to the receive E1 or T1
twisted pair (or coaxial cable in 75Ω E1 applications) via a 1:1 transformer. See Table 9-3 for transformer
details. Figure 9-1, Figure 9-2, and Figure 9-3 along with Table 9-1 and Table 9-2 show the receive
termination requirements. The DS21348 has the option of using internal termination resistors.
The DS21348 is designed to be fully software-selectable for E1 and T1 without the need to change any
external resistors for the receive-side. The receive-side will allow the user to configure the DS21348 for
75Ω, 100Ω, or 120Ω receive termination by setting the RT1 (CCR5.1) and RT0 (CCR5.0) bits. When
using the internal termination feature, the Rr resistors should be 60Ω each. See Figure 9-1 for details. If
external termination is required, RT1 and RT0 should be set to 0 and both Rr resistors in Figure 9-1 will
need to be 37.5Ω, 50Ω, or 60Ω each depending on the line impedance.
The resultant E1 or T1 clock derived from the 2.048/1.544 PLL (JACLK in ) is internally multiplied by
16 via another internal PLL and fed to the clock recovery system. The clock recovery system uses the
clock from the PLL circuit to form a 16 times oversampler which is used to recover the clock and data.
This oversampling technique offers outstanding performance to meet jitter tolerance specifications shown
in Figure 9-.
Normally, the clock that is output at the RCLK pin is the recovered clock from the E1 AMI/HDB3 or T1
AMI/B8ZS waveform presented at the RTIP and RRING inputs. When no signal is present at RTIP and
RRING, a Receive Carrier Loss (RCL) condition will occur and the RCLK will be derived from the
JACLK source. See . If the jitter attenuator is placed in the receive path (as is the case in most
applications), the jitter attenuator restores the RCLK to an approximate 50% duty cycle. If the jitter
attenuator is either placed in the transmit path or is disabled, the RCLK output can exhibit slightly shorter
high cycles of the clock. This is due to the highly oversampled digital clock recovery circuitry. See the
Receive AC Timing Characteristics in Section 12 for more details.
The receive-side circuitry also contains a clock synthesizer which outputs a user configurable clock (up to
16.384MHz) synthesized to RCLK at BPCLK (pin 31). See Table 6-3 for details on output clock
frequencies at BPCLK. In hardware mode, BPCLK defaults to a 16.384MHz output.
The DS21348 has a bypass mode for the receive side clock and data. This allows the BPCLK to be
derived from RCLK after the jitter attenuator while the clock and data presented at RCLK, RPOS, and
RNEG go unaltered. This is intended for applications where the receive side jitter attenuation will be
done after the LIU. Setting RJAB (CCR6.3) to a logic 1 will enable the bypass. Be sure that the jitter
attenuator is in the receive path (CCR4.3 = 0). See for details.
The DS21348 will report the signal strength at RTIP and RRING in 2.5dB increments via RL3-RL0
located in the Receive Information Register 2. This feature is helpful when trouble shooting line
performance problems. See Table 7-2 for details.
Monitor applications in both E1 and T1 require various flat gain settings for the receive-side circuitry.
The DS21348 can be programmed to support these applications via the Monitor Mode control bits MM1
and MM0. When the monitor modes are enabled, the receiver will tolerate normal line loss up to -6dB.
See Table 6-4 for details.
46 of 73
DS21348/Q348
9.2
Transmitter
The DS21348 uses a set of laser-trimmed delay lines along with a precision Digital-to-Analog Converter
(DAC) to create the waveforms that are transmitted onto the E1 or T1 line. The waveforms created by the
DS21348 meet the latest ETSI, ITU, ANSI, and AT&T specifications. The user will select which
waveform is to be generated by setting the ETS bit (CCR1.7) for E1 or T1 operation, then programming
the L2/L1/L0 bits in Common Control Register 4 for the appropriate application. See Table 9-1 and Table
9-2 for the proper L2/L1/L0 settings.
A 2.048MHz or 1.544MHz TTL clock is required at TCLK for transmitting data at TPOS and TNEG.
ITU specification G.703 requires an accuracy of ±50ppm for both T1 and E1. TR62411 and ANSI specs
require an accuracy of ±32ppm for T1 interfaces. The clock can be sourced internally by RCLK or
JACLK. See CCR1.2, CCR1.1, CCR1.0, and for details. Due to the nature of the design of the
transmitter in the DS21348, very little jitter (less than 0.005 UIpp broadband from 10Hz to 100kHz) is
added to the jitter present on TCLK. Also, the waveforms created are independent of the duty cycle of
TCLK. The transmitter in the DS21348 couples to the E1 or T1 transmit twisted pair (or coaxial cable in
some E1 applications) via a 1:2 step-up transformer. In order for the device to create the proper
waveforms, the transformer used must meet the specifications listed in Table 9-3.
The DS21348 has automatic short-circuit limiter which limits the source current to 50mA (rms) into a 1Ω
load. This feature can be disabled by setting the SCLD bit (CCR2.5) = 1. When the current limiter is
activated, TCLE (SR.2) will be set even if short circuit limiter is disabled. The TPD bit (CCR4.0) will
power-down the transmit line driver and 3-state the TTIP and TRING pins. The DS21348 can also detect
when the TTIP or TRING outputs are open circuited. When an open circuit is detected, TOCD (SR.1)
will be set.
9.3
Jitter Attenuator
The DS21348 contains an onboard jitter attenuator that can be set to a depth of either 32 or 128 bits via
the JABDS bit (CCR4.2). The 128-bit mode is used in applications where large excursions of wander are
expected. The 32-bit mode is used in delay sensitive applications. The characteristics of the attenuation
are shown in . The jitter attenuator can be placed in either the receive path or the transmit path by
appropriately setting or clearing the JAS bit (CCR4.3). Also, the jitter attenuator can be disabled (in
effect, removed) by setting the DJA bit (CCR4.1). In order for the jitter attenuator to operate properly, a
2.048MHz or 1.544MHz clock must be applied at MCLK. ITU specification G.703 requires an accuracy
of ±50ppm for both T1 and E1. TR62411 and ANSI specs require an accuracy of ±32ppm for T1
interfaces. There is an onboard PLL for the jitter attenuator, which will convert the 2.048MHz clock to a
1.544 MHz rate for T1 applications. Setting JAMUX (CCR1.3) to a logic 0 bypasses this PLL. Onboard
circuitry adjusts either the recovered clock from the clock/data recovery block or the clock applied at the
TCLK pin to create a smooth jitter free clock which is used to clock data out of the jitter attenuator FIFO.
It is acceptable to provide a gapped/bursty clock at the TCLK pin if the jitter attenuator is placed on the
transmit side. If the incoming jitter exceeds either 120 UIpp (buffer depth is 128 bits) or 28 UIpp (buffer
depth is 32 bits), then the DS21348 will divide the internal nominal 32.768MHz (E1) or 24.704MHz (T1)
clock by either 15 or 17 instead of the normal 16 to keep the buffer from overflowing. When the device
divides by either 15 or 17, it also sets the Jitter Attenuator Limit Trip (JALT) bit in the Receive
Information Register 1 (RIR1).
47 of 73
DS21348/Q348
9.4
G.703 Synchronization Signal
The DS21348 is capable of receiving a 2.048MHz square-wave synchronization clock as specified in
section 10 of ITU G.703. In order to use the DS21348 in this mode, set the Receive Synchronization
Clock Enable (CCR5.3) = 1. The DS21348 can also transmit the 2.048MHz square-wave synchronization
clock as specified in section 10 of G.703. In order to transmit the 2.048 MHz clock, set the Transmit
Synchronization Clock Enable (CCR5.2) = 1.
LINE BUILD OUT SELECT FOR E1 IN REGISTER CCR4 (ETS = 0) Table 9-1
L2
0
0
1
1
L1
0
0
0
0
L0
0
1
0
1
VDD
3.3V
3.3V
3.3V
3.3V
APPLICATION
75W normal
120W normal
75W w/ high return loss
120W w/ high return loss
N
1:2
1:2
1:2
1:2
RETURN LOSS
NM
NM
21dB
21dB
Rt
0W
0W
6.2W
11.6W
Note: See Figure 9-1, Figure 9-2, and Figure 9-3.
LINE BUILD OUT SELECT FOR T1 IN REGISTER CCR4 (ETS = 1) Table 9-2
L2
0
L1
0
L0
0
VDD
3.3V
0
0
0
1
1
1
1
0
1
1
0
0
1
1
1
0
1
0
1
0
1
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
APPLICATION
DSX-1 (0 to 133 feet) /
0 DB CSU
DSX-1 (133 to 266 feet)
DSX-1 (266 to 399 feet)
DSX-1 (399 to 533 feet)
DSX-1 (533 to 655 feet)
-7.5dB CSU
-15dB CSU
-22.5dB CSU
N
1:2
RETURN LOSS
NM
Rt
0W
1:2
1:2
1:2
1:2
1:2
1:2
1:2
NM
NM
NM
NM
NM
NM
NM
0W
0W
0W
0W
0W
0W
0W
Note: See Figure 9-1, Figure 9-2, and Figure 9-3.
TRANSFORMER SPECIFICATIONS FOR 3.3V OPERATION Table 9-3
SPECIFICATION
Turns Ratio 3.3V Applications
Primary Inductance
Leakage Inductance
Intertwining Capacitance
Transmit Transformer DC Resistance
Primary (Device Side)
Secondary
Receive Transformer DC Resistance
Primary (Device Side)
Secondary
RECOMMENDED VALUE
1:1 (receive) and 1:2 (transmit) ±2%
600mH minimum
1.0mH maximum
40pF maximum
1.0W maximum
2.0W maximum
1.2W maximum
1.2W maximum
48 of 73
DS21348/Q348
BASIC INTERFACE Figure 9-1
DS21348
Rt
Transmit
Line
TTIP
1.0µF
(nonpolarized)
Rt
VDD (21)
VSS (22)
TRING
N:1
(larger winding
toward the network)
VDD (36)
VSS (35)
RTIP
Receive
Line
RRING
MCLK
+VDD
0.1µF
0.01µF
10µF
0.1µF
10µF
2.048MHz
(this clock can also
be 1.544MHz for T1
only applications)
1:1
Rr
Rr
0.1µF
NOTES:
1) All resistor values are ±1%.
2) In E1 applications, the Rt resistors are used to increase the transmitter return loss (Table 9-1). No
return loss is required for T1 applications.
3) The Rr resistors should be set to 60W each if the internal receive-side termination feature is enabled.
When this feature is disabled, Rr = 37.5W for 75W or 60W for 120W E1 systems, or 50W for 100W
T1 lines.
4) See Table 9-1 and Table 9-2 for the appropriate transmit transformer turns ratio (N).
49 of 73
DS21348/Q348
Figure 9-2 PROTECTED INTERFACE USING INTERNAL RECEIVE
TERMINATION
+VDD
D1
(optional)
Rp
Fuse
Rt
Transmit
Line
Fuse
TTIP
1.0µF
(nonpolarized)
S
C1
TRING
Rt
Rp
D3
N:1
(larger winding
toward the network)
DS21348
D2
D4
VDD (21)
VSS (22)
VDD (36)
VSS (35)
+VDD
0.1µF
0.01µF
10µF
68µF
0.1µF
10µF
+VDD
D6
D5
Fuse
Rp
RTIP
Receive
Line
S
Fuse
Rp
(optional)
C2
RRING
MCLK
2.048MHz
(this clock can also
be 1.544MHz for T1
only applications)
1:1
60
60 D7
D8
0.1µF
NOTES:
1.
2.
3.
4.
5.
6.
All resistor values are ±1%.
C1 = C2 = 0.1µF.
S is a 6V transient suppresser.
D1 to D8 are Schottky diodes.
The fuses are optional to prevent AC power line crosses from compromising the transformers.
Rp resistors exist to keep the Fuses from opening during a surge. If they are used, then the 60W
receive termination resistance must be adjusted to match the line impedance.
7. The Rt resistors are used to increase the transmitter return loss (Table 9-1). No return loss is required
for T1 applications.
8. The transmit transformer turns ratio (N) would be 1:2 for 3.3V operation.
9. The 68mF is used to keep the local power plane potential within tolerance during a surge.
50 of 73
DS21348/Q348
PROTECTED INTERFACE USING EXTERNAL RECEIVE TERMINATION
Figure 9-3
+VDD
D1
(optional)
Rp
Fuse
Rt
Transmit
Line
Fuse
Fuse
TTIP
1.0µF
(nonpolarized)
S
D3
N:1
(larger winding
toward the network)
Rp
470
Receive
Line
Fuse
Rp
(optional)
C1
TRING
Rt
Rp
470
1:1
Rr
DS21348
D2
D4
RTIP
RRING
VDD (21)
VSS (22)
VDD (36)
VSS (35)
MCLK
+VDD
0.1µF
0.01µF
10µF
68µF
0.1µF
10µF
2.048MHz
(this clock can also
be 1.544MHz for T1
only applications)
Rr
0.1µF
NOTES:
1.
2.
3.
4.
5.
6.
All resistor values are ±1%.
C1 = 0.1µF.
S is a 6V transient suppresser.
D1 to D4 are Schottky diodes.
The fuses are optional to prevent AC power line crosses from compromising the transformers.
Rp resistors exist to keep the Fuses from opening during a surge. If they are used, then Rr must be
adjusted to match the line impedance.
7. Rr = 37.5W for 75W or 60W for 120W E1 systems, or 50W for 100W T1 lines.
8. The Rt resistors are used to increase the transmitter return loss (Table 9-1). No return loss is required
for T1 applications.
9. The transmit transformer turns ratio (N) would be 1:2 for 3.3V operation.
10. The 68mF is used to keep the local power plane potential within tolerance during a surge.
51 of 73
DS21348/Q348
E1 TRANSMIT PULSE TEMPLATE Figure 9-4
1.2
1.1
269ns
SCALED AMPLITUDE
(in 75 ohm systems, 1.0 on the scale = 2.37Vpeak
in 120 ohm systems, 1.0 on the scale = 3.00Vpeak)
1.0
0.9
0.8
0.7
G.703
Template
194ns
0.6
0.5
219ns
0.4
0.3
0.2
0.1
0
-0.1
-0.2
-250
-200
-150
-100
-50
0
50
TIME (ns)
52 of 73
100
150
200
250
DS21348/Q348
T1 TRANSMIT PULSE TEMPLATE Figure 9-5
1.2
1.0
-0.77
-0.39
-0.27
-0.27
-0.12
0.00
0.27
0.35
0.93
1.16
0.9
0.8
0.7
NORMALIZED AMPLITUDE
MINIMUM CURVE
UI
Time Amp.
MAXIMUM CURVE
UI
Time Amp.
1.1
0.6
-500
-255
-175
-175
-75
0
175
225
600
750
0.05
0.05
0.80
1.15
1.15
1.05
1.05
-0.07
0.05
0.05
0.5
-0.77
-0.23
-0.23
-0.15
0.00
0.15
0.23
0.23
0.46
0.66
0.93
1.16
-500
-150
-150
-100
0
100
150
150
300
430
600
750
-0.05
-0.05
0.50
0.95
0.95
0.90
0.50
-0.45
-0.45
-0.20
-0.05
-0.05
0.4
0.3
0.2
0.1
0
-0.1
-0.2
-0.3
T1.102/87, T1.403,
CB 119 (Oct. 79), &
I.431 Template
-0.4
-0.5
-500 -400 -300
-200 -100
0
100
200
300
400
TIME (ns)
53 of 73
500
600
700
DS21348/Q348
JITTER TOLERANCE Figure 9-6
UNIT INTERVALS (UIpp)
1K
100
DS21348
TR 62411 (Dec. 90)
Tolerance
10
ITU-T G.823
1
0.1
1
10
100
1K
FREQUENCY (Hz)
10K
100K
JITTER ATTENUATION Figure 9-7
ITU G.7XX
Prohibited Area
TBR12
Prohibited
Area
-20dB
ur
C
ve
A
E1
T1
-40dB
TR 62411 (Dec. 90)
Prohibited Area
Cu
B
rve
JITTER ATTENUATION (dB)
0dB
-60dB
1
10
100
1K
FREQUENCY (Hz)
10K
54 of 73
100K
DS21348/Q348
10.
DS21Q348 QUAD LIU
The DS21Q348 is a quad version of the DS21348G utilizing CABGA on carrier packaging technology.
The four LIUs are controlled via the parallel port mode. Serial and hardware modes are unavailable in
this package.
DS21Q348 PIN ASSIGNMENT Table 10-1
DS21Q348
PIN#
J1
K3
I/O
I
I
PARALLEL
PORT MODE
Connect to VSS
Connect to VSS
J2
H1
K2
K1
L1
H11
H12
G12
J10
H10
G11
J9
E3
D4
F3
D5
G4
K9
K7
L9
J6
L7
M8
M12
I
I
I
I/O
I
I
I
I
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
I/O
I
I
I
I
I
I
RD*(DS*)
WR*(R/W*)
ALE(AS)
A4
A3
A2
A1
A0
D7/AD7
D6/AD6
D5/AD5
D4/AD4
D3/AD3
D2/AD2
D1/AD1
D0/AD0
VSM
INT*
TEST
HRST*
MCLK
BIS0
BIS1
PBTS
J3
D3
D10
K10
K5
G3
E10
K8
L6
D7
F9
I
I
I
I
O
O
O
O
O
O
O
CS*1
CS*2
CS*3
CS*4
PBEO1
PBEO2
PBEO3
PBEO4
RCL/LOTC1
RCL/LOTC2
RCL/LOTC3
55 of 73
DS21348/Q348
DS21Q348
PIN#
J7
A1
A4
A7
A10
B2
B5
B8
B11
H4
D6
F10
L8
A2
A5
A8
A11
B3
B6
B9
B12
K4
E1
D11
K11
G2
E2
F11
M10
H3
F1
E11
L11
G1
F2
E12
M11
H2
M1
D12
K12
M2
L2
F12
L12
I/O
O
I
I
I
I
I
I
I
I
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
I
I
I
I
I
I
I
I
I
I
I
I
PARALLEL
PORT MODE
RCL/LOTC4
RTIP1
RTIP2
RTIP3
RTIP4
RRING1
RRING2
RRING3
RRING4
BPCLK1
BPCLK2
BPCLK3
BPCLK4
TTIP1
TTIP2
TTIP3
TTIP4
TRING1
TRING2
TRING3
TRING4
RPOS1
RPOS2
RPOS3
RPOS4
RNEG1
RNEG2
RNEG3
RNEG4
RCLK1
RCLK2
RCLK3
RCLK4
TPOS1
TPOS2
TPOS3
TPOS4
TNEG1
TNEG2
TNEG3
TNEG4
TCLK1
TCLK2
TCLK3
TCLK4
56 of 73
DS21348/Q348
DS21Q348
PIN#
J5
D2
G9
M9
L5
E4
D8
J8
J4
D1
E9
L10
M4
F4
D9
H9
I/O
-
PARALLEL
PORT MODE
VDD1
VDD2
VDD3
VDD4
VDD1
VDD2
VDD3
VDD4
VSS1
VSS2
VSS3
VSS4
VSS1
VSS2
VSS3
VSS4
57 of 73
DS21348/Q348
BGA 12 x 12 PIN LAYOUT Figure 10-1
1
2
3
4
5
6
7
8
9
10
11
12
A
RTIP
1
TTIP
1
NC
RTIP
2
TTIP
2
NC
RTIP
3
TTIP
3
NC
RTIP
4
TTIP
4
NC
B
NC
C
NC
NC
NC
NC
NC
D
VSS
2
VDD
2
CS*
2
D2/
AD2
D0/
AD0
E
RPOS
2
RNEG
2
D3/
AD3
VDD
2
NC
NC
F
RCLK
2
TPOS
2
D1/
AD1
VSS
2
NC
G
TPOS
1
RNEG
1
PEBO
2
VSM
H
WR*
(R/W*)
TNEG
1
RCLK BPCLK
1
1
J
See
Note 2
RD*
(DS*)
K
A4
ALE
(AS)
L
A3
TCLK
2
NC
M
TNEG
2
TCLK
1
NC
RRING TRING
1
1
CS*
1
NC
RRING TRING
2
2
NC
RRING TRING
4
4
NC
NC
NC
NC
VDD
3
VSS
3
CS*
3
RPOS
3
TNEG
3
NC
NC
VSS
3
PEBO
3
RCLK
3
TPOS
3
NC
NC
NC
RCL/ BPCLK RNEG
LOTC3
3
3
TCLK
3
NC
NC
NC
NC
VDD
3
NC
D5/
AD5
A0
NC
NC
NC
NC
VSS
4
D6/
AD6
A2
A1
VDD
1
MCLK
RCL/
LOTC4
VDD
4
D4/
AD4
D7/
AD7
NC
NC
PEBO
1
NC
TEST
PEBO
4
INT*
CS*
4
RPOS
4
TNEG
4
NC
VDD
1
RCL/
LOTC1
BIS0
BPCLK HRST*
4
VSS
4
RCLK
4
TCLK
4
VSS
1
NC
NC
NC
RNEG
4
TPOS
4
PBTS
See
RPOS
Note 2
1
NC
RRING TRING
3
3
NC
VSS
1
NC
NC
BPCLK RCL/
2
LOTC2
NOTES:
1) Shaded areas are signals common to all four devices
2) Connect to VSS.
58 of 73
BIS1
VDD
4
DS21348/Q348
11.
DC CHARACTERISTICS
ABSOLUTE MAXIMUM RATINGS*
Voltage Range on Any Pin Relative to Ground
Operating Temperature Range for DS21348TN
Storage Temperature Range
-1.0V to +6.0V
-40°C to +85°C
See J-STD-020A specification
* This is a stress rating only and functional operation of the device at these or any other conditions
beyond those indicated in the operation sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods of time can affect reliability.
RECOMMENDED DC OPERATING CONDITIONS
PARAMETER
Logic 1
Logic 0
Supply for 3.3V Operation
SYMBOL
VIH
VIL
VDD
MIN
2.0
–0.3
3.135
TYP
3.3
(-40°C to +85°C)
MAX
5.5
+0.8
3.465
CAPACITANCE
PARAMETER
Input Capacitance
Output Capacitance
SYMBOL
CIN
COUT
MIN
TYP
5
7
SYMBOL
IIL
ILO
IOH
IOL
IDD
MIN
-1.0
–1.0
+4.0
-
MAX
UNITS
pF
pF
1
NOTES
(-40°C to +85°C; VDD = 3.3V ± 5%)
TYP
MAX
+1.0
1.0
66
100
UNITS
mA
mA
mA
mA
mA
NOTES:
1.
2.
3.
4.
5.
NOTES
(TA = +25°C)
DC CHARACTERISTICS
PARAMETER
Input Leakage
Output Leakage
Output Current (2.4V)
Output Current (0.4V)
Supply Current
UNITS
V
V
V
Applies to VDD.
TCLK = MCLK = 2.048MHz.
0.0V < VIN < VDD.
Applied to INT* when 3-stated.
Power dissipation with TTIP and TRING driving a 30W load, for an all one’s data density.
59 of 73
NOTES
3
4
2, 5
DS21348/Q348
THERMAL CHARACTERISTICS OF DS21Q48 BGA PACKAGE
PARAMETER
Ambient Temperature
Junction Temperature
Theta-JA (θJA) in Still Air
Theta-JC (θJC) in Still Air
MIN
-40ºC
-
TYP
+24ºC/W
+4.1ºC/W
MAX
+85ºC
+125ºC
-
NOTES
1
2
3
NOTES:
1) The package is mounted on a four-layer JEDEC-standard test board.
2) Theta-JA (θJA) is the junction to ambient thermal resistance, when the package is mounted on a fourlayer JEDEC-standard test board.
3) While Theta-JC (θJC) is commonly used as the thermal parameter that provides a correlation between the
junction temperature (Tj) and the average temperature on top center of four of the chip-scale BGA
packages (TC), the proper term is Psi-JT. It is defined by:
(TJ - TC) / overall package power
The method of measurement of the thermal parameters is defined in EIA/JEDEC-standard document
EIA-JESD51-2.
THETA-JA (θJA) VERSUS AIRFLOW
FORCED AIR (m/s)
0
1
2.5
THETA-JA (θJA)
24ºC/W
21ºC/W
19ºC/W
60 of 73
DS21348/Q348
12.
AC CHARACTERISTICS
AC CHARACTERISTICS—MULTIPLEXED PARALLEL PORT
(BIS1 = 0, BIS0 = 0)
(-40°C to +85°C; VDD = 3.3V ± 5%;
-40°C to +85°C; VDD = 5.0V ± 5%)
PARAMETER
SYMBOL
Cycle Time
tCYC
Pulse Width, DS Low or
PWEL
RD* High
Pulse Width, DS High
PWEH
or RD* Low
Input Rise/Fall Times
tR , tF
R/W* Hold Time
tRWH
R/W* Setup Time
tRWS
Before DS High
CS* Setup Time Before
tCS
DS, WR* or RD*
Active
CS* Hold Time
tCH
Read Data Hold Time
tDHR
Write Data Hold Time
tDHW
Muxed Address Valid to
tASL
AS or ALE Fall
Muxed Address Hold
tAHL
Time
Delay Time DS, WR*
tASD
or RD* to AS or ALE
Rise
Pulse Width AS or ALE
PWASH
High
Delay Time, AS or ALE
tASED
to DS, WR* or RD*
Output Data Delay
tDDR
Time from DS or RD*
Data Setup Time
tDSW
See Figure 12-1, Figure 12-2, Figure 12-3
MIN
200
100
TYP
MAX
100
UNITS
ns
ns
ns
20
10
50
ns
ns
ns
20
ns
0
10
0
15
50
ns
ns
ns
ns
10
ns
20
ns
30
ns
10
ns
20
80
50
ns
ns
61 of 73
NOTES
DS21348/Q348
INTEL BUS READ TIMING (PBTS = 0, BIS1 = 0, BIS0 = 0) Figure 12-1
t CYC
ALE
WR*
PWASH
t ASD
t ASD
t ASED
RD*
PWEL
PWEH
t CH
t CS
CS*
t ASL
t DHR
t DDR
AD0-AD7
t AHL
INTEL BUS WRITE TIMING (PBTS = 0, BIS1 = 0, BIS0 = 0) Figure 12-2
t CYC
ALE
RD*
PWASH
t ASD
t ASED
t ASD
WR*
PWEL
PWEH
t CH
t CS
CS*
t ASL
t DHW
AD0-AD7
t AHL
t DSW
62 of 73
DS21348/Q348
MOTOROLA BUS TIMING (PBTS = 1, BIS1 = 0, BIS0 = 0) Figure 12-3
PWASH
AS
DS
PWEH
t ASED
t ASD
PWEL
t CYC
t RWS
t RWH
R/W*
AD0-AD7
(read)
t DDR
t ASL
t AHL
t DHR
t CH
t CS
CS*
AD0-AD7
(write)
t DSW
t ASL
t DHW
t AHL
63 of 73
DS21348/Q348
AC CHARACTERISTICS—NONMULTIPLEXED PARALLEL PORT
(BIS1 = 0, BIS0 = 1)
(-40°C to +85°C; VDD = 3.3V ± 5%)
PARAMETER
SYMBOL
MIN
TYP
Setup Time for A0 to
t1
0
A4, Valid to CS* Active
Setup Time for CS*
t2
0
Active to Either RD*,
WR*, or DS* Active
Delay Time from Either
t3
RD* or DS* Active to
Data Valid
Hold Time from Either
t4
0
RD*, WR*, or DS*
Inactive to CS* Inactive
Hold Time from CS*
t5
5
Inactive to Data Bus
3-State
Wait Time from Either
t6
75
WR* or DS* Active to
Latch Data
Data Setup Time to
t7
10
Either WR* or DS*
Inactive
Data Hold Time from
t8
10
Either WR* or DS*
Inactive
Address Hold from
t9
10
Either WR* or DS*
Inactive
See Figure 12-4, Figure 12-5, Figure 12-6, and Figure 12-7
64 of 73
MAX
UNITS
ns
ns
75
ns
ns
20
ns
ns
ns
ns
ns
NOTES
DS21348/Q348
INTEL BUS READ TIMING (PBTS = 0, BIS1 = 0, BIS0 = 1) Figure12-4
A0 to A4
Address Valid
D0 to D7
Data Valid
5ns min. / 20ns max.
t5
WR*
t1
0ns min.
CS*
0ns min.
t2
RD*
t3
75ns max.
t4
0ns min.
INTEL BUS WRITE TIMING (PBTS = 0, BIS1 = 0, BIS0 = 1) Figure 12-5
A0 to A4
Address Valid
D0 to D7
t7
10ns
min.
RD*
t1
t8
10ns
min.
0ns min.
CS*
0ns min.
WR*
t2
t6
75ns min.
65 of 73
t4
0ns min.
DS21348/Q348
MOTOROLA BUS READ TIMING (PBTS = 1, BIS1 = 0, BIS0 = 1) Figure 12-6
A0 to A4
Address Valid
D0 to D7
Data Valid
5ns min. / 20ns max.
t5
R/W*
t1
0ns min.
CS*
0ns min.
t2
t3
t4
0ns min.
75ns max.
DS*
MOTOROLA BUS WRITE TIMING (PBTS = 1, BIS1 = 0, BIS0 = 1) Figure 12-7
A0 to A4
Address Valid
D0 to D7
10ns
min.
R/W*
t1
t7 t8
10ns
min.
0ns min.
CS*
0ns min.
DS*
t2
t6
75ns min.
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t4
0ns min.
DS21348/Q348
AC CHARACTERISTICS—SERIAL PORT
(BIS1 = 1, BIS0 = 0)
PARAMETER
Setup Time CS* to SCLK
Setup Time SDI to SCLK
Hold Time SCLK to SDI
SCLK High/Low Time
SCLK Rise/Fall Time
SCLK to CS* Inactive
CS* Inactive Time
SCLK to SDO Valid
SCLK to SDO 3-State
CS* Inactive to SDO 3-State
See
SYMBOL
tCSS
tSSS
tSSH
tSLH
tSRF
tLSC
tCM
tSSV
tSSH
tCSH
MIN
50
50
50
200
(-40°C to +85°C; VDD = 3.3V ± 5%)
TYP
MAX
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
50
50
250
50
100
100
SERIAL BUS TIMING (BIS1 = 1, BIS0 = 0) Figure 12-8
tCM
CS*
tSRF
tCSS
tLSC
tSLH
SCLK1
SCLK2
SDI
tSSS
tSSH
LSB
tCSH
MSB
LSB
MSB
tSSV
SDO
HIGH Z
LSB
NOTES:
1) OCES =1 and ICES = 0.
2) OCES = 0 and ICES = 1.
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tSSH
MSB
HIGH Z
NOTES
DS21348/Q348
(-40°C to +85°C; VDD = 3.3V ± 5%
AC CHARACTERISTICS—RECEIVE SIDE
PARAMETER
RCLK Period
RCLK Pulse Width
RCLK Pulse Width
Delay RCLK to RPOS, RNEG,
PBEO, RBPV Valid
See Figure 12-9
SYMBOL
tCP
MIN
tCH
tCL
tCH
tCL
tDD
200
200
150
150
TYP
488
648
MAX
50
NOTES:
1)
2)
3)
4)
E1 Mode.
T1 or J1 Mode.
Jitter attenuator enabled in the receive path.
Jitter attenuator disabled or enabled in the transmit path.
Figure 12-9 RECEIVE SIDE TIMING
RCLK1
t CL
RCLK2
t CH
t CP
t DD
RPOS, RNEG
PBEO
bit
error
PRBS Detector Out of Sync
t DD
RNEG3
BPV/
EXZ/
CV
BPV/
EXZ/
CV
NOTES:
1) RCES = 1 (CCR2.0) or CES = 1.
2) RCES = 0 (CCR2.0) or CES = 0.
3) RNEG is in NRZ mode (CCR1.6 = 1).
68 of 73
UNITS
ns
ns
ns
ns
ns
ns
ns
NOTES
1
2
3
3
4
4
DS21348/Q348
AC CHARACTERISTICS—TRANSMIT SIDE (-40°C to +85°C; VDD = 3.3V ± 5%)
PARAMETER
TCLK Period
TCLK Pulse Width
TPOS/TNEG Setup to TCLK
Falling or Rising
TPOS/TNEG Hold from TCLK
Falling or Rising
TCLK Rise and Fall Times
See
SYMBOL
tCP
MIN
TYP
488
648
tCH
tCL
tSU
75
75
20
UNITS
ns
ns
ns
ns
ns
tHD
20
ns
tR , tF
25
NOTES:
1) E1 Mode.
2) T1 or J1 Mode.
TRANSMIT SIDE TIMING Figure 12-10
t CP
tR
MAX
t CL
tF
TCLK1
TCLK2
t SU
TPOS, TNEG
t HD
NOTES:
1) TCES = 0 (CCR2.1) or CES = 0.
2) TCES = 1 (CCR2.1) or CES = 1.
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t CH
ns
NOTES
1
2
DS21348/Q348
13.
MECHANICAL DIMENSIONS
SUGGESTED PAD LAYOUT
44 PIN TQFP, 10*10*1.0
SEE DETAIL "A"
DIMENSIONS ARE IN MILLIMETERS
70 of 73
DS21348/Q348
71 of 73
DS21348/Q348
13.1 Mechanical Dimensions—Quad Version
A1
3
A1
12 11 10
1
9
8
7
6
5
4
3
2
A
B C D E
1.27
17.0
F G H I
13.97
J
0.20
K
1.52
Y
X
4
17.0
0
1.27
13.97
1.52
DETAIL A
TOP VIEW (DIE SIDE)
BOTTOM VIEW (BALL SIDE)
0.05
2.60
REF
1.99
0.76
Z
DETAIL B
SIDE VIEW
72 of 73
0.61
0.59
DS21348/Q348
SOLDER BALL
f 0.76 REF
f 0.76
L
X
f 0.76
L
Z
Y
Z
DETAIL A
0.05 LABEL THICKNESS
//
2.60
REF
0.24
Z
//
SEATING PLANE
0.76
REF
DETAIL B
73 of 73
0.17
Z
0.10
2
Z