EPC EPC111 Fully integrated standalone light barrier driver & receiver Datasheet

epc111/112
Fully integrated standalone light barrier driver & receiver
General Description
Features
The epc111/112 is a general purpose, fully integrated self-contained
CMOS circuit family to be used in light-barrier applications.
 Fully integrated light barrier chip
 Needs just a photo diode and a LED with a LED driver
 Various types are available, i.e. high sensitivity or high speed
 Integrated clock generator
 CSP10 package with very small footprint
The chip contains a controller which drives an LED, typically an IRLED. The LED is used in a pulsed mode to increase the signal-tonoise ratio even when there is very strong sunlight biasing the photo
diode.
It contains also a high sensitive photo diode amplifier and a signal
conditioning circuitry to cancel unwanted environmental light including
strong sunlight and pulsed light sources. The receiver is built around a
synchronous demodulator circuitry. Two output signals with different
threshold levels are implemented in order to trigger the light barrier
output or to indicate light reserve.
Applications
 Light barriers ranging from millimeters to tens of meters
 Smoke detectors
 Liquid detectors
The chip also includes a power supply circuitry to establish all
internally required voltages from one source only.
It can be used as a standalone device forming the whole core of an
industrial light barrier.
Functional Block Diagram
for 10-Pin Chip Scale Package (for 16-pin QFN Package)
VDD
VDD 1 (9)
VLED
LED
Parameter
Memory
Interface
8 (14)
VDD33
VDD18
LED
Voltage Regulator
9 (12)
Processor
10 (10)
PD
Signal
Processor
Controller
f
3 (6)
D1
2 (7)
GND
4 (4)
7 (15)
NC
NC
6 (1)
5 (2)
OUTN OUTH
Figure 1: Block Diagram
Type
Response Time
Sensitivity
Typical Application
epc111
Medium
Medium (High)
Long range light barrier
epc112
Fast
Medium
High speed detection rate
Table 1: Characteristics of available types
© 2013 ESPROS Photonics Corporation
Characteristics subject to change without notice
1
Datasheet epc111_112 - V2.5
www.espros.ch
epc111/112
Absolute Maximum Ratings (Notes 1, 2)
Recommended Operating Conditions
Power Supply Voltage at pin VDD
-0.3V to +5.5V
Min.
Max.
Units
Voltage to any pin except VDD
-0.3V to VDD +0.3 V
Supply voltage at VDD (=VDD33)
3.0
3.6
V
Output current at any pin except LED
-6mA to +6mA
Supply voltage at VDD33 (=VDD)
3.0
3.6
V
Power Consumption with maximum load
125 mW
Operating Temperature (T O)
-40°
+85°
C
Lead Temperature solder, 4 sec. (T L)
+260°C
Relative Humidity (non-condensing)
+5
+95
%
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Recommended operating conditions
indicate conditions for which the device is intended to be functional, but do not guarantee specific performance limits. For guaranteed
specifications and test conditions, see Electrical Characteristics.
Note 2: This device is a highly sensitive CMOS ac current amplifier with an ESD rating of JEDEC HBM class 0 (<250V). Handling and
assembly of this device should only be done at ESD protected workstations.
Electrical Characteristics
3.0V < VDD < 3.6V, -40°C < T A < +85°C, unless otherwise specified
General Data
Symbol
VN
Parameter
Conditions/Comments
Values
Power supply voltage
at VDD and VDD33
VPUP
Power-up Threshold Voltage
Voltage at VDD33 when the device starts up
VPP
Ripple on supply voltage,
peak to peak
Type
V
mV
mV
2
mA
VHOH
Output high voltage OUTH
see Figure 6
@ 3mA source. See Figure 6.
in operation mode I PD = 0 mA, no load
VN- 0.5V
V
0.5
V
0.5
V
VN- 0.5V
V
0.5
ILED
Source current maximum
@ Pin LED
fclk
Reference clock
of internal oscillator - for information only
dfclk
Temperature drift
of the oscillator - for information only
Characteristics subject to change without notice
3
600
@ 4mA source
© 2013 ESPROS Photonics Corporation
2.4
250
Output low voltage OUTN
Output low voltage
3.6
60nA
Output high voltage OUTN
VLEDL
3.3
108nA
VNOL
Output high voltage
3.0
epc111
VNOH
Output low voltage OUTH
Max.
epc112
Current consumption
VHOL
Typ.
Input pulse I PD NST
IDD_OP
VLEDH
Units
Min.
0.7
2
V
mA
1
MHz
640
ppm/K
Datasheet epc111_112 - V2.5
www.espros.ch
epc111/112
Other Data
Symbol
Parameter
Conditions/Comments
Types
Values
Min.
IPDN
IPDH
Ipulse
Photo Current Sensitivity OUTN
Photo Current Sensitivity OUTH
Maximum Input Pulse Current
Typ.
Pulse height to trigger internal threshold
OUTN. Refer to Functional Description
epc111
60
epc112
108
Pulse height to trigger internal threshold
OUTH. Refer to Functional Description
epc111
96
epc112
144
If the input current pulse is above this level,
the recovery time t REC becomes trelax . (refer to
parameter trelax)
Units
Max.
nA
nA
epc111
100
epc112
100
µA
IN_Imin
Input related noise
@ IPDDC =0
15
nA RMS
IN_Imax
Input related noise
@ IPDDC =IPDDCMax
20
nA RMS
IPDDC
DC Photo Diode Current
generated by ambient light with no effect to
the sensitivity
2
mA
CPD
Photodiode Capacitance
Refer to section Application Information,
Photodiode Capacitance
50
pF
tPulse
LED Pulse Length
tCycle
trelax
tR
tF
nV
nM
0.0
LED Cycle Time
Recovery time
after a strong current pulse (I pulse = 100µA)
Response Time
Release Time (fall time)
Valid pulse counts
Missing pulse counts
epc111
2
epc112
1
epc111
100
epc112
10
µs
µs
epc111
50
epc112
50
Minimum time from light beam detection to
status change of the output OUTN or OUTH.
tR_MAX = ( nV + 1 ) * tCycle
epc111
800
900
epc112
30
40
Minimum time from beam interruption to
status change of the output OUTN or OUTH.
tF_MAX = ( nM + 1 ) * tCycle
epc111
800
900
epc112
20
30
Number of valid (non-missing) pulses to
trigger the output. Refer to Functional
Description
epc111
8
epc112
3
epc111
8
epc112
2
Number of missing pulses to release the
output. Refer to Functional Description
µs
µs
µs
Other Parameters
Sensitivity [nA]
(typical values, T amb = 25°C, VDD = 3.3V)
120
110
100
90
80
70
60
50
40
0
1
2
3
4
5
6
Pulse width [us]
Figure 2: Input Sensitivity vs. LED pulse width
© 2013 ESPROS Photonics Corporation
Characteristics subject to change without notice
3
Datasheet epc111_112 - V2.5
www.espros.ch
epc111/112
4
10-Pin Chip Scale Package (CSP)
Pin Name Type
1
2
3
4
NC
3
NC_GND
2
OUTH
1
8
7
6
NC_GND
OUTN
NC
NC
16
PD
GND
PD
NC_GND
Top View
15
GND
LED
NC_GND
5
5
VDD
VDD
12
OUTH
Top View
14
VDD18
NC_GND
13
10
VDD18
6
OUTN
NC_GND
7
NC
11
8
LED
10
9
VDD33
9
VDD33
Connection Diagrams
16-Pin QFN Package
Note: For sampling only. Limited quantities. Please inquire.
10-Pin
CSP
16-Pin
QFN
Description
1
9
VDD
Power Supply
Positive power supply. To be connect to VDD33.
2
7
GND
Power Supply
Negative power supply pin.
3
6
PD
Analog Input
Photo diode input.
4
4
NC
5
2
OUTH
Digital Out
Load depending
Light reserve detected - see Figure 6.
Threshold level around 50% above the threshold of the filtered signal level.
Open drain output
6
1
OUTN
Digital Output
Light pulses detected by the photo diode - see Functional Description
Amplified and filtered signal
Open drain output
7
15
NC
8
14
LED
9
12
10
n/a
Do not connect this pin. Internally terminated.
Do not connect this pin. Internally terminated.
Digital Out
Output to LED driver. Signal is low active.
VDD33
Power Supply
Positive power
supply. ToQFN16-VEEDbe connected to VDD.
LST
PIN Connections
10
VDD18
Decoupling
Pin for external filter/decoupling of the internal 1.8V supply: 4.7nF ceramic type
Not for supply of external circuits
3, 5, 8,
11, 13,
16
NC_GND
© 2013 ESPROS Photonics Corporation
Characteristics subject to change without notice
1VN4
PIN Connections QFN16-VEED-
Not connected. Connect this1VN4
pins to GND (Guarding).
LST
15.12.2010
Page 1
File: Unbenannt
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4
Datasheet epc111_112 - V2.5
www.espros.ch
epc111/112
Functional Description
Evaluation of single light pulse
For each single light pulse, received and detected by the LED, the threshold levels are processed according to the following principle to
propagate the output signals OUTN and OUTH resp. OUTNINT and OUTHINT. As far the received light pulse signal exceeds the corresponding
threshold level, the pulse will be recognized as a valid pulse and the detection circuit sets the appropriate output signal OUTN INT or OUTHINT.
IPD
Light pulse detection
IPD
Light reserve detection
Threshold levels:
Light reserve OUTH
Signal output OUTN
t
t
t
t
t
t
OUTNINT
OUTHINT
Figure 3: Pulse evaluation
Pulse Modulated Operation (e.g. OUTN int to OUTN)
The epc111/112 chip operates the LED and the receiver path on a pulse modulated concept. Thus, the LED is operated with short pulses
whereas the receiver channel does synchronous demodulation of the received light pulses by reading the current pulses of the photodiode.
This concept allows a very high sensitivity, high speed operation, and a high suppression of input ambient or foreign light (DC currents)
generated by sunlight or other DC light sources like light bulbs.
In order to eliminate interference caused by modulated light, e.g. a flashing light or by other light barriers, the input signal from the photodiode
is amplified, filtered, and processed by an integrated signal processor. If the photodiode signal meets the required frequency, pattern and
amplitude, the output(s) are triggered. The following timing diagram shows the basic concept.
tCycle
tPulse
on
off
Emitter LED
yes
Beam interrupted
no
Photo diode current IPD
1
2
nM
1
2
nV
OUTNINT or OUTHINT
OUTN or OUTH
[V]
tF
tR
Release time
missing pulses
Response time
valid (non-missing) pulses
Figure 4: Pulse modulation concept
It is in fact a digital filter which counts missing and non-missing pulses to change the ou tput state of OUTN or OUTH.
© 2013 ESPROS Photonics Corporation
Characteristics subject to change without notice
5
Datasheet epc111_112 - V2.5
www.espros.ch
epc111/112
Working principle of the digital filter e.g. for the signal OUTNint to OUTN Filter:
The aim of this programmable filter is to suppress single pulses, so they cannot trigger the output and generate a false signal.
This filter is based on a counter, which is counting up (increment) the valid pulses and counting down (decrement) the missing pulses in a
weighted manner. There are separate weighting factors for valid pulses (parameter nV) and missing pulses (parameter nM). If the counter
reaches the upper limit (maximum count, response time), the signal OUTN is set to LOW. Similar in the opposite direction, if the counter
reaches zero, the lower limit (minimum count, release time), the signal OUTN is put to HIGH. With the parameters nV and nM the filter has the
advantage of individual selectable gradients of the slopes. Counter will never exceed maximum nor minimum limit. In between it acts as an
integrator of both parameters.
IF Pulse then
–
IF Pulse = valid then
Counter = Counter + (nV * 1024)
IF counter > 2 15 (maximum limit) then Counter = maximum limit
IF counter = maximum limit then OUTN = 0
–
IF Pulse = missing then
Counter = Counter – (2 nM)
IF counter < 0 (minimum limit) then Counter = minimum limit
IF counter = minimum limit then OUTN = 1
ELSE wait for Pulse
Lets assume that the photodiode does not receive light pulses for a long time: This means the light beam is interrupted. Then OUTN is at high
level. If the light beam is not interrupted anymore, the photodiode receives light pulses which are strong enough to trigger the OUTNINT
threshold and the internal pulse evaluation unit (designated in Figure 3 with 'Pulse evaluation') starts to count the received pulses. If the
number of received pulses reach the set level n V, the output OUTN turns to low level. Thus, single pulses cannot trigger the output and
generate a false signal.
The same procedure is used when a beam changes from not interrupted to interrupted. The internal pulse evaluation unit counts the missing
pulses. If the number of missing pulses reaches the level n M, OUTN is turned to high level.
The same principle applies to the counter and signal of OUTH.
The counter limit values are different, depending on the device:
Type
No. of
Pulses nM
No. of
missing Pulses n V
epc111
8
8
3
2
epc112
Table 2: Filter coefficients
Light Pulse Detection Output OUTN
The epc111/112 contains two digital outputs to indicate that a valid signal of light pulses are received by the photodiode. The first output OUTN
is triggered, when the lower threshold is reached by the input signal (see Figure 3). This output is used usually to drive the output of the light
barrier. This is a fully CMOS compatible digital output.
© 2013 ESPROS Photonics Corporation
Characteristics subject to change without notice
6
Datasheet epc111_112 - V2.5
www.espros.ch
epc111/112
Light Reserve Output OUTH
However, if the incoming signal is just at the trigger threshold of OUTN, an unstable situation can occur. Thus, a second output OUTH is
integrated with a higher trigger threshold to indicate that a certain 'light reserve' is reached (see Figure 3). This output is usually used to drive
a visible LED to indicate to the operator a stable detection function of the light barrier. To have not too short pulses OUTH, this signal is
stimulated by signal OUTH Filter and synchronously reset by OUTN.
The trigger threshold of OUTH is set approx. 50% above the trigger threshold of OUTN.
Emitter LED
OUTN Filter
OUTH Filter
OUTN
OUTH
Figure 5: synchronization OUTH with OUTN
This output is not CMOS compatible. Its voltage is depending of the load according to Figure 6. To have still digital compatible signals a level
conversion is necessary.
OUTH low max.
Current OUTH [mA]
OUTH high max.: 3.6V / - 40ºC
OUTH high typ.
OUTH high min.: 3.0V / + 85ºC
Voltage OUTH [V]
Figure 6: Output voltage versus output current of output OUTH
File: Unbenannt
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© 2013 ESPROS Photonics Corporation
Characteristics subject to change without notice
7
.
Datasheet epc111_112 - V2.5
www.espros.ch
epc111/112
Below you find some examples for such circuits for converting OUTH levels to full CMOS compatible digital output.
+3.3V
R4
10k
VDD
epc11x
R1
3k6
VDD33
VDD18
R2
12k
T1
BC846 B
LED
PD
OUTH
OUTN
OUTH
GND
R3
4k7
GND
Figure 7: Non-inverting, low power level shifter (additional current ca.0.6mA)
+3.3V
+3.3V
VDD
epc11x
VDD18
File:
R3
33k
R1
1k5
VDD33
R4
22k
VDD
epc11x
VDD33
OUTH
VDD18
LED
<Title>
PD
OUTN
OUTH
R1
3k6
T1
BC846 B
10k
OUTH
T1
T2
BC846 B <name>BC846 B
Figure 8: Simple inverting level shifter
(additional current ca.1.6mA or 2.6mA)
R3
4k7
Figure 9: Inverting, low power level shifter
(additional current ca.0.8 ... 1.0mA)
<name>
<Title>
<xx>
File:
This document is confidential and protected by law and international trades. It must not be shown to any third party nor be copied in any form without our written permission .
<name>
02.12.2011
<xx>
Page 1
cted by law and international trades. It must not be shown to any third party nor be copied in any form without our written permission
.
Characteristics subject to change without notice
Page 1
GND
GND
© 2013 ESPROS Photonics Corporation
02.12.
<xx>
OUTN
OUTH
R2 trades. It must not be shown to any third party nor be copied in any formGND
This document is confidential and protected by law and international
without our written permission .
GND
R2
12k
LED
PD
R5
33k
8
Datasheet epc111_112 - V2.5
www.espros.ch
epc111/112
Applications
Long range light barrier application
Figure 10 shows the epc111 as an example in a long range light barrier application with minimal part count. The LED flashes according to the
description of the previous chapter. Light of the LED is passing either direct, reflected from a reflecting object or a retro reflector to the photo
diode PD. If the received light fulfills the criteria according to the description in the previous chapter, the output signals OUTN and OUTH are
set.
The epc111 device is designed to operate at 3.3V power supply (VDD and VDD33).
LED Driver:
The output LED of the epc111 is a current source capable to drive typically 1mA and has an inverted output signal. For a high performance
long range light barrier (>8m) an LED peak current of up to 1.5A is needed. To generate such a high LED current, an external driver circuit is
necessary. The circuitry in Figure 10 is a simple implementation of such a driver circuit. T3, R4 and R5 inverse the signal. The current source
for the output LED is built by the darlington circuit T1 / T2 and R2 and R3. In order to avoid interference on the supply voltage, the supply is
isolated (filtered) with R1 and C1. The high peak LED pulse current is delivered by the capacitor C1, which itself is charged by R1. Make sure,
that there is no coupling of the high LED current to the ground of the epc111 or to the cathode of the photo diode. This driver circuit operates
with a VDDLED in a range of 10 to 30 VDC.
+3.3V
VDDLED= +24V
C2 1μF
C3 100nF
R6
10k
R8
12k
epc111
C5 4.7nF
R7
3k6
VDD33
VDD18
IR LED
TSML1000
T3
BC856
T4
BC846
LED
PD
PD
epc300
R10
10k
VDD
C4 100nF
R1
100R
R4
10k
OUTN
OUTH
T1
BC846
GND
R9
4k7
GND
R5
1k
OUTN
R2
1k
T2
BCP56
R3
1R2
C1
47μF
Low ESR
OUTH
Marked conductors must be short and low ohmic
C2
The epc111 device with its very sensitive input PD needs a well decoupled power supply
Figure 10: Long range light barrier application with minimal part count
Notice:
The schematic is for illustrating the basic circuit idea only. For the real built up the designer has to take all other additional influence factors in
consideration too e.g. design rules, power rating, heat dissipation, ...
© 2013 ESPROS Photonics Corporation
Characteristics subject to change without notice
9
Datasheet epc111_112 - V2.5
www.espros.ch
epc111/112
High speed detection rate design
Figure 11 shows the epc 112 as an example in a high speed detection rate light barrier application with minimal part count. This design is
optimized for a fast reading of light beam interruptions. Whereas the working principle is similar to the above example. This driver circuit
operates with a VDD LED in a range of 6 to 20 VDC.
The epc112 device is designed to operate at 3.3V power supply (VDD and VDD33).
+3.3V
VDDLED= +12V
C2 1μF
C3 100nF
R5
10k
R7
12k
VDD
C4 100nF
epc112
C5 4.7nF
R6
3k6
VDD33
VDD18
R3
10k
OUTN
OUTH
GND
PD
epc300
GND
IR LED
TSML1000
T2
BC856
T3
BC846B
LED
PD
R1
47R
R9
10k
R8
4k7
T1
BC846B
R4
1k
R2
13R
C1
10μF
Low ESR
OUTH
OUTN
Marked conductors must be short and low ohmic
C2
The epc112 device with its very sensitive input PD needs a well decoupled power supply
Figure 11: High speed detection rate light barrier application with minimal part count
Notice:
The schematic is for illustrating the basic circuit idea only. For the real built up the designer has to take all other additional influence factors in
consideration too eg. design rules, power rating, heat dissipation, ...
Design Precautions: EMC shielding
The sensitivity at pin PD is very high in order to achieve a long operation range of light barriers even without
lenses in front of the IR LED and/or the photo diode. Thus, the pin PD is very sensitive to EMI. Special care
should be taken to keep the PCB track at pin PD as short as possible (a few mm only!). This track should be
kept away from the IR LED signal tracks and from other sources which may induce unwanted signals. It is
strongly recommended to cover the chip, the photodiode and all passive components around the chip with a
metal shield. A recommended part is shown in Figure 12. The pins at the bottom are to solder the shield to
Figure 12: Recommended EMC
the PCB with electrical connection to GND. The hole in the front is the opening window for the photo diode.
shield
The backside of the PCB below the sensitive area (PD, epc111 or epc112) shall be a polygon connected to
GND to shield the circuit from the backside as well.
Ambient Light
Photodiode DC current can be generated by ambient light, e.g. sunlight. DC current at pin PD does not generate a DC output signal. However,
if IPDDC is above the stated maximal value, the input is saturated. This blocks the detection of AC current pulses.
Photodiode Capacitance
If the photo diode capacity is above the specified value, a lower detection sensitivity and a possible higher sensitivity spread results.
© 2013 ESPROS Photonics Corporation
Characteristics subject to change without notice
10
Datasheet epc111_112 - V2.5
www.espros.ch
Layout Information (all measures in mm,
)
CSP-10 Package
Mechanical Dimensions
Designed
Approved
Scale
Page
Part Name
<Name>
<Partname>
26.02.2009
<Name>
<Data>
M 1:1
DIN A4
1
Part No.
<x000 000>
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.
epc111/112
Layout Recommendations
File: Unben annt
0.15
0.15
1.89 +0.00/-0.09
∅ 0.3
0.5
0.5
Pin 1
0.5
Solder balls Sn97.5Ag2.5
0.5
0.5
2.5
A
0.3
0.15
2.0
0.5
1.39 +0.00/-0.09
0.5
Bottom View
no solder mask inside this area
Revision:
Dimension A:
-
A
0.12 ±0.02
0.15 ±0.02
Figure 13: CSP10: Mechanical dimensions
Figure 14: CSP10: Layout recommendation
Recommendations for reliable soldering of solder balls:
•
Use a pad layout similar to the one shown in Figure 14. Notice that all tracks should go underneath the solder mask area.
•
Do not connect any pins direct pin to pin inside of the opening of the solder mask.
•
In case of the conductors are with a Au-Ni surface finish the preferred landing pad design for the solder balls will be covering the
round landing pad with a gold surface finish as a solderable area only.
QFN-16 Package
Note: For sampling only. Limited quantities. Please inquire.
<name>
<Title>
VDD18
VDD
VDD33
11
10
9
le:
NC_GND
Opening in solder mask
20.09.2012
Page 1
Conductor layout
8
14
7
13
LED
NC_GND
GND
6
12
NC_GND
PD
5
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NC_GND
Top View
16
NC_GND
15
NC
3
OUTH
NC_GND
4
NC
2
OUTN
Shielding of PD pin
1
Figure 15: QFN-16: Layout recommendation
© 2013 ESPROS Photonics Corporation
Characteristics subject to change without notice
11
Datasheet epc111_112 - V2.5
www.espros.ch
epc111/112
1.9
Bottom View
0.25
Top view
2.9 - 3.1
1.9
0.9
0.5
0.1 - 0.2
0.02
2.9 - 3.1
0.25
0.3
Figure 16: QFN-16: Mechanical dimensions
Reflow
Solder Profile
Mechanical dimension QFN16 Package
LST
15.08.2010
Page 1
For infrared or conventional soldering the solder profile has to follow the recommendations of IPC/JEDEC J-STD-020C (min. revision C) for
assembly
for
types
ofIt must
packages.
The
peak
soldering
t emperature
(TLpermission
) should
This document is Pb-free
confidential and
protected by law
andboth
international
trades.
not be shown to
any third
party nor
be copied in any
form without our written
. not exceed +260°C for a maximum of 4 sec.
File:
hanical dimension SOT23-6L
LST
© 2013 ESPROS Photonics Corporation
Characteristics subject to change without notice
12
Datasheet epc111_112 - V2.5
www.espros.ch
CSP6 Tape
QFN16 Tape
Pin 1
Pin 1
8
epc111/112
12
Packaging Information (all measures in mm)
Tape & Reel Information
The devices are mounted on embossed tape for2 automatic placement systems. The tape is wound on 178 mm (7 inch) or 330 mm (13 inch)
reels and individually packaged for shipment. General tape-and-reel specification data are available in a separate data sheet and indicate the
tape sizes for various package types. Further tape-and-reel specifications can be found in the Electronic Industries Association (EIA) standard
8
481-1, 481-2, 481-3.
CSP6 Tape
QFN16 Tape
Pin 1
12
8
Pin 1
4
8
Figure 17: CSP10 and QFN16 Tape Dimension. Parts are placed with solder pads on bottom side
ESPROS Photonics AG does not guarantee that there are no empty cavities. Thus, the pick-and-place machine should check the presence of
a chip during picking.
Ordering Information
Standard products:
Response Time
Sensitivity
Package
RoHS compliance
Packaging Method
epc111-CSP10
Type
Medium
High
CSP10
Yes
Reel
epc112-CSP10
Fast
Medium
CSP10
Yes
Reel
Sensitivity
Package
RoHS compliance
Packaging Method
For sampling only. Limited quantities. Please inquire.
Type
Response Time
epc111-QFN16
Medium
High
QFN16
Yes
Reel
epc112-QFN16
Fast
Medium
QFN16
Yes
Reel
© 2013 ESPROS Photonics Corporation
Characteristics subject to change without notice
13
Datasheet epc111_112 - V2.5
www.espros.ch
epc111/112
IMPORTANT NOTICE
ESPROS Photonics AG and its subsidiaries (epc) reserve the right to make corrections, modifications, enhancements, improvements, and
other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the
latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject
to epc’s terms and conditions of sale supplied at the time of order acknowledgment.
epc warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with epc’s standard war ranty. Testing and other quality control techniques are used to the extent epc deems necessary to support this warranty. Except where man dated by government requirements, testing of all parameters of each product is not necessarily performed.
epc assumes no liability for applications assistance or customer product design. Customers are responsible for their products and applications
using epc components. To minimize the risks associated with customer products and applications, customers should provide adequate design
and operating safeguards.
epc does not warrant or represent that any license, either express or implied, is granted under any epc patent right, copyright, mask work
right, or other epc intellectual property right relating to any combination, machine, or process in which epc products or services are used.
Information published by epc regarding third-party products or services does not constitute a license from epc to use such products or
services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other
intellectual property of the third party, or a license from epc under the patents or other intellectual property of epc.
Resale of epc products or services with statements different from or beyond the parameters stated by epc for that product or service voids all
express and any implied warranties for the associated epc product or service. epc is not responsible or liable for any such statements.
epc products are not authorized for use in safety-critical applications (such as life support) where a failure of the epc product would
reasonably be expected to cause severe personal injury or death, unless officers of the parties have executed an agreement specifically
governing such use. Buyers represent that they have all necessary expertise in the safety and regulatory ramifications of their applications,
and acknowledge and agree that they are solely responsible for all legal, regulatory and safety-related requirements concerning their products
and any use of epc products in such safety-critical applications, notwithstanding any applications-related information or support that may be
provided by epc. Further, Buyers must fully indemnify epc and its representatives against any damages arising out of the use of epc products
in such safety-critical applications.
epc products are neither designed nor intended for use in military/aerospace applications or environments unless the epc products are specifically designated by epc as military-grade or "enhanced plastic." Only products designated by epc as military-grade meet military specifications. Buyers acknowledge and agree that any such use of epc products which epc has not designated as military-grade is solely at the
Buyer's risk, and that they are solely responsible for compliance with all legal and regulatory requirements in connection with such use.
epc products are neither designed nor intended for use in automotive applications or environments unless the specific epc products are designated by epc as compliant with ISO/TS 16949 requirements. Buyers acknowledge and agree that, if they use any non-designated products in
automotive applications, epc will not be responsible for any failure to meet such requirements.
© 2013 ESPROS Photonics Corporation
Characteristics subject to change without notice
14
Datasheet epc111_112 - V2.5
www.espros.ch