Linear Dimensions LT3055 500ma, linear regulator with precision current limit and diagnostic Datasheet

LT3055
500mA, Linear Regulator
with Precision Current Limit
and Diagnostics
DESCRIPTION
FEATURES
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Output Current: 500mA
Dropout Voltage: 350mV
Input Voltage Range: 2V to 45V
Programmable Precision Current Limit: ±10%
Output Current Monitor: 1/500th of IOUT
Programmable Minimum IOUT Monitor
Temperature Monitor: 10mV/°C
FAULT Indicator: Current Limit, Thermal Limit or
Minimum IOUT
Low Noise: 25μVRMS (10Hz to 100kHz)
Adjustable Output (VREF = VOUT(MIN) = 0.6V)
Output Tolerance: ±2% Over Load, Line and Temperature
Stable with Low ESR, Ceramic Output Capacitors
(3.3μF Minimum)
Shutdown Current: <1μA
Reverse Battery and Thermal Limit Protection
16-Lead 4mm × 3mm DFN and MSOP Packages
The LT®3055 is a micropower, low noise, low dropout voltage (LDO) linear regulator. The device supplies 500mA of
output current with a dropout voltage of 350mV. A 10nF
bypass capacitor reduces output noise to 25μVRMS in a
10Hz to 100kHz bandwidth and soft starts the reference.
The LT3055’s ±45V input voltage rating combined with its
precision current limit and diagnostic functions make the
IC an ideal choice for robust, high reliability applications.
A single resistor programs the LT3055’s current limit, accurate to ±10% over a wide input voltage and temperature
range. Another resistor programs the LT3055’s minimum
output current monitor, useful for detecting open-circuit
conditions. The current monitor function sources a current
equal to 1/500th of output current. Logic fault pins assert
low if the LT3055 is in current limit (FAULT2), operating
below its minimum output current (FAULT1) or is in thermal
limit (both FAULT1 and FAULT2). PWRGD indicates output
regulation. The TEMP pin indicates average die temperature.
APPLICATIONS
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The LT3055 optimizes stability and transient response
with low ESR ceramic capacitors, requiring a minimum of
3.3μF. Internal protection circuitry includes current limiting, thermal limiting, reverse battery protection, reverse
current protection and reverse output protection.
Protected Antenna Supplies
Automotive Telematics
Industrial Applications (Trucks, Forklifts, etc.)
High Reliability Applications
Noise-Sensitive RF or DSP Supplies
The LT3055 is available as an adjustable device with an
output voltage range from 0.6V to 40V.
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and
ThinSOT is a trademark of Linear Technology Corporation. All other trademarks are the property
of their respective owners.
TYPICAL APPLICATION
Precision Current Limit, RIMAX = 604Ω
550
5V Supply with 497mA Precision Current Limit, 10mA IMIN
VIN
12V
+
IN
10µF
22nF
0.1µF
200k
200k
200k
604Ω
(THRESHOLD = 497mA)
120k
(THRESHOLD = 10mA)
LT3055
OUT
SHDN
FAULT1
FAULT2
PWRGD
IMAX
IMIN
ADJ
IMON
TEMP
REF/BYP
GND
442k
1%
5V
10nF
10µF
60.4k
1%
1k
(ADC
FULL-SCALE = 1V)
0.1µF
TO
µP
ADC
TO
µP
ADC
10nF
3055 TA01a
CURRENT LIMIT FAULT THRESHOLD (mA)
n
540
VOUT(NOMINAL) = 5V
530
520
510
500
490
VIN = 7V
VIN = 5.6V
480
470
460
450
–75 –50 –25 0 25 50 75 100 125 150 175
TEMPERATURE (°C)
3055 TA01b
3055f
For more information www.linear.com/LT3055
1
LT3055
ABSOLUTE MAXIMUM RATINGS
(Note 1)
IN Pin Voltage..........................................................±50V
OUT Pin Voltage............................................ +40V, –50V
Input-to-Output Differential Voltage...............+50V, –40V
ADJ Pin Voltage.......................................................±50V
SHDN Pin Voltage....................................................±50V
FAULT1, FAULT2, PWRGD Pin Voltage.............–0.3V, 50V
IMON Pin Voltage...............................................–0.3V, 7V
IMIN Pin Voltage................................................–0.3V, 7V
IMAX Pin Voltage...............................................–0.3V, 7V
TEMP Pin Voltage.............................................–0.3V, 7V
REF/BYP Pin Voltage....................................................1V
Output Short-Circuit Duration........................... Indefinite
Operating Junction Temperature Range (Notes 2, 3)
E-, I-Grades........................................ –40°C to 125°C
MP-Grade........................................... –55°C to 150°C
H-Grade.............................................. –40°C to 150°C
Storage Temperature Range................... –65°C to 150°C
Lead Temperature: (Soldering, 10 sec)
MSOP Package Only.......................................... 300°C
PIN CONFIGURATION
TOP VIEW
TOP VIEW
IN
IN
SHDN
FAULT1
FAULT2
PWRGD
TEMP
IMON
1
2
3
4
5
6
7
8
17
GND
16
15
14
13
12
11
10
9
OUT
OUT
ADJ
GND
GND
REF/BYP
IMAX
IMIN
MSE PACKAGE
16-LEAD PLASTIC MSOP
TJMAX = 125°C, θJA = 37°C/W, θJC = 5°C/W TO 10°C/W
TJMAX = 150°C FOR H-GRADE
EXPOSED PAD (PIN 17) IS GND, MUST BE SOLDERED TO PCB
IN
1
IN
2
SHDN
3
FAULT1
4
FAULT2
5
PWRGD
6
TEMP
7
IMON
8
16 OUT
15 OUT
17
GND
14 ADJ
13 GND
12 GND
11 REF/BYP
10 IMAX
9 IMIN
DE PACKAGE
16-LEAD (4mm × 3mm) PLASTIC DFN
TJMAX = 125°C, θJA = 38°C/W, θJC = 4.3°C/W
EXPOSED PAD (PIN 17) IS GND, MUST BE SOLDERED TO PCB
ORDER INFORMATION
LEAD FREE FINISH
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LT3055EMSE#PBF
LT3055EMSE#TRPBF
3055
16-Lead Plastic MSOP
–40°C to 125°C
LT3055IMSE#PBF
LT3055IMSE#TRPBF
3055
16-Lead Plastic MSOP
–40°C to 125°C
LT3055MPMSE#PBF
LT3055MPMSE#TRPBF
3055
16-Lead Plastic MSOP
–55°C to 150°C
LT3055HMSE#PBF
LT3055HMSE#TRPBF
3055
16-Lead Plastic MSOP
–40°C to 150°C
LT3055EDE#PBF
LT3055EDE#TRPBF
3055
16-Lead (4mm × 3mm) Plastic DFN
–40°C to 125°C
LT3055IDE#PBF
LT3055IDE#TRPBF
3055
16-Lead (4mm × 3mm) Plastic DFN
–40°C to 125°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
3055f
2
For more information www.linear.com/LT3055
LT3055
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 2)
PARAMETER
CONDITIONS
Minimum Input Voltage (Note 3, 11)
ILOAD = 500mA
ADJ Pin Voltage (Note 3, 4)
VIN = 2.2V, ILOAD = 1mA
2.2V < VIN < 45V, 1mA < ILOAD < 500mA
Line Regulation (Note 3)
∆VIN = 2.2V to 45V, ILOAD = 1mA
Load Regulation (Note 3)
VIN = 2.2V, ILOAD = 1mA to 500mA
Dropout Voltage, VIN = VOUT(NOMINAL) (Notes 5, 6)
ILOAD = 10mA
MIN
TYP
1.8
2.2
V
594
588
600
606
612
mV
mV
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0.25
3
mV
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0.5
4
mV
140
175
260
mV
mV
200
250
370
mV
mV
225
275
410
mV
mV
350
400
590
mV
mV
65
100
270
1.8
11
130
200
550
4.5
25
μA
μA
μA
mA
mA
0.2
1
μA
16
60
nA
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l
ILOAD = 50mA
l
ILOAD = 100mA
l
ILOAD = 500mA
l
MAX
UNITS
GND Pin Current, VIN = VOUT(NOMINAL) + 0.6V
(Notes 6, 7)
ILOAD = 0mA
ILOAD = 1mA
ILOAD = 10mA
ILOAD = 100mA
ILOAD = 500mA
Quiescent Current in Shutdown
VIN = 45V, VSHDN = 0V
ADJ Pin Bias Current (Notes 3,12)
VIN = 12V
Output Voltage Noise
COUT = 10µF, ILOAD = 500mA, VOUT = 600mV,
BW = 10Hz to 100kHz
90
μVRMS
COUT = 10µF, CBYP = 10nF, ILOAD = 500mA,
VOUT = 600mV, BW = 10Hz to 100kHz
25
μVRMS
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Shutdown Threshold
VOUT = Off to On
VOUT = On to Off
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SHDN Pin Current (Note 13)
VSHDN = 0V, VIN = 45V
VSHDN = 45V, VIN = 45V
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Ripple Rejection
VIN-VOUT = 2V, VRIPPLE = 0.5VP-P, fRIPPLE = 120Hz,
ILOAD = 500mA
Input Reverse Leakage Current
VIN = –45V, VOUT = 0
Reverse Output Current (Note 14)
VOUT = 1.2V, VIN = 0
Internal Current Limit (Note 3)
VIN = 2.2V, VOUT = 0, IMAX = 0
VIN = 2.2V, ∆VOUT = –5%
0.9
1.3
1.1
0.5
70
1.42
V
V
1
3
μA
µA
85
l
0
dB
300
μA
10
μA
900
mA
mA
l
520
5.6V < VIN < 10V, VOUT = 5V, RIMAX = 1.5k,
FAULT2 Pin Threshold (IFAULT)
l
180
200
220
mA
5.6V < VIN < 7V, VOUT = 5V, RIMAX = 604Ω,
FAULT2 Pin Threshold (IFAULT)
l
445
495
545
mA
FAULT, PWRGD Pins Logic Low Voltage
Pull-Up Current = 50μA
l
0.14
0.25
V
FAULT, PWRGD Pins Leakage Current
VFAULT1, VFAULT2, VPWRGD = 5V
0.01
1
μA
IMIN Threshold Accuracy (Notes 6, 9)
5.6V < VIN < 15V, VOUT = 5V, RIMIN = 1.2M
5.6V < VIN < 15V, VOUT = 5V, RIMIN = 120K
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0.9
9
1
10
1.1
11
mA
mA
PWRGD Trip Point
% of Nominal Output Voltage, Output Rising
l
86
90
94
%
PWRGD Trip Point Hysteresis
% of Nominal Output Voltage
External Programmed Current Limit, VOUT = 5V
(Notes 6, 8)
1
%
3055f
For more information www.linear.com/LT3055
3
LT3055
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 2)
PARAMETER
CONDITIONS
Current Monitor Ratio (Notes 6,10), Ratio = IOUT/IMON ILOAD = 10mA, 250mA, 500mA
TEMP Voltage (Note 16)
TJ = 25°C
TJ = 125°C
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TEMP Error (Note 16)
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Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime. Absolute maximum input-to-output differential
voltage is not achievable with all combinations of rated IN pin and OUT pin
voltages. With the IN pin at 50V, the OUT pin may not be pulled below 0V.
The total differential voltage from IN to OUT must not exceed +50V, –40V.
If OUT is pulled above GND and IN, the total differential voltage from OUT
to IN must not exceed 40V.
Note 2: The LT3055 is tested and specified under pulse load conditions
such that TJ ~ TA. The LT3055E is 100% production tested at TA = 25°C
and performance is guaranteed from 0°C to 125°C. Performance at –40°C
and 125°C is assured by design, characterization and correlation with
statistical process controls. The LT3055I is guaranteed over the full –40°C
to 125°C operating junction temperature range. The LT3055MP is 100%
tested over the –55°C to 150°C operating junction temperature range. The
LT3055H is 100% tested at 150°C operating junction temperature.
Note 3: The LT3055 adjustable version is tested and specified for these
conditions with ADJ pin connected to the OUT pin.
Note 4: Maximum junction temperature limits operating conditions.
Regulated output voltage specifications do not apply for all possible
combinations of input voltage and output current. If operating at the
maximum input voltage, limit the output current range. If operating at
the maximum output current, limit the input voltage range. Current limit
foldback limits the maximum output current as a function of input-tooutput voltage. See Current Limit vs VIN-VOUT in the Typical Performance
Characteristics section.
Note 5: Dropout voltage is the minimum differential IN-to-OUT voltage
needed to maintain regulation at a specified output current. In dropout,
the output voltage equals (VIN – VDROPOUT). For some output voltages,
minimum input voltage requirements limit dropout voltage.
Note 6: To satisfy minimum input voltage requirements, the LT3055
adjustable version is tested and specified for these conditions with an
external resistor divider (60k bottom, 440k top) which sets VOUT to 5V. The
external resistor divider adds 10μA of DC load on the output. This external
current is not factored into GND pin current.
MIN
TYP
MAX
UNITS
450
500
550
mA/mA
0.25
1.25
–0.08
V
V
0.08
V
Note 7: GND pin current is tested with VIN = VOUT(NOMINAL) + 0.6V and a
current source load. GND pin current increases in dropout. See GND pin
current curves in the Typical Performance Characteristics section.
Note 8: Current limit varies inversely with the external resistor value tied
from the IMAX pin to GND. For detailed information on how to set the IMAX
pin resistor value, please see the Operation section. If a programmed
current limit is not needed, tie the IMAX pin to GND and internal protection
circuitry implements short-circuit protection as specified.
Note 9: The IMIN fault condition asserts if the output current falls below the
IMIN threshold defined by an external resistor from the IMIN pin to GND.
For detailed information on how to set the IMIN pin resistor value, please
see the Operation section. If the IMIN fault condition is not needed, the IMIN
pin must be left floating (unconnected).
Note 10: Current monitor ratio is tested with the IMON pin fixed at
VOUT – 0.5V and with the input range limited to VOUT + 0.6V < VIN < VOUT
+ 10V for IOUT = 10mA; VOUT + 0.6V < VIN < VOUT + 4V for IOUT = 250mA,
and VOUT + 0.6V < VIN < VOUT + 2V for IOUT = 500mA. Input voltage range
conditions are set to limit power dissipation in the IC to 1W maximum for
test purposes. The current monitor ratio varies slightly when in current
limit or when the IMON voltage exceeds VOUT – 0.5V. Please see the
Operation section for more information. If the current monitor function is
not needed, tie the IMON pin to GND.
Note 11: To satisfy requirements for minimum input voltage, current limit
is tested at VIN = VOUT(NOMINAL) + 1V or VIN = 2.2V, whichever is greater.
Note 12: ADJ pin bias current flows out of the ADJ pin.
Note 13: SHDN pin current flows into the SHDN pin.
Note 14: Reverse output current is tested with the IN pin grounded and the
OUT pin forced to the specified voltage. This current flows into the OUT
pin and out of the GND pin.
Note 15: 500mA of output current does not apply to the full range of input
voltage due to the internal current limit foldback.
Note 16: The TEMP output voltage represents the average temperature of
the die while dissipating quiescent power. Due to the pass device power
dissipation and temperature gradients across the die, the TEMP output
voltage measurement does not guarantee that absolute maximum junction
temperature is not exceeded.
3055f
4
For more information www.linear.com/LT3055
LT3055
TYPICAL PERFORMANCE CHARACTERISTICS
Guaranteed Dropout Voltage
600
550
TJ = 150°C
450
TJ = 125°C
350
300
TJ = 25°C
250
200
150
100
50
0
0
50 100 150 200 250 300 350 400 450 500
OUTPUT CURRENT (mA)
550
500
TJ = 150°C
TJ = 25°C
0
200
150
3055 G03
Output Voltage = 3.3V
3.366
IL = 1mA
4.98
4.96
4.94
4.92
4.90
–75 –50 –25 0 25 50 75 100 125 150 175
TEMPERATURE (°C)
3055 G07
IL = 1mA
3.355
3.344
3.333
OUTPUT VOLTAGE (V)
608
606
604
602
600
598
596
594
3.322
3.311
3.300
3.289
3.278
3.267
592
3.256
590
3.245
588
–75 –50 –25 0 25 50 75 100 125 150 175
TEMPERATURE (°C)
3.234
–75 –50 –25 0 25 50 75 100 125 150 175
TEMPERATURE (°C)
3055 G06
Quiescent Current
5.00
IL = 10mA
3055 G05
QUIESCENT CURRENT (µA)
OUTPUT VOLTAGE (V)
250
0
–75 –50 –25 0 25 50 75 100 125 150 175
TEMPERATURE (°C)
50 100 150 200 250 300 350 400 450 500
OUTPUT CURRENT (mA)
IL = 1mA
610
ADJ PIN VOLTAGE (mV)
QUIESCENT CURRENT (µA)
612
Output Voltage = 5V
5.02
IL = 50mA
50
3055 G04
5.04
IL = 100mA
300
ADJ Pin Voltage
5.06
IL = 500mA
400
350
3055 G02
Quiescent Current
130
120
110
100
VIN = VSHDN = 12V
90
VOUT = 5V
IL = 10µA
80
70
60
50
40
30
20
VIN = 12V
10
ALL OTHER PINS = 0V
0
–75 –50 –25 0 25 50 75 100 125 150 175
TEMPERATURE (°C)
5.08
450
100
3055 G01
5.10
Dropout Voltage
600
= TEST POINTS
130
120
110
100
90
80
70
60
50
40
30
20
10
0
12
GND Pin Current, VOUT = 3.3V
11
RL = 6.6Ω, IL = 500mA
10
GND PIN CURRENT (mA)
400
DROPOUT VOLTAGE (mV)
DROPOUT VOLTAGE (mV)
500
700
650
600
550
500
450
400
350
300
250
200
150
100
50
0
DROPOUT VOLTAGE (mV)
Typical Dropout Voltage
TJ = 25°C, unless otherwise noted.
TJ = 25°C, VOUT = 5V, IL = 10µA
9
8
7
6
5
RL = 13.2Ω, IL = 250mA
4
3
RL = 33Ω, IL = 100mA
2
1
VSHDN = 0V, RL = 0Ω
0
5
10
15
20 25
VIN (V)
30
35
40
45
3055 G08
0
RL = 330Ω, IL = 10mA
0
1
2
3
4
5 6 7
VIN (V)
8
9 10 11 12
3055 G09
3055f
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5
LT3055
TYPICAL PERFORMANCE CHARACTERISTICS
GND Pin Current, VOUT = 5V
GND Pin Current vs ILOAD
20
RL = 10Ω, IL = 500mA
11
GND PIN CURRENT (mA)
GND PIN CURRENT (mA)
9
8
7
6
5
RL = 20Ω, IL = 250mA
4
3
16
14
12
10
8
6
2
RL = 50Ω, IL = 100mA
4
1
RL = 500Ω, IL = 10mA
2
0
0
1
2
3
4
5 6 7
VIN (V)
8
VIN = 5.6V
VOUT = 5V
18
10
0
9 10 11 12
SHDN Pin Threshold
SHDN PIN THRESHOLD (V)
12
0
50 100 150 200 250 300 350 400 450 500
ILOAD (mA)
3055 G10
3055 G12
SHDN Pin Input Current
ADJ Pin Bias Current
50
3.0
2.5
2.0
1.5
1.0
0.5
45
2.5
ADJ PIN BIAS CURRENT (nA)
SHDN = 45V
SHDN PIN INPUT CURRENT (µA)
SHDN PIN INPUT CURRENT (µA)
1.5
1.4
OFF TO ON
1.3
ON TO OFF
1.2
1.1
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
–75 –50 –25 0 25 50 75 100 125 150 175
TEMPERATURE (°C)
3055 G11
SHDN Pin Input Current
3.0
TJ = 25°C, unless otherwise noted.
2.0
1.5
1.0
0.5
40
35
30
25
20
15
10
5
0
–75 –50 –25 0 25 50 75 100 125 150 175
TEMPERATURE (°C)
0
0
5
10 15 20 25 30 35
SHDN PIN VOLTAGE (V)
3055 G13
0
–75 –50 –25 0 25 50 75 100 125 150 175
TEMPERATURE (°C)
45
3055 G15
3055 G14
Internal Current Limit
3055 G16
1.0
Reverse Output Current
TJ = –55°C
TJ = –40°C
TJ = 25°C
TJ = 125°C
TJ = 150°C
0.9
0.8
CURRENT LIMIT (A)
1.5
1.4 VIN = 6V
1.3 VOUT = 0V
1.2
1.1
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
–75 –50 –25 0 25 50 75 100 125 150 175
TEMPERATURE (°C)
0.7
0.6
0.5
0.4
0.3
1.0
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.2
0.1
0.1
0
0
5
10
15 20 25 30 35
INPUT VOLTAGE (V)
40
45
3055 G17
VIN = 0
0.9
OUTPUT CURRENT (µA)
Internal Current Limit
CURRENT LIMIT (A)
40
0
0
5
10
15
20 25
VOUT (V)
30
35
40
3055 G18
3055f
6
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LT3055
TYPICAL PERFORMANCE CHARACTERISTICS
Input Ripple Rejection
90
VOUT = VADJ = 1.2V
VIN = 0V
RIPPLE REJECTION (dB)
OUTPUT CURRENT (µA)
80
70
60
50
40
30
IADJ
20
CREF/BYP = 0pF
CREF/BYP = 100pF
CREF/BYP = 10nF
80
60
50
40
30
ILOAD = 500mA
COUT = 10µF
VOUT = 3.3V
VIN = 4.3V + 50mVRMS RIPPLE
20
10
IOUT
10
70
0
0
–75 –50 –25 0 25 50 75 100 125 150 175
TEMPERATURE (°C)
10
1M
80
2.0
60
50
40
ILOAD = 500mA
CREF/BYP = 10nF
VOUT = 3.3V
VIN = 4.3V + 50mVRMS RIPPLE
f = 120Hz
1.8
1.6
2
ILOAD = 500mA
1.4
1.2
0.01
10
100
1k
10k
FREQUENCY (Hz)
100k
3055 G25
1M
10M
1.0
0.8
0.6
0.4
1
0
–1
–2
–3
–4
–75 –50 –25 0 25 50 75 100 125 150 175
TEMPERATURE (°C)
3055 G24
3055 G23
Output Noise Spectral Density
vs CREF/BYP, CFF = 0
VOUT = 5V
VOUT = 3.3V
VOUT = 2.5V
VOUT = 1.2V
VOUT = 0.6V
1k
10k 100k
FREQUENCY (Hz)
Load Regulation
0
–75 –50 –25 0 25 50 75 100 125 150 175
TEMPERATURE (°C)
OUTPUT NOISE SPECTRAL DENSITY (µV/√Hz)
OUTPUT NOISE SPECTRAL DENSITY (µV/√Hz)
0.1
100
∆IL = 1mA TO 500mA
3 VOUT = 0.6V
VIN = 2.2V
Output Noise Spectral Density
CREF/BYP = 0, CFF = 0
1
10
4
3055 G22
COUT = 10µF
IL = 500mA
ILOAD = 500mA
CREF/BYP = 10nF
VOUT = 3.3V
VIN = 4.3V + 50mVRMS RIPPLE
20
3055 G21
0.2
0
–75 –50 –25 0 25 50 75 100 125 150 175
TEMPERATURE (°C)
10
40
30
0
10M
LOAD REGULATION (nV)
70
10
50
Minimum Input Voltage
2.2
MINIMUM INPUT VOLTAGE (V)
RIPPLE REJECTION (dB)
Input Ripple Rejection
90
20
60
3055 G20
3055 G19
30
70
10
1k
10k 100k
FREQUENCY (Hz)
100
COUT = 10µF
COUT = 3.3µF
80
10
VOUT = 5V
Output Noise Spectral Density
vs CFF, CREF/BYP = 10nF
COUT = 10µF
IL = 500mA
1
VOUT = 0.6V
0.1
0.01
CREF/BYP = 100pF
CREF/BYP = 1nF
CREF/BYP = 10nF
10
100
1k
10k
FREQUENCY (Hz)
100k
3055 G26
OUTPUT NOISE SPECTRAL DENSITY (µV/√Hz)
90
Input Ripple Rejection
90
RIPPLE REJECTION (dB)
Reverse Output Current
100
TJ = 25°C, unless otherwise noted.
10
VOUT = 5V
COUT = 10µF
IL = 500mA
1
0.1
0.01
CFF = 0pF
CFF = 100pF
CFF = 1nF
CFF = 10nF
10
100
1k
10k
FREQUENCY (Hz)
100k
3055 G27
3055f
For more information www.linear.com/LT3055
7
LT3055
TYPICAL PERFORMANCE CHARACTERISTICS
CREF/BYP = 0pF
80
70
CREF/BYP = 100pF
60
50
40
CREF/BYP = 1nF
30
20
CREF/BYP = 10nF
10
0
0.01
0.1
1
10
100
LOAD CURRENT (mA)
1000
160
150 f = 10Hz TO 100kHz
VOUT = 5V
140 COUT = 10µF
130
120
VOUT = 3.3V
110
100
90
80
VOUT = 2.5V
70
60
50
40
VOUT = 1.2V
30
20
VOUT = 0.6V
10
0
0.01
0.1
1
10
100
1000
LOAD CURRENT (mA)
RMS Output Noise
vs Feedforward Capacitor (CFF)
120
110
OUTPUT NOISE VOLTAGE (µVRMS)
110
f = 10Hz TO 100kHz
100 C
OUT = 10µF
90
RMS Output Noise vs Load
Current, CREF/BYP = 10nF, CFF = 0
OUTPUT NOISE VOLTAGE (µVRMS)
OUTPUT NOISE VOLTAGE (µVRMS)
RMS Output Noise vs CREF/BYP,
VOUT = 0.6V, CFF = 0
TJ = 25°C, unless otherwise noted.
VOUT = 5V
100
VOUT = 3.3V
90
80
f = 10Hz TO 100kHz
CREF/BYP = 10nF
COUT = 10µF
IFB-DIVIDER = 10µA
ILOAD = 500mA
VOUT = 2.5V
70
60
50
40
30 VOUT = 1.2V
20
10
VOUT = 0.6V
0
0.01
0.1
1
FEEDFORWARD CAPACITOR, CFF (F)
3055 G30
3055 G29
3055 G28
Start-Up Time
vs REF/BYP Capacitor
10
10Hz to 100kHz Output Noise
CREF/BYP = 10nF, CFF = 0
10Hz to 100kHz Output Noise
CREF/BYP = 10nF, CFF = 10nF
60
START-UP TIME (ms)
50
40
VOUT
100µV/DIV
VOUT
100µV/DIV
30
20
10
0
COUT = 10µF
ILOAD = 500mA
VOUT = 5V
0
1ms/DIV
3055 G32
COUT = 10µF
ILOAD = 500mA
VOUT = 5V
1ms/DIV
3055 G33
10 20 30 40 50 60 70 80 90 100
REF/BYP CAPACITOR (nF)
3055 G31
5V Transient Response
CFF = 0, IOUT = 50mA to 500mA
5V Transient Response
CFF = 10nF, IOUT = 10mA to 500mA
VOUT
200mV/DIV
VOUT
100mV/DIV
IOUT
500mA/DIV
IOUT
500mA/DIV
VIN = 6V
100µs/DIV
COUT = CIN = 10µF
IFB-DIVIDER = 10µA
VOUT = 5V
3055 G34
Transient Response (Load Dump)
VOUT
20mV/DIV
VIN
10V/DIV
VIN = 6V
20µs/DIV
COUT = CIN = 10µF
IFB-DIVIDER = 10µA
VOUT = 5V
3055 G35
VOUT = 5V
IOUT = 100mA
COUT = 10µF
1ms/DIV
3055 G36
3055f
8
For more information www.linear.com/LT3055
LT3055
TYPICAL PERFORMANCE CHARACTERISTICS
SHDN Transient Response
CREF/BYP = 0
TJ = 25°C, unless otherwise noted.
SHDN Transient Response
CREF/BYP = 10nF
Precision Current Limit,
RIMAX = 1.5k
OUT
5V/DIV
IL=500mA
OUT
5V/DIV
IL = 500mA
REF/BYP
500mV/DIV
REF/BYP
500mV/DIV
SHDN
2V/DIV
SHDN
2V/DIV
2ms/DIV
2ms/DIV
3055 G37
3055 G38
CURRENT LIMIT FAULT THRESHOLD (mA)
220
VOUT(NOMINAL) = 5V
216
212
208
204
VIN = 10V
200
VIN = 5.6V
196
192
188
184
180
–75 –50 –25 0 25 50 75 100 125 150 175
TEMPERATURE (°C)
3055 G39
Precision Current Limit,
RIMAX = 604Ω
IOUT/IMON Ratio, IOUT = 500mA
550
530
520
VIN = 7V
500
490
VIN = 5.6V
480
470
460
530
520
510
500
490
TJ = 150°C
TJ = 125°C
TJ = 25°C
TJ = –40°C
TJ = –55°C
480
470
460
450
450
–75 –50 –25 0 25 50 75 100 125 150 175
TEMPERATURE (°C)
VOUT = 5V
VIN = 5.6V
540
0
1
3
2
VIMON (V)
IOUT/IMON Current Ratio
510
500
490
TJ = 150°C
TJ = 125°C
TJ = 25°C
TJ = –40°C
TJ = –55°C
0
50 100 150 200 250 300 350 400 450 500
IOUT (mA)
3055 G43
IOUT/IMON CURRENT RATIO (mA/mA)
IOUT/IMON CURRENT RATIO (mA/mA)
520
450
510
500
490
TJ = 150°C
TJ = 125°C
TJ = 25°C
TJ = –40°C
TJ = –55°C
480
470
460
0
1
3
2
VIMON (V)
4
VOUT = 5V
540 VIMON = 3.5V
I
= 10mA at VIN = 15V
530 OUT
IOUT = 250mA at VIN = 9V
520 IOUT = 500mA at VIN = 7V
510
500
490
TJ = 150°C
TJ = 125°C
TJ = 25°C
TJ = –40°C
TJ = –55°C
480
470
460
450
0
5
3055 G41
Minimum Output Current
Threshold, RIMIN = 1.2M
550
VOUT = 5V
540 VIN = 5.6V
VIMON = 3.5V
530
460
520
IOUT/IMON Current Ratio
550
470
530
450
5
VOUT = 5V
VIN = 7V
540
3055 G41
3055 G40
480
4
50 100 150 200 250 300 350 400 450 500
IOUT (mA)
3055 G44
MINIMUM OUTPUT CURRENT THRESHOLD (mA)
510
IOUT/IMON Ratio, IOUT = 500mA
550
IOUT/IMON CURRENT RATIO (mA/mA)
VOUT(NOMINAL) = 5V
540
IOUT/IMON CURRENT RATIO (mA/mA)
CURRENT LIMIT FAULT THRESHOLD (mA)
550
1.10
1.08
1.06
1.04
1.02
IMIN RISING THRESHOLD
1.00
0.98
IMIN FALLING THRESHOLD
0.96
0.94
0.92
0.90
–75 –50 –25 0 25 50 75 100 125 150 175
TEMPERATURE (°C)
3055 G45
3055f
For more information www.linear.com/LT3055
9
LT3055
TYPICAL PERFORMANCE CHARACTERISTICS
TJ = 25°C, unless otherwise noted.
TEMP Output Voltage
vs Temperature
11.0
1.75
10.8
1.50
10.6
1.25
TEMP PIN VOLTAGE (V)
MINIMUM OUTPUT CURRENT THRESHOLD (mA)
Minimum Output Current
Threshold RIMIN = 120k
10.4
10.2
IMIN RISING THRESHOLD
10.0
9.8
IMIN FALLING THRESHOLD
9.6
1.00
0.75
0.50
0.25
0
9.4
–0.25
9.2
–0.50
9.0
–75 –50 –25 0 25 50 75 100 125 150 175
TEMPERATURE (°C)
–0.75
–75 –50 –25 0 25 50 75 100 125 150 175
TEMPERATURE (°C)
3055 G46
3055 G47
PWRGD Threshold Voltage
590
580
570
ADJ PIN VOLTAGE (mV)
TEMP PIN ERROR (°C)
TEMP Pin Error
7
6
5
4
3
2
1
0
–1
–2
–3
–4
–5
–6
–7
560
550
540
530
ADJ PIN RISING THRESHOLD
ADJ PIN FALLING THRESHOLD
520
510
500
0
25
100
75
50
TEMPERATURE (°C)
125
150
490
–75 –50 –25 0 25 50 75 100 125 150 175
TEMPERATURE (°C)
3055 G48
3055 G49
3055f
10
For more information www.linear.com/LT3055
LT3055
PIN FUNCTIONS
IN (Pins 1, 2): Input. These pins supply power to the
device. The LT3055 requires a local IN bypass capacitor
if it is located more than six inches from the main input
filter capacitor. In general, battery output impedance rises
with frequency, so adding a bypass capacitor in batterypowered circuits is advisable. A bypass capacitor in the
range of 1µF to 10µF is sufficient. See Input Capacitance
and Stability in the Applications Information section for
more information.
The LT3055 regulator withstands reverse voltages on the
IN pins with respect to ground and the OUT pins. In the
case of a reverse input, which can happen if a battery is
plugged in backwards, the device acts as if there is a diode
in series with its input. No reverse current flows into the
regulator and no reverse voltage appears at the load.The
device protects both itself and the load.
SHDN (Pin 3): Shutdown. Pulling the SHDN pin low puts
the LT3055 into a low power state and turns the output off.
Drive the SHDN pin with either logic or an open-collector/
drain with a pull-up resistor. The resistor supplies the
pull-up current to the open-collector/drain logic, normally
several microamperes, and the SHDN pin current, typically
less than 2μA. If unused, connect the SHDN pin to IN. The
LT3055 does not function if the SHDN pin is not connected.
FAULT1 (Pin 4), FAULT2 (Pin 5): Fault Indicator Pins.
FAULT1 and FAULT2 are open-collector logic pins. If the
output current drops below the minimum current threshold, FAULT1 asserts low. If the output current exceeds the
current limit threshold, FAULT2 asserts low. If the LT3055
enters thermal shutdown, both FAULT1 and FAULT2 assert
low. The FAULT1 and FAULT2 pins are capable of sinking
50μA. There is no internal pull-up resistor; an external
pull-up resistor must be used.
PWRGD (Pin 6): Power Good Pin. The PWRGD pin is an
open-collector output that actively pulls low if the output
is less than 90% of the nominal output value. The PWRGD
pin is capable of sinking 50μA. There is no internal pull-up
resistor, an external pull-up resistor must be used.
TEMP (Pin 7): Temperature Output. The TEMP pin outputs
a voltage proportional to the average junction temperature.
The pin voltage is 250mV for 25°C and has a slope of
10mV/°C.The TEMP pin output impedance is approximately
1500Ω. The TEMP pin is stable with no bypass capacitor
or with a bypass capacitor with a value between 100pF
and 1nF. A 100pF capacitor is recommended to improve
TEMP pin power supply rejection.
IMON (Pin 8): Output Current Monitor. This pin is the collector of a PNP current mirror that outputs 1/500th of the
power PNP current. The IMON pin requires a small (22nF
minimum) decoupling capacitor. In applications where the
IMON pin is used in an external feedback network (current
sharing, cable drop compensation, etc.) smaller bypass
capacitance values may be used to ensure stability of the
external feedback network. If not used, tie IMON to GND.
IMIN (Pin 9): Minimum Output Current Programming
Pin. This pin is the collector of a PNP current mirror that
outputs 1/2000th of the power PNP load current. This pin
is also the input to the minimum output current fault comparator. Connecting a resistor between IMIN and GND sets
the minimum output current fault threshold. For detailed
information on how to set the IMIN pin resistor value, please
see the Operation section. A small external decoupling
capacitor (10nF minimum) is required to improve IMIN
PSRR. If minimum output current programming is not
required, float the IMIN pin (unconnected).
IMAX (Pin 10): Precision Current Limit Programming Pin.
This pin is the collector of a current mirror PNP that is
1/500th the size of the output power PNP. This pin is also the
input to the current limit amplifier. Current limit threshold
is set by connecting a resistor between the IMAX pin and
GND. For detailed information on how to set the IMAX pin
resistor value, please see the Operation section. The IMAX
pin requires a 22nF decoupling capacitor to ground. If not
used, tie IMAX to GND.
3055f
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11
LT3055
PIN FUNCTIONS
REF/BYP (Pin 11): Bypass/Soft-Start. Connecting a capacitor from this pin to GND bypasses the LT3055’s reference
noise and soft starts the reference. A 10nF bypass capacitor typically reduces output voltage noise to 25μVRMS in
a 10Hz to 100kHz bandwidth. Soft-start time is directly
proportional to BYP/SS capacitor value. If the LT3055 is
placed in shutdown, BYP/SS is actively pulled low by an
internal device to reset soft-start. If low noise or soft-start
performance is not required, this pin must be left floating
(unconnected). Do not drive this pin with any active circuitry. Because the REF/BYP pin is the reference input to
the error amplifier, stray capacitance at this point should
be minimized. Special attention should be given to any
stray capacitances that can couple external signals onto
the REF/BYP pin producing undesirable output transients
or ripple. A minimum REF/BYP capacitance of 100pF is
recommended.
ADJ (Pin 14): Adjust. This pin is the error amplifier’s inverting terminal. The typical bias current of 15nA flows out
of the pin (see the ADJ pin Bias Current vs Temperature
curve in the Typical Performance Characteristics section).
The ADJ pin voltage is 600mV referenced to GND.
Connecting a capacitor from ADJ to OUT reduces output
noise and improves transient response for output voltages
greater than 600mV. See the Applications information section for calculating the value of the feedforward capacitor.
OUT (Pins 15,16): Output. These pins supply power to
the load. Stability requirements demand a minimum 3.3μF
ceramic output capacitor with an ESR < 1Ω to prevent
oscillations. For output voltages less than 1.2V, a minimum 4.7µF ceramic output capacitor is required. Large
load transient applications require larger output capacitors to limit peak voltage transients. See the Applications
Information section for details on output capacitance and
reverse output characteristics. Permissible output voltage
range is 600mV to 40V.
GND (Pin 12, Pin 13, Exposed Pad Pin 17): Ground.
The exposed pad of the DFN and MSOP packages is an
electrical connection to GND. To ensure proper electrical
and thermal performance, solder Pin 17 to the PCB ground
and tie it directly to Pins 12, 13. Connect the bottom of
the output voltage setting resistor divider directly to GND
(Pin 12) for optimum load regulation.
IN
OUT
RP
LT3055
+
VIN
+
SHDN
+
SENSE
LOAD
GND
RP
3055 F01
Figure 1. Kelvin Sense Connection
3055f
12
For more information www.linear.com/LT3055
LT3055
BLOCK DIAGRAM
IN
R1
ADJ
30k
R4
Q3
ERROR
AMPLIFIER
D2
CURRENT
LIMIT
AMPLIFIER
QPOWER
1
OUT
100k
R3
+
–
IDEAL
DIODE
D3
SHDN
QIMAX
1/500
THERMAL/
CURRENT LIMITS
–
+
Q2
QIMON
1/500
QIMIN
1/2000
D1
IMAX
IMON
IMIN
COMPARATOR
+
–
100k
R2
+
–
600mV
REFERENCE
IMIN
FAULT1
IMIN
QFAULT1
U1
THERMAL LIMIT
FAULT2
CURRENT LIMITS
QFAULT2
U2
THERMAL LIMIT
–
+
+
–
REF/BYP
PWRGD
QPWRGD
540mV
REFERENCE
GND
3055 F02
Figure 2
3055f
For more information www.linear.com/LT3055
13
LT3055
OPERATION
IMON Pin Operation (Current Monitor)
The IMON pin is the collector of a PNP which mirrors the
LT3055 output PNP at a ratio of 1:500 (see Block Diagram).
There is additional circuitry which compensates for early
voltage variation by regulating the collector of the IMON
mirror PNP at the output voltage. This circuitry is active
for VIMON ≤ (VOUT – 500mV). For the range where the
early voltage compensation circuit is active, calculate the
output current from the simple equation:
IOUT = 500 •
VIMON
RIMON
For VIMON > (VOUT-500mV), the IMON mirror PNP collector is VIMON + VDSSAT (500mV at 500mA). Early voltage
effects increase the IOUT to IMON ratio as VIMON increases.
IOUT:IIMON RATIO (mA/mA)
520
515
EARLY VOLTAGE
EFFECTS
505
500
495
The IMIN pin is the collector of a PNP which mirrors
the LT3055 output PNP at a ratio of 1:2000 (see Block
Diagram). The IMIN fault comparator asserts the FAULT1
pin if the IMIN pin voltage is below 0.6V. This low output
current fault threshold voltage (IOPEN) is set by attaching
a resistor from IMIN to GND:
RIMIN = 2000 •
0.6
IOPEN
IMAX Pin Operation
490
485
VIN = 6V
VIMON = 2.5V
IOUT = 500mA (IN CURRENT LIMIT)
480
475
1
0
3
2
VOUT (V)
5
4
3055 F03a
Figure 3a. IOUT:IIMON Ratio vs VOUT
525
VIN = 6V
VOUT = 5V
IOUT = 500mA
520
IOUT:IIMON RATIO (mA/mA)
Open-Circuit Detection (IMIN Pin)
If the open-circuit detection function is not needed, the
IMIN pin must be left floating (unconnected). A small decoupling capacitor (10nF minimum) from IMIN to GND is
required to improve IMIN pin power supply rejection and to
prevent FAULT1 pin glitches. See the Typical Performance
Characteristics section for additional information.
525
510
In addition, if VIN – VIMON < 1V, the IMON mirror PNP
saturates at high loads, causing the IOUT-to-IMON ratio
to increase quickly. The IMON mirror ratio is affected by
power dissipation in the LT3055; it increases at a rate of
approximately 0.5 percent per watt.
515
IMON MIRROR
PNP SATURATING
510
505
RIMAX = 500 •
500
EARLY VOLTAGE
EFFECTS
495
490
485
480
475
The IMAX pin is the collector of a PNP which mirrors the
LT3055 output PNP at a ratio of 1:500 (see Block Diagram).
The IMAX pin is also the input to the precision current limit
amplifier. If the output load increases to the point where it
causes the IMAX pin voltage to reach 0.6V, the current limit
amplifier takes control of the output regulation so that the
IMAX pin regulates at 0.6V, regardless of the output voltage.
The current limit threshold (ILIMIT) is set by connecting a
resistor (RIMAX) from IMAX to GND:
0
1
2
3
VIMON (V)
4
5
6
3055 F03b
Figure 3b. IOUT:IIMON Ratio vs VIMON
0.6V
ILIMIT
In cases where the IN to OUT differential voltage exceeds
10V, fold-back current limit lowers the internal current
limit level, possibly causing it to override the external
programmable current limit. See the Internal Current Limit
vs VIN-VOUT graph in the Typical Performance Characteristics section.
3055f
14
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LT3055
OPERATION
The IMAX pin requires a 22nF decoupling capacitor. If the
external programmable current limit is not needed, the
IMAX pin must be connected to GND. The IMAX threshold
is affected by power dissipation in the LT3055; it increases
at a rate of approximately 0.5 percent per watt.
FAULT Pins Operation
The FAULT1 and FAULT2 pins are open-drain high voltage
NMOS digital outputs. The FAULT1 pin asserts during a low
current fault (open circuit). The FAULT2 pin asserts during
a current limit fault (internal or externally programmed).
Both FAULT1 and FAULT2 assert during thermal shutdown.
There is no internal pull-up on the FAULT pins; an external
pull-up resistor is required. The FAULT pins sink up to
50μA of pull-down current. Off state logic may be as high
as 45V, regardless of the input voltage used.
Table 1. FAULT Pins Truth Table
STATUS
FAULT1
FAULT2
Open Circuit
Low
High
Current Limit
High
Low
Thermal Shutdown
Low
Low
Depending on the IMIN capacitance, BYP capacitance,
and OUT capacitance, the FAULT pins may assert during
start-up. Consideration should be given to masking the
fault signals during start-up. The FAULT pin circuitry is
inactive (not asserted) during shutdown and when the
OUT pin is pulled above IN pin.
PWRGD Pin Operation
The PWRGD pin is an open-drain high voltage NMOS
digital output. The PWRGD pin deasserts and becomes
high impedance if the output rises above 90% of its
nominal value. If the output falls below 89% of its nominal
value for more than 25μs, the PWRGD pin asserts low.
The PWRGD comparator has 1% hysteresis and 25μs
of deglitching. The PWRGD comparator has a dedicated
reference that does not soft-start when a capacitor is
added to the REF/BYP pin.
Operation in Dropout
There may be some degradation of the current mirror accuracy for output currents less than 50mA when operating
in dropout.
APPLICATIONS INFORMATION
The LT3055 is a micropower, low noise and low dropout voltage, 500mA linear regulator with micropower shutdown,
programmable current limit, and diagnostic functions. The
device supplies up to 500mA at a typical dropout voltage
of 350mV and operates over a 2.2V to 45V input range.
A single external capacitor provides low noise reference
performance and output soft-start functionality. For example, connecting a 10nF capacitor from the REF/BYP
pin to GND lowers output noise to 25μVRMS over a 10Hz
to 100kHz bandwidth. This capacitor also soft starts the
reference and prevents output voltage overshoot at turn-on.
The LT3055’s quiescent current is merely 65μA but provides
fast transient response with a minimum low ESR 3.3μF
ceramic output capacitor. In shutdown, quiescent current is
less than 1μA and the reference soft-start capacitor is reset.
The LT3055 optimizes stability and transient response
with low ESR, ceramic output capacitors. The regulator
does not require the addition of ESR as is common with
other regulators. The LT3055 typically provides 0.1% line
regulation and 0.1% load regulation. Internal protection
circuitry includes reverse battery protection, reverse output
protection, reverse current protection, current limit with
fold-back and thermal shutdown.
This “bullet-proof” protection set makes it ideal for use
in battery-powered, automotive and industrial systems.
In battery backup applications where the output is held
up by a backup battery and the input is pulled to ground,
the LT3055 acts like it has a diode in series with its output
and prevents reverse current flow.
3055f
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15
LT3055
APPLICATIONS INFORMATION
Adjustable Operation
+
The adjustable LT3055 has an output voltage range of
0.6V to 40V. The output voltage is set by the ratio of
two external resistors, as shown in Figure 4. The device
servos the output to maintain the ADJ pin voltage at 0.6V
referenced to ground. The current in R1 is then equal to
0.6V/R1, and the current in R2 is the current in R1 minus
the ADJ pin bias current.
The ADJ pin bias current, 16nA at 25°C, flows from the
ADJ pin through R1 to GND. Calculate the output voltage
using the formula in Figure 4. The value of R1 should be
no greater than 62k to provide a minimum 10μA load current so that output voltage errors, caused by the ADJ pin
bias current, are minimized. Note that in shutdown, the
output is turned off and the divider current is zero. Curves
of ADJ Pin Voltage vs Temperature and ADJ Pin Bias Current vs Temperature appear in the Typical Performance
Characteristics section.
The LT3055 is tested and specified with the ADJ pin tied
to the OUT pin, yielding VOUT = 0.6V. Specifications for
output voltages greater than 0.6V are proportional to the
ratio of the desired output voltage to 0.6V: VOUT/0.6V. For
example, load regulation for an output current change of
1mA to 500mA is 0.5mV (typical) at VOUT = 0.6V. At VOUT
= 12V, load regulation is:
12V
• ( 0.5mV) = 10mV
0.6V
Table 2 shows 1% resistor divider values for some common
output voltages with a resistor divider current of 10μA.
Table 2. Output Voltage Resistor Divider Values
VOUT (V)
R1 (kΩ)
R2 (kΩ)
1.2
60.4
60.4
1.5
59
88.7
1.8
59
118
2.5
60.4
191
3
59
237
3.3
61.9
280
5
59
432
IN
VIN
VOUT
OUT
LT3055
SHDN
R2
ADJ
GND
R1
3055 F04
 R2 
VOUT = 0.6V  1+  – (IADJ •R2) TT
 R1
VADJ = 0.6V
IADJ = 16nA AT 25°C
OUTPUT RANGE = 0.6V TO 40V
Figure 4. Adjustable Operation
Bypass Capacitance and Output Voltage Noise
The LT3055 regulator provides low output voltage
noise over a 10Hz to 100kHz bandwidth while operating at full load with the addition of a bypass capacitor
(CREF/BYP) from the REF/BYP pin to GND. A high quality
low leakage capacitor is recommended. This capacitor
bypasses the internal reference of the regulator, providing a low frequency noise pole for the internal reference.
With the use of 10nF for CREF/BYP, output voltage noise
decreases to as low as 25μVRMS when the output voltage
is set for 0.6V. For higher output voltages (generated by
using a feedback resistor divider), the output voltage noise
gains up proportionately when using CREF/BYP.
To lower the higher output voltage noise, include a feedforward capacitor (CFF) from VOUT to the ADJ pin. A high
quality, low leakage capacitor is recommended. This
capacitor bypasses the error amplifier of the regulator,
providing an additional low frequency noise pole. With
the use of 10nF for both CFF and CREF/BYP, output voltage
noise decreases to 25μVRMS when the output voltage is
set to 5V by a 10μA feedback resistor divider. If the current in the feedback resistor divider is doubled, CFF must
also be doubled to achieve equivalent noise performance.
Higher values of output voltage noise can occur if care
is not exercised with regard to circuit layout and testing.
Crosstalk from nearby traces induces unwanted noise
onto the LT3055’s output. Power supply ripple rejection
must also be considered. The LT3055 regulator does not
have unlimited power supply rejection and passes a small
portion of the input noise through to the output.
3055f
16
For more information www.linear.com/LT3055
LT3055
APPLICATIONS INFORMATION
Using a feedforward capacitor (CFF) from VOUT to the
ADJ pin has the added benefit of improving transient
response for output voltages greater than 0.6V. With no
feedforward capacitor, the settling time increases as the
output voltage increases above 0.6V. Use the equation in
Figure 5 to determine the minimum value of CFF to achieve
a transient response that is similar to the 0.6V output
voltage performance regardless of the chosen output voltage (See Figure 6 and Transient Response in the Typical
Performance Characteristics section).
Start-up time is also affected by the presence of a feedforward capacitor. Start-up time is directly proportional to
the size of the feedforward capacitor and the output voltage, and is inversely proportional to the feedback resistor
divider current, slowing to 15ms with a 10nF feedforward
capacitor and a 10μF output capacitor for an output voltage
set to 5V by a 10μA feedback resistor divider.
Output Capacitance and Transient Response
The LT3055 regulator is stable with a wide range of output
capacitors. The ESR of the output capacitor affects stability,
most notably with small capacitors. Use a minimum output
capacitor of 3.3μF with an ESR of 1Ω or less to prevent
oscillations. If a feedforward capacitor is used with output
voltages set for greater than 24V, use a minimum output
capacitor of 10μF. The LT3055 is a micropower device and
output load transient response is a function of output capacitance. Larger values of output capacitance decrease the
peak deviations and provide improved transient response
for larger load current changes. Bypass capacitors, used to
decouple individual components powered by the LT3055,
increase the effective output capacitor value. For applications with large load current transients, a low ESR ceramic
capacitor in parallel with a bulk tantalum capacitor often
provides an optimally damped response.
VIN
IN
OUT
LT3055
SHDN
ADJ
GND REF/BYP
R2
CFF
VOUT
COUT
R1
CREF/BYP
3055 F05
CFF ≥
10nF
• IFB _ DIVIDER
10µA
(
IFB _ DIVIDER =
)
VOUT
R1+R2
FEEDFORWARD
CAPACITOR, CFF
Figure 5. Feedforward Capacitor for Fast Transient Response
0
VOUT
50mV/DIV
During start-up, the internal reference soft-starts when
a bypass capacitor is present. Regulator start-up time is
directly proportional to the size of the bypass capacitor
(See Start-Up Time vs REF/BYP Capacitor in the Typical
Performance Characteristics section). The reference bypass capacitor is actively pulled low during shutdown to
reset the internal reference.
+
100pF
1nF
10nF
LOAD CURRENT
500mA/DIV
50µs/DIV
VOUT = 5V
COUT = 10µF
IFB-DIVIDER = 10µA
3055 F06
Figure 6. Transient Response vs Feedforward Capacitor
Give extra consideration to the use of ceramic capacitors.
Manufacturers make ceramic capacitors with a variety of
dielectrics, each with different behavior across temperature and applied voltage. The most common dielectrics
are specified with EIA temperature characteristic codes
of Z5U, Y5V, X5R and X7R. The Z5U and Y5V dielectrics
provide high C-V products in a small package at low cost,
but exhibit strong voltage and temperature coefficients, as
shown in Figures 7 and 8. When used with a 5V regulator,
a 16V 10μF Y5V capacitor can exhibit an effective value
as low as 1μF to 2μF for the DC bias voltage applied, and
over the operating temperature range. The X5R and X7R
dielectrics yield much more stable characteristics and are
more suitable for use as the output capacitor.
The X7R type works over a wider temperature range and
has better temperature stability, while the X5R is less
expensive and is available in higher values. Care still must
be exercised when using X5R and X7R capacitors; the X5R
and X7R codes only specify operating temperature range
3055f
For more information www.linear.com/LT3055
17
LT3055
APPLICATIONS INFORMATION
20
BOTH CAPACITORS ARE 16V,
1210 CASE SIZE, 10µF
CHANGE IN VALUE (%)
0
X5R
–20
VOUT
1mV/DIV
–40
–60
Y5V
–80
–100
0
2
4
14
8
6
10 12
DC BIAS VOLTAGE (V)
16
3055 F07
VOUT = 5V
COUT = 10µF
CREF/BYP = 10nF
10ms/DIV
3055 F09
Figure 9. Noise Resulting from Tapping On a Ceramic Capacitor
Figure 7. Ceramic Capacitor DC Bias Characteristics
Figure 9 in response to light tapping from a pencil. Similar
vibration induced behavior can masquerade as increased
output voltage noise.
40
CHANGE IN VALUE (%)
20
X5R
0
Stability and Input Capacitance
–20
–40
Y5V
–60
–80
BOTH CAPACITORS ARE 16V,
1210 CASE SIZE, 10µF
–100
–50 –25
50
25
75
0
TEMPERATURE (°C)
100
125
3055 F08
Figure 8. Ceramic Capacitor Temperature Characteristics
and maximum capacitance change over temperature.
Capacitance change due to DC bias with X5R and X7R
capacitors is better than Y5V and Z5U capacitors, but can
still be significant enough to drop capacitor values below
appropriate levels. Capacitor DC bias characteristics tend
to improve as component case size increases, but expected
capacitance at operating voltage should be verified.
Voltage and temperature coefficients are not the only
sources of problems. Some ceramic capacitors have a
piezoelectric response. A piezoelectric device generates
voltage across its terminals due to mechanical stress,
similar to the way a piezoelectric accelerometer or microphone works. For a ceramic capacitor, the stress is induced
by vibrations in the system or thermal transients. The
resulting voltages produced cause appreciable amounts
of noise. A ceramic capacitor produced the trace in
Low ESR, ceramic input bypass capacitors are acceptable
for applications without long input leads. However, applitions connecting a power supply to an LT3055 circuit’s
IN and GND pins with long input wires combined with a
low ESR, ceramic input capacitors are prone to voltage
spikes, reliability concerns and application-specific board
oscillations.
The input wire inductance found in many battery-powered
applications, combined with the low ESR ceramic input
capacitor, forms a high Q LC resonant tank circuit. In
some instances this resonant frequency beats against the
output current dependent LDO bandwidth and interferes
with proper operation. Simple circuit modifications/solutions are then required. This behavior is not indicative of
LT3055 instability, but is a common ceramic input bypass
capacitor application issue.
The self-inductance, or isolated inductance, of a wire is
directly proportional to its length. Wire diameter is not a
major factor on its self-inductance. For example, the selfinductance of a 2-AWG isolated wire (diameter = 0.26") is
about half the self-inductance of a 30-AWG wire (diameter
= 0.01"). One foot of 30-AWG wire has approximately
465nH of self-inductance.
Two methods can reduce wire self-inductance. One method
divides the current flowing towards the LT3055 between
3055f
18
For more information www.linear.com/LT3055
LT3055
APPLICATIONS INFORMATION
two parallel conductors. In this case, the farther apart the
wires are from each other, the more the self-inductance is
reduced; up to a 50% reduction when placed a few inches
apart. Splitting the wires connects two equal inductors in
parallel, but placing them in close proximity creates mutual
inductance adding to the self-inductance. The second and
most effective way to reduce overall inductance is to place
both forward and return current conductors (the input and
GND wires) in very close proximity. Two 30-AWG wires
separated by only 0.02”, used as forward- and returncurrent conductors, reduce the overall self-inductance
to approximately one-fifth that of a single isolated wire.
If a battery, mounted in close proximity, powers the LT3055,
a 10µF input capacitor suffices for stability. However, if a
distant supply powers the LT3055, use a larger value input
capacitor. Use a rough guideline of 1µF (in addition to the
10µF minimum) per 8 inches of wire length. The minimum
input capacitance needed to stabilize the application also
varies with power supply output impedance variations.
Placing additional capacitance on the LT3055’s output also
helps. However, this requires an order of magnitude more
capacitance in comparison with additional LT3055 input
bypassing. Series resistance between the supply and the
LT3055 input also helps stabilize the application; as little
as 0.1Ω to 0.5Ω suffices. This impedance dampens the
REF
+
–
+
–
Higher output current is obtained by paralleling multiple
LT3055 together. Tie the individual OUT pins together
and tie the individual IN pins together. An external NPN
or NMOS current mirror is used in combination with the
LT3055 IMON pins to create a simple amplifier. This amplifier injects current into or out of the feedback divider of
the slave LT3055 in order to ensure that the IMON currents
from each LT3055 are equal.
In Figure 10, this is implemented using inexpensive 2N3904
NPN devices. Precision 1k resistors provide 1V emitter
degeneration at full load to guarantee good current mirror
matching. The feedback resistors of the slave LT3055 are
split into sections to ensure adequate headroom for the
slave 2N3904. A 1nF capacitor added to the IMON pin of
the slave device frequency compensates the feedback loop.
This circuit architecture is scalable to as many LT3055s
as are needed simply by extending the current mirror and
adding slave LT3055 devices.
600mV
500x
1x
IMON
REF
+
–
+
–
600mV
VOUT
5V
1A
OUT
ADJ
440k
500x
10µF
60k
LT3055 (SLAVE)
IN
10µF
Paralleling Devices
LT3055 (MASTER)
IN
VIN
5.6V TO 45V
LC tank circuit at the expense of dropout voltage. A better
alternative is to use higher ESR tantalum or electrolytic capacitors at the LT3055 input in place of ceramic capacitors.
1x
IMON
1nF
OUT
ADJ
300k
140k
60k
2N3904
1k
1k
3055 F10
Figure 10. Parallel Devices
For more information www.linear.com/LT3055
3055f
19
LT3055
APPLICATIONS INFORMATION
Spreading the devices on the PC board also spreads the
heat. Series input resistors can further spread the heat if
the input-to-output differential is high.
Overload Recovery
Like many IC power regulators, the LT3055 has safe operating area protection. The safe area protection decreases
current limit as input-to-output voltage increases, and
keeps the power transistor inside a safe operating region
for all values of input-to-output voltage. The LT3055 provides some output current at all values of input-to-output
voltage up to the device breakdown.
When power is first applied, the input voltage rises and the
output follows the input; allowing the regulator to start-up
into very heavy loads. During start-up, as the input voltage
is rising, the input-to-output voltage differential is small,
allowing the regulator to supply large output currents.
With a high input voltage, a problem can occur wherein
the removal of an output short will not allow the output
to recover. Other regulators, such as the LT1083/LT1084/
LT1085 family and LT1764A also exhibit this phenomenon,
so it is not unique to the LT3055. The problem occurs with
a heavy output load when the input voltage is high and the
output voltage is low. Common situations are immediately
after the removal of a short circuit or if the shutdown pin is
pulled high after the input voltage is already turned on. The
load line intersects the output current curve at two points. If
this happens, there are two stable output operating points
for the regulator. With this double intersection, the input
power supply needs to be cycled down to zero and back
up again to recover the output.
Thermal Considerations
The LT3055’s maximum rated junction temperature of
125°C (E-, I-grades) or 150°C (MP-, H-grades) limits its
power handling capability. Two components comprise the
power dissipated by the device:
GND pin current is determined using the GND Pin Current
curves in the Typical Performance Characteristics section.
Power dissipation equals the sum of the two components
listed above.
The LT3055 regulator has internal thermal limiting that
protects the device during overload conditions. For continuous normal conditions, do not exceed the maximum
junction temperature of 125°C (E-, I-grades) or 150°C
(MP-, H-grades). Carefully consider all sources of thermal
resistance from junction-to-ambient including other heat
sources mounted in proximity to the LT3055.
The undersides of the LT3055 DFN and MSE packages have
exposed metal from the lead frame to the die attachment.
These packages allow heat to directly transfer from the
die junction to the printed circuit board metal to control
maximum operating junction temperature. The dual-inline pin arrangement allows metal to extend beyond the
ends of the package on the topside (component side) of a
PCB. Connect this metal to GND on the PCB. The multiple
IN and OUT pins of the LT3055 also assist in spreading
heat to the PCB.
For surface mount devices, heat sinking is accomplished
by using the heat spreading capabilities of the PC board
and its copper traces. Copper board stiffeners and plated
through-holes also can spread the heat generated by
power devices.
Tables 3 and 4 list thermal resistance as a function of copper
area in a fixed board size. All measurements were taken
in still air on a 4-layer FR-4 board with 1oz solid internal
planes, and 2oz external trace planes with a total board
thickness of 1.6mm. For further information on thermal
resistance and using thermal information, refer to JEDEC
standard JESD51, notably JESD51-12.
Table 3. MSOP Measured Thermal Resistance
COPPER AREA
TOPSIDE
BACKSIDE
THERMAL RESISTANCE
BOARD AREA (JUNCTION-TO-AMBIENT)
1. Output current multiplied by the input/output voltage
differential:
2500 sq mm 2500 sq mm 2500 sq mm
35°C/W
IOUT • (VIN – VOUT), and
1000 sq mm 2500 sq mm 2500 sq mm
36°C/W
225 sq mm 2500 sq mm 2500 sq mm
37°C/W
100 sq mm 2500 sq mm 2500 sq mm
39°C/W
2. GND pin current multiplied by the input voltage:
IGND • VIN
20
3055f
For more information www.linear.com/LT3055
LT3055
APPLICATIONS INFORMATION
Table 4. DFN Measured Thermal Resistance
COPPER AREA
TOPSIDE
BOARD AREA
THERMAL RESISTANCE
(JUNCTION-TO-AMBIENT)
2500 sq mm
2500 sq mm
36°C/W
1000 sq mm
2500 sq mm
37°C/W
225 sq mm
2500 sq mm
38°C/W
100 sq mm
2500 sq mm
40°C/W
Calculating Junction Temperature
Example: Given an output voltage of 5V, an input voltage
range of 12V ±5%, a maximum output current range of
75mA and a maximum ambient temperature of 85°C, what
is the maximum junction temperature?
The power dissipated by the device equals:
IOUT(MAX) • (VIN(MAX) – VOUT) + IGND • VIN(MAX)
where:
IOUT(MAX) = 75mA
VIN(MAX) = 12.6V
IGND at (IOUT = 75mA, VIN = 12V) = 3.5mA
So:
P = 75mA • (12.6V – 5V) + 3.5mA • 12.6V = 0.614W
Using a DFN package, the thermal resistance ranges from
36°C/W to 40°C/W depending on the copper area. So the
junction temperature rise above ambient approximately
equals:
limiting, the device also protects against reverse input
voltages, reverse output voltages and reverse output-toinput voltages.
Current limit protection and thermal overload protection
protect the device against current overload conditions at
the output of the device. For normal operation, do not
exceed a junction temperature of 125°C (E-, I-grades) or
150°C (MP-, H-grades).
The LT3055 IN pin withstands reverse voltages of 50V. The
device limits current flow to less than 1μA (typically less
than 25nA) and no negative voltage appears at OUT. The
device protects both itself and the load against batteries
that are plugged in backwards.
The LT3055 incurs no damage if its output is pulled below
ground. If the input is left open circuit or grounded, the
output can be pulled below ground by 50V. No current
flows through the pass transistor from the output. However,
current flows in (but is limited by) the feedback resistor
divider that sets the output voltage. Current flows from
the bottom resistor in the divider and from the ADJ pin’s
internal clamp through the top resistor in the divider to
the external circuitry pulling OUT below ground. If the
input is powered by a voltage source, the output sources
current equal to its current limit capability and the LT3055
protects itself by thermal limiting. In this case, grounding
the SHDN pin turns off the device and stops the output
from sourcing current.
1.0
0.614W • 40°C/W = 24.6°C
VIN = 0
0.9
TJMAX = 85°C + 24.6°C = 110°C
Protection Features
0.8
OUTPUT CURRENT (µA)
The maximum junction temperature equals the maximum
ambient temperature plus the maximum junction temperature rise above ambient or:
0.7
0.6
0.5
0.4
0.3
0.2
The LT3055 incorporates several protection features that
make it ideal for use in battery-powered circuits. In addition to the normal protection features associated with
monolithic regulators, such as current limiting and thermal
0.1
0
5
0
10
15
20 25
VOUT (V)
30
35
40
3055 F11
Figure 11. Reverse Output Current
3055f
For more information www.linear.com/LT3055
21
LT3055
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
MSE Package
16-Lead Plastic MSOP, Exposed Die Pad
(Reference LTC DWG # 05-08-1667 Rev E)
BOTTOM VIEW OF
EXPOSED PAD OPTION
2.845 ±0.102
(.112 ±.004)
5.23
(.206)
MIN
2.845 ±0.102
(.112 ±.004)
0.889 ±0.127
(.035 ±.005)
8
1
1.651 ±0.102
(.065 ±.004)
1.651 ±0.102 3.20 – 3.45
(.065 ±.004) (.126 – .136)
0.305 ±0.038
(.0120 ±.0015)
TYP
16
0.50
(.0197)
BSC
4.039 ±0.102
(.159 ±.004)
(NOTE 3)
RECOMMENDED SOLDER PAD LAYOUT
0.254
(.010)
0.35
REF
0.12 REF
DETAIL “B”
CORNER TAIL IS PART OF
DETAIL “B” THE LEADFRAME FEATURE.
FOR REFERENCE ONLY
9
NO MEASUREMENT PURPOSE
0.280 ±0.076
(.011 ±.003)
REF
16151413121110 9
DETAIL “A”
0° – 6° TYP
3.00 ±0.102
(.118 ±.004)
(NOTE 4)
4.90 ±0.152
(.193 ±.006)
GAUGE PLANE
0.53 ±0.152
(.021 ±.006)
DETAIL “A”
1.10
(.043)
MAX
0.18
(.007)
SEATING
PLANE
0.17 – 0.27
(.007 – .011)
TYP
1234567 8
0.50
(.0197)
BSC
NOTE:
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
6. EXPOSED PAD DIMENSION DOES INCLUDE MOLD FLASH. MOLD FLASH ON E-PAD SHALL
NOT EXCEED 0.254mm (.010") PER SIDE.
0.86
(.034)
REF
0.1016 ±0.0508
(.004 ±.002)
MSOP (MSE16) 0911 REV E
3055f
22
For more information www.linear.com/LT3055
LT3055
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
DE Package
16-Lead Plastic DFN (4mm × 3mm)
(Reference LTC DWG # 05-08-1732 Rev Ø)
0.70 ±0.05
3.30 ±0.05
3.60 ±0.05
2.20 ±0.05
1.70 ±0.05
PACKAGE
OUTLINE
0.25 ±0.05
0.45 BSC
3.15 REF
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
4.00 ±0.10
(2 SIDES)
R = 0.05
TYP
9
R = 0.115
TYP
0.40 ±0.10
16
3.30 ±0.10
3.00 ±0.10
(2 SIDES)
1.70 ±0.10
PIN 1 NOTCH
R = 0.20 OR
0.35 × 45°
CHAMFER
PIN 1
TOP MARK
(SEE NOTE 6)
(DE16) DFN 0806 REV Ø
8
0.200 REF
1
0.23 ±0.05
0.45 BSC
0.75 ±0.05
3.15 REF
0.00 – 0.05
BOTTOM VIEW—EXPOSED PAD
NOTE:
1. DRAWING PROPOSED TO BE MADE VARIATION OF VERSION (WGED-3) IN JEDEC
PACKAGE OUTLINE MO-229
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE
TOP AND BOTTOM OF PACKAGE
3055f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection
of its circuits
as described
herein will not infringe on existing patent rights.
For more
information
www.linear.com/LT3055
23
LT3055
TYPICAL APPLICATION
Cable Drop Compensation
VIN
5.6V TO 45V
LT3055
IN
10µF
REF
1x 500x
+
–
+
–
600mV
RCABLE/2
OUT
IMON
ADJ
100nF
10µF
RCABLE • 500
+
5V, COMPENSATED
10µF FOR DROP ALONG
RCABLE/2 RESISTORS
–
RCABLE/2
440k – RCABLE • 500
2N3904
1k
1k
10nF
60k
3055 TA02FF
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LT1761
100mA, Low Noise LDO
300mV Dropout Voltage, Low Noise: 20μVRMS, VIN: 1.8V to 20V, ThinSOT™ Package
LT1762
150mA, Low Noise LDO
300mV Dropout Voltage, Low Noise: 20μVRMS, VIN: 1.8V to 20V, MS8 Package
LT1763
500mA, Low Noise LDO
300mV Dropout Voltage, Low Noise: 20μVRMS, VIN: 1.8V to 20V, SO-8 Package
LT1962
300mA, Low Noise LDO
270mV Dropout Voltage, Low Noise: 20μVRMS, VIN: 1.8V to 20V, MS8 Package
LT1964
200mA, Low Noise, Negative LDO
340mV Dropout Voltage, Low Noise: 30μVRMS, VIN: –1.8V to –20V, ThinSOT Package
LT1965
1.1A, Low Noise, Low Dropout Linear
Regulator
290mV Dropout Voltage, Low Noise: 40μVRMS, VIN: 1.8V to 20V, VOUT: 1.2V to 19.5V,
Stable with Ceramic Capacitors, TO-220, DDPak, MSOP and 3mm × 3mm DFN
Packages
LT3008
20mA, 45V, 3µA IQ Micropower LDO
300mV Dropout Voltage, Low IQ = 3μA, VIN: 2.0V to 45V, VOUT: 0.6V to 39.5V,
ThinSOT and 2mm × 2mm DFN-6 Packages
LT3009
20mA, 3µA IQ Micropower LDO
280mV Dropout Voltage, Low IQ = 3μA, VIN: 1.6V to 20V, ThinSOT and SC-70
Packages
LT3010
50mA, High Voltage, Micropower LDO
VIN: 3V to 80V, VOUT: 1.275V to 60V, VDO = 0.3V, IQ = 30μA, ISD < 1μA,
Low Noise: <100μVRMSP-P, Stable with 1μF Output Capacitor, Exposed MS8 Package
LT3011
50mA, High Voltage, Micropower LDO with
PWRGD
VIN: 3V to 80V, VOUT: 1.275V to 60V, VDO = 0.3V, IQ = 46μA, ISD < 1μA,
Low Noise: <100μVRMS, PowerGood, Stable with 1μF Output Capacitor,
3mm × 3mm DFN-10 and Exposed MS12E Packages
LT3012
250mA, 4V to 80V, Low Dropout Micropower
Linear Regulator
VIN: 4V to 80V, VOUT: 1.24V to 60V, VDO = 0.4V, IQ = 40μA, ISD < 1μA, TSSOP-16E and
4mm × 3mm DFN-12 Packages
LT3013
250mA, 4V to 80V, Low Dropout Micropower
Linear Regulator with PWRGD
VIN: 4V to 80V, VOUT: 1.24V to 60V, VDO = 0.4V, IQ = 65μA, ISD < 1μA, PowerGood
Feature, TSSOP-16E and 4mm × 3mm DFN-12 Packages
LT3014/LT3014HV 20mA, 3V to 80V, Low Dropout Micropower
Linear Regulator
VIN: 3V to 80V (100V for 2ms, LT3014HV Version), VOUT: 1.22V to 60V, VDO = 0.35V,
IQ = 7μA, ISD < 1μA, ThinSOT and 3mm × 3mm DFN-8 Packages
LT3080/LT3080-1
1.1A, Parallelable, Low Noise, Low Dropout
Linear Regulator
300mV Dropout Voltage (2-Supply 0peration), Low Noise: 40μVRMS, VIN: 1.2V to
36V, VOUT: 0V to 35.7V, Current-Based Reference with 1-Resistor VOUT Set, Directly
Parallelable (No Op Amp Required), Stable with Ceramic Capacitors, TO-220,
SOT-223, MSOP and 3mm × 3mm DFN Packages, LT3080-1 Version Has Integrated
Internal Ballast Resistor
LT3050
100mA LDO with Diagnostics and Precision
Current Limit
340mV Dropout Voltage, Low Noise: 20μVRMS, VIN: 1.8V to 45V, DFN and MSOP
Packages
LT3060
100mA, Low Noise LDO with Soft-Start
300mV Dropout Voltage, Low Noise: 20μVRMS, VIN: 1.8V to 45V, DFN Package
3055f
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Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
For more information www.linear.com/LT3055
(408) 432-1900 ● FAX: (408) 434-0507
●
www.linear.com/LT3055
LT 0513 • PRINTED IN USA
 LINEAR TECHNOLOGY CORPORATION 2013