Sanyo LC866424 8-bit single chip microcontroller with one-time programmable prom Datasheet

Ordering number : ENN*6689
CMOS IC
LC86P6449
8-Bit Single Chip Microcontroller
with One-Time Programmable PROM
Preliminary
Overview
The LC86P6449 is a CMOS 8-bit single chip microcontroller with one-time PROM for the LC866400 series.
This microcontroller has the function and the pin description of the LC866400 series mask ROM version, and 48K-byte
PROM.
Features
(1) Option switching by PROM data
The option function of the LC866400 series can be specified by the PROM data.
LC86P6449 can be checked the function of the trial pieces using the mass production board.
(2) Internal one-time PROM capacity
: 49408 bytes
(3) Internal RAM capacity
:
1152 bytes
Used PROM or RAM capacity are equal ROM or RAM capacity of mask ROM version which applies LC86P6449.
Mask ROM version
LC866448
LC866444
LC866440
LC866436
LC866432
LC866428
LC866424
LC866420
LC866416
LC866412
LC866408
PROM capacity
49152 bytes
45056 bytes
40960 bytes
36864 bytes
32768 bytes
28672 bytes
24576 bytes
20480 bytes
16384 bytes
12288 bytes
8192 bytes
RAM capacity
1152 bytes
1152 bytes
1152 bytes
1152 bytes
768 bytes
768 bytes
768 bytes
640 bytes
640 bytes
512 bytes
512 bytes
Programming service
We offers various services at nominal charges. These include the ROM writing, the ROM reading, the package stamping
and the screening. Contact our representative for further information
Ver.1.01
80796
91400 RM (IM) SK No.6689-1/22
LC86P6449
(4) Operating supply voltage
: 4.5V to 6.0V
(5) Instruction cycle time
: 1.0µs to 366µs
(6) Operating temperature
: -30°C to +70°C
(7) The pin and the package compatible with the LC866400 series mask ROM devices
(8) Applicable mask ROM version
: LC866448/LC866444/LC866440/LC866436//LC866432/LC866428
/LC866424/LC866420/LC866416/LC866412/LC866408
Notice for use
LC86P6449 is provided for the first release and small shipping of the LC866400 series.
At using, take notice of the followings.
(1) A point of difference LC86P6449 and LC866400 series
Item
Operation after reset
releasing
LC86P6449
The option is specified until 3ms after
going to a ‘H’ level to the reset terminal by
dgrees. The program is executed from
00H of the program counter.
Pull-down resistor
provided/not provided
Not provided
Provided (fixed)
Provided (fixed)
Not provided
4.5V to 6.0V
LC866448/44/40/36/32/28/24/20/16/12/08
The program is executed from 00H of the
program counter immediately after going to a
‘H’ level to reset terminal.
Pull-down resistor of
Pull-down resistor
the following pins
provided/not provided
•S0/T0 – S6/T6
Specified by the option
•S7/T7 – S15/T15
Provided (fixed)
•S16 – S27
Specified by the option
•S28 – S37
Specified by the option
Operating supply
2.5V to 6.0V
Voltage range (VDD)
“L” level hold Tr. of the
high voltage withstand input Refer to ‘electrical characteristics’ on the semiconductor news.
terminal
Power dissipation
LC86P6449 uses 256 bytes that is addressed on FF00H to FFFFH in the program memory as the option configuration
data area. This option configuration cannot execute all options which LC866400 series have. Next tables show the
options that correspond and not correspond to LC86P6449.
• A kind of the option corresponding of the LC86P6449
A kind of option
Input/output form of
Input/output ports
Pins, Circuits
Port 0
Port 1
*1
Port 3
*1
Pull-up MOS Tr. of input ports
Port 7
*1
*1) Specified in a bit
*2) Specified in nibble unit.
Contents of the option
1. N-channel open drain output
2. CMOS output
*1
1. Pull-up MOS Tr. proveded
2. Pull-up MOS Tr. not provided
*2
1. Input : Programmable pull-up MOS Tr.
Output : N-channel open drain
2. Input : Programmable pull-up MOS Tr.
Output : CMOS
1. Input : No Programmable pull-up MOS Tr.
Output : N-channel open drain
2. Input : Programmable pull-up MOS Tr.
Output : CMOS
1. No Pull-up MOS Tr.
2. Pull-up MOS Tr.
The port of N-channel open drain output does not have the Pull-up MOS Tr..
No.6689-2/22
LC86P6449
• A kind of the option not corresponding of the LC86P6449
A kind of option
Pull-down resistor of
the high voltage
Withstand output terminals
Pins, Circuits
•S0/T0 to S6/T6
•S16 to S27
•S28 to S37
LC86P6449
Not provided
Provided (fixed)
Not provided
LC866448/44/40/36/32/28/24/20/16/12/08
Specified by the option
Specified by the option
Specified by the option
(2) Option
The option data is created by the option specified program “SU86K.EXE”.
program area by linkage loader “L86K.EXE”.
The created option data is linked to the
(3) ROM space
LC86P6449 and LC866400 series use 256 bytes that is addressed on 0FF00H to 0FFFFH in the program memory as the
option specified data area. These program memory capacity are 61440 bytes that is addressed on 0000H to BFFFH.
0FFFFH The option specified
area 256 bytes
0FF00H
0EFFFH
0DFFFH
0CFFFH
0BFFFH
0AFFFH
9FFFH
8FFFH
7FFFH
6FFFH
5FFFH
4FFFH
3FFFH
2FFFH
1FFFH
Program area
0FFFH
48K bytes
0000H
0FFFFH
0FF00H
0EFFFH
0DFFFH
0CFFFH
0BFFFH
0AFFFH
9FFFH
8FFFH
7FFFH
6FFFH
5FFFH
4FFFH
3FFFH
2FFFH
1FFFH
0FFFH
0000H
The option
specified area
The option
specified area
The option
specified area
The option
specified area
The option
specified area
Program area
44K bytes
Program area
40K bytes
Program area
36K bytes
Program area
32K bytes
Program area
28K bytes
LC866448
LC866444
LC866440
LC866436
LC866432
LC866428
The option
specified area
The option
specified area
The option
specified area
The option
specified area
The option
specified area
Program area
24K bytes
Program area
20K bytes
Program area
16K bytes
Program area
12K bytes
Program area
8K bytes
LC866424
LC866420
LC866416
LC866412
LC866408
No.6689-3/22
LC86P6449
(4) Ordering information
1. When ordering the identical mask ROM and PROM devices simultaneously.
Provide an EPROM containing the target memory contents together with the separate order forms for each of the mask
ROM and PROM versions.
2. When ordering a PROM device.
Provide an EPROM containing the target memory contents together with an order form.
How to use
(1) Specification of option
Programming data for PROM of the LC86P6449 is required.
Debugged evaluation file (EVA file) must be converted to an INTEL-HEX formatted file (HEX file) with file converter
program, EVA2HEX.EXE. The HEX file is used as the programming data for the LC86P6449.
(2) How to program for the PROM
LC86P6449 can be programmed by the EPROM programmer with attachment ; W86EP6448Q.
• Recommended EPROM programmer
Productor
Advantest
Andou
AVAL
Minato electronics
EPROM programmer
R4945, R4944, R4943
AF-9704
PKW-1100, PKW-3000
MODEL 1890A
• “27512 (Vpp=12.5V) Intel high speed programming” mode available. The address must be set to “0 to
0FFFFH” and a jumper (DASEC) must be set to ‘OFF’ at programming.
(3) How to use the data security function
“Data security” is the disabled function to read the data of the PROM.
The following is the process in order to execute the data security.
1. Set ‘ON’ the jumper of attachment.
2.Program again. Then EPROM programmer displays the error. The error means normally activity of the data
security. It is not a trouble of the EPROM programmer or the LSI.
Notes
• Data security is not executed when the data of all address have ‘FFH’ at the sequence 2 above.
• The programming by a sequential operation “BLANK⇒PROGRAM⇒VERIFY” cannot be executed data security at the
sequence 2 above.
• Set to ‘OFF’ the jumper after executing the data security.
Data security
1 pin mark
of LSI
Not data security
1 pin
W86EP6448Q
No.6689-4/22
P00
P01
P02
P03
P04
P05
P06
P07
VSS2
P10/SO0
P11/SI0/SB0
P12/SCK0
P13/SO1
P14/SI1/SB1
P15/SCK1
P16/BUZ
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
RES
XT1/P74
XT2/P75
VSS1
CF1
CF2
VDD1
P80/AN0
P81/AN1
P82/AN2
P83/AN3
P84/AN4
P85/AN5
P86/AN6
P87/AN7
P71/INT1
P72/INT2/T0IN
P73/INT3/T0IN
P17/PWM0
P30
P31
P32
P33
P70/INT0
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
S37/PE5
S36/PE4
S35/PE3
S34/PE2
S33/PE1
S32/PE0
S31/PD7
S30/PD6
S29/PD5
S28/PD4
S27/PD3
S26/PD2
S25/PD1
S24/PD0
S23/PC7
S22/PC6
S21/PC5
S20/PC4
S19/PC3
S18/PC2
S17/PC1
S16/PC0
VP
VDD2
LC86P6449
Pin Assignment
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
S15/T15
S14/T14
S13/T13
S12/T12
S11/T11
S10/T10
S9/T9
S8/T8
S7/T7
S6/T6
S5/T5
S4/T4
S3/T3
S2/T2
S1/T1
S0/T0
Package Dimension
(unit : mm)
3174
SANYO : QIP-80E
No.6689-5/22
LC86P6449
System Block Diagram
Interrupt Control
IR
PLA
A15-A0
D7-D0
TA
CE
OE
DASEC
Stand-by Control
CF
RC
Clock
Generator
PROM
Control
PROM(48KB)
X’tal
PC
Base Timer
Bus Interface
ACC
SIO0
Port 1
B Register
SIO1
Port 3
C Register
Timer 0
Port 7
ALU
Timer 1
Port 8
ADC
PSW
INT0 to 3
Noise Filter
RAR
Real Time Service
RAM
RAM
128 bytes
Stack Pointer
Port 0
VFD
Controller
Watchdog Timer
High Voltage Output
No.6689-6/22
LC86P6449
LC86P6449 Pin description
Pin name I/O
Function description
Option
VSS1,2
- Power pin (-)
VDD1,2
- Power pin (+)
*4
Refer to Notes
VP
- Power pin (-) for the VFD output pull-down resist
PORT0
I/O •8-bit input/output port
•Pull-up resistor :
P00 to P07
•Input for port 0 interrupt
Provided/Not provided
•Input/output in nibble units
•Output form :
•Input for HOLD release
CMOS/N-channel open
•15V withstand at N-channel open drain
drain
output
PORT1
I/O •8-bit input/output port
•Output form :
P10 to P17
•Input/output can be specified in a bit unit
CMOS/N-channel open
•Other pin functions
drain
P10 SIO0 data output
P11 SIO0 data input/bus input/output
P12 SIO0 clock input/output
P13 SIO1 data output
P14 SIO1 data input/bus input/output
P15 SIO1 clock input/output
P16 Buzzer output
P17 Timer 1 output (PWM0 output)
PORT3
I/O •4-bit input/output port
•Output form :
P30 to P33
•Input/output can be specified
CMOS/N-channel open
•15V withstand at N-channel open drain
drain
output
PORT7
•6-bit input port
Pull-up resistor :
•Other functions
Provided/Not provided
P70 : INT0 input/HOLD release input/
(P70,71,72,73)
N-ch Tr. output for watchdog timer
* P74 ,P75 don’t have
P70
P71 : INT1 input/HOLD release input
I/O
pull-up
P72 : INT2 input/timer 0 event input
resistor option.
P71 to P75 I
P73 : INT3 input with noise rejection
filter/timer 0 event input
P74 : XT1 terminal for 32.768kHz crystal
oscillation
P75 : XT2 terminal for 32.768kHz crystal
oscillation
•Interrupt received forms, the vector addresses
rising falling rising high low vector
& level level
falling
INT0 enable enable disable enable enable 03H
INT1 enable enable disable enable enable 0BH
INT2 enable enable enable disabledisable 13H
INT3 enable enable enable disabledisable 1BH
Continue.
PROM mode
-
Data line
D0 to D7
-
PROM control
signals
DASEC (*1)
OE (*2)
‚bE
CE (*3)
No.6689-7/22
LC86P6449
Pin name
PORT8
P80 to 87
S0/T0 to
S6/T6 *6
S7/T7 to
S15/T15
*7
S16 to S31
*8
I/O
Function description
I •8-bit input port
•Other function
AD input port (8 port pins)
O Output for VFD display controller
Segment/timing in common
O •Output for VFD display controller
Segment/timing with internal pull-down
resistor in common
I/O •Output for VFD display controller Segment
output
•Other function
S16 : High voltage input port PC0
S17 : High voltage input port PC1
S18 : High voltage input port PC2
S19 : High voltage input port PC3
S20 : High voltage input port PC4
S21 : High voltage input port PC5
S22 : High voltage input port PC6
S23 : High voltage input port PC7
S24 : High voltage input port PD0
S25 : High voltage input port PD1
S26 : High voltage input port PD2
S27 : High voltage input port PD3
S28 : High voltage input port PD4
S29 : High voltage input port PD5
S30 : High voltage input port PD6
S31 : High voltage input port PD7
S32 to S37 I/O •Output for VFD display controller Segment
*9
•Other function
S32 : High voltage I/O port PE0
S33 : High voltage I/O port PE1
S34 : High voltage I/O port PE2
S35 : High voltage I/O port PE3
S36 : High voltage I/O port PE4
S37 : High voltage I/O port PE5
I Reset pin
RES
I •Input pin for 32.768kHz crystal oscillation
XT1/ P74
•Other function
XT1 : Input port P74
In case of non use, connect to VDD1.
XT2/P75 O •Output pin for 32.768kHz crystal
oscillation
•Other function
XT2 : Input port P75
In case of non use, connect to VDD1 at using
as port or unconnect at using as oscillation.
Option
PROM mode
-
-
-
-
-
TA (*5)
-
•Address input
A15 to A0
•PROM
control
signal input
-
-
-
-
-
-
No.6689-8/22
LC86P6449
Pin name I/O
Function description
Option
CF1
I Input pin for the ceramic resonator oscillation
CF2
O Output pin for the ceramic resonator oscillation ♦ All of port options except the pull-up resistor option of port 0 can be specified in a bit unit.
*1
*2
*3
*4
*5
*6
*7
*8
*9
*10
PROM mode
-
Memory select input for data security
Output enable input
Chip enable input
Connect like the following figure to reduce noise into a VDD1 terminal.
TA ! PROM control signal input
S0/T0 to S6/T6 : not provided the pull-down resistor
S7/T7 to S15/T15 : provided the pull-down resistor (fixed)
S16 to S27 : provided the pull-down resistor (fixed)
S28 to S31 : not provided the pull-down resistor
S32 to S37 : not provided the pull-down resistor
[Notes]
When connecting to the power supply, the power pins must be connected like following figure.
For the LC866448B/44B/40B/36B
LSI
VDD1
Power
Supply
For back-up
VDD2
(VFD power pin)
VSS1
VSS2
For the LC866432A/28A/24A/20A/16A/12A/08A
LSI
VDD1
Power
Supply
For back-up
VDD2
(VFD power pin)
VSS1
VSS2
No.6689-9/22
LC86P6449
1. Absolute Maximum Ratings at VSS1=VSS2=0V and Ta=25°C
Parameter
Supply voltage
Input voltage
Output voltage
Input/Output
voltage
High
level
output
current
Peak
output
current
Total
output
current
Low
level
output
current
Peak
output
current
Total
output
current
Maximum power
dissipation
Operating
temperature
range
Storage
temperature
range
Symbol
Pins
VDDMAX VDD1, VDD2
VI(1)
•Ports 71,72,73, 74 ,75,8
• RES
VI(2)
VP
VO(1)
S0/T0 to S15/T15
VIO(1)
•Port 1
•Port 70
•Ports 0, 3 of CMOS
output
VIO(2)
Ports 0, 3 of open
drain output
VIO(3)
S16 to S37
IOPH(1) Ports 0, 1, 3
IOPH(2)
IOPH(3)
ΣIOAH(1)
ΣIOAH(2)
ΣIOAH(3)
IOPL(1)
IOPL(2)
S0/T0 to S15/T15
S16 to S37
Ports 0,1,3
S0/T0 to S15/T15
S16 to S37
Ports 0,1,3
Port 70
Conditions
VDD1=VDD2
•CMOS output
•At each pins
At each pins
At each pins
The total of all pins
The total of all pins
The total of all pins
At each pins
At each pins
VDD[V]
min.
-0.3
-0.3
Ratings
typ.
max.
+7.0
VDD+0.3
VDD-45
VDD-45
-0.3
VDD+0.3
VDD+0.3
VDD+0.3
-0.3
15
VDD-45
-10
VDD+0.3
unit
V
mA
-30
-15
-30
-55
-115
20
15
ΣIOAL(1) Port 0
ΣIOAL(2) Ports 1,3
The total of all pins
The total of all pins
40
40
Pdmax
Ta=-30 to+70°C
480
mW
°C
QFP80E
Topr
-30
70
Tstg
-55
125
No.6689-10/22
LC86P6449
2. Recommended Operating Range at Ta=-30°C to +70°C, VSS1=VSS2=0V
Parameter
Symbol
Pins
Operating
Supply voltage
Hold voltage
VDD(1)
VDD1=VDD2
VHD
VDD1=VDD2
Pull-down
Voltage
Input high
voltage
VP
VP
VIH(1)
Port 0 at CMOS
output
Port 0 at open drain
output
•Port 1
•Ports 72,73
•Port 3 at CMOS
output
•Port 3 at open
drain output
•Port 70
Port input/interrupt
•Port 71
• RES
Port 70
Watchdog timer
•Port 8
•Ports 74 ,75
S16 to S37
VIH(2)
VIH(3)
VIH(4)
VIH(5)
VIH(6)
VIH(7)
VIH(8)
Input low
voltage
VIL(1)
VIL(2)
VIL(3)
VIL(4)
VIL(5)
VIL(6)
VIL(7)
Operation
cycle time
Port 0 at CMOS
output option
Port 0 at open
drain output
•Ports 1,3
•Ports 72,73
•Port 70
Port input/interrupt
•Port 71
• RES
Port 70
Watchdog timer
•Port 8
•Ports 74 ,75
S16 to S37
Conditions
VDD[V]
98µs≤tCYC
tCYC≤400µs
RAMs and the registers
hold voltage at HOLD
mode.
4.5 to 6.0
Output disable
min.
4.5
Ratings
typ.
max.
6.0
2.0
6.0
-35
VDD
VDD
Output disable
4.5 to 6.0 0.33VDD
+1.0
4.5 to 6.0 0.75VDD
Output disable
4.5 to 6.0 0.75VDD
VDD
Output disable
4.5 to 6.0 0.75VDD
13.5
Output N-channel
Tr. OFF
4.5 to 6.0 0.75VDD
VDD
Output N-channel
Tr. OFF
Using as port
4.5 to 6.0 0.9VDD
VDD
4.5 to 6.0 0.75VDD
VDD
Output P-channel
Tr. OFF
Output disable
4.5 to 6.0 0. 33VDD
+1.0
4.5 to 6.0
VSS
VDD
0.2VDD
Output disable
4.5 to 6.0
VSS
0.25VDD
Output disable
4.5 to 6.0
VSS
0.25VDD
Output N-channel
Tr. OFF
4.5 to 6.0
VSS
0.25VDD
Output N-channel
Tr. OFF
Using as port
4.5 to 6.0
VSS
0. 8VDD
4.5 to 6.0
VSS
-1.0
0.25VDD
4.5 to 6.0
VP
0.2VDD
4.5 to 6.0
0.98
400
Output P-channel
Tr. OFF
tCYC
unit
V
13.5
µs
Continue.
No.6689-11/22
LC86P6449
Parameter
Symbol
Oscillation
FmCF(1)
frequency
range
(Note 1)
FmCF(2)
Oscillation
stabilizing
time period
(Note 1)
Pins
Conditions
CF1, CF2
•6MHz
(ceramic resonator
oscillation)
•Refer to figure 1
•3MHz
(ceramic resonator
oscillation)
•Refer to figure 1
RC oscillation
•32.768kHz
(crystal oscillation)
•Refer to figure 2
•6MHz
(ceramic resonator
oscillation)
•Refer to figure 3
•3MHz
(ceramic resonator
oscillation)
•Refer to figure 3
•32.768kHz
(crystal oscillation)
•Refer to figure 3
CF1, CF2
FmRC
FsXtal
XT1, XT2
tmsCF(1)
CF1, CF2
tmsCF(2)
CF1, CF2
tssXtal
XT1, XT2
VDD[V]
4.5 to 6.0
min.
4.5 to 6.0
4.5 to 6.0
4.5 to 6.0
4.5 to 6.0
Ratings
typ.
6
max.
unit
MHz
3
0.3
0.8
32.768
3.0
kHz
ms
4.5 to 6.0
4.5 to 6.0
s
(Note 1) The oscillation constant is shown on table 1 and table 2.
No.6689-12/22
LC86P6449
3. Electrical Characteristics at Ta=-30°C to +70°C, VSS1=VSS2=0V
Parameter
Input high
current
Input low
current
Output high
voltage
Symbol
Pins
IIH(1)
Ports 0,3 at open
drain output
IIH(2)
•Ports 1,3
•Port 0 without
pull-up MOS Tr.
IIH(3)
•Ports 70,71,72,73
without pull-up
MOS Tr.
•Port 8
IIH(4)
IIH(5)
RES
Ports 74 ,75
IIH(6)
•S28 to S37
IIL(1)
•Ports 1,3
•Port 0 without
pull-up MOS Tr.
IIL(2)
•Ports 70,71,72,73
without pull-up
MOS Tr.
•Port 8
IIL(3)
IIL(4)
RES
Ports 74 ,75
VOH(1) Ports 0,1,3 of
VOH(2) CMOS output
VOH(3) S0/T0 to S15/T15
VOH(4)
VOH(5) S16 to S37
VOH(6)
Output low
voltage
Pull-up MOS
Tr. resistor
VOL(1) Ports 0,1,3
VOL(2)
VOL(3)
VOL(4) Port 70
Rpu
•Ports 0,1,3
•Ports 70,71,72,73
Conditions
•Output disable
•VIN=13.5V
(including off-leakage
current of output Tr.)
•Output disable
•Pull-up MOS Tr. OFF.
•VIN=VDD
(including off-leakage
current of output Tr.)
VIN=VDD
VDD[V]
4.5 to 6.0
min.
Ratings
typ.
max.
5
4.5 to 6.0
1
4.5 to 6.0
1
VIN=VDD
Using as port
VIN=VDD
•Output disable
•VIN=VDD
•Output disable
•Pull-up MOS Tr. OFF.
•VIN=VSS
(including off-leakage
current of output Tr.)
VIN=VSS
4.5 to 6.0
4.5 to 6.0
1
1
4.5 to 6.0
1
VIN=VSS
Using as port
VIN=VSS
IOH=-1.0mA
IOH=-0.1mA
IOH=-20mA
•IOH=-1.0mA
•The current of these each
pins is not over 1mA.
IOH=-5mA
•IOH=-1.0mA
•The current of these each
pins is not over 1mA.
IOL=10mA
IOL=1.6mA
•IOL=1mA
•The current of these each
pins is not over 1mA.
IOL=1mA
VOH=0.9VDD
4.5 to 6.0
-1
4.5 to 6.0
-1
4.5 to 6.0
4.5 to 6.0
-1
-1
4.5 to 6.0
4.5 to 6.0
4.5 to 6.0
4.5 to 6.0
VDD-1
VDD-0.5
VDD-1.8
VDD-1
4.5 to 6.0
4.5 to 6.0
VDD-1.8
VDD-1
µA
V
4.5 to 6.0
4.5 to 6.0
4.5 to 6.0
4.5 to 6.0
4.5 to 6.0
unit
1.5
0.4
0.4
15
40
0.4
70
kΩ
Continue.
No.6689-13/22
LC86P6449
Parameter
Output offleakage current
Symbol
Pins
Conditions
IOFF(1) •S0/T0 to S6/T6
•S28 to S37
(without pull-down
IOFF(2) resistor)
‘L’ level hold Tr.
of high voltage
withstand input
pull-down
transistor resistor
Rinpd
S16 to S37
Rpd
Hysteresis
voltage
VHIS
Pin capacitance
CP
•S7/T7 to S15/T15
•S16 to S27
(without pull-down
resistor)
•Port 1
•Ports 70,71,72,73
• RES
All pins
•Output P-channel
Tr. OFF
•VOUT=VSS
•Output P-channel
Tr. OFF
•VOUT=VDD-40V
Output P-channel
Tr. OFF
•Output P-channel
Tr. OFF
•VOUT=3V
•Vp=-30V
Output disable
•f=1MHz
•VIN=VSS for all
unmeasured terminals.
•Ta=25°C
VDD[V]
4.5 to 6.0
min.
-1
4.5 to 6.0
-30
4.5 to 6.0
Ratings
typ.
max.
µA
400
5.0
60
unit
kΩ
100
200
kΩ
4.5 to 6.0
0.1VDD
V
4.5 to 6.0
10
pF
Pins
Input clock
Serial input
Serial clock
Parameter
Serial output
Symbol
Cycle
Low Level
pulse width
High Level
pulse width
Cycle
Low Level
pulse width
High Level
pulse width
Data set-up time
tCKCY(1)
tCKL(1)
SCK0,SCK1
Output clock
4. Serial Input/output Characteristics at Ta=-30°C to +70°C, VSS1=VSS2=0V
tCKCY(2)
tCKL(2)
Data hold time
tCKI
Output delay time
(External clock
using for serial
transfer clock)
Output delay time
(Internal clock
using for serial
transfer clock)
tCKO(1)
Conditions
Refer to figure 5
VDD[V]
4.5 to 6.0
tCKH(1)
tCKO(2)
Ratings
typ.
max.
unit
tCYC
1
SCK0,SCK1
tCKH(2)
tICK
min.
2
1
•SI0,SI1
•SB0,SB1
•SO0,SO1
•SB0,SB1
•Use pull-up
resistor (1kΩ)
in the open drain
output.
•Refer to figure 5
•Data set-up to
SCK0,1
•Data hold from
SCK0,1
•Refer to figure 5
•Use pull-up
resistor (1kΩ) in
the open drain
output.
•Data hold from
SCK0,1
•Refer to figure 5
4.5 to 6.0
2
1/2tCKCY
1/2tCKCY
4.5 to 6.0
µs
0.1
0.1
4.5 to 6.0
7/12
tCYC
+0.2
1/3
tCYC
+0.2
No.6689-14/22
LC86P6449
5. Pulse Input Conditions at Ta=-30°C to +70°C, VSS1=VSS2=0V
Parameter
Symbol
High/low level
pulse width
tPIH(1)
tPIL(1)
tPIH(2)
tPIL(2)
Pins
•INT0, INT1
•INT2/T0IN
INT3/T0IN
(The noise rejection clock
selected to 1/1.)
tPIH(3) INT3/T0IN
tPIL(3) (The noise rejection clock
selected to 1/16.)
tPIH(4) INT3/T0IN
tPIL(4) (The noise rejection clock
selected to 1/64.)
tPIL(5) RES
Conditions
VDD[V]
4.5 to 6.0
min.
1
4.5 to 6.0
2
•Interrupt acceptable
•Timer0-countable
4.5 to 6.0
32
•Interrupt acceptable
•Timer0-countable
4.5 to 6.0
128
Reset acceptable
4.5 to 6.0
200
•Interrupt acceptable
•Timer0-countable
•Interrupt acceptable
•Timer0-countable
Ratings
typ.
max.
unit
tCYC
µs
6. AD Converter Characteristics at Ta=-30°C to + 70°C, VSS1=VSS2=0V
Parameter
Resolution
Absolute precision
(Note 2)
Conversion time
Analog input
voltage range
Analog port
input current
Symbol
Pins
Conditions
N
ET
tCAD
VAIN
IAINH
IAINL
AD conversion time =
16 × tCYC
(ADCR2=0)
(Note 3)
AD conversion time =
32 × tCYC
(ADCR2=1)
(Note 3)
AN0 to AN7
VAIN=VDD
VAIN=VSS
Ratings
typ.
8
max.
unit
VDD[V]
4.5 to 6.0
4.5 to 6.0
min.
4.5 to 6.0
15.68
(tCYC=
0.98µs)
65.28
(tCYC=
4.08µs)
31.36
(tCYC=
0.98µs)
130.56
(tCYC=
4.08µs)
4.5 to 6.0
VSS
VDD
V
4.5 to 6.0
4.5 to 6.0
1
µA
-1
±1.5
bit
LSB
µs
(Note 2) Absolute precision excepts the quantizing error (±1/2 LSB).
(Note 3) The conversion time means the time from executing the AD conversion instruction to setting the complete digital
conversion value to the register.
No.6689-15/22
LC86P6449
7. Current Dissipation Characteristics at Ta=-30°C to +70°C, VSS1=VSS2=0V
Parameter
Symbol
Current dissipation
IDDOP(1)
during basic
operation
(Note 4)
IDDOP(2)
IDDOP(3)
IDDOP(4)
Pins
Conditions
•FmCF=6MHz
Ceramic resonator
oscillation
•FsXtal=32.768kHz
crystal oscillation
•System clock :
CF oscillation
•Internal RC
oscillation stops
•1/1 divided
•FmCF=3MHz
Ceramic resonator
oscillation
•FsXtal=32.768kHz
crystal oscillation
•System clock :
CF oscillation
•Internal RC
oscillation stops
•1/2 divided
•FmCF=0Hz
(The oscillation
stops)
•FsXtal=32.768kHz
crystal oscillation
•System clock :
RC oscillation
•1/2 divided
•FmCF=0Hz
(The oscillation
stops)
•FsXtal=32.768kHz
crystal oscillation
•System clock :
32.768kHz
•Internal RC
oscillation stops
•1/2 divided
Ratings
typ.
14
max.
33
4.5 to 6.0
6
18
4.5 to 6.0
4
13
4.5 to 6.0
3
10
VDD[V]
4.5 to 6.0
min.
unit
mA
Continue.
No.6689-16/22
LC86P6449
Parameter
Symbol
Current dissipation
IDDHALT(1)
in HALT mode
(Note 4)
IDDHALT(2)
IDDHALT(3)
IDDHALT(4)
Current dissipation
IDDHOLD(1)
in HOLD mode
(Note 4)
Pins
Conditions
•HALT mode
•FmCF=6MHz
Ceramic resonator
oscillation
•FsXtal=32.768kHz
crystal oscillation
•System clock :
CF oscillation
•Internal RC
oscillation stops
•1/1 divided
•HALT mode
•FmCF=3MHz
Ceramic resonator
oscillation
•FsXtal=32.768kHz
crystal oscillation
•System clock :
CF oscillation
•Internal RC
oscillation stops
•1/2 divided
•HALT mode
FmCF=0Hz
(The oscillation
stops)
•FsXtal=32.768kHz
crystal oscillation
•System clock :
RC oscillation
•1/2 divided
•HALT mode
FmCF=0Hz
(The oscillation
stops)
•FsXtal=32.768kHz
crystal oscillation
•System clock :
crystal oscillation
•Internal RC
oscillation stops
•1/2 divided
HOLD mode
Ratings
typ.
5
max.
14
4.5 to 6.0
2.2
7
4.5 to 6.0
400
1600
4.5 to 6.0
25
100
4.5 to 6.0
0.05
30
VDD[V]
4.5 to 6.0
min.
unit
mA
µA
(Note 4) The currents of the output transistors and the pull-up MOS transistors are ignored.
No.6689-17/22
LC86P6449
Table 1. Ceramic resonator oscillation recommended constant (main-clock)
Oscillation type
Maker
Oscillator
6MHz ceramic resonator
Murata
oscillation
Kyocera
3MHz ceramic resonator
Murata
oscillation
Kyocera
* Both C1 and C2 must be use K rank (±10%) and SL characteristics.
C1
on chip
on chip
Table 2. Crystal oscillation guaranteed constant (sub-clock)
Oscillation type
Maker
Oscillator
C3
32.768kHz crystal
oscillation
* Both C3 and C4 must be use J rank (±5%) and CH characteristics.
(Not in need of high precision, use K rank (±10%) and SL characteristics.)
(Notes)
C2
C4
Rd
• Please place the oscillation-related parts as close to the oscillation pins as possible with the shortest
possible pattern length since the circuit pattern affects the oscillation frequency.
• If you use other oscillators herein, we provide no guarantee for the characteristics.
CF1
CF2
XT1
XT2
Rd
CF
C1
Figure 1
C2
Main-clock circuit
Ceramic resonator oscillation
X’tal
C3
Figure 2
C4
Sub-clock circuit
Crystal oscillation
No.6689-18/22
LC86P6449
VDD
VDD limit
0V
Power supply
Reset time
RES
Internal RC
resonator oscillation
tmsCF
CF1, CF2
tssXtal
XT1, XT2
Operation mode
Unfixed
Instruction
execution
mode
OCR6=1
Reset
Instruction execution mode
<Reset time and oscillation stable time>
HOLD release signal
Valid
Internal RC
resonator oscillation
tmsCF
CF1, CF2
tssXtal
XT1, XT2
Operation mode
HOLD
Instruction execution mode
<HOLD release signal and oscillation stable time>
Figure 3
Oscillation stable time
No.6689-19/22
LC86P6449
VDD
RRES
(Note) Fix the value of CRES, RRES that is
sure to reset until 200µs, after Power
supply has been over inferior limit of
supply voltage.
RES
CRES
Figure 4
Reset circuit
0.5VDD
<AC timing point>
VDD
tCKCY
tCKL
tCKH
SCK0
SCK1
1kΩ
tICK
tCKI
SI0
SI1
tCKO
50pF
SO0, SO1
SB0, SB1
<Timing>
Figure 5
<Test load>
Serial input / output test condition
tPIL
Figure 6
tPIH
Pulse input timing condition
No.6689-20/22
LC86P6449
Notice for use
• The construction of the one-time programmable microcomputer with a blank built-in PROM makes it impossible for Sanyo to
completely factory-test it before shipping. To probe reliability of the programmed devices, the screening procedure shown
in the following figure should always be followed.
• It is not possible to perform a writing test on the blank PROM.
100% yield, therefore, cannot be guaranteed.
• Keeping the dry packing
The environment must be held at a temperature of 30°C or less and a humidity level of 70% or less.
• After opening the packing
The preparation procedures shown in the following figure should always be followed prior to mounting the packages on the
substrate. After opening the packing, a controlled environment must be maintained until soldering. The environment
must be held at a temperature of 30°C or less and a humidity level of 70% or less. Please solder within 96 hours.
Unused devices should be kept in the dry atmosphere such as inside of desiccator or dry these up before assembling on the
board.
a. Shipping with a blank PROM
(Programming the data by yourself)
DIP
Writing data for program/Verifying
b. Shipping with a programmed PROM
(Programming the data by Sanyo)
QFP
Mounting
Recommended process of screening
Heat-soak
150±5°C, 24 +1
-0 Hr
Reading ascertation of program
VDD=5±0.5V
Mounting
No.6689-21/22
LC86P6449
memo:
PS No.6689-22/22