CY28410-2 Clock Generator for Intel Grantsdale Chipset Features • 33-MHz PCI clock • Low-voltage frequency select input • Compliant with Intel CK410 • I2C support with readback capabilities • Supports Intel P4 and Tejas CPU • Ideal Lexmark Spread Spectrum profile for maximum electromagnetic interference (EMI) reduction • Selectable CPU frequencies • Differential CPU clock pairs • 3.3V power supply • 100-MHz differential SRC clocks • 56-pin SSOP and TSSOP packages • 96-MHz differential dot clock • 48-MHz USB clocks Block Diagram XIN XOUT XTAL OSC PLL1 SRC PCI REF DOT96 USB_48 x6 / x7 x9 x1 x1 x1 Pin Configuration VDD_REF REF PLL Ref Freq Divider Network IREF PD PLL2 I2C Logic 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 CY28410 VDD_PCI VSS_PCI PCI3 VDD_CPU PCI4 CPUT[0:1], CPUC[0:1], CPU(T/C)2_ITP] PCI5 VDD_SRC VSS_PCI SRCT[1:6], SRCC[1:6] VDD_PCI PCIF0/ITP_EN PCIF1 PCIF2 VDD_PCI VDD_48 PCI[0:5] USB_48 VDD_PCIF PCIF[0:2] VSS_48 DOT96T DOT96C VDD_48 MHz FS_B/TEST_MODE DOT96T VTT_PWRGD#/PD DOT96C FS_A USB_48 SRCT1 SRCC1 VDD_SRC SRCT2 SRCC2 SRCT3 SRCC3 SRC4-SATAT SRC4_SATAC VDD_SRC FS_[C:A] VTT_PWRGD# SDATA SCLK CPU x2 / x3 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 PCI2 PCI1 PCI0 FS_C/TEST_SEL REF VSS_REF XIN XOUT VDD_REF SDATA SCLK VSS_CPU CPUT0 CPUC0 VDD_CPU CPUT1 CPUC1 IREF VSSA VDDA CPUT2_ITP/SRCT7 CPUC2_ITP/SRCC7 VDD_SRC SRCT6 SRCC6 SRCT5 SRCC5 VSS_SRC 56 SSOP/TSSOP Cypress Semiconductor Corporation Document #: 38-07747 Rev *.* • 3901 North First Street • San Jose, CA 95134 • 408-943-2600 Revised March 1, 2005 CY28410-2 Pin Definitions Pin No. Name Type Description 44,43,41,40 CPUT/C 36,35 CPUT2_ITP/SRCT7, O, DIF Selectable Differential CPU or SRC clock output. CPUC2_ITP/SRCC7 ITP_EN = 0 @ VTT_PWRGD# assertion = SRC7 ITP_EN = 1 @ VTT_PWRGD# assertion = CPU2 O, DIF Differential CPU clock outputs. 14,15 DOT96T, DOT96C 18 FS_A I 3.3V tolerant input for CPU frequency selection. Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications. 16 FS_B/TEST_MODE I 3.3V tolerant input for CPU frequency selection. Selects Ref/N or Hi-Z when in test mode 0 = Hi-Z,1 = Ref/N Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications. 53 FS_C/TEST_SEL I 3.3V tolerant input for CPU frequency selection. Selects test mode if pulled to VIHFS_C when VTT_PWRGD# is asserted LOW. Refer to DC Electrical Specifications table for VILFS_C,VIMFS_C,VIHFS_C specifications. 39 IREF I A Precision resistor is attached to this pin, which is connected to the internal current reference. 54,55,56,3,4,5 PCI O, DIF Fixed 96-MHz clock output. O, SE 33-MHz clocks. 9,10 PCIF O, SE 33-MHz clocks. 8 PCIF0/ITP_EN I/O, SE 33-MHz clock/CPU2 select (sampled on the VTT_PWRGD# assertion). 1 = CPU2_ITP, 0 = SRC7 52 REF O, SE Reference clock. 3.3V 14.318-MHz clock output. 46 SCLK I 47 SDATA I/O 26,27 SRC4_SATAT, SRC4_SATAC SMBus-compatible SCLOCK. SMBus-compatible SDATA. O, DIF Differential serial reference clock. Recommended output for SATA. 19,20,22,23,2 SRCT/C 4,25,31,30,33, 32 O, DIF Differential serial reference clocks. 12 USB_48 I/O, SE Fixed 48 MHz clock output. 11 VDD_48 PWR 3.3V power supply for outputs. 42 VDD_CPU PWR 3.3V power supply for outputs. 1,7 VDD_PCI PWR 3.3V power supply for outputs. 48 VDD_REF PWR 3.3V power supply for outputs. 21,28,34 VDD_SRC PWR 3.3V power supply for outputs. 37 VDDA PWR 3.3V power supply for PLL. 13 VSS_48 GND Ground for outputs. 45 VSS_CPU GND Ground for outputs. 2,6 VSS_PCI GND Ground for outputs. 51 VSS_REF GND Ground for outputs. 29 VSS_SRC GND Ground for outputs. 38 VSSA GND Ground for PLL. 17 VTT_PWRGD#/PD I, PU 3.3V LVTTL input is a level sensitive strobe used to latch the USB_48/FS_A, FS_B, FS_C/TEST_SEL and PCIF0/ITP_EN inputs. After VTT_PWRGD# (active LOW) assertion, this pin becomes a realtime input for asserting power-down (active HIGH) 50 XIN 49 XOUT Document #: 38-07747 Rev *.* I 14.318-MHz Crystal Input O, SE 14.318-MHz Crystal Output Page 2 of 17 CY28410-2 Table 1. Frequency Select Table FS_A, FS_B, and FS_C FS_C FS_B FS_A CPU SRC PCIF/PCI REF0 DOT96 USB MID 0 1 100 MHz 100 MHz 33 MHz 14.318 MHz 96 MHz 48 MHz 0 0 1 133 MHz 100 MHz 33 MHz 14.318 MHz 96 MHz 48 MHz 0 1 0 200 MHz 100 MHz 33 MHz 14.318 MHz 96 MHz 48 MHz 0 0 0 266 MHz 100 MHz 33 MHz 14.318 MHz 96 MHz 48 MHz 1 0 x Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z 1 1 0 REF/2 REF/8 REF/24 REF REF REF 1 1 1 REF/2 REF/8 REF/24 REF REF REF Frequency Select Pins (FS_A, FS_B, and FS_C) Host clock frequency selection is achieved by applying the appropriate logic levels to FS_A, FS_B, FS_C inputs prior to VTT_PWRGD# assertion (as seen by the clock synthesizer). Upon VTT_PWRGD# being sampled LOW by the clock chip (indicating processor VTT voltage is stable), the clock chip samples the FS_A, FS_B, and FS_C input values. For all logic levels of FS_A, FS_B, and FS_C, VTT_PWRGD# employs a one-shot functionality in that once a valid LOW on VTT_PWRGD# has been sampled, all further VTT_PWRGD#, FS_A, FS_B, and FS_C transitions will be ignored, except in test mode. Serial Data Interface To enhance the flexibility and function of the clock synthesizer, a two-signal serial interface is provided. Through the Serial Data Interface, various device functions, such as individual clock output buffers, can be individually enabled or disabled. The registers associated with the Serial Data Interface Table 2. Command Code Definition Bit 7 (6:0) initialize to their default setting upon power-up, and therefore use of this interface is optional. Clock device register changes are normally made upon system initialization, if any are required. The interface cannot be used during system operation for power management functions. Data Protocol The clock driver serial protocol accepts byte write, byte read, block write, and block read operations from the controller. For block write/read operation, the bytes must be accessed in sequential order from lowest to highest byte (most significant bit first) with the ability to stop after any complete byte has been transferred. For byte write and byte read operations, the system controller can access individually indexed bytes. The offset of the indexed byte is encoded in the command code, as described in Table 2. The block write and block read protocol is outlined in Table 3 while Table 4 outlines the corresponding byte write and byte read protocol. The slave receiver address is 11010010 (D2h). Description 0 = Block read or block write operation, 1 = Byte read or byte write operation Byte offset for byte read or byte write operation. For block read or block write operations, these bits should be '0000000' Table 3. Block Read and Block Write Protocol Block Write Protocol Bit 1 8:2 Description Start Slave address – 7 bits 9 Write 10 18:11 19 27:20 28 36:29 37 45:38 46 Block Read Protocol Bit 1 8:2 Description Start Slave address – 7 bits 9 Write Acknowledge from slave 10 Acknowledge from slave Command Code – 8 bits 18:11 Command Code – 8 bits Acknowledge from slave 19 Acknowledge from slave Byte Count – 8 bits (Skip this step if I2C_EN bit set) 20 Repeat start Acknowledge from slave 27:21 Slave address – 7 bits Data byte 1 – 8 bits 28 Read = 1 Acknowledge from slave 29 Acknowledge from slave Data byte 2 – 8 bits Acknowledge from slave Document #: 38-07747 Rev *.* 37:30 38 Byte Count from slave – 8 bits Acknowledge Page 3 of 17 CY28410-2 Table 3. Block Read and Block Write Protocol (continued) Block Write Protocol Bit Description .... Data Byte / Slave Acknowledges .... Data Byte N – 8 bits .... Acknowledge from slave .... Stop Block Read Protocol Bit 46:39 47 55:48 Description Data byte 1 from slave – 8 bits Acknowledge Data byte 2 from slave – 8 bits 56 Acknowledge .... Data bytes from slave / Acknowledge .... Data Byte N from slave – 8 bits .... NOT Acknowledge .... Stop Table 4. Byte Read and Byte Write Protocol Byte Write Protocol Bit 1 8:2 Description Start Byte Read Protocol Bit 1 Slave address – 7 bits 8:2 Description Start Slave address – 7 bits 9 Write 9 Write 10 Acknowledge from slave 10 Acknowledge from slave 18:11 Command Code – 8 bits 18:11 Command Code – 8 bits 19 Acknowledge from slave 19 Acknowledge from slave 27:20 Data byte – 8 bits 20 28 Acknowledge from slave 29 Stop 27:21 Repeated start Slave address – 7 bits 28 Read 29 Acknowledge from slave 37:30 Data from slave – 8 bits 38 NOT Acknowledge 39 Stop Control Registers Byte 0:Control Register 0 Bit @Pup Name 7 1 CPUT2_ITP/SRCT7 CPUC2_ITP/SRCC7 6 1 SRC[T/C]6 SRC[T/C]6 Output Enable 0 = Disable (Hi-Z), 1 = Enable 5 1 SRC[T/C]5 SRC[T/C]5 Output Enable 0 = Disable (Hi-Z), 1 = Enable 4 1 SRC[T/C]4 SRC[T/C]4 Output Enable 0 = Disable (Hi-Z), 1 = Enable 3 1 SRC[T/C]3 SRC[T/C]3 Output Enable 0 = Disable (Hi-Z), 1 = Enable 2 1 SRC[T/C]2 SRC[T/C]2 Output Enable 0 = Disable (Hi-Z), 1 = Enable 1 1 SRC[T/C]1 SRC[T/C]1 Output Enable 0 = Disable (Hi-Z), 1 = Enable 0 1 Reserved Reserved, Set = 1 Document #: 38-07747 Rev *.* Description CPU[T/C]2_ITP/SRC[T/C]7 Output Enable 0 = Disable (Hi-Z), 1 = Enable Page 4 of 17 CY28410-2 Byte 1: Control Register 1 Bit @Pup Name Description 7 1 PCIF0 6 1 DOT_96T/C 5 1 USB_48 4 1 REF 3 0 CPU PLL Spread Percentage 2 1 CPU[T/C]1 CPU[T/C]1 Output Enable 0 = Disable (Hi-Z), 1 = Enabled 1 1 CPU[T/C]0 CPU[T/C]0 Output Enable 0 = Disable (Hi-Z), 1 = Enabled 0 0 CPUT/C SRCT/C PCIF PCI PCIF0 Output Enable 0 = Disabled, 1 = Enabled DOT_96 MHz Output Enable 0 = Disable (Hi-Z), 1 = Enabled USB_48 MHz Output Enable 0 = Disabled, 1 = Enabled REF Output Enable 0 = Disabled, 1 = Enabled Select CPU PLL Spread Percentage 0: –0.5% Downspread 1:±0.25% Centerspread Spread Spectrum Enable 0 = Spread off, 1 = Spread on Byte 2: Control Register 2 Bit @Pup Name 7 1 PCI5 PCI5 Output Enable 0 = Disabled, 1 = Enabled Description 6 1 PCI4 PCI4 Output Enable 0 = Disabled, 1 = Enabled 5 1 PCI3 PCI3 Output Enable 0 = Disabled, 1 = Enabled 4 1 PCI2 PCI2 Output Enable 0 = Disabled, 1 = Enabled 3 1 PCI1 PCI1 Output Enable 0 = Disabled, 1 = Enabled 2 1 PCI0 PCI0 Output Enable 0 = Disabled, 1 = Enabled 1 1 PCIF2 PCIF2 Output Enable 0 = Disabled, 1 = Enabled 0 1 PCIF1 PCIF1 Output Enable 0 = Disabled, 1 = Enabled Byte 3: Control Register 3 Bit @Pup Name 7 0 SRC7 Allow control of SRC[T/C]7 with assertion of SW PCI_STP# 0 = Free running, 1 = Stopped with SW PCI_STP# 6 0 SRC6 Allow control of SRC[T/C]6 with assertion of SW PCI_STP# 0 = Free running, 1 = Stopped with SW PCI_STP# 5 0 SRC5 Allow control of SRC[T/C]5 with assertion of SW PCI_STP# 0 = Free running, 1 = Stopped with SW PCI_STP# 4 0 SRC4 Allow control of SRC[T/C]4 with assertion of SW PCI_STP# 0 = Free running, 1 = Stopped with SW PCI_STP# 3 0 SRC3 Allow control of SRC[T/C]3 with assertion of SW PCI_STP# 0 = Free running, 1 = Stopped with SW PCI_STP# Document #: 38-07747 Rev *.* Description Page 5 of 17 CY28410-2 Byte 3: Control Register 3 (continued) Bit @Pup Name Description 2 0 SRC2 Allow control of SRC[T/C]2 with assertion of SW PCI_STP# 0 = Free running, 1 = Stopped with SW PCI_STP# 1 0 SRC1 Allow control of SRC[T/C]1 with assertion of SW PCI_STP# 0 = Free running, 1 = Stopped with SW PCI_STP# 0 0 Reserved Reserved, Set = 0 Byte 4: Control Register 4 Bit @Pup Name 7 0 Reserved Description 6 0 DOT96[T/C] 5 0 PCIF2 Allow control of PCIF2 with assertion of SW PCI_STP# 0 = Free running, 1 = Stopped with SW PCI_STP# 4 0 PCIF1 Allow control of PCIF1 with assertion of SW PCI_STP# 0 = Free running, 1 = Stopped with SW PCI_STP# 3 0 PCIF0 Allow control of PCIF0 with assertion of SW PCI_STP# 0 = Free running, 1 = Stopped with SW PCI_STP# 2 1 Reserved Reserved, Set = 1 1 1 Reserved Reserved, Set = 1 0 1 Reserved Reserved, Set = 1 Reserved, Set = 0 DOT_PWRDWN Drive Mode 0 = Driven in PWRDWN, 1 = Hi-Z Byte 5: Control Register 5 Bit @Pup Name Description 7 0 SRC[T/C][7:0] 6 0 Reserved Reserved, Set = 0 5 0 Reserved Reserved, Set = 0 4 0 Reserved Reserved, Set = 0 3 0 SRC[T/C][7:0] SRC[T/C] PWRDWN Drive Mode 0 = Driven when PD asserted,1 = Hi-Z when PD asserted 2 0 CPU[T/C]2 CPU[T/C]2 PWRDWN Drive Mode 0 = Driven when PD asserted,1 = Hi-Z when PD asserted 1 0 CPU[T/C]1 CPU[T/C]1 PWRDWN Drive Mode 0 = Driven when PD asserted,1 = Hi-Z when PD asserted 0 0 CPU[T/C]0 CPU[T/C]0 PWRDWN Drive Mode 0 = Driven when PD asserted,1 = Hi-Z when PD asserted SRC[T/C] Stop Drive Mode 0 = Driven when SW PCI_STP# asserted,1 = Hi-Z when PCI_STP# asserted Byte 6: Control Register 6 Bit @Pup 7 0 REF/N or Hi-Z Select 1 = REF/N Clock, 0 = Hi-Z 6 0 Test Clock Mode Entry Control 1 = REF/N or Hi-Z mode, 0 = Normal operation 5 0 Reserved 4 1 REF Document #: 38-07747 Rev *.* Name Description Reserved, Set = 0 REF Output Drive Strength 0 = Low, 1 = High Page 6 of 17 CY28410-2 Byte 6: Control Register 6 (continued) Bit @Pup Name Description 3 1 PCIF, SRC, PCI SW PCI_STP# Function 0=SW PCI_STP assert, 1 = SW PCI_STP deassert When this bit is set to 0, all STOPPABLE PCI, PCIF and SRC outputs will be stopped in a synchronous manner with no short pulses. When this bit is set to 1, all STOPPED PCI, PCIF and SRC outputs will resume in a synchronous manner with no short pulses. 2 Externally selected CPUT/C FS_C. Reflects the value of the FS_C pin sampled on power-up 0 = FS_C was low during VTT_PWRGD# assertion 1 Externally selected CPUT/C FS_B. Reflects the value of the FS_B pin sampled on power-up 0 = FS_B was low during VTT_PWRGD# assertion 0 Externally selected CPUT/C FS_A. Reflects the value of the FS_A pin sampled on power-up 0 = FS_A was low during VTT_PWRGD# assertion Byte 7: Vendor ID Bit @Pup Name Description 7 0 Revision Code Bit 3 Revision Code Bit 3 6 0 Revision Code Bit 2 Revision Code Bit 2 5 1 Revision Code Bit 1 Revision Code Bit 1 4 0 Revision Code Bit 0 Revision Code Bit 0 3 1 Vendor ID Bit 3 Vendor ID Bit 3 2 0 Vendor ID Bit 2 Vendor ID Bit 2 1 0 Vendor ID Bit 1 Vendor ID Bit 1 0 0 Vendor ID Bit 0 Vendor ID Bit 0 Crystal Recommendations The CY28410-2 requires a Parallel Resonance Crystal. Substituting a series resonance crystal will cause the CY28410-2 to operate at the wrong frequency and violate the ppm specification. For most applications there is a 300-ppm frequency shift between series and parallel crystals due to incorrect loading. Figure 1 shows a typical crystal configuration using the two trim capacitors. An important clarification for the following discussion is that the trim capacitors are in series with the crystal not parallel. It’s a common misconception that load capacitors are in parallel with the crystal and should be approximately equal to the load capacitance of the crystal. This is not true. Crystal Loading Crystal loading plays a critical role in achieving low ppm performance. To realize low ppm performance, the total capacitance the crystal will see must be considered to calculate the appropriate capacitive loading (CL). Figure 1. Crystal Capacitive Clarification Table 5. Crystal Recommendations Frequency (Fund) Cut Loading Load Cap Drive (max.) Shunt Cap (max.) Motional (max.) Tolerance (max.) Stability (max.) Aging (max.) 14.31818 MHz AT Parallel 0.1 mW 5 pF 0.016 pF 35 ppm 30 ppm 5 ppm Document #: 38-07747 Rev *.* 20 pF Page 7 of 17 CY28410-2 Calculating Load Capacitors PD (Power-down) Clarification In addition to the standard external trim capacitors, trace capacitance and pin capacitance must also be considered to correctly calculate crystal loading. As mentioned previously, the capacitance on each side of the crystal is in series with the crystal. This means the total capacitance on each side of the crystal must be twice the specified crystal load capacitance (CL). While the capacitance on each side of the crystal is in series with the crystal, trim capacitors (Ce1,Ce2) should be calculated to provide equal capacitive loading on both sides. The VTT_PWRGD# /PD pin is a dual-function pin. During initial power-up, the pin functions as VTT_PWRGD#. Once VTT_PWRGD# has been sampled LOW by the clock chip, the pin assumes PD functionality. The PD pin is an asynchronous active HIGH input used to shut off all clocks cleanly prior to shutting off power to the device. This signal is synchronized internal to the device prior to powering down the clock synthesizer. PD is also an asynchronous input for powering up the system. When PD is asserted HIGH, all clocks are driven to a low value and held prior to turning off the VCOs and the crystal oscillator. Clock Chip PD (Power-down) – Assertion Ci2 Ci1 Pin 3 to 6p X2 X1 Cs1 Cs2 Trace 2.8pF XTAL Ce1 Ce2 Trim 33pF Figure 2. Crystal Loading Example As mentioned previously, the capacitance on each side of the crystal is in series with the crystal. This means the total capacitance on each side of the crystal must be twice the specified load capacitance (CL). While the capacitance on each side of the crystal is in series with the crystal, trim capacitors (Ce1,Ce2) should be calculated to provide equal capacitance loading on both sides. Use the following formulas to calculate the trim capacitor values for Ce1 and Ce2. Load Capacitance (each side) When PD is sampled HIGH by two consecutive rising edges of CPUC, all single-ended outputs will be held LOW on their next HIGH-to-LOW transition and differential clocks must be held HIGH or Hi-Z (depending on the state of the control register drive mode bit) on the next diff clock# HIGH-to-LOW transition within 4 clock periods. When the SMBus PD drive mode bit corresponding to the differential (CPU, SRC, and DOT) clock output of interest is programmed to ‘0’, the clock output must be held with “Diff clock” pin driven HIGH at 2 x Iref, and “Diff clock#” tri-state. If the control register PD drive mode bit corresponding to the output of interest is programmed to “1”, then both the “Diff clock” and the “Diff clock#” are Hi-Z. Note the example below shows CPUT = 133 MHz and PD drive mode = ‘1’ for all differential outputs. Figure 3 and this description is applicable to valid CPU frequencies 100, 133, 166, 200, 266, 333, and 400 MHz. In the event that PD mode is desired as the initial power-on state, PD must be asserted high in less than 10 µs after asserting VTT_PWRGD#. PD Deassertion The power-up latency is less than 1.8 ms. This is the time from the deassertion of the PD pin or the ramping of the power supply until the time that stable clocks are output from the clock chip. All differential outputs stopped in a three-state condition resulting from power-down must be driven HIGH in less than 300 µs of PD deassertion to a voltage greater than 200 mV. After the clock chip’s internal PLL is powered up and locked, all outputs are enabled within a few clock cycles of Ce = 2 * CL – (Cs + Ci) Total Capacitance (as seen by the crystal) CLe = 1 1 ( Ce1 + Cs1 + Ci1 + 1 Ce2 + Cs2 + Ci2 ) CL ................................................... Crystal load capacitance CLe .........................................Actual loading seen by crystal using standard value trim capacitors Ce .....................................................External trim capacitors Cs.............................................. Stray capacitance (terraced) Ci ........................................................... Internal capacitance (lead frame, bond wires etc.) Document #: 38-07747 Rev *.* Page 8 of 17 CY28410-2 each other. Figure 4 is an example showing the relationship of clocks coming up. PD CPUT, 133MHz CPUC, 133MHz SRCT 100MHz SRCC 100MHz USB, 48MHz DOT96T DOT96C PCI, 33 MHz REF Figure 3. Power-down Assertion Timing Waveform Tstable <1.8nS PD CPUT, 133MHz CPUC, 133MHz SRCT 100MHz SRCC 100MHz USB, 48MHz DOT96T DOT96C PCI, 33MHz REF Tdrive_PW RDN# <300µS, >200mV Figure 4. Power-down Deassertion Timing Waveform Document #: 38-07747 Rev *.* Page 9 of 17 CY28410-2 FS_A, FS_B,FS_C VTT_PW RGD# PW RGD_VRM 0.2-0.3mS Delay VDD Clock Gen Clock State Clock Outputs Clock VCO State 0 W ait for VTT_PW RGD# Device is not affected, VTT_PW RGD# is ignored Sample Sels State 1 State 2 Off State 3 On On Off Figure 5. VTT_PWRGD# Timing Diagram S2 S1 D elay >0.25m S VTT_PW R G D# = Low S am ple Inputs straps VDD _A = 2.0V W ait for <1.8m s S0 S3 VD D_A = off P ow er O ff N orm al O peration Enable O utputs VTT_PW RG D # = toggle Figure 6. Clock Generator Power-up/Run State Diagram Absolute Maximum Conditions Parameter Description Condition Min. Max. Unit –0.5 4.6 V VDD Core Supply Voltage VDD_A Analog Supply Voltage –0.5 4.6 V VIN Input Voltage Relative to VSS –0.5 VDD + 0.5 VDC TS Temperature, Storage Non-functional –65 150 °C TA Temperature, Operating Ambient Functional 0 70 °C TJ Temperature, Junction Functional – ØJC Dissipation, Junction to Case (Mil-Spec 883E Method 1012.1) SSOP 39.56 TSSOP 20.62 ØJA Dissipation, Junction to Ambient JEDEC (JESD 51) SSOP 45.29 ESDHBM ESD Protection (Human Body Model) MIL-STD-883, Method 3015 UL-94 Flammability Rating At 1/8 in. MSL Moisture Sensitivity Level Document #: 38-07747 Rev *.* TSSOP 150 °C °C/W °C/W 62.26 2000 – V V–0 1 Page 10 of 17 CY28410-2 Absolute Maximum Conditions Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required. DC Electrical Specifications Parameter Description Condition Min. Max. Unit 3.135 3.465 V – 1.0 V 2.2 – V VSS – 0.3 0.35 V 3.3V Operating Voltage VDD_A, VDD_REF, VDD_PCI, VDD_3V66, VDD_48, VDD_CPU 3.3 ± 5% VILI2C Input Low Voltage SDATA, SCLK VIHI2C Input High Voltage SDATA, SCLK VIL_FS FS_A/FS_B Input Low Voltage 0.7 VDD + 0.5 V 0 0.35 V VIH_FS FS_A/FS_B Input High Voltage VILFS_C FS_C Low Range VIMFS_C FS_C Mid Range 0.7 1.7 V VIH FS_C FS_C High Range 2.1 VDD V VIL Input Low Voltage VSS – 0.5 0.8 V VIH Input High Voltage 2.0 VDD + 0.5 V IIL Input Low Leakage Current except internal pull-up resistors, 0 < VIN < VDD IIH Input High Leakage Current except internal pull-down resistors, 0 < VIN < VDD µA –5 5 µA VOL Output Low Voltage IOL = 1 mA VOH Output High Voltage IOH = –1 mA IOZ High-impedance Output Current CIN Input Pin Capacitance COUT Output Pin Capacitance 3 6 pF LIN Pin Inductance – 7 nH – 0.4 V 2.4 – V –10 10 µA 2 5 pF VXIH Xin High Voltage 0.7VDD VDD V VXIL Xin Low Voltage 0 0.3VDD V IDD3.3V Dynamic Supply Current At max load and freq per Figure 7 – 550 mA IPD3.3V Power-down Supply Current PD asserted, Outputs driven – 70 mA IPD3.3V Power-down Supply Current PD asserted, Outputs Hi-Z – 2 mA Condition Min. Max. Unit AC Electrical Specifications Parameter Description Crystal TDC XIN Duty Cycle The device will operate reliably with input duty cycles up to 30/70 but the REF clock duty cycle will not be within specification 47.5 52.5 % TPERIOD XIN Period When XIN is driven from an external clock source 69.841 71.0 ns TR / TF XIN Rise and Fall Times Measured between 0.3VDD and 0.7VDD – 10.0 ns TCCJ XIN Cycle to Cycle Jitter As an average over 1-µs duration – 500 ps LACC Long-term Accuracy Over 150 ms – 300 ppm CPU at 0.7V TDC CPUT and CPUC Duty Cycle Measured at crossing point VOX 43 57 % TPERIOD 100-MHz CPUT and CPUC Period Measured at crossing point VOX Document #: 38-07747 Rev *.* 9.997001 10.00300 ns Page 11 of 17 CY28410-2 AC Electrical Specifications (continued) Parameter Description Condition Min. Max. Unit TPERIOD 133-MHz CPUT and CPUC Period Measured at crossing point VOX 7.497751 7.502251 TPERIOD 200-MHz CPUT and CPUC Period Measured at crossing point VOX 4.998500 5.001500 ns TPERIOD 266-MHz CPUT and CPUC Period Measured at crossing point VOX 3.748875 3.751125 ns TPERIODSS 100-MHz CPUT and CPUC Period, SSC Measured at crossing point VOX 9.997001 10.05327 ns TPERIODSS 133-MHz CPUT and CPUC Period, SSC Measured at crossing point VOX 7.497751 7.539950 ns TPERIODSS 200-MHz CPUT and CPUC Period, SSC Measured at crossing point VOX 4.998500 5.026634 ns TPERIODSS 266-MHz CPUT and CPUC Period, SSC Measured at crossing point VOX 3.748875 3.769975 ns TPERIODAbs 100-MHz CPUT and CPUC Absolute Measured at crossing point VOX period 9.912001 10.08800 ns TPERIODAbs 133-MHz CPUT and CPUC Absolute Measured at crossing point VOX period 7.412751 7.587251 ns TPERIODSSAbs 100-MHz CPUT and CPUC Absolute Measured at crossing point VOX period, SSC 9.912001 10.13827 ns TPERIODSSAbs 133-MHz CPUT and CPUC Absolute Measured at crossing point VOX period, SSC 7.412751 7.624950 ns TPERIODSSAbs 200-MHz CPUT and CPUC Absolute Measured at crossing point VOX period, SSC 4.913500 5.111634 ns TPERIODSSAbs 266-MHz CPUT and CPUC Absolute Measured at crossing point VOX period, SSC 3.663875 3.854975 ns TPERIODSSAbs 400-MHz CPUT and CPUC Absolute Measured at crossing point VOX period, SSC 2.414250 2.598317 ns ns TSKEW Any CPUT/C to CPUT/C Clock Skew, Measured at crossing point VOX SSC – 100 ps TCCJ2 CPU2_ITP Cycle to Cycle Jitter Measured at crossing point VOX – 125 ps TCCJ CPUT/C Cycle to Cycle Jitter Measured at crossing point VOX – 115 ps TSKEW2 CPU2_ITP to CPU0 Clock Skew Measured at crossing point VOX TR / TF CPUT and CPUC Rise and Fall Times Measured from VOL = 0.175 to VOH = 0.525V TRFM Rise/Fall Matching ∆TR Rise Time Variation ∆TF Fall Time Variation VHIGH Voltage High Math averages Figure 7 Math averages Figure 7 –150 – mV 250 550 mV – VHIGH + 0.3 V –0.3 – V – 0.2 V 45 55 Determined as a fraction of 2*(TR – TF)/(TR + TF) – 150 ps 175 1100 ps – 20 % – 125 ps – 125 ps 660 850 mV VLOW Voltage Low VOX Crossing Point Voltage at 0.7V Swing VOVS Maximum Overshoot Voltage VUDS Minimum Undershoot Voltage VRB Ring Back Voltage See Figure 7. Measure SE SRC TDC SRCT and SRCC Duty Cycle Measured at crossing point VOX TPERIOD 100-MHz SRCT and SRCC Period Measured at crossing point VOX 9.997001 10.00300 ns TPERIODSS 100-MHz SRCT and SRCC Period, SSC Measured at crossing point VOX 9.997001 10.05327 ns Document #: 38-07747 Rev *.* % Page 12 of 17 CY28410-2 AC Electrical Specifications (continued) Parameter TPERIODAbs Description Condition Min. Max. Unit 100-MHz SRCT and SRCC Absolute Measured at crossing point VOX Period 10.12800 9.872001 ns TPERIODSSAbs 100-MHz SRCT and SRCC Absolute Measured at crossing point VOX Period, SSC 9.872001 10.17827 ns TSKEW SRC Skew Measured at crossing point VOX – 250 TCCJ LACC TR / TF SRCT and SRCC Rise and Fall Times Measured from VOL = 0.175 to VOH = 0.525V TRFM Rise/Fall Matching SRCT/C Cycle to Cycle Jitter Measured at crossing point VOX – 125 ps SRCT/C Long Term Accuracy Measured at crossing point VOX – 300 ppm 175 1100 ps – 20 % Determined as a fraction of 2*(TR – TF)/(TR + TF) ps ∆TR Rise Time Variation – 125 ps ∆TF Fall Time Variation – 125 ps VHIGH Voltage High Math averages Figure 7 660 850 mV VLOW Voltage Low Math averages Figure 7 –150 – mV VOX Crossing Point Voltage at 0.7V Swing 250 550 mV VOVS Maximum Overshoot Voltage – VHIGH + 0.3 V VUDS Minimum Undershoot Voltage –0.3 – V VRB Ring Back Voltage See Figure 7. Measure SE – 0.2 V PCI/PCIF TDC PCI Duty Cycle Measurement at 1.5V 45 55 % TPERIOD Spread Disabled PCIF/PCI Period Measurement at 1.5V 29.99100 30.00900 ns TPERIODSS Spread Enabled PCIF/PCI Period, SSC Measurement at 1.5V 29.9910 30.15980 ns TPERIODAbs Spread Disabled PCIF/PCI Period Measurement at 1.5V 29.49100 30.50900 ns TPERIODSSAbs Spread Enabled PCIF/PCI Period, SSC Measurement at 1.5V 29.49100 30.65980 ns THIGH PCIF and PCI high time Measurement at 2.4V 11.5 – ns TLOW PCIF and PCI low time Measurement at 0.4V 11.5 – ns TR / TF PCIF and PCI rise and fall times Measured between 0.8V and 2.0V 0.5 2.0 ns TSKEW Any PCI clock to Any PCI clock Skew Measurement at 1.5V – 500 ps TCCJ PCIF and PCI Cycle to Cycle Jitter Measurement at 1.5V – 500 ps DOT TDC DOT96T and DOT96C Duty Cycle Measured at crossing point VOX 45 55 % TPERIOD DOT96T and DOT96C Period Measured at crossing point VOX 10.41354 10.41979 ns TPERIODAbs DOT96T and DOT96C Absolute Period Measured at crossing point VOX 10.16354 10.66979 ns TCCJ DOT96T/C Cycle to Cycle Jitter Measured at crossing point VOX LACC DOT96T/C Long Term Accuracy Measured at crossing point VOX TR / TF DOT96T and DOT96C Rise and Fall Times Measured from VOL = 0.175 to VOH = 0.525V TRFM Rise/Fall Matching Determined as a fraction of 2*(TR – TF)/(TR + TF) ∆TR Rise Time Variation ∆TF Fall Time Variation VHIGH Voltage High Document #: 38-07747 Rev *.* Math averages Figure 7 – 250 ps – 100 ppm 175 1100 ps – 20 % – 125 ps – 125 ps 660 850 mV Page 13 of 17 CY28410-2 AC Electrical Specifications (continued) Parameter Description Condition VLOW Voltage Low VOX Crossing Point Voltage at 0.7V Swing VOVS Maximum Overshoot Voltage VUDS Minimum Undershoot Voltage Math averages Figure 7 Min. Max. Unit –150 – mV 250 550 mV – VHIGH + 0.3 V –0.3 – V VRB Ring Back Voltage See Figure 7. Measure SE – 0.2 V USB TDC Duty Cycle Measurement at 1.5V 45 55 % TPERIOD Period Measurement at 1.5V 20.83125 20.83542 ns TPERIODAbs Absolute Period Measurement at 1.5V 20.48125 21.18542 ns THIGH USB high time Measurement at 2.4V 8.094 10.036 ns TLOW USB low time Measurement at 0.4V 7.694 9.836 ns TR / TF Rise and Fall Times Measured between 0.8V and 2.0V 0.475 1.4 ns TCCJ Cycle to Cycle Jitter Measurement at 1.5V – 350 ps LACC USB Long Term Accuracy – 100 ppm REF TDC REF Duty Cycle Measurement at 1.5V 45 55 % TPERIOD REF Period Measurement at 1.5V 69.8203 69.8622 ns TPERIODAbs REF Absolute Period Measurement at 1.5V 68.82033 70.86224 ns TR / TF REF Rise and Fall Times Measured between 0.8V and 2.0V TCCJ REF Cycle to Cycle Jitter Measurement at 1.5V ENABLE/DISABLE and SET-UP TSTABLE Clock Stabilization from Power-up TSS Stopclock Set-up Time TSH Stopclock Hold Time 0.35 2.0 V/ns – 1000 ps – 1.8 ms 10.0 – ns 0 – ns Test and Measurement Set-up For Differential CPU, SRC and DOT96 Output Signals The following diagram shows the test load configuration for the differential CPU and SRC outputs. CPUT SRCT D O T96T CPUC SRCC D O T96C IR E F M e a s u re m e n t P o in t 33Ω 4 9 .9 Ω 2pF 1 0 0 Ω D iff e r e n tia l M e a s u re m e n t P o in t 33Ω 4 9 .9 Ω 2pF 475Ω Figure 7. 0.7V Single-ended Load Configuration Document #: 38-07747 Rev *.* Page 14 of 17 CY28410-2 For PCI Single-ended Signals and Reference The following diagram shows the test load configurations for the single-ended PCI, USB, and REF output signals. PCI/ USB 12Ω 60Ω 12Ω 60Ω Measurement Point 5pF Measurement Point 5pF Measurement Point 60Ω 12Ω 5pF Measurement Point 60Ω 12Ω REF 5pF Measurement Point 60Ω 12Ω 5pF Figure 8. Single-ended Load Configuration 3 .3 V s ig n a l s T DC - - 3 .3 V 2 .4 V 1 .5 V 0 .4 V 0V TF TR Figure 9. Single-ended Output Signals (for AC Parameters Measurement) Ordering Information Part Number Package Type Product Flow Lead-free and ROHS compliant CY28410OXC -2 56-pin SSOP Commercial, 0° to 70°C CY28410OXC -2T 56-pin SSOP – Tape and Reel Commercial, 0° to 70°C CY28410ZXC -2 56-pin TSSOP Commercial, 0° to 70°C CY28410ZXC -2T 56-pin TSSOP – Tape and Reel Commercial, 0° to 70°C Document #: 38-07747 Rev *.* Page 15 of 17 CY28410-2 Package Drawing and Dimensions 56-lead Shrunk Small Outline Package O56 51-85062-*C 56-Lead Thin Shrunk Small Outline Package, Type II (6 mm x 12 mm) Z56 0.249[0.009] 28 1 DIMENSIONS IN MM[INCHES] MIN. MAX. REFERENCE JEDEC MO-153 7.950[0.313] 8.255[0.325] PACKAGE WEIGHT 0.42gms 5.994[0.236] 6.198[0.244] PART # Z5624 STANDARD PKG. ZZ5624 LEAD FREE PKG. 29 56 13.894[0.547] 14.097[0.555] 1.100[0.043] MAX. GAUGE PLANE 0.25[0.010] 0.20[0.008] 0.851[0.033] 0.950[0.037] 0.500[0.020] BSC 0.170[0.006] 0.279[0.011] 0.051[0.002] 0.152[0.006] 0°-8° SEATING PLANE 0.508[0.020] 0.762[0.030] 0.100[0.003] 0.200[0.008] 51-85060-*C Purchase of I2C components from Cypress or one of its sublicensed Associated Companies conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. Intel and Pentium are registered trademarks of Intel Corporation. All product and company names mentioned in this document are the trademarks of their respective holders. Document #: 38-07747 Rev *.* Page 16 of 17 © Cypress Semiconductor Corporation, 2005. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. CY28410-2 Document History Page Document Title: CY28410-2 Clock Generator for Intel Grantsdale Chipset Document Number: 38-07747 REV. ECN NO. Issue Date Orig. of Change ** 331162 See ECN RGL Document #: 38-07747 Rev *.* Description of Change New Data Sheet Page 17 of 17