Zarlink MT88E43AS Extended voltage calling number identification circuit 2 Datasheet

CMOS
MT88E43
Extended Voltage Calling Number
Identification Circuit 2
Features
•
ISSUE 3
Compatible with:
Ordering Information
MT88E43AE 24 Pin Plastic DIP
(0.6 inch package only)
MT88E43AS 24 Pin SOIC
-40 °C to +85 °C
•
•
•
British Telecom (BT) SIN227 & SIN242
U.K.’s Cable Communications Association
(CCA) specification TW/P&E/312
• Bellcore GR-30-CORE (formerly known as
TR-NWT-000030) & SR-TSV-002476
Bellcore "CPE Alerting Signal (CAS)" and BT
"Idle State Tone Alert Signal" detection
•
Ring and line reversal detection
•
1200 baud Bell 202 and CCITT V.23 Frequency
Shift Keying (FSK) demodulation
•
3 or 5V ±10% supply voltage
•
High input sensitivity (-40dBV Tone and FSK
Detection)
•
Selectable 3-wire data interface
(microcontroller or MT88E43 controlled)
•
Low power CMOS with powerdown mode
•
Input gain adjustable amplifier
•
Carrier detect status output
•
Uses 3.58 MHz crystal
Applications
•
March 1997
•
Feature phones, including Analog Display
Services Interface (ADSI) phones
•
Phone set adjunct boxes
•
FAX and answering machines
•
Database query and Computer Telephony
Integration (CTI) systems
Description
The MT88E43 Calling Number Identification Circuit 2
(ECNIC2) is a low power CMOS integrated circuit
intended for receiving physical layer signals
transmitted according to BT (British Telecom)
SIN227 & SIN242, the U.K.’s CCA (Cable
Communications Association) TW/P&E/312 and
Bellcore
GR-30-CORE
&
SR-TSV-002476
specifications. The MT88E43 is suitable for
applications using a fixed voltage power source
between 3 and 5V ±10%.
BT Calling Line Identity Presentation (CLIP),
CCA CLIP, and Bellcore Calling Identity
Delivery (CID) systems
MODE
FSKen
IN+
INGS
VRef
+
-
Anti-alias
Filter
FSK Bandpass
Filter
FSK
Demodulator
Data Timing
Recovery
To internal
cct.
CAP
PWDN
Interrupt
Generator
Alert Signal High
Tone Filter
Tone
Detection
Algorithm
To internal cct.
Alert Signal Low
Tone Filter
Guard
Time
INT
StD
St/GT
ESt
Oscillator
OSCin OSCout TRIGin
CD
Carrier
Detector
Bias
Generator
DCLK
DATA
DR
VDD
VSS
TRIGRC
TRIGout
Figure 1- Functional Block Diagram
5-53
MT88E43
Data Sheet
IN+
INGS
VRef
CAP
TRIGin
TRIGRC
TRIGout
MODE
OSCin
OSCout
VSS
24
23
22
21
20
19
18
17
16
15
14
13
1
2
3
4
5
6
7
8
9
10
11
12
VDD
St/GT
ESt
StD
INT
CD
DR
DATA
DCLK
FSKen
PWDN
IC
Figure 2 - Pin Connections
Pin Description
Pin #
Name
1
IN+
Non-inverting Input of the internal opamp.
2
IN-
Inverting Input of the internal opamp.
3
GS
Gain Select (Output) of internal opamp. The opamp’s gain should be set according to the
nominal Vdd of the application using the information in Figure 10.
4
VRef
Reference Voltage (Output). Nominally VDD/2. It is used to bias the input opamp.
5
CAP
Capacitor. A 0.1µF decoupling capacitor should be connected across this pin and VSS.
6
Description
TRIGin Trigger Input. Schmitt trigger buffer input. Used for line reversal and ring detection.
7
TRIGRC Trigger RC (Open Drain Output/Schmitt Input). Used to set the (RC) time interval from
TRIGin going low to TRIGout going high. An external resistor connected to VDD and capacitor
connected to VSS determine the duration of the (RC) time interval.
8
TRIGout Trigger Out (CMOS Output). Schmitt trigger buffer output. Used to indicate detection of line
reversal and/or ringing.
9
MODE
3-wire interface: Mode Select (CMOS Input). When low, selects interface mode 0. When high,
selects interface mode 1. See pin 16 (DCLK) description to understand how MODE affects the
DCLK pin.
10
OSCin
Oscillator Input. A 3.579545MHz crystal should be connected between this pin and OSCout. It
may also be driven directly from an external clock source.
11
OSCout Oscillator Output. A 3.579545MHz crystal should be connected between this pin and OSCin.
When OSCin is driven by an external clock, this pin should be left open.
12
VSS
13
IC
Power Supply Ground.
Internal Connection. Must be connected to VSS for normal operation.
14
PWDN Power Down (Schmitt Input). Active high. When high, the device consumes minimal power by
disabling all functionality except TRIGin, TRIGRC and TRIGout. Must be pulled low for device
operation.
15
FSKen
FSK Enable (CMOS Input). Must be high for FSK demodulation. This pin should be set low to
prevent the FSK demodulator from reacting to extraneous signals (such as speech, alert signal
and DTMF which are all in the same frequency band as FSK).
16
DCLK
3-wire Interface: Data Clock (CMOS Input/Output). In mode 0 (MODE pin low), this pin is an
output. In mode 1 (MODE pin high), this pin is an input.
17
DATA
3-wire Interface: Data (CMOS Output). In mode 0 data appears at the pin once demodulated.
In mode 1 data is shifted out on the rising edge of the microcontroller supplied DCLK.
5-54
MT88E43
Data Sheet
Pin Description
Pin #
Name
Description
18
DR
3-wire Interface: Data Ready (CMOS Output). Active low. In mode 0 this output goes low after
the last DCLK pulse of each data word. This identifies the 8-bit word boundary on the serial
output stream. Typically, DR is used to latch 8-bit words from a serial-to-parallel converter into a
microcontroller. In mode 1 this pin will signal the availability of data.
19
CD
Carrier Detect (CMOS Output). Active low. A logic low indicates the presence of in-band signal
at the output of the FSK bandpass filter.
20
INT
Interrupt (Open Drain Output). Active low. It is active when TRIGout or DR is low, or StD is
high. This output stays low until all three signals have become inactive.
21
StD
Dual Tone Alert Signal Delayed Steering Output (CMOS Output). When high, it indicates
that a guard time qualified alert signal has been detected.
22
ESt
Dual Tone Alert Signal Early Steering Output (CMOS Output). Alert signal detection output.
Used in conjunction with St/GT and external circuitry to implement the detect and non-detect
guard times.
23
St/GT
Dual Tone Alert Signal Steering Input/Guard Time (Analog Input/CMOS Output).
A
voltage greater than VTGt (see figure 4) at the St/GT pin causes the device to indicate that a
dual tone has been detected by asserting StD high. A voltage less than VTGt frees the device to
accept a new dual tone.
24
VDD
Positive Power Supply.
The MT88E43 provides all the features and
functions offered by Zarlink’s MT8841 (CNIC),
including 1200 baud Bell 202 and CCITT V.23 FSK
demodulation. The 3-wire serial data interface
provided by CNIC has been enhanced to operate in
two modes. In the CNIC compatible mode data
transfer is initiated by the device. A second mode
allows a microcontroller to extract 8-bit data words
from the device. Furthermore, the MT88E43 offers
Idle State Tone Alert Signal and line reversal
detection capability for BT’s CLIP, ring burst
detection for the U.K.’s CCA’s CLIP, and ring and
CAS detection for Bellcore’s CID.
Functional Overview
The MT88E43, Extended Voltage Calling Number
Identification Circuit 2 (ECNIC2) is a device
compatible with BT, the U.K.’s CCA and Bellcore
specifications. As shown in Figure 1, the MT88E43
provides an FSK demodulator as well as a 3-wire
serial interface similar to that of it’s predecessor, the
MT8841 (CNIC). The 3-wire interface has been
enhanced to provide two modes of operation - a
mode whereby data transfer is initiated by the device
and a mode whereby data transfer is initiated by an
external microcontroller.
In addition to supporting all the features and
functions of the MT8841, the MT88E43 also
provides line reversal detection, ring detection and
dual tone alert signal/CAS detection. These new
functions eliminate some external circuitry previously
required with the MT8841.
The MT88E43 is compatible with the caller identity
specifications of BT, the U.K.’s CCA, and Bellcore.
BT specifications SIN227 and SIN242 describe the
signalling mechanism between the network and the
Terminal Equipment (TE) for the Caller Display
Service (CDS). CDS provides Calling Line Identity
Presentation (CLIP), which delivers to an on hook
(idle state) TE the identity of an incoming caller
before the first ring.
An incoming CDS call is indicated by a polarity
reversal on the A and B wires (see Figure 3),
followed by an Idle State Tone Alert Signal. Caller ID
FSK information is then transmitted in CCITT V.23
format. MT88E43 can detect the line reversal, tone
alert signal, and demodulate the incoming CCITT
V.23 FSK signals.
The U.K.’s CCA specification TW/P&E/312 proposes
an alternate CDS TE interface. According to TW/
P&E/312, data is transmitted after a single burst of
ringing rather than before the first ringing cycle (as
specified in the BT standards). The Idle State Tone
Alert Signal is not required as it is replaced by a
single ring burst. MT88E43 has the capability to
detect the ring burst. It can also demodulate either
5-55
MT88E43
Data Sheet
Functional Description
Bell-202 or CCITT V.23 FSK data following the ring
burst. The U.K.’s CCA specifies that data can be
transmitted in either format.
Detection of CLIP/CID Call Arrival Indicators
Bellcore specification GR-30-CORE is the generic
requirement
for
transmitting
asynchronous
voiceband data to Customer Premises Equipment
(CPE). Another Bellcore specification SR-TSV002476 describes the same requirements from the
CPE’s perspective. The data transmission technique
specified in both documents is applicable in a variety
of services like Calling Number Delivery (CND),
Calling Name Delivery (CNAM) and Calling Identity
Delivery on Call Waiting (CIDCW) - services
promoted by Bellcore.
The circuit in Figure 3 illustrates the relationship
between the TRIGin, TRIGRC and TRIGout signals.
Typically, the three pin combination is used to detect
an event indicated by an increase of the TRIGin
voltage from VSS to above the Schmitt trigger high
going
threshold
VT+ (see
DC
electrical
characteristics).
Figure 3 shows a circuit to detect any one of three
CLIP/CID call arrival indicators: line reversal, ring
burst and ringing.
In CND/CNAM service, information about a calling
party is embedded in the silent interval between the
first and second ring burst. The MT88E43 detects
the first ring burst and can then be setup to receive
and demodulate the incoming Bell-202 FSK data.
The device will output the demodulated data onto a
3-wire serial interface.
1. Line Reversal Detection
Line reversal, or polarity reversal on the A and B
wires indicates the arrival of an incoming CDS call,
as specified in SIN227. When the event (line
reversal) occurs, TRIGin rises past the high going
Schmitt threshold VT+ and TRIGout, which is
normally high, is pulled low. When the event is over,
TRIGin falls back to below the low going Schmitt
threshold VT- and TRIGout returns high. The
components R5 and C3 (see Figure 3) at TRIGRC
ensure a minimum TRIGout low interval.
In CIDCW service, information about an incoming
caller is sent to the subscriber, while he/she is
engaged in another call. A CPE Alerting Signal
(CAS) indicates the arrival of CIDCW information.
The MT88E43 can detect the alert signal and then be
setup to demodulate incoming FSK data containing
CIDCW information.
Tip/A
In a TE designed for CLIP, the TRIGout high to low
transition may be used to interrupt or wake-up the
microcontroller. The controller can thus be put into
power-down mode to conserve power in a battery
operated TE.
VDD
C1=100nF
V1
MT88E43
V3
R1=499K
max VT+ = 0.68 VDD
min VT+ = 0.48 VDD
V4
Notes:
The application circuit must ensure that,
VTRIGin>max V T+
where max V T+=3.74V @VDD=5.5V.
Tolerance to noise between A/B and VSS is:
max V noise = (min V T+)/0.30+0.7 =5.6Vrms @4.5V V DD
where min VT+ = 2.16V @VDD=4.5V.
Suggested R 5C3 component values:
R5 from 10KΩ to 500KΩ
C3 from 47nF to 0.68µF
An example is C3=220nF, R5=150KΩ; TRIGout low
from 21.6ms to 37.6ms after TRIGin Signal stops
triggering the circuit.
R5=150K
R2=499K
TRIGin
TRIGRC
To determine values for C3 and R5:
R5C3=-t / ln(1-V TRIGRC/VDD)
C3=220nF
Ring/B
C2=100nF
V2
R4=301K
R3=200K
TRIGout
To Microcontroller
Figure 3 - Circuit to Detect Line Reversal, Ring Burst and Ringing
5-56
MT88E43
Data Sheet
2. Ring Burst Detection
CCA does not support the dual tone alert signal
(refer to Dual Tone Alert Signal Detection section).
Instead, CCA requires that the TE be able to detect a
single burst of ringing (duration 200-450ms) that
precedes CLIP FSK data. The ring burst may vary
from 30 to 75Vrms and is approximately 25Hz.
Again in a TE designed for CCA CLIP, the TRIGout
high to low transition may be used to interrupt or
wake-up the microcontroller. The controller can thus
be put into power-down mode to conserve power in a
battery operated TE.
3. Ring Detection
In Bellcore’s CND/CNAM scheme, the CID FSK data
is transmitted between the first and second ringing
cycles. The circuit in Figure 3 will generate a ring
envelope signal (active low) at TRIGout for a ring
voltage of at least 40Vrms. R5 and C3 filter the ring
signal to provide an envelope output.
The diode bridge shown in Figure 3 works for both
single ended and balanced ringing. A fraction of the
ring voltage is applied to the TRIGin input. When the
voltage at TRIGin is above the Schmitt trigger high
going threshold VT+, TRIGRC is pulled low as C3
discharges. TRIGout stays low as long as the C3
voltage stays below the minimum VT+.
In a CPE designed for CND/CNAM, the TRIGout
high to low transition may be used to interrupt or
wake-up the microcontroller. The controller can thus
be put into power-down mode to conserve power.
If precise ring duration determination is critical,
capacitor C3 in Figure 3 may be removed. The
microcontroller will now be able to time the ring
duration directly. The result will be that TRIGout will
be low only as long as the ringing signal is present.
Previously the RC time constant would cause only
one interrupt.
Dual Tone Alert Signal Detection
The BT on hook (idle state) caller ID scheme uses a
dual tone alert signal whose characteristics are
shown in Table 1.
In the MT88E43 the dual tone alert signal is
separated into a high and a low tone by two
bandpass filters. A detection algorithm examines the
two filter outputs to determine the presence of a dual
tone alert signal. The ESt pin goes high when both
tones are present. Note that ESt is only a preliminary
indication. The indication must be sustained over the
tone present guard time to be considered valid. Tone
present and tone absent guard times can be
implemented with external RC components. The
tone present guard time rejects signals of insufficient
duration. The tone absent guard time masks
momentary detection dropout once the present
guard time has been satisfied. StD is the guard time
qualified detector output.
Item
BT
Bellcore
Low tone
frequency
2130Hz ±1.1%
2130Hz ±0.5%
High tone
frequency
2750Hz ± 1.1%
2750Hz ± 0.5%
Received
signal level
-2dBV to -40dBV
per tone on-hooka
(0.22dBmb to
-37.78dBm)
-14dBmb to
- 32dBm per tone
off-hook
Signal reject
level
-46dBV
(-43.78dBm)
-45dBm
Signal level
differential
(twist)
up to 7dB
up to 6dB
<= -20dB
(300-3400Hz)
<= -7dBm ASLc
near end speech
Duration
88ms to 110msd
75ms to 85ms
Speech
present
No
Yes
Unwanted
signals
Table 1 - Dual Tone Alert Signal
Characteristics
a. In the future BT may specify the off-hook signal level as
-15dBm to -34dBm per tone for BT CIDCW.
b. The signal power is expressed in dBm referenced to 600 ohm
at the CPE A/B (tip/ring) interface.
c. ASL = active speech level expressed in dBm referenced to
600 ohm at the CPE tip/ring interface. The level is measured
according to method B of Recommendation P.56 "Objective
Measurement of Active Speech Level" published in the CCITT
Blue Book, volume V "Telephone Transmission Quality" 1989.
EPL (Equivalent Peak Level) = ASL+11.7dB
d. SIN227 suggests that the recognition time should be not less
than 20ms if both tones are detected.
Bellcore specifies a similar dual tone alert signal
called CPE Alerting Signal (CAS) for use in off-hook
data transmission (see Table 1). Bellcore states that
the CPE should be able to detect the CAS in the
presence of near end speech. The CAS detector
should also be immune to imitation from near and far
end speech.
5-57
MT88E43
Dual Tone Detection Guard Time
When the dual tone alert signal is detected by the
MT88E43, ESt goes high. When the alerting signal
ceases to be detected, ESt goes low.
The ESt pin signals raw detection of CAS/Alerting
Tones. Since both Bellcore and BT applications
require a minimum duration for valid signals, ESt
detection must be guard time qualified. The StD pin
provides guard time qualified CAS/Alerting Tone
detection. When the MT88E43 is used in a caller
identity system, StD indicates correct CAS/Alerting
Tone detection.
Preliminary Information
Figures 9 and 11 (R2=R3=422K, C=0.1µF) will meet
the BT timing requirements.
MT88E43
VDD
Tones detected
P
From
detector
Q1
C
St/GT
+
VTGt
Comparator
R
N
Q2
= VSS
A
SW1
B
ESt
Figure 4 shows the relationship between the St/GT,
ESt and StD pins. It also shows the operation of a
guard time circuit.
The total recognition time is tREC = tGP + tDP, where
tGP is the tone present guard time and tDP is the tone
present detect time (refer to timing between ESt, St/
GT and StD in Figures 17 and 20).
StD
Figure 4 - Guard Time Circuit Operation
MT88E43
VDD
C
VD=diode forward voltage
St/GT
R1
The total tone absent time is tABS = tGA + tDA, where
tGA is the tone absent guard time and tDA is the tone
absent detect time (refer to timing between ESt, St/
GT and StD in Figures 17 and 20).
Bellcore states that it is desirable to be able to turn
off CAS detection for an off-hook capable CPE. The
disable switch allows the subscriber who
disconnects a service that relies on CAS detection
(e.g., CIDCW) but retains the CPE, to turn off the
detector and not be bothered by false detection.
VSS
R2
ESt
(a) tGP > tGA
tGP = R1C ln [VDD/(VDD-VTGt)]
tGA = R PC ln [(VDD-VD(R P/R2))/(VTGt-V D(RP/R2))]
RP = R1R2/(R1+R2)
MT88E43
VDD
C
VD=diode forward voltage
St/GT
R1
R2
ESt
When SW1 in Figure 4 is in the B position the guard
time circuit is disabled. The detector will still process
CAS/Alerting tones but the MT88E43 will not signal
their presence by ensuring StD is low.
BT specifies that the idle state tone alert signal
recognition time should not be less than 20ms when
both tones are used for detection. That is, both tones
must be detected together for at least 20ms before
the signal can be declared valid. This requirement
can be met by setting the tGP (refer to Figure 5) to at
least 20ms.
BT also specifies that the TE is required to apply a
D.C. wetting pulse and an AC load 15-25ms after the
end of the alerting signal. If tABS=tDA+tGA is 15 to
25ms, the D.C. current wetting pulse and the A.C.
load can both be applied at the falling edge of StD.
The maximum tDA is 8ms so tGA should be 15-17ms.
Therefore, tGP must be greater than tGA. Figure 5(a)
shows a possible implementation. The values in
5-58
(b) tGP < tGA
tGP = RPC ln [VDD-VD(RP/R2))/(VDD-VTGt-VD(RP/R2))]
tGA = R1C ln (VDD/VTGt)
RP = R1R2/(R1+R2)
Figure 5 - Guard Time Circuits with
Unequal Times
Input Configuration
The MT88E43 provides an input arrangement
comprised of an operational amplifier and a bias
source (VRef); which is used to bias the opamp inputs
at VDD/2. The feedback resistor at the opamp output
(GS) can be used to adjust the gain. In a singleended configuration, the opamp is connected as
shown in Figure 6. For a differential input
configuration, Figure 7 shows the necessary
connections.
MT88E43
Data Sheet
Item
BT
Bellcore
Mark
frequency
(logic 1)
1300Hz
±1.5%
1200Hz
±1%
Space
frequency
(logic 0)
2100Hz
±1.5%
2200Hz
±1%
Received
signal level mark
-8dBV to
-40dBV
(-5.78dBm to
-37.78dBm)
-12dBma to
-32dBm
Received
signal level space
-8dBV to
-40dBV
-12dBm to
-36dBm
up to 6dB
up to 10dBb
IN-
Signal level
differential
(twist)
GS
Unwanted
signals
IN+
IN-
RIN
C
RF
GS
VRef
Voltage Gain
(AV) = RF / RIN
Figure 6 - Single-Ended Input
Configuration
C1
C2
R1
IN+
R4
R5
R3
R2
VRef
Differential Input Amplifier
C1 = C2
R1 = R4 (For unity gain R5= R4)
R3 = (R2R5) / (R2 + R5)
Voltage Gain
(AVdiff) = R5/R1 (see Figure 9,10,11)
Input Impedance
(ZINdiff) = 2
R12 + (1/ωC)2
Figure 7 - Differential Input Configuration
FSK Demodulation
The MT88E43 first bandpass filters and then
demodulates the incoming FSK signal. The carrier
detector provides an indication of the presence of
signal at the bandpass filter output. The MT88E43’s
dual mode 3-wire interface allows convenient
extraction of the 8-bit data words in the demodulated
FSK bit stream.
Note that signals such as dual tone alert signal,
speech and DTMF tones lie in the same frequency
band as FSK. They will, therefore, be demodulated
and as a result, false data will be generated. To
avoid demodulation of false data, an FSKen pin is
provided so that the FSK demodulator may be
disabled when FSK signal is not expected. There are
two events that if either is true, should be used to
disable FSKen. The events are CD returning high or
receiving all the data indicated by the message
length word.
<= -20dB
(300-3400Hz)
<= -25dB
(0-4kHz)c
Transmission
rate
1200 baud
±± 1%
1200 baud
±± 1%
Word format
1 start bit (logic
0), 8 bit word
(LSB first), 1 to
10 stop bits
(logic 1)
1 start bit (logic
0), 8 bit word
(LSB first),
1 stop bit
(logic 1)d
Table 2 - FSK Characteristics
a. The signal power is expressed in dBm referenced to 600
ohm at the CPE tip/ring (A/B) interface.
b. SR-3004,Issue 2, January 1995.
c. The frequency range is specified in GR-30-CORE.
d. Up to 20 marks may be inserted in specific places in a single
or multiple data message.
The FSK characteristics described in Table 2 are listed
in BT and Bellcore specifications. The BT signal
frequencies correspond to CCITT V.23. The Bellcore
frequencies correspond to Bell 202. The U.K.’s CCA
requires that the TE be able to receive both CCITT
V.23 and Bell 202, as specified in the BT and Bellcore
specifications. The MT88E43 is compatible with both
formats without any adjustment.
•
3-wire User Interface
The MT88E43 provides a powerful dual mode 3-wire
interface so that the 8-bit data words in the
demodulated FSK bit stream can be extracted
without the need either for an external UART or for
the TE/CPE’s microcontroller to perform the UART
function in software. The interface is specifically
designed for the 1200 baud rate and is comprised of
the DATA, DCLK (data clock) and DR (data ready)
pins. Two modes (modes 0 and 1) are selectable via
control of the device’s MODE pin: in mode 0, data
5-59
MT88E43
transfer is initiated by the MT88E43; in mode 1, data
transfer is initiated by the external microcontroller.
Mode 0
This mode is selected when the MODE pin is low. It
is the MT8841 compatible mode where data transfer
is initiated by the device.
In this mode, the MT88E43 receives the FSK signal,
demodulates it, and outputs the data directly to the
DATA pin (refer to Figure 14). For each received
stop and start bit sequence, the MT88E43 outputs a
fixed frequency clock string of 8 pulses at the DCLK
pin. Each clock rising edge occurs in the centre of
each DATA bit cell. DCLK is not generated for the
stop and start bits. Consequently, DCLK will clock
only valid data into a peripheral device such as a
serial to parallel shift register or a micro-controller.
The MT88E43 also outputs an end of word pulse
(data ready) on the DR pin. The data ready signal
indicates the reception of every 10-bit word
(including start and stop bits) sent from the network
to the TE/CPE. This DR signal can be used to
interrupt a micro-controller. DR can also cause a
serial to parallel converter to parallel load its data
into a microcontroller. The mode 0 data pin can also
be connected to a personal computer’s serial
communication port after converting from CMOS to
RS-232 voltage levels.
Preliminary Information
•
Carrier Detect
The carrier detector provides an indication of the
presence of a signal in the FSK frequency band. It
detects the presence of a signal of sufficient
amplitude at the output of the FSK bandpass filter.
The signal is qualified by a digital algorithm before
the CD output is set low to indicate carrier detection.
An 8ms hysteresis is provided to allow for
momentary signal drop out once CD has been
activated. CD is released when there is no activity at
the FSK bandpass filter output for 8 ms.
When CD is inactive (high), the raw output of the
demodulator is ignored by the data timing recovery
circuit (refer to Figure 1). In mode 0, the DATA pin is
forced high. No DCLK or DR signal is generated. In
mode 1, the internal shift register is not updated. No
DR is generated. If DCLK is clocked (in mode 1),
DATA is undefined.
Note that signals such as dual tone alert signal,
speech and DTMF tones also lie in the FSK
frequency band and the carrier detector may be
activated by these signals. The signals will be
demodulated and presented as data. To avoid false
data detection, the FSKen pin should be used to
disable the FSK demodulator when no FSK signal is
expected.
Ringing, on the other hand, does not pose a problem
as it is ignored by the carrier detector.
Mode 1
Interrupt
This mode is selected when the MODE pin is high. In
this mode, the microcontroller supplies read pulses
(DCLK) to shift the 8-bit data words out of the
MT88E43, onto the DATA pin. The MT88E43 asserts
DR to denote the word boundary and indicate to the
microprocessor that a new word has become
available (refer to Figure 16).
Internal to the MT88E43, the demodulated data bits
are sampled and stored. After the 8th bit, the word is
parallel loaded into an 8 bit shift register and DR
goes low. The shift register’s contents are shifted out
to the DATA pin on the supplied DCLK’s rising edge
in the order they were received.
If DCLK begins while DR is low, DR will return to high
upon the first DCLK. This feature allows the
associated interrupt (see section on "Interrupt") to be
cleared by the first read pulse. Otherwise DR is low for
half a nominal bit time (1/2400 sec).
After the last bit has been read, additional DCLKs
are ignored.
5-60
To facilitate interfacing with microcontrollers running
interrupt driven firmwear, an open drain interrupt
output INT is provided. INT is asserted when
TRIGout is low, StD is high, or DR is low. When INT
is asserted, these signals should be read (through an
input port of the microcontroller) to determine the
cause of the interrupt (TRIGout, StD or DR) so that
the appropriate response can be made.
When system power is first applied, TRIGout will be
low because capacitor C3 at TRIGRC (see Figure 3)
has no initial charge. This will result in an interrupt
upon power up. Also when system power is first
applied and the PWDN pin is low, an interrupt will
occur due to StD. Since there is no charge across
the capacitor at the St/GT pin in Figure 4, StD will be
high triggering an interrupt. The interrupts will not
clear until both capacitors are charged. The
microcontroller should ignore interrupt from these
sources on initial power up until there is sufficient
time to charge the capacitors.
MT88E43
Data Sheet
It is possible to clear StD and its interrupt by
asserting PWDN immediately after system power up.
When PWDN is high, StD is low. PWDN will also
force both ESt and the comparator output low, Q2
will turn on so that the capacitor at the St/GT pin
charges up quickly (refer to Figure 4).
can be D.C. coupled as shown, or the OSC1 input on
all devices can be driven from a CMOS buffer (dc
coupled) with the OSC2 outputs left unconnected.
To meet BT and Bellcore requirements for proper
tone detection the crystal must have a frequency
tolerance of 0.1%.
Power Down Mode
VRef and CAP Inputs
For
applications
requiring
reduced
power
consumption, the MT88E43 can be powered up only
when it is required, that is, upon detection of one of
three CLIP/CID call arrival indicators: line reversal,
ring burst and ringing.
VRef is the output of a low impedance voltage source
equal to VDD/2 and is used to bias the input opamp. A
0.1µF capacitor is required between CAP and VSS to
eliminate noise on VRef.
The MT88E43 is powered down by asserting the
PWDN pin. In powerdown mode, the crystal
oscillator, opamp and all internal circuitry, except for
TRIGin, TRIGRC and TRIGout pins, are disabled.
The three TRIG pins are not affected by power down,
such that, the MT88E43 can still react to call arrival
indicators. The MT88E43 can be powered up by
grounding the PWDN pin.
Crystal Oscillator
The MT88E43 requires a 3.579545MHz crystal
oscillator as the master timing source.
MT88E43
OSC1
OSC2
MT88E43
OSC1
OSC2
MT88E43
OSC1
OSC2
to the
next MT88E43
3.579545 MHz
Figure 8 - Common Crystal Connection
The crystal specification is as follows:
Frequency:
Frequency tolerance:
Resonance mode:
Load capacitance:
Maximum series resistance:
Maximum drive level (mW):
e.g., CTS MP036S
3.579545 MHz
±0.1%(-40oC+85oC)
Parallel
18 pF
150 ohms
2 mW
Any number of MT88E43 devices can be connected
as shown in Figure 8 such that only one crystal is
required. The connection between OSC2 and OSC1
5-61
MT88E43
Data Sheet
Vdd
1N4003
TIP / A
R4
MT88E43
R1
1N4003
Vdd
22nF
5%
R1
1N4003
499K, 5%
100nF
5%
Vdd
Vdd
100nF 1N914
5%
499K, 5%
R4
464K
60K4
1N4003
RING / B
53K6
TISP4180,
TISP5180,
TPA150A12 or
TPB150B12
22nF
5%
100nF
Vdd
1N914
1N914
150K
5%
200K
5%
1N914
301K
5%
220nF
100nF
IN+
VDD
IN-
St/GT
GS
ESt
VRef
StD
CAP
INT
TRIGin
CD
TRIGRC
DR
TRIGout
DATA
MODE
DCLK
OSCin
FSKen
OSCout
PWDN
VSS
NOTE: Resistors must have 1% tolerance and capacitors have 20%
tolerance unless otherwise specified.
: Crystal is 3.579545MHz, 0.1% frequency tolerance.
: For BT Application C=0.1µF ±5%, R3=422kΩ ±1%, R2=422kΩ ±1%
: For applications where CAS speech immunity is required (e.g. CIDCW)
C=0.1µF ±5%, R3=825kΩ ±1%, R 2=226kΩ ±1%
Vdd
C
100K
20%
R3
R2
1N914
IC
= To microcontroller
= From microcontroller
(FSK Interface Mode 0 selected)
: R1 = 430K, R 4 = 34K for VDD = 5V ± 10% (See Figure 10)
: R1 = 620K, R 4 = 63K4 for VDD = 3V ± 10% (See Figure 10)
Figure 9 - Application Circuit
Application Circuits
The circuits shown in Figures 9 and 11 are
application circuits for the MT88E43. As supply
voltage (VDD ) is decreased, the threshold of the
device’s tone and FSK detectors will be reduced.
Therefore, to meet the BT or Bellcore tone reject
level requirements the gain of the internal opamp
should be reduced according to the graph in Figure
10. For example when VDD=5V (+/- 10%), R1 should
equal 430kΩ and R4 should equal 34kΩ; and if
VDD=3V (+/- 10%) R1 should equal 620kΩ and R4
should equal 63.4kΩ. Resistors R1 and R4 are
shown in Figures 9 and 11.
The circuit shown in Figure 9 illustrates the use of the
MT88E43 in a proprietary system that doesn’t need to
meet FCC, DOC, and UL approvals. It should be noted
that if glitches on the tip/ring interface are of sufficient
amplitude, the circuit will falsely detect these signals as
ringing or line reversal.
The circuit shown in Figure 11 will provide common
mode rejection of signals received by the ringing circuit.
This circuit should pass safety related tests specified by
FCC Part 68, DOC CS-03, UL 1459, and CSA C22.2.
5-62
These safety tests will simulate high voltage faults that
may occur on the line. The circuit provides isolation
from these high voltage faults via R1 and the 12k1Ω resistors as well as the 22nF & 330nF capacitors. IRC
manufactures a resistor (part number GS3) that should
be used for R1. This resistor is a 3W, 5%, 1kV power
resistor. The 12k1 resistor is manufactured by IRC (part
number FA8425F). This resistor is a 1.5W, 5%, fuseable type resistor. The 22nF and 330nF capacitors have
a 400V rating.
See the application note "MSAN-164: Applications of
the MT8843 Calling Number Identification Circuit 2" for
information on designing the MT88E43 into CID and
CIDCW systems.
MT88E43
Data Sheet
1
0.95
0.9
Gain Ratio
0.85
0.8
0.75
0.7
0.65
0.6
2
2.5
3
3.5
4
4.5
5
5.5
6
Norminal Vdd (Volts)
Figure 10: Gain Ratio as a function of Nominal Vdd
Note: In the application circuits shown in Figures 9 and 11, the Gain Ratio of MT88E43 opamp is
464kΩ
GainRatio = -----------------R1 + R 4
5-63
MT88E43
Data Sheet
R1
MT88E43
1N4003
1N4003
R1
R4
464K
60K4
RING / B
R4
Vdd
22nF
5%
Vdd
150K
5%
VDD
IN-
St/GT
GS
ESt
StD
CAP
INT
TRIGin
CD
TRIGRC
DR
TRIGout
DATA
MODE
DCLK
OSCin
FSKen
OSCout
PWDN
VSS
200K
5%
464K
5%
100nF
220nF
100nF
10%
330nF 12K1 Vdd
Motorola
10% 5%
4N25
IN+
VRef
1N4003
1N5231B
100nF
1N4003
53K6
TIP / A
Vdd
Vdd
22nF
5%
Vdd
C
R3
R2
100K
1N914
20%
IC
10nF
NOTE: Resistors must have 1% tolerance, capacitors have 20%
tolerance unless specified otherwise.
: Bridge rectifier diodes are 1N914.
: For BT Application C=0.1µF ±5%, R 3=422kΩ ±1%, R2=422kΩ ±1%
: For applications where CAS speech immunity is required (e.g. CIDCW)
C=0.1µF ±5%, R3=825kΩ ±1%, R 2=226kΩ ±1%
= To microcontroller
= From microcontroller
(FSK Interface Mode 0 selected)
: R1 = 430K, R4 = 34K for VDD = 5V ± 10% (See Figure 10)
: R1 = 620K, R4 = 63K4 for VDD = 3V ± 10% (See Figure 10)
Figure 11 - Application Circuit with Improved Common Mode Noise Immunity and Isolation in
Line Interface
Approvals
FCC Part 68, DOC CS-03, UL 1459, and CAN/CSA22.2 No. 225-M90 are all system (i.e. connectors,
power supply, cabinet, etc.) requirements. Since the
MT88E43 is a component and not a system, the
application circuit (Figure 11) has been designed to
meet the CO Trunk interface requirements of FCC,
DOC, UL, and CSA; thus enabling the complete
system to be approved by these standards bodies.
Products are designed in accordance with meeting
the above requirements; however, full conformance
to these standards is dependent upon the application
in which the MT88E43 is being used, and therefore,
approvals are the responsibility of the customer and
Zarlink will not have tested the product to meet the
above standards.
5-64
MT88E43
Data Sheet
Absolute Maximum Ratings* - Voltages are with respect to VSS unless otherwise stated.
Parameter
Symbol
Min
Max
Units
1
Supply voltage with respect to Vss
VDD
-0.3
6
V
2
Voltage on any pin other than supplies **
VPIN
Vss-0.3
VDD+0.3
V
3
Current at any pin other than supplies
IPIN
10
mA
4
Storage Temperature
TST
-65
150
o
C
* Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied.
**
Under normal operating conditions voltage on any pin except supplies can be minimum V SS-1V to maximum V DD+1V for an input current
limited to less than 200µΑ
.
Recommended Operating Conditions - Voltages are with respect to ground (VSS) unless otherwise stated.
Characteristics
Sym
Min
Typ‡
Max
Units
2.7
-
5.5
V
1
Power Supplies
VDD
2
Clock Frequency
fOSC
3
Tolerance on Clock Frequency
∆fc
-0.1
+0.1
%
4
Operating Temperature
TOP
-40
85
oC
3.579545
MHz
o
‡ Typical figures are at 25 C and are for design aid only: not guaranteed and not subject to production testing.
DC Electrical Characteristics†
Characteristics
Standby Supply Current
1
2
S
U
P
P
L
Y
Operating Supply Current
Sym
Min
IDDQ
Typ
‡
Max
Units
Test Conditions
0.5
15
µA
AlI inputs are
VDD/VSS except
for oscillator pins.
No analog input.
outputs unloaded.
PWDN=VDD
IDD
VDD = 5V ±10%
VDD = 3V ±10%
4.7
2.5
8
4.5
mA
mA
All inputs are
VDD/VSS except
for oscillator pins.
No analog input.
outputs unloaded.
PWDN=VSS
FSKen=VDD
3
Power Consumption
PO
4
Schmitt Input High
Threshold
VT+
Schmitt Input Low
Threshold
TRIGin,
TRIGRC
, PWDN
5
6
DCLK,
MODE,
FSKen
44
mW
0.48*VDD
0.68*VDD
V
VT-
0.28*VDD
0.48*VDD
V
Schmitt Hysteresis
VHYS
0.2
CMOS Input High
Voltage
VIH
0.7*VDD
VDD
V
CMOS Input Low Voltage
VIL
VSS
0.3*VDD
V
V
5-65
MT88E43
Data Sheet
DC Electrical Characteristics† (continued)
Characteristics
Sym
Min
Typ
‡
Max
Units
Test Conditions
7
TRIGout
, DCLK,
DATA,
DR, CD,
StD,
ESt,
St/GT
Output High Sourcing
Current
IOH
0.8
mA
VOH=0.9*VDD
8
TRIGout
, DCLK,
DATA,
DR, CD,
StD,
ESt,
St/GT
TRIGRC
, INT
Output Low Sinking
Current
IOL
2
mA
VOL=0.1*VDD
9
IN+, IN-,
TRIGin
Input Current
Iin1
1
µA
Vin=VDD to VSS
Iin2
10
µA
Vin=VDD to VSS
Ioz1
1
µA
Vout =VDD to VSS
Ioz2
10
µA
Ioz3
5
µΑ
0.5VDD+
0.05
V
2
kΩ
0.5VDD+
0.05
V
PWDN,
DCLK,
MODE,
FSKen
10
TRIGRC
11
INT
12
St/GT
13
VRef
14
15
St/GT
Output High-Impedance
Current
Output Voltage
VRef
Output Resistance
RRef
Comparator Threshold
Voltage
VTGt
0.5VDD 0.05
0.5VDD0.05
† DC Electrical Characteristics are over recommended operating conditions unless otherwise stated.
‡ Typical figures are at 25oC and are for design aid only: not guaranteed and not subject to production testing.
5-66
No Load
MT88E43
Data Sheet
AC Electrical Characteristics† - Dual Tone Alert Signal Detection
Characteristic
Sym
Min
Typ‡
Max
Unit
Notes*
1
Low tone frequency
fL
-
2130
-
Hz
2
High tone frequency
fH
-
2750
-
Hz
3
Frequency deviation accept
1.1%
-
-
range within which
tones are
accepted
4
Frequency deviation reject
3.5%
-
-
ranges outside of
which tones are
rejected
5
Accept signal level per tone
-40
-37.78
-
-2
0.22
dBVa
dBmb
See Note 3
6
Reject signal level per tone
-
-
-46
-43.78
dBV
dBm
See Note 3
7
Positive and negative twist
accept
7
-
-
dBc
8
Signal to Noise Ratio
20
-
-
dB
SNRTONE
1,2
a. dBV = decibels above or below a reference voltage of 1Vrms. Signal level is per tone.
b. dBm = decibels above or below a reference power of 1mW into 600 ohms, 0dBm = 0.7746Vrms. Signal level is per tone.
c. Twist = 20 log (fH amplitude / fL amplitude).
*Notes:
1. Both tones have the same amplitude.
2. Band limited random noise 300-3400Hz. Measurement valid only when tone is present.
3. With gain setting as shown in Figure 10. Production tested at 3V ±10%, 5V ±10%.
=AC Electrical Characteristics are over recommended operating conditions, unless otherwise stated.
‡Typical figures are at 25 oC and are for design aid only: not guaranteed and not subject to production testing
AC Electrical Characteristics - Timing Parameter Measurement Voltage Levels
Characteristics
Sym
Level
Units
1
CMOS Threshold Voltage
VCT
0.5*VDD
V
2
Rise/Fall Threshold Voltage High
VHM
0.7*VDD
V
3
Rise/Fall Threshold Voltage Low
VLM
0.3*VDD
V
Notes
5-67
MT88E43
Data Sheet
Electrical Characteristics† - Gain Setting Amplifier
Characteristics
Sym
Min
Max
Units
1
µA
Test Conditions
VSS ≤ VIN ≤ VDD
1
Input Leakage Current
IIN
2
Input Resistance
Rin
3
Input Offset Voltage
VOS
4
Power Supply Rejection Ratio
PSRR
40
dB
1kHz ripple on VDD
5
Common Mode Rejection
CMRR
40
dB
VCMmin ≤ VIN ≤ VCMmax
6
DC Open Loop Voltage Gain
AVOL
30
dB
7
Unity Gain Bandwidth
fC
0.3
MHz
8
Output Voltage Swing
VO
0.5
9
Maximum Capacitive Load (GS)
CL
10
MΩ
25
10 Maximum Resistive Load (GS)
RL
50
11 Common Mode Range Voltage
VCM
1.0
mV
VDD-0.5
Vpp
100
pF
Load ≥ 50kΩ
kΩ
V
VDD-1.0
† Electrical characteristics are over recommended operating conditions, unless otherwise stated.
AC Electrical Characteristics† - FSK Detection
Characteristics
Sym
1 Input Detection Level
Min
Typ‡
Max
Units
-8
dBVa 1,3
-5.78 dBmb
398.1 mVrms
-40
-37.78
10.0
2 Transmission Rate
1188
1200
1212
baud
3 Input Frequency Detection
Bell 202 1 (Mark)
Bell 202 0 (Space)
1188
2178
1200
2200
1212
2222
Hz
Hz
1280.5 1300 1319.5
2068.5 2100 2131.5
CCITT V.23 1 (Mark)
CCITT V.23 0
Notes*
Hz
Hz
(Space)
4 Signal to Noise Ratio
SNRFSK
20
dB
1,2
a. dBV = decibels above or below a reference voltage of 1Vrms.
b. dBm = decibels above or below a reference power of 1mW into 600 ohms. 0dBm = 0.7746Vrms.
*Notes
1. Both mark and space have the same amplitude.
2. Band limited random noise (200-3400Hz). Present when FSK signal is present. Note that the BT band is 300-3400Hz, the Bellcore
band is 0-4kHz.
3. Production tested at VDD =3V ±10%, 5V ±10%.
† AC Electrical Characteristics are over recommended operating conditions, unless otherwise stated.
‡ Typical figures are nominal values and are for design aid only: not guaranteed and not subject to production testing.
AC Electrical Characteristics† - Dual Tone Alert Signal Timing
Characteristics
Sym
Min
Max
Units
Notes*
1
Alert Signal present detect time
tDP
0.5
10
ms
1
2
Alert Signal absent detect time
tDA
0.1
8
ms
1
*Notes
1. Refer to Figures 16 and 19
5-68
MT88E43
Data Sheet
AC Electrical Characteristics† - 3-Wire Interface Timing
Characteristics
1
2
PWDN
OSC1
3
4
CD
5
Sym
Min
Max
Units
Power-up time
tPU
50
ms
Power-down time
tPD
1
ms
Input FSK to CD low delay
tCP
25
ms
Input FSK to CD high delay
tCA
Hysteresis
8
ms
8
ms
Notes
† AC Electrical Characteristics are over recommended operating conditions unless otherwise stated.
AC Electrical Characteristics† - 3-Wire Interface Timing (Mode 0)
Characteristics
1
2
DR
3
4
Sym
Min
Typ‡
Max
Units
Notes*
Rise time
tRR
200
ns
into 50pF Load
Fall time
tRF
200
ns
into 50pF Load
Low time
tRL
Rate
415
416
417
µs
2
1188
1200
1212
baud
1
1
5
ms
DATA
5
Input FSK to DATA delay
6
Rise time
tR
200
ns
into 50pF Load
Fall time
tF
200
ns
into 50pF Load
7
DATA
DCLK
tIDD
DATA to DCLK delay
tDCD
6
416
µs
1, 2, 3
9
DCLK to DATA delay
tCDD
6
416
µs
1, 2, 3
10
Frequency
fDCLK0
1201.6
1202.8
1204
Hz
2
High time
tCH
415
416
417
µs
2
Low time
tCL
415
416
417
µs
2
DCLK
DCLK to DR delay
tCRD
415
416
417
µs
DR
† AC Electrical Characteristics are over recommended operating conditions unless otherwise stated.
‡ Typical figures are at 25oC and are for design aid only: not guaranteed and not subject to production testing.
*Notes:
1. FSK input data at 1200 ±12 baud.
2. OSC1 at 3.579545 MHz ±0.1%.
3. Function of signal condition.
2
8
11
DCLK
12
13
AC Electrical Characteristics† - 3-Wire Interface Timing (Mode 1)
Characteristics
1
2
Frequency
DCLK
3
4
5
DCLK,
DR
Sym
Min
fDCLK1
Duty cycle
30
Max
Units
1
MHz
70
%
20
ns
Rise time
tR1
DCLK low set up to DR
tDDS
500
ns
DCLK low hold time after DR
tDDH
500
ns
Notes
† AC Electrical Characteristics are over recommended operating conditions unless otherwise stated.
5-69
MT88E43
Data Sheet
tCDD
tDCD
VHM
VCT
VLM
DATA
tF
tR
VHM
VCT
VLM
DCLK
tCL
tCH
tR
tF
Figure 12 - DATA and DCLK Mode 0 Output Timing
tRR
tRF
VHM
VCT
VLM
DR
tRL
Figure 13 - DR Output Timing
TIP/RING
(A/B)
WIRES
start
stop
b7
1
0
start
stop
b0 b1 b2 b3 b4 b5 b6 b7
1
start
stop
b0 b1 b2 b3 b4 b5 b6 b7
0
1
0
b0 b1 b2
tIDD
start
DATA
start
b0 b1 b2 b3 b4 b5 b6 b7
b7
stop
start
b0 b1 b2 b3 b4 b5 b6 b7
stop
1/fDCLK0
DCLK
tRL
tCRD
DR
Figure 14 - Serial Data Interface Timing (MODE 0)
5-70
b0 b1 b2
stop
MT88E43
Data Sheet
VHM
DCLK
VLM
tR1
Figure 15 - DCLK Mode 1 Input Timing
Demodulated
internal bit
stream
word N+1
word N
stop
7
0
start
2
1
3
4
5
6
7
stop
tRL
DR
ëëëëëë¿
tDDS
¡
1/fDCLK1
tDDH
DCLK
DATA
6
word N-1
7
0
1
2
3
4
5
6
7
0
word N
¿ DCLK clears DR
¡ DCLK does not clear DR, so DR is low for maximum time (1/2 bit width)
Figure 16 - Serial Data Interface Timing (Mode 1)
5-71
MT88E43
Data Sheet
Alerting Signal
Line Reversal
Ch. seizure
A/B Wires
A
B
C
D
Mark
E
Ring
Data Packet
F
G
TRIGout
Note 6
Note 1
Note 2
PWDN
tDA
tDP
ESt
50-150ms
tGP
tGA
VTGt
St/GT
tREC
tABS
StD
TE DC load
Note 3
15±1ms
<120µµA
20±5ms
TE AC load
< 0.5mA (optional)
Current wetting pulse (see SIN227)
Note 4
Zss (Refer to SIN227)
FSKen
Note 5
tCP
tCA
CD
DR
DCLK
DATA
..101010..
tPU
OSCout
Data
tPD
A ≥ 100ms
B = 88-110ms
C ≥ 45ms (up to 5sec)
D = 80-262ms
E = 45-75ms
F ≤ 2.5sec (typ. 500ms)
G > 200ms
Note: All values obtained
from SIN227 Issue 1
Figure 17 - Input and Output Timing for BT Caller Display Service (CDS), e.g., CLIP
Notes:
1) The total recognition time is t REC = t GP + t DP, where t GP is the tone present guard time and t DP is the tone present detect time (refer
to section “Dual Tone Detection Guard Time” on page 58 for details). V TGt is the comparator threshold (refer to Figure 4).
2) The total tone absent time is t ABS = t GA + t DA, where t GA is the tone absent guard time and t DA is the tone absent detect time (refer
to section “Dual Tone Detection Guard Time” on page 58 for details). V TGt is the comparator threshold (refer to Figure 4).
3) By choosing t GA=15ms, t ABS will be 15-25ms so that the current wetting pulse and AC load can be applied right after the StD falling
edge.
4) SIN227 specifies that the AC and DC loads should be removed between 50-150ms after the end of the FSK signal, indicated by CD
returning to high. The MT88E43 may also be powered down at this time.
5) FSKen should be set low when FSK is not expected to prevent the FSK demodulator from reacting to other in-band signals such as
speech, tone alert signal and DTMF tones.
6) TRIGout is the ring envelope during ringing.
5-72
MT88E43
Data Sheet
First Ring Cycle
Ring Burst
Line Reversal
Ch. seizure
Mark
Data Packet
A/B Wires
A
TRIGout
B
C
D
E
F
Note 3
Note 3
50-150ms
PWDN
250-400ms
TE DC load
TE AC load
Note 1
FSKen
Note 2
tCP
tCA
CD
DR
DCLK
DATA
OSCout
tPU
..101010..
Data
tPD
A = 200-450ms
B ≥ 500ms
C = 80-262ms
D = 45-262ms
E ≤ 2.5s (typ. 500ms)
F >200ms
Note: Parameter F
from "CCA Exceptions
Document Issue 3"
Figure 18 - Input and Output Timing for CCA Caller Display Service (CDS), e.g., CLIP
Notes:
1) TW/P&E/312 specifies that the AC and DC loads should be removed between 50 to 150ms after the end of the FSK signal, indicated
by CD returning to high. The MT88E43 may also be powered down at this time.
2) FSKen should be set low when FSK is not expected to prevent the FSK demodulator from reacting to other in-band signals such as
speech, and DTMF tones.
3) TRIGout represents the ring envelope during ringing.
5-73
MT88E43
TIP/RING
Data Sheet
1st Ring
A
Ch. seizure
B
C
Mark
D
2nd Ring
Data Packet
E
F
TRIGout
Note 4
PWDN
Note 1
Note 3
Note 1
tPU
OSCout
tPD
FSKen
Note 2
tCP
tCA
CD
A = 2sec typical
B = 250-500ms
C = 250ms
D = 150ms
E = feature specific
Max C+D+E = 2.9 to 3.7sec
F ≥ 200ms
DR
DCLK
DATA
.101010..
Data
Figure 19 - Input and Output Timing for Bellcore On-hook Data Transmission Associated with
Ringing, e.g., CID
Notes:
This on-hook case application is included because a CIDCW (off-hook) CPE should also be capable of receiving on-hook data
transmission (with ringing) from the end office. TR-NWT-000575 specifies that CIDCW will be offered only to lines which subscribe to
CID.
1) The CPE designer may choose to enable the MT88E43 only after the end of ringing to conserve power in a battery operated CPE. CD is not
activated by ringing.
2) The CPE designer may choose to set FSKen always high while the CPE is on-hook. Setting FSKen low prevents the FSK
demodulator from reacting to other in-band signals such as speech, CAS or DTMF tones.
3) The microcontroller in the CPE powers down the MT88E43 after CD has become inactive.
4) The microcontroller times out if CD is not activated.
5-74
MT88E43
Data Sheet
CPE goes off-hook
CPE unmutes handset
and enables keypad
CPE mutes handset & disables keypad
CPE sends
CAS
TIP/RING
A
Note 1
C
B
D
E
Data
Packet
F
G
Note 5
PWDN
FSKen
Mark
ACK
Note 2
Note 3
Note 4
tPU
OSCout
tDP
tDA
ESt
tGA
VTGt
tGP
St/GT
tABS
tREC
StD (Note 6)
CD
Note 7
Note 8
tCP
tCA
DR
DCLK
DATA
Data
A = 75-85ms
B = 0-100ms
C = 55-65ms
D = 0-500ms
E = 58-75ms
F = feature specific
G ≤ 50ms
Figure 20 - Input and Output Timing for Bellcore Off-hook Data Transmission, e.g., CIDCW
Notes:
1) In a CPE where AC power is not available, the designer may choose to switch over to line power when the CPE goes off-hook and
use battery power while on-hook. The CPE should also be CID (on-hook) capable because TR-NWT-000575 specifies that CIDCW
will be offered only to lines which subscribe to CID.
2) Non-FSK signals such as CAS, speech and DTMF tones are in the same frequency band as FSK. They will be demodulated and
give false data. The FSKen pin should be set low to disable the FSK demodulator when FSK is not expected.
3) FSKen may be set high as soon as the CPE has finished sending the acknowledgment signal ACK. TR-NWT-000575 specifies that
ACK = DTMF D for non-ADSI CPE, A for ADSI CPE.
4) FSKen should be set low when CD has become inactive.
5) In an unsuccessful attempt where the end office does not send the FSK signal, the CPE should unmute the handset and enable the
keypad after this interval.
6) SR-TSV-002476 states that it is desirable that the CPE have an on/off switch for the CAS detector. See SW1 in Figure 4.
7) The total recognition time is t REC = t GP + t DP, where t GP is the tone present guard time and t DP is the tone present detect time (refer
to section “Dual Tone Detection Guard Time” on page 58 for details). V TGt is the comparator threshold (refer to Figure 4).
8) The total tone absent time is t ABS = t GA + t DA, where t GA is the tone absent guard time and t DA is the tone absent detect time (refer
to section “Dual Tone Detection Guard Time” on page 58 for details). V TGt is the comparator threshold (refer to Figure 4).
5-75
MT88E43
Notes:
5-76
Preliminary Information
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