NB3N51034 3.3V, Crystal to 100MHz/ 200MHz Quad HCSL/LVDS Clock Generator The NB3N51034 is a high precision, low phase noise clock generator that supports spread spectrum designed for PCI Express applications. This device takes a 25 MHz fundamental mode parallel resonant crystal and generates 4 differential HCSL/LVDS outputs at 100 MHz or 200 MHz (See Figure 6 for LVDS interface). The NB3N51034 provides selectable spread options of −0.5%, −1.0%, −1.5%, for applications demanding low Electromagnetic Interference (EMI). No spread setting is also available. http://onsemi.com MARKING DIAGRAM NB3N 1034 ALYWG G Features • • • • • • • Uses 25 MHz Fundamental Mode Parallel Resonant Crystal TSSOP−20 Power Down Mode DT SUFFIX CASE 948E 4 Low Skew HCSL or LVDS Outputs A = Assembly Location OE Tri−States Outputs L = Wafer Lot Spread of −0.5%, −1.0%, −1.5% and No Spread Y = Year PCIe Gen 1, 2, 3 Jitter Compliant W = Work Week G = Pb−Free Package Phase Noise (SS OFF) @ 100 MHz: (Note: Microdot may be in either location) Offset Noise Power 100 Hz −110 dBc/Hz ORDERING INFORMATION 1 kHz −123 dBc/Hz See detailed ordering and shipping information in the package 10 kHz −134 dBc/Hz dimensions section on page 8 of this data sheet. 100 kHz −137 dBc/Hz 1 MHz −138 dBc/Hz 10 MHz −154 dBc/Hz • Operating Range 3.3 V ±5% • Computing and Peripherals • Industrial Temperature Range −40°C to +85°C • Industrial Equipment • Functionally Compatible with IDT557−05, • PCIe Clock Generation Gen I, Gen II and Gen III IDT5V41066, IDT5V41236 End Products • These are Pb−Free Devices • Switch and Router Applications • Set Top Box, LCD TV • Networking • Servers, Desktop Computers • Consumer • Automated Test Equipment VDD S0 S1 S2 PD Spread Spectrum Circuit X1/CLK 25 MHz Clock or Crystal X2 Clock Buffer Crystal Oscillator Charge Pump Phase Detector VCO BN GND Figure 1. NB3N51034 Simplified Logic Diagram © Semiconductor Components Industries, LLC, 2013 October, 2013 − Rev. 1 1 OE HCSL Output CLK0 CLK0 HCSL Output CLK1 CLK1 HCSL Output CLK2 CLK2 HCSL Output CLK3 CLK3 IREF Publication Order Number: NB3N51034/D NB3N51034 VDDXD 1 20 CLK0 S0 2 19 CLK0 S1 3 18 CLK1 S2 4 17 CLK1 X1/CLK 5 16 GNDODA X2 6 15 VDDODA PD 7 14 CLK2 OE 8 13 CLK2 GNDXD 9 12 CLK3 10 11 CLK3 IREF Figure 2. Pin Configuration (Top View) Table 1. PIN DESCRIPTION Pin Symbol I/O Description 1 VDDXD Power 2 S0 Input Spread Spectrum Select pin 0. See Spread Spectrum Select table. Internal pull−up resistor. 3 S1 Input Spread Spectrum Select pin 1. See Spread Spectrum Select table. Internal pull−up resistor. 4 S2 Input Spread Spectrum Select pin 2. See Spread Spectrum Select table. Internal pull−up resistor. 5 X1/CLK Input Crystal interface or single−ended reference clock input. 6 X2 Output 7 PD Input Power down. Internal pull−up resistor. Output enable. Tri−state output (High=enable outputs, Low=disable outputs). Internal pull−up resistor. Connect to a +3.3 V source. Crystal interface. Float this pin for reference clock input CLK. 8 OE Input 9 GNDXD Power Connect to digital circuit ground. 10 IREF Output Precision resistor attached to this pin is connected to the internal current reference. 11 CLK3 Output Selectable 100/200 MHz Spread Spectrum differential compliment output clock 3. 12 CLK3 Output Selectable 100/200 MHz Spread Spectrum differential true output clock 3. 13 CLK2 Output Selectable 100/200 MHz Spread Spectrum differential compliment output clock 2. 14 CLK2 Output Selectable 100/200 MHz Spread Spectrum differential true output clock 2. 15 VDDODA Power Connect to a +3.3 V analog source. 16 GNDODA Power Output and analog circuit ground. 17 CLK1 Output Selectable 100/200 MHz Spread Spectrum differential compliment output clock 1. 18 CLK1 Output Selectable 100/200 MHz Spread Spectrum differential true output clock 1. 19 CLK0 Output Selectable 100/200 MHz Spread Spectrum differential compliment output clock 0. 20 CLK0 Output Selectable 100/200 MHz Spread Spectrum differential true output clock 0. Recommended Crystal Parameters Table 2. OUTPUT FREQUENCY AND SPREAD SPECTRUM SELECT TABLE S2 S1 S0 Spread% Spread Type Output Frequency 0 0 0 −0.5 Down 100 0 0 1 −1.0 Down 100 0 1 0 −1.5 Down 100 0 1 1 No Spread N/A 100 1 0 0 −0.5 Down 200 1 0 1 −1.0 Down 200 1 1 0 −1.5 Down 200 1 1 1 No Spread N/A 200 Crystal Frequency Load Capacitance Shunt Capacitance, C0 Equivalent Series Resistance Initial Accuracy at 25 °C Temperature Stability Aging http://onsemi.com 2 Fundamental AT−Cut 25 MHz 16−20 pF 7 pF Max 50 W Max ±20 ppm ±30 ppm ±20 ppm NB3N51034 Table 3. ATTRIBUTES Characteristic Value Internal Input Default State Resistor (OE, Sx, PD) ESD Protection 110 kW Human Body Model 2 kV Moisture Sensitivity, Indefinite Time Out of Dray Pack (Note 1) Flammability Rating Level 1 Oxygen Index: 28 to 34 UL 94 V−0 @ 0.125 in Transistor Count 132,000 Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 1. For additional information, see Application Note AND8003/D. Table 4. MAXIMUM RATINGS (Note 2) Symbol Parameter Condition 1 Condition 2 Rating Units 4.6 V −0.5 V to VDD+0.5 V V VDD Positive Power Supply GND = 0 V VI Input Voltage (VIN) GND = 0 V TA Operating Temperature Range −40 to +85 °C Tstg Storage Temperature Range −65 to +150 °C qJA Thermal Resistance (Junction−to−Ambient) 0 lfpm 500 lfpm TSSOP–20 TSSOP–20 140 50 °C/W °C/W qJC Thermal Resistance (Junction−to−Case) (Note 3) TSSOP−20 23 to 41 °C/W Tsol Wave Solder 265 °C GND v VI v VDD Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 2. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and not valid simultaneously. If stress limits are exceeded device functional operation is not implied, damage may occur and reliability may be affected. 3. JEDEC standard multilayer board − 2S2P (2 signal, 2 power). Table 5. DC CHARACTERISTICS (VDD = 3.3 V ±5%, GND = 0 V, TA = −40°C to +85°C, Note 4) Symbol Characteristic Min Typ Max Unit 3.135 3.3 3.465 V VDD Power Supply Voltage IDD Power Supply Current, 200 Mhz output, SSON 135 mA IDDOE Power Supply Current when OE is Set Low 60 mA IDDPD Power Supply Current (PD = Low, no load) 1.5 mA VIH Input HIGH Voltage (X1/CLK, S0, S1, S2 and OE) 2000 VDD + 300 mV VIL Input LOW Voltage (X1/CLK, S0, S1, S2 and OE) GND − 300 800 mV NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 4. Measurement taken with outputs terminated with RS = 33.2 W, RL = 50 W, with test load capacitance of 2 pF and current biasing resistor set at 475 W. See Figure 5. Guaranteed by characterization. http://onsemi.com 3 NB3N51034 Table 6. AC CHARACTERISTICS (VDD = 3.3 V ±5%, GND = 0 V, TA = −40°C to +85°C; Note 5) Characteristic Symbol Min Typ Max Unit fCLKIN Clock/Crystal Input Frequency 25 MHz fCLKOUT Output Clock Frequency 100/200 MHz Vmax Absolute Maximum Output Voltage (Notes 6, 7) Vmin Absolute Minimum Output Voltage (Notes 6, 8) −300 Vrb Ringback Voltage (Notes 9, 10) −100 100 mV VOH Output High Voltage (Note 6) 660 850 mV VOL Output Low Voltage (Note 6) −150 27 mV VCROSS Absolute Crossing Voltage (Notes 6, 10, 11) 250 550 mV DVCROSS Total Variation of VCROSS (Notes 6, 10, 12) 140 mV fMOD Spread Spectrum Modulation Frequency 33.33 kHz SSCRED Spectral Reduction (Note 13), 3rd harmonic tSKEW Within Device Output to Output Skew fNOISE Phase−Noise Performance SS OFF 1150 30 mV mV 31.5 −10 dB 40 ps dBc/Hz fCLKout = 100 MHz @ 100 Hz offset from carrier −110 @ 1 kHz offset from carrier −123 @ 10 kHz offset from carrier −134 @ 100 kHz offset from carrier −137 @ 1 MHz offset from carrier −138 @ 10 MHz offset from carrier −154 tOE Output Enable/Disable Time (All outputs) (Note 14) 10 ms tDUTY_CYCLE Output Clock Duty Cycle (Measured at cross point) 45 50 55 % tR Output Risetime (Measured from 175 mV to 525 mV, Figure 7) tF Output Falltime (Measured from 525 mV to 175 mV, Figure 7) 175 340 700 ps 175 400 700 ps DtR Output Risetime Variation (Single−Ended) 125 ps DtF Output Falltime Variation (Single−Ended) 125 ps Stabilization Time Stabilization Time From Powerup VDD = 3.3 V 3.0 ms NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 5. Measurement taken from differential output on single−ended channel terminated with RS = 33.2 W, RL = 50 W, with test load capacitance of 2 pF and current biasing resistor set at 475 W. See Figure 5. Guaranteed by characterization. 6. Measurement taken from single-ended waveform 7. Defined as the maximum instantaneous voltage value including positive overshoot 8. Defined as the maximum instantaneous voltage value including negative overshoot 9. Measurement taken from differential waveform 10. Measured at crossing point where the instantaneous voltage value of the rising edge of CLKx+ equals the falling edge of CLKx-. 11. Refers to the total variation from the lowest crossing point to the highest, regardless of which edge is crossing. Refers to all crossing points for this measurement. 12. Defined as the total variation of all crossing voltage of rising CLKx+ and falling CLKx-. This is maximum allowed variance in the VCROSS for any particular system. 13. Spread spectrum clocking enabled. 14. Output pins are tri−stated when OE is asserted LOW. Output pins are driven differentially when OE is HIGH unless device is in power down mode, PD = Low. http://onsemi.com 4 NB3N51034 Table 7. AC ELECTRICAL CHARACTERISTICS − PCI EXPRESS JITTER SPECIFICATIONS, VDD = 3.3 V ± 5%, TA = −40°C to 85°C Symbol tj (PCIe Gen 1) Parameter Typ Max PCIe Industry Spec SSOFF 10 20 86 ps SSON (−0.5%) 19 28 SSOFF 1.0 1.8 3.1 ps SSON (−0.5%) 1.1 1.9 SSOFF 0.1 0.15 3.0 ps SSON (−0.5%) 0.8 1.1 SSOFF 0.35 0.7 1.0 ps SSON (−0.5%) 0.55 0.8 Test Conditions Phase Jitter Peak−to−Peak (Notes 16 and 19) f = 100 MHz, 25 MHz Crystal Input Evaluation Band: 0 Hz − Nyquist (clock frequency/2) tREFCLK_HF_RMS (PCIe Gen 2) Phase Jitter RMS (Notes 17 and 19) f = 100 MHz, 25 MHz Crystal Input High Band: 1.5 MHz − Nyquist (clock frequency/2) tREFCLK_LF_RMS (PCIe Gen 2) Phase Jitter RMS (Notes 17 and 19) f = 100 MHz, 25 MHz Crystal Input Low Band: 10 kHz − 1.5 MHz tREFCLK_RMS (PCIe Gen 3) Phase Jitter RMS (Notes 18 and 19) f = 100 MHz, 25 MHz Crystal Input Evaluation Band: 0 Hz − Nyquist (clock frequency/2) Min Unit 15. Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. 16. Peak−to−Peak jitter after applying system transfer function for the Common Clock Architecture. Maximum limit for PCI Express Gen 1 is 86 ps peak−to−peak for a sample size of 106 clock periods. 17. RMS jitter after applying the two evaluation bands to the two transfer functions defined in the Common Clock Architecture and reporting the worst case results for each evaluation band. Maximum limit for PCI Express Generation 2 is 3.1 ps RMS for tREFCLK_HF_RMS (High Band) and 3.0ps RMS for tREFCLK_LF_RMS (Low Band). 18. RMS jitter after applying system transfer function for the common clock architecture. 19. Measurement taken from differential output on single−ended channel terminated with RS = 33.2 W, RL = 50 W, with test load capacitance of 2 pF and current biasing resistor set at 475 W. See Figure 5. This parameter is guaranteed by characterization. Not tested in production. http://onsemi.com 5 NB3N51034 NOISE POWEER (dBc/Hz) PHASE NOISE OFFSET FREQUENCY (Hz) NOISE POWEER (dBc/Hz) Figure 3. Typical Phase Noise at 100 MHz; integration range 12 kHz to 20 MHz (Input source at 25 MHz and HCSL output termination) OFFSET FREQUENCY (Hz) Figure 4. Typical Phase Noise at 200 MHz; integration range 12 kHz to 20 MHz (Input source at 25 MHz and HCSL output termination) http://onsemi.com 6 NB3N51034 HCSL INTERFACE CLK0 RL* = 33.2 W Zo = 50 W RL* = 33.2 W Zo = 50 W CLK0 RL = 50 W RL = 50 W NB3N51034 Receiver CLK3 RL* = 33.2 W Zo = 50 W RL* = 33.2 W Zo = 50 W CLK3 IREF RL = 50 W *Optional RL = 50 W RREF = 475 W Figure 5. Typical Termination for HCSL Output Driver and Device Evaluation LVDS COMPATIBLE INTERFACE CLK0 RL* = 33.2 W Zo = 50 W 100 W RL* = 33.2 W 100 W Zo = 50 W CLK0 RL = 150 W RL = 150 W NB3N51034 Receiver CLK3 RL* = 33.2 W Zo = 50 W 100 W RL* = 33.2 W 100 W Zo = 50 W CLK3 IREF RL = 150 W *Optional RL = 150 W LVDS Device Load RREF = 475 W Figure 6. Typical Termination for LVDS Device Load 700 mV 525 mV 525 mV 175 mV 175 mV 0 mV tR tF Figure 7. HCSL Output Parameter Characteristics http://onsemi.com 7 NB3N51034 ORDERING INFORMATION Package Shipping† NB3N51034DTG TSSOP−20 (Pb−Free) 75 Units / Rail NB3N51034DTR2G TSSOP−20 (Pb−Free) 2500 / Tape & Reel Device †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. http://onsemi.com 8 NB3N51034 PACKAGE DIMENSIONS 20X 0.15 (0.006) T U 2X L TSSOP−20 CASE 948E−02 ISSUE C K REF 0.10 (0.004) S L/2 20 M T U S V ÍÍÍÍ ÍÍÍÍ ÍÍÍÍ S J J1 11 B −U− PIN 1 IDENT SECTION N−N 0.25 (0.010) N 1 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE −W−. K K1 10 M 0.15 (0.006) T U S A −V− N F DETAIL E −W− C G D H 0.100 (0.004) −T− SEATING DETAIL E SOLDERING FOOTPRINT PLANE DIM A B C D F G H J J1 K K1 L M MILLIMETERS MIN MAX 6.40 6.60 4.30 4.50 --1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.27 0.37 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.252 0.260 0.169 0.177 --0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.011 0.015 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_ 7.06 1 0.65 PITCH 16X 0.36 16X DIMENSIONS: MILLIMETERS 1.26 ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). 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