¨ ADS1610 SBAS344C – AUGUST 2005 – REVISED OCTOBER 2006 16-Bit, 10 MSPS ANALOG-TO-DIGITAL CONVERTER FEATURES • • • • • • • • • • • • High-Speed, Wide Bandwidth ∆Σ ADC 10MSPS Output Data Rate 4.9MHz Signal Bandwidth 86dBFS Signal-to-Noise Ratio –94dB Total Harmonic Distortion 95dB Spurious-Free Dynamic Range On-Chip Digital Filter Simplifies Anti-Alias Requirements SYNC Pin for Simultaneous Sampling with Multiple ADS1610s Low 3µs Group Delay Parallel Interface Directly Connects to TMS320 DSPs Out-of-Range Alert Pin APPLICATIONS • • • Scientific Instruments Test Equipment Communications The ADS1610 ∆Σ topology provides key system-level design advantages with respect to anti-alias filtering and clock jitter. The design of the user's front-end anti-alias filter is simplified since the on-chip digital filter greatly attenuates out-of-band signals. The ADS1610s filter has a brick wall response with a very flat passband (±0.0002dB of ripple) followed immediately by a very wide stop band (5MHz to 55MHz). Clock jitter becomes especially critical when digitizing high frequency, large-amplitude signals. The ADS1610 significantly reduces clock jitter sensitivity by an effective averaging of clock jitter as a result of oversampling the input signal. Output data is supplied over a parallel interface and easily connects to TMS320 digital signal processors (DSPs). The power dissipation can be adjusted with an external resistor, allowing for reduction at lower operating speeds. With its outstanding high-speed performance, the ADS1610 is well-suited for demanding applications in data acquisition, scientific instruments, test and measurement equipment, and communications. The ADS1610 is offered in a TQFP64 package and is specified from –40°C to 85°C. DESCRIPTION The ADS1610 is a high-speed, high-precision, delta-sigma (∆Σ) analog-to-digital converter (ADC) with 16-bit resolution operating from a 5V analog and a 3V digital supply. Featuring an advanced multi-stage analog modulator combined with an on-chip digital decimation filter, the ADS1610 achieves 86 dBFS signal-to-noise ratio (SNR) in a 5MHz signal bandwidth; while the total harmonic distortion is -94dB. AVDD VREFP VREFN VMID RBIAS VCAP DVDD PD Bias Circuits SYNC CLK AINP ∆Σ Modulator AINN Digital Filter Parallel Interface MODE0 MODE1 RD DRDY OTR DOUT[15:0] ADS1610 AGND DGND Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PowerPAD is a trademark of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2005–2006, Texas Instruments Incorporated ADS1610 www.ti.com SBAS344C – AUGUST 2005 – REVISED OCTOBER 2006 This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ADS1610 passes 1.5K CDM testing. ADS1610 passes 1kV human body model testing (TI Standard is 2kV). ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. PACKAGE/ORDERING INFORMATION For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com. ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) (1) VALUE UNIT AVDD to AGND –0.3 to +6 V DVDD to DGND –0.3 to +3.6 V AGND to DGND –0.3 to +0.3 V 100, Momentary Input current, II mA 10, Continuous Analog I/O to AGND -0.3 to AVDD + 0.3 Digital I/O to DGND -0.3 to DVDD + 0.3 V 150 °C Operating free-air temperature range, TA -40 to +105 °C Storage temperature range, Tstg -60 to +150 °C 260 °C Maximum junction temperature, TJ Lead temperature (soldering, 10s) (1) V Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not implied. ELECTRICAL CHARACTERISTICS All specifications at –40°C to 85°C, AVDD = 5V, DVDD = 3V, fCLK = 60MHz, VREF = 3V, MODE = 00, VCM = 2.5V, and RBIAS = 19kΩ (unless otherwise noted). PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ANALOG INPUT VID(AINP - AINN) Differential input voltage (AINP-AINN) VIC(AINP + AINN)/2 Common-mode input voltage VIHA Absolute input voltage (AINP or AINN with respect to AGND) ±VREF V 2.5 V –0.1 4.2 V DYNAMIC SPECIFICATIONS ǒ 10 Data rate SNR (1) 2 Signal-to-noise ration relative to full-scale (1) fIN = 100kHz, –2dBFS 83 f CLK 60 MHz 86 Ǔ MSPS dBFS For reference, this dynamic specification is extrapolated to full-scale and is thus dBFS. Subsequent dynamic specifications are dBc (dB), which is: Specification (in dBc) = Specification (in dBFS) + AIN (input amplitude in dBFS). For more information see Understanding and comparing datasheets for high-speed ADCs. Submit Documentation Feedback ADS1610 www.ti.com SBAS344C – AUGUST 2005 – REVISED OCTOBER 2006 ELECTRICAL CHARACTERISTICS (continued) All specifications at –40°C to 85°C, AVDD = 5V, DVDD = 3V, fCLK = 60MHz, VREF = 3V, MODE = 00, VCM = 2.5V, and RBIAS = 19kΩ (unless otherwise noted). PARAMETER SNR Signal-to-noise ratio MIN TYP fIN = 100kHz, –2dBFS TEST CONDITIONS 81 84 fIN = 100kHz, –6dBFS 77 80 fIN = 100kHz, –20dBFS 66 fIN = 1MHz, –2dBFS 83 fIN = 1MHz, –6dBFS 80 fIN = 1MHz, –20dBFS THD SINAD Total harmonic distortion Signal-to-noise and distortion Spurious-free dynamic range Aperture jitter UNIT dB 66 fIN = 4MHz, –2dBFS 79.5 83 fIN = 4MHz, –6dBFS 76 79 fIN = 4MHz, –20dBFS 65 fIN = 100kHz, –2dBFS –90 –83 fIN = 100kHz, –6dBFS –95 –85 fIN = 100kHz, –20dBFS –95 fIN = 1MHz, –2dBFS –91 fIN = 1MHz, –6dBFS –93 fIN = 1MHz, –20dBFS –95 fIN = 4MHz, –2dBFS –109 –100 fIN = 4MHz, –6dBFS –105 –100 fIN = 4MHz, –20dBFS –95 fIN = 100kHz, –2dBFS 83 fIN = 100kHz, –6dBFS 79 fIN = 100kHz, –20dBFS 65 fIN = 1MHz, –2dBFS 82 fIN = 1MHz, –6dBFS 79 fIN = 1MHz, –20dBFS 65 fIN = 4MHz, –2dBFS 83 fIN = 4MHz, –6dBFS 79 fIN = 4MHz, –20dBFS SFDR MAX dB dB 65 fIN = 100kHz, –2dBFS 85 90 fIN = 100kHz, –6dBFS 90 96 fIN = 100kHz, –20dBFS 96 fIN = 1MHz, –2dBFS 94 fIN = 1MHz, –6dBFS 94 fIN = 1MHz, –20 dBFS 96 fIN = 4MHz, –2dBFS 100 109 fIN = 4MHz, –6dBFS 100 105 dB fIN = 4MHz, –20dBFS 95 Excludes jitter of CLK source 2 ps, rms 4 ns Aperture delay Submit Documentation Feedback 3 ADS1610 www.ti.com SBAS344C – AUGUST 2005 – REVISED OCTOBER 2006 ELECTRICAL CHARACTERISTICS (Continued) All specifications at –40°C to 85°C, AVDD = 5V, DVDD = 3V, fCLK = 60MHz, VREF = 3V, MODE = 00, VCM = 2.5V, and RBIAS = 19kΩ (unless otherwise noted). PARAMETER TEST CONDITIONS MIN TYP MAX UNIT DIGITAL FILTER CHARACTERISTICS Passband ǒ 4.4 0 Passband ripple ǒ ǒ 4.6 Passband transition Stop band 5.6 Stop band attentuation 80 ts Settling time f CLK 60 MHz f CLK 4.9 60 MHz –3.0dB attenuation Group delay Ǔ ±0.0002 –0.1dB attenuation td(grp) f CLK 60 MHz 54.4 ǒ ǒ 5.5 60 MHz f CLK dB MHz See Figure 34 3.0 60 MHz f CLK To ±0.001% Ǔ Ǔ MHz MHz dB Ǔ Ǔ µs µs STATIC SPECIFICATIONS Resolution No missing codes Input rms noise Shorted input 1.0 1V input ±0.4 LSB 2.5V input ±1.5 LSB Integral nonlinearity 16 Differential nonlinearity VIO Offset error Bits 1.4 LSB (rms) ±0.5 LSB T = 25°C 0.05 %FS 5 ppm/°C ±0.3 (1) %FS Offset drift G(ERR) Gain error T = 25°C G Gain drift Excluding reference drift 10 ppm/°C CMRR Common-mode rejection ratio At DC 60 dB PSRR Supply-voltage rejection ratiio At DC 80 dB VOLTAGE REFERENCE Vref 2.9 3.0 3.1 V VREFP Reference voltage, (VREFP - VREFN) 3.6 4.0 4.4 V VREFN 0.9 1.0 1.1 V VMID 2.2 2.5 3.8 V DIGITAL INPUT/OUTPUT VIH High-level input voltage 0.7DVDD DVDD V VIL Low-level input voltage DGND 0.3DVDD V VOH High-level output voltage IOH = –50µA VOL Low-level output voltage IOL = 50µA Ilkg Input leakage current DGND < VDIGITAL INPUT < DVDD 0.8DVDD V 0.2DVDD V ±10 µA V POWER-SUPPLY REQUIREMENTS VAVDD AVDD voltage 4.9 5.0 5.1 VDVDD DVDD voltage 2.7 3.0 3.6 V IAVDD AVDD current 150 170 mA IDVDD DVDD current 70 80 mA 960 1100 PD (1) 4 Power dissipation PD = low 4 There is a constant gain error of 3.8% in addition to the variable gain eror of ±0.3%. Therefore, the gain error is 3.8 ±0.3%. Submit Documentation Feedback mW ADS1610 www.ti.com SBAS344C – AUGUST 2005 – REVISED OCTOBER 2006 DEVICE INFORMATION PIN CONFIGURATION HTQFP VREFN VCAP AVDD2 AGND2 CLK AGND DGND DVDD 61 60 59 58 57 56 55 54 53 DVDD VREFN 62 DVDD VMID 63 DVDD VREFP 64 DGND VREFP (TOP VIEW) 52 51 50 49 AGND 1 48 NC AVDD 2 47 NC AGND 3 46 NC AINN 4 45 NC AINP 5 44 DOUT[15] AGND 6 43 DOUT[14] AVDD 7 42 DOUT[13] RBIAS 8 AGND 41 DOUT[12] ADS1610 9 40 DOUT[11] 19 20 21 22 23 24 25 26 27 28 29 30 31 32 DOUT[3] 18 DOUT[2] 17 DOUT[1] 33 DOUT[4] NC NC 16 DOUT[0] 34 DOUT[5] NC MODE 1 15 DVDD 35 DOUT[6] DGND MODE 0 14 DRDY 36 DOUT[7] OTR NC 13 RD 37 DOUT[8] CS AVDD 12 SYNC 38 DOUT[9] DGND AGND 11 DVDD 39 DOUT[10] PD AVDD 10 TERMINAL FUNCTIONS TERMINAL NO. ANALOG/DIGITAL INPUT/OUTPUT AGND 1, 3, 6, 9, 11, 55 Analog Analog ground AVDD 2, 7, 10, 12 Analog Analog supply AINN 4 Analog input Negative analog input AINP 5 Analog input Positive analog input RBIAS 8 Analog Analog bias setting resistor 13, 16, 27, 28, 45–48 — Must be left unconnected. NAME NC MODE DESCRIPTION 14, 15 Digital input 17 Digital input; active low Power-down DVDD 18, 26, 49, 50, 52, 53 Digital Digital supply DGND 19, 25, 51, 54 Digital Digital ground SYNC 20 Digital input; active low Digital reset CS 21 Digital input; active low Chip-select PD Control for four output modes (See MODE SELECTION section) Submit Documentation Feedback 5 ADS1610 www.ti.com SBAS344C – AUGUST 2005 – REVISED OCTOBER 2006 TERMINAL FUNCTIONS (continued) TERMINAL NO. ANALOG/DIGITAL INPUT/OUTPUT RD 22 Digital input; Active low OTR 23 Digital output Analog inputs out-of-range NAME DRDY DESCRIPTION Read enable 24 Digital output Data ready 29–44 Digital output Data output. DOUT[15] is the MSB and DOUT[0] is the LSB. CLK 56 Digital input AGND2 57 Analog Analog ground for AVDD2 AVDD2 58 Analog Analog supply for modulator clocking VCAP 59 Analog Bypass capacitor 60, 61 Analog Negative reference voltage 62 Analog Midpoint voltage 63, 64 Analog Positive reference voltage DOUT[15:0] VREFN VMID VREFP Clock input TIMING SPECIFICATIONS t2 t1 CLK t2 t3 t4 DRDY t4 t6 t5 DOUT[15:0] Data N Data N + 1 Figure 1. Data Retrieval Timing RD, CS t7 t8 DOUT[15:0] Figure 2. DOUT Inactive/Active Timing 6 Submit Documentation Feedback Data N + 2 ADS1610 www.ti.com SBAS344C – AUGUST 2005 – REVISED OCTOBER 2006 CLK DRDY t11 SYNC t9 t10 Valid Data DOUT[15:0] Figure 3. Reset Timing Timing Specifications (1) DESCRIPTION t1 CLK period (1/fCLK) MIN TYP MAX UNIT 1 60 MHz 45% 55% 16.667 1/t1 fCLK ns t2 CLK pulse width, high or low t3 CLK to DRDY high (propagation delay) t4 DRDY pulse width, high or low t5 Previous data valid (hold time) t6 New data valid (setup time) t7 RD and/or CS inactive (high) to DOUT high impedance 15 ns t8 RD and/or CS active (low) to DOUT active 15 ns t9 Delay from SYNC active (low) to all-zero DOUT[15:0] 12 t10 Delay from SYNC inactive (high) to non-zero DOUT[15:0] t11 Delay from SYNC inactive (high )to valid DOUT[15:0] (time – 55 DRDY cycles; required for digital filter to settle). (1) ns 12 ns 3 t1 ns 0 ns 5 ns 21 55 ns DRDY DRDY Output load = 10pF|| 500kΩ. Submit Documentation Feedback 7 ADS1610 www.ti.com SBAS344C – AUGUST 2005 – REVISED OCTOBER 2006 TYPICAL CHARACTERISTICS At TA = 25°C, RBIAS = 19kΩ, AVDD = 5V, DVDD = 3V, fCLK = 60MHz, VREF = 3V, MODE = 00,and VCM = 2.5V (unless otherwise noted). SPECTRAL RESPONSE 0 fIN = 100kHz, −2dBFS SNR = 86dBFS THD = −90dB SFDR = 90dB −20 −60 −80 −100 fIN = 100kHz, −6dBFS SNR = 86dBFS THD = −95dB SFDR = 97dB −20 −40 Amplitude (dB) −40 Amplitude (dB) SPECTRAL RESPONSE 0 −60 −80 −100 −120 −120 −140 −140 −160 −160 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 0 0.5 1.0 3.0 Figure 5. 4.0 4.5 5.0 −60 −80 −100 fIN = 1.0MHz, −6dBFS SNR = 86dBFS THD = −93dB SFDR = 94dB −20 −40 Amplitude (dB) −40 3.5 SPECTRAL RESPONSE 0 fIN = 1.0MHz, −2dBFS SNR = 86dBFS THD = −91dB SFDR = 94dB −20 Amplitude (dB) 2.5 Figure 4. SPECTRAL RESPONSE −60 −80 −100 −120 −120 −140 −140 −160 −160 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 0 0.5 1.0 2.5 3.0 Figure 6. Figure 7. 3.5 4.0 4.5 5.0 4.0 4.5 5.0 SPECTRAL RESPONSE 0 fIN = 4.0MHz, −6dBFS SNR = 86dBFS SFDR = 105dB −20 −40 Amplitude (dB) −40 2.0 Frequency (MHz) fIN = 4.0MHz, −2dBFS SNR = 86dBFS SFDR = 109dB −20 1.5 Frequency (MHz) SPECTRAL RESPONSE 0 Amplitude (dB) 2.0 Frequency (MHz) 0 −60 −80 −100 −60 −80 −100 −120 −120 −140 −140 −160 −160 0 8 1.5 Frequency (MHz) 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 0 0.5 1.0 1.5 2.0 2.5 3.0 Frequency (MHz) Frequency (MHz) Figure 8. Figure 9. Submit Documentation Feedback 3.5 ADS1610 www.ti.com SBAS344C – AUGUST 2005 – REVISED OCTOBER 2006 TYPICAL CHARACTERISTICS (continued) At TA = 25°C, RBIAS = 19kΩ, AVDD = 5V, DVDD = 3V, fCLK = 60MHz, VREF = 3V, MODE = 00,and VCM = 2.5V (unless otherwise noted). SIGNAL-TO-NOISE RATIO, TOTAL HARMONIC DISTORTION, AND SPURIOUS-FREE DYNAMIC RANGE vs INPUT SIGNAL AMPLITUDE SIGNAL-TO-NOISE RATIO vs INPUT FREQUENCY 90 100 VIN = 2 dBFS 85 90 SFDR 80 −THD SNR (dB) SNR, THD, SFDR (dB) 80 70 60 SNR 50 VIN = -6 dBFS 75 70 VIN = -20 dBFS 40 65 30 20 10 −70 60 0.01 fIN = 100 kHz −60 −50 −40 −30 Input Signal (dB) −20 −10 0.1 1 fIN - Input Frequency - Mhz 0 Figure 10. 10 Figure 11. TOTAL HARMONIC DISTORTION vs INPUT FREQUENCY SPURIOUS-FREE DYNAMIC RANGE vs INPUT FREQUENCY -85 110 VIN = -20 dBFS -90 105 VIN = -2 dBFS -95 SFDR (dB) THD (dB) VIN = -6 dBFS -100 VIN = -6 dBFS 100 95 VIN = -2 dBFS -105 VIN = -20 dBFS 90 -110 0.01 0.1 1 fIN - Input Frequency - Mhz 85 0.01 10 0.1 1 fIN - Input Frequency - Mhz Figure 12. 10 Figure 13. TOTAL HARMONIC DISTORTION vs CLK FREQUENCY SIGNAL-TO-NOISE RATIO vs CLK FREQUENCY −80 90 RBIAS = 25 k 88 RBIAS = 31 k −85 RBIAS = 19 k THD (dB) SNR (dB) RBIAS = 37 k 86 RBIAS = 25 k 84 RBIAS = 31 k −90 −95 −100 RBIAS = 19 k RBIAS = 37 k 82 −105 fIN = 100 kHz,−6 dBFS 80 5 6 7 fin = 100 KHz, 6 dBFs 8 9 10 11 −110 5 CLK Frequency, fCLK (MHz) 6 7 8 9 10 11 CLK Frequency, fCLK (MHz) Figure 14. Figure 15. Submit Documentation Feedback 9 ADS1610 www.ti.com SBAS344C – AUGUST 2005 – REVISED OCTOBER 2006 TYPICAL CHARACTERISTICS (continued) At TA = 25°C, RBIAS = 19kΩ, AVDD = 5V, DVDD = 3V, fCLK = 60MHz, VREF = 3V, MODE = 00,and VCM = 2.5V (unless otherwise noted). SPURIOUS-FREE DYNAMIC RANGE vs CLK FREQUENCY SIGNAL-TO-NOISE RATIO vs TEMPERATURE 110 90 RBIAS = 19 k Vin = −2 dBFs 105 85 100 80 SNR (dB) SFDR (dB) Vin = −6 dBFs 95 RBIAS = 25 k 90 75 70 Vin = −20 dBFs RBIAS = 31 k fin = 100 kHz, −6 dBFs 85 65 RBIAS = 37 k fin = 100 KHz 80 5 6 7 8 9 CLK Frequency, fCLK (MHz) 10 60 −40 11 −20 0 20 40 60 80 Temperature (°C) Figure 16. Figure 17. SPURIOUS-FREE DYNAMIC RANGE vs TEMPERATURE TOTAL HARMONIC DISTORTION vs TEMPERATURE 110 −85 Vin = −2 dBFs fin = 100 KHz −90 Vin = −6 dBFs 105 Vin = −20 dBFs SFDR (dB) THD (dB) Vin = −6 dBFs −95 −100 Vin = −2 dBFs −105 100 95 Vin = −20 dBFs 90 fin = 100 KHz −20 0 20 40 Temperature (°C) 60 85 −40 80 20 40 Figure 19. INL ERROR vs INPUT VOLTAGE INL ERROR vs INPUT VOLTAGE 1 2 0.8 1.5 0.6 1 0.5 60 80 0 -0.5 -1 0.4 0.2 0 -0.2 -0.4 -1.5 -0.6 -2 -0.8 -1 -2 -1 0 1 2 2.5 -1 VI - Input Voltage - V -0.5 0 VI - Input Voltage - V Figure 20. 10 0 Figure 18. 2.5 -2.5 -2.5 −20 Temperature (°C) INL Error - (16-bit LSB) INL Error - (16-bit LSB) −110 −40 Figure 21. Submit Documentation Feedback 0.5 1 ADS1610 www.ti.com SBAS344C – AUGUST 2005 – REVISED OCTOBER 2006 TYPICAL CHARACTERISTICS (continued) At TA = 25°C, RBIAS = 19kΩ, AVDD = 5V, DVDD = 3V, fCLK = 60MHz, VREF = 3V, MODE = 00,and VCM = 2.5V (unless otherwise noted). NOISE HISTOGRAM (With Inputs Shorted) OUTPUT DATA RATE vs POWER CONSUMPTION 25k 1000 VIN = 0 V 900 Power consumption - mW Occurrences 20k 15k 1k 500 Rbias = 19 KW Rbias = 25 KW 800 700 600 Rbias = 37 KW 500 0 −6 Rbias = 31 KW −4 −2 0 2 Output Code (LSB) 4 6 400 1 Figure 22. 2 3 4 7 5 6 Output Data Rate - Mhz 8 9 10 Figure 23. Submit Documentation Feedback 11 ADS1610 www.ti.com SBAS344C – AUGUST 2005 – REVISED OCTOBER 2006 OVERVIEW ANALOG INPUTS (AINP, AINN) The ADS1610 is a high-performance, delta-sigma ADC. The modulator uses an inherently stable, pipelined, delta-sigma modulator architecture incorporating proprietary circuitry that allows for very linear high-speed operation. The modulator samples the input signal at 60MSPS (when fCLK = 60MHz). A low-ripple linear phase digital filter decimates the modulator output by 6 to provide data output word rates of 10MSPS with a signal passband out to 4.9MHz. The ADS1610 supports a very wide range of input signals. Having such a wide input range makes out-of-range signals unlikely. However, should an out-of-range signal occur, the digital output OTR will go high. Conceptually, the modulator and digital filter measure the differential input signal, VID = (AINP – AINN), against the differential reference, Vref = (VREFP – VREFN), as shown in Figure 11. A 16-bit parallel data bus, designed for direct connection to DSPs, outputs the data. A separate power supply for the I/O allows flexibility for interfacing to different logic families. Out-of-range conditions are indicated with a dedicated digital output pin. Analog power dissipation is controlled using an external resistor. This allows reduced dissipation when operating at slower speeds. When not in use, power consumption can be dramatically reduced using the PD pin. The analog inputs must be driven with a differential signal to achieve optimum performance. The recommended common-mode voltage of the input V + AINP ) AINN 2 signal, CM is 2.5V. To achieve the highest analog performance, it is recommended that the inputs be limited to no greater than 0.891VREF (-1dBFS). For VREF = 3V, the corresponding recommended input range is 2.67V. In addition to the differential and common-mode input voltages, the absolute input voltage is also important. This is the voltage on either input (AINP or AINN) with respect to AGND. The range for this voltage is: *0.1 V t (AINN or AINP) t 4.2 V (1) If either input is taken below –0.1V, ESD protection diodes on the inputs will turn on. Exceeding 4.2V on either input will result in linearity performance degradation. ESD protection diodes will also turn on if the inputs are taken above AVDD (+5V). VREFP VREFN Σ VREF OTR AINP AINN Σ VIN Σ∆ Modulator Digital Filter Parallel Interface DOUT[15:0] MODE[1:0] Figure 24. Conceptual Block Diagram INPUT CIRCUITRY The ADS1610 uses switched-capacitor circuitry to measure the input voltage. Internal capacitors are charged by the inputs and then discharged internally with this cycle repeating at the frequency of CLK. Figure 25 shows a conceptual diagram of these 12 circuits. Switches S2 represent the net effect of the modulator circuitry in discharging the sampling capacitors, the actual implementation is different. The timing for switches S1 and S2 is shown in Figure 26. Submit Documentation Feedback ADS1610 www.ti.com SBAS344C – AUGUST 2005 – REVISED OCTOBER 2006 driver circuits low-thermal noise in the driver circuits degrades the overall noise performance. When the signal can be AC-coupled to the ADS1610 inputs, a simple RC filter can set the input common mode voltage. The ADS1610 is a high-speed, highperformance ADC. Special care must be taken when selecting the test equipment and setup used with this device. Pay particular attention to the signal sources to ensure they do not limit performance when measuring the ADS1610. ADS1610 S1 AINP S2 10pF 8pF VMID S1 AINN S2 10pF 8pF 10 pF ADS1610 VMID 787Ω AGND 374Ω Figure 25. Conceptual Diagram of Internal Circuitry Connected to the Analog Inputs 12.5Ω AINP VIN 100pF 56.2Ω VCM 374Ω THS4503 100pF AINN −VIN 787Ω 56 .2Ω t SAMPLE = 1/f CLK 12.5Ω 100pF On S1 10 pF Off On S2 Off Figure 27. Recommended Single-Ended to Differential Conversion Circuit Using the THS4503 Differential Amplifier Figure 26. Timing for the Switches in Figure 25 DRIVING THE INPUTS The external circuits driving the ADS1610 inputs must be able to handle the load presented by the switching capacitors within the ADS1610. The input switches S1 in Figure 25 are closed approximately one half of the sampling period, tSAMPLE, allowing only ~8 ns for the internal capacitors to be charged by the inputs, when fCLK = 60MHz. Figure 27 and Figure 28 show the recommended circuits when using single-ended or differential op amps, respectively. The analog inputs must be driven differentially to achieve optimum performance. If only a single-ended input signal is available, the configuration in Figure 27 can be used by shorting –VIN to ground. This configuration would implement the single-ended to differential conversion. The external capacitors, between the inputs and from each input to AGND, improve linearity and should be placed as close to the pins as possible. Place the drivers close to the inputs and use good capacitor bypass techniques on their supplies; usually a smaller high-quality ceramic capacitor in parallel with a larger capacitor. Keep the resistances used in the 392 Ω − V IN 392Ω 20 pF 392 Ω O P A 2 8 22 2 0.01 µF V CM(1) 12.5 Ω AINP (2) 100pF 392 Ω 1kΩ 1 µF (2) 392Ω V CM(1) V IN 392 Ω 20 pF 392Ω O P A 2 8 22 100pF (3) A D S 1 6 10 (2) 1kΩ 2 0.01 µF V CM(1) 12.5 Ω AINN (2) 100pF 392Ω 1µF AGND (1) Recommended VCM = 2.5V. (2) Optional ac−coupling circuit provides common−mode input voltage. (3) Increase to 390pF when fIN ≤ 100kHz for improved SNR and THD. Figure 28. Recommended Driver Circuit Using the OPA2822 Submit Documentation Feedback 13 ADS1610 www.ti.com SBAS344C – AUGUST 2005 – REVISED OCTOBER 2006 REFERENCE INPUTS (VREFN, VREFP, VMID) The ADS1610 operates from an external voltage reference. The reference voltage (Vref) is set by the differential voltage between VREFN and VREFP: Vref = (VREFP – VREFN). VREFP and VREFN each use two pins, which should be shorted together. VMID, approximately 2.5V, is used by the modulator. VCAP connects to an internal node and must also be bypassed with an external capacitor. 392Ω 0.001µF ADS1610 10µF 0.1µF 392Ω 0.1µF 0.001µF 22µF The voltages applied to these pins must be within the values specified in the Electrical Characteristics table. Typically VREFP = 4V, VMID = 2.5V, and VREFN = 1V. The external circuitry must be capable of providing both a DC and a transient current. Figure 29 shows a simplified diagram of the internal circuitry of the reference. As with the input circuitry, switches S1 and S2 open and close as shown in Figure 26. VREFP VREFP OPA2822 4V 22µF VMID OPA2822 10µF 2.5V 0.1µF 392Ω 0.001µF 22µF VREFN VREFN OPA2822 1V 10µF 0.1µF VCAP 0.1µF ADS1610 AGND S1 VREFP VREFP 300Ω VREFN VREFN S1 Figure 30. Recommended Reference Buffer Circuit 50pF S2 Figure 29. Conceptual Circuitry for the Reference Inputs Figure 30 shows the recommended circuitry for driving these reference inputs. Keep the resistances used in the buffer circuits low to prevent excessive thermal noise from degrading performance. Layout of these circuits is critical, make sure to follow good high-speed layout practices. Place the buffers and especially the bypass capacitors as close to the pins as possible. CLOCK INPUT (CLK) The ADS1610 uses an external clock signal to be applied to the CLK input pin. The sampling of the modulator is controlled by this clock signal. As with any high-speed data converter, a high quality clock is essential for optimum performance. Crystal clock oscillators are the recommended CLK source; other sources, such as frequency synthesizers may not be adequate. Make sure to avoid excess ringing on the CLK input; keeping the trace as short as possible will help. Measuring high-frequency, large-amplitude signals requires tight control of clock jitter. The uncertainty during sampling of the input from clock jitter limits the maximum achievable SNR. This effect becomes more pronounced with higher frequency and larger magnitude inputs. The ADS1610 oversampling topology reduces clock jitter sensitivity over that of Nyquist rate converters like pipeline and successive approximation converters by a factor of √6. In order to not limit the ADS1610 SNR performance, keep the jitter on the clock source below the values shown in Table 1. When measuring lower frequency and lower amplitude inputs, more CLK jitter can be tolerated. In determining the allowable clock source jitter, select the worst-case input (highest frequency, largest amplitude) that will be seen in the application. 14 Submit Documentation Feedback ADS1610 www.ti.com SBAS344C – AUGUST 2005 – REVISED OCTOBER 2006 DATA FORMAT OUT-OF-RANGE INDICATION (OTR) The 16-bit output data is in binary two's complement format, as shown in Table 2. When the input is positive out-of-range, exceeding the positive full-scale value of VREF, the output clips to all 7FFFH and the OTR output goes high. If the output code on DOUT[15:0] exceeds the positive or negative full-scale, the out-of-range digital output (OTR) will go high on the falling edge of DRDY. When the output code returns within the full-scale range, OTR returns low on the falling edge of DRDY. Table 1. Maximum Allowable Clock Source Jitter for Different Input Signal Frequencies and Amplitude INPUT SIGNAL MAXIMUM ALLOWABLE CLOCK SOURCE JITTER DATA RETRIEVAL Data retrieval is controlled through a simple parallel interface. The falling edge of the DRDY output indicates new data is available. To activate the output bus, both CS and RD must be low, as shown in Table 3. Make sure the DOUT bus does not drive heavy loads (> 20pF), as this will degrade performance. Use an external buffer when driving an edge connector or cables. MAXIMUM FREQUENCY MAXIMUM AMPLITUDE 4MHz –1dB 4MHz –20dB 14ps 2MHz –1dB 3.3ps 2MHz –20dB 29ps 1MHz –1dB 6.5ps Table 3. Truth Table for CS and RD 1.6ps 1MHz –20dB 58ps CS RD 100kHz –1dB 65ps 0 0 Active 100kHz –20dB 581ps 0 1 High impedance 1 0 High impedance 1 1 High impedance Table 2. Output Code Versus Input Signal INPUT SIGNAL (INP – INN) IDEAL OUTPUT CODE(1) OTR ≥ +Vref (> 0dB) 7FFFH 1 Vref (0dB) 7FFFH 0 )V 0001H 0 REF 2 15 * 1 0 *V REF 215 * 1 ǒ2 2 * 1Ǔ 15 *VREF SYNCHRONISING MULTIPLE ADS1610s 0000H 0 FFFFH 0 8000H 0 8000H 1 15 ǒ2 2 * 1Ǔ v *V REF (1)Excludes 15 DOUT [15:0] 15 effects of noise, INL, offset and gain errors. Likewise, when the input is negative out-of-range by going below the negative full-scale value of Vref, the output clips to 8000H and the OTR output goes high. The OTR remains high while the input signal is out-of-range. The ADS1610 is asynchronously reset when the SYNC pin is taken low. During reset, all of the digital circuits are cleared, DOUT[15:0] are forced low, and DRDY forced high. It is recommended that the SYNC pin be released on the falling edge of CLK. Afterwards, DRDY goes low on the second rising edge of CLK. Allow 55 DRDY cycles for the digital filter to settle before retrieving data. See Figure 3 for the timing specifications. Reset can be used to synchronize multiple ADS1610s. All devices to be synchronized must use a common CLK input. With the CLK inputs running, pulse SYNC on the falling edge of CLK, as shown in Figure 31. Afterwards, the converters will be converting synchronously with the DRDY outputs updating simultaneously. After synchronization, allow 55 DRDY cycles (t11) for output data to fully settle. Submit Documentation Feedback 15 ADS1610 www.ti.com SBAS344C – AUGUST 2005 – REVISED OCTOBER 2006 Figure 32 shows the settling error as a function of time for a full-scale signal step applied at t = 0, with MODE = 00 (See Table 4). This figure uses DRDY cycles for the ADS1610 for the time scale (X-axis). After 55 DRDY cycles, the settling error drops below 0.001%. For fCLK = 60MHz, this corresponds to a settling time of 5.5µs. ADS16101 SYNC SYNC Clock CLK DRDY DRDY1 DOUT[15:0] DOUT[15:0]1 101 ADS16102 CLK DRDY DRDY2 100 DOUT[15:0]2 DOUT[15:0] CLK SYNC Settling Error (%) SYNC 10−1 10−2 10−3 10−4 t11 10−5 DRDY1 30 35 40 45 50 55 60 Settling Time (DRDY cycles) Settled Data DOUT[15:0]1 Figure 32. Settling Time DRDY2 Settled Data DOUT[15:0]2 Synchronized Figure 31. Synchronizing Multiple Converters IMPULSE RESPONSE Figure 33 plots the normalized response for an input applied at t = 0, with MODE = 00. The X-axis units of time are DRDY cycles for the ADS1610. As shown in Figure 33, the peak of the impulse takes 30 DRDY cycles to propagate to the output. For fCLK = 60 MHz, a DRDY cycle is 0.1µs in duration and the propagation time (or group delay) is 30 × 0.1µs = 3.0 µs. 1.0 The settling time is an important consideration when measuring signals with large steps or when using a multiplexer in front of the analog inputs. The ADS1610 digital filter requires time for an instantaneous change in signal level to propagate to the output. 0.8 Be sure to allow the filter time to settle after applying a large step in the input signal, switching the channel on a multiplexer placed in front of the inputs, resetting the ADS1610, or exiting the power-down mode. Normalized Response SETTLING TIME 0.6 0.4 0.2 0 −0.2 −0.4 0 10 20 30 40 Time (DRDY cycles) Figure 33. Impulse Response 16 Submit Documentation Feedback 50 60 ADS1610 www.ti.com SBAS344C – AUGUST 2005 – REVISED OCTOBER 2006 FREQUENCY RESPONSE 0 −1 Magnitude (dB) The linear phase FIR digital filter sets the overall frequency response. The decimation rate is set to 6 (MODE = 00) for all the figures shown in this section. Figure 34 shows the frequency response from DC to 30 MHz for fCLK = 60 MHz. The frequency response of the ADS1610 filter scales directly with CLK frequency. For example, if the CLK frequency is decreased by half (to 30 MHz), the values on the X-axis in Figure 34 would need to be scaled by half, with the span becoming DC to 15MHz. −2 −3 −4 −5 −6 −7 4.0 4.1 4.2 0 Magnitude (dB) 4.4 4.5 4.6 4.7 4.8 4.9 5.0 Frequency (MHz) −20 Figure 36. Passband Transition −40 −60 −80 −100 −120 0 5 10 15 20 25 30 Frequency (MHz) Figure 34. Frequency Response The overall frequency response repeats at multiples of the CLK frequency. To help illustrate this, Figure 37 shows the response out to 180 MHz (fCLK = 60MHz). Notice how the passband response repeats at 60MHz, 120MHz, and 180MHz; it is important to consider this sequence when there is high-frequency noise present with the signal. The modulator bandwidth extends to 100MHz. High-frequency noise around 60MHz and 120MHz will not be attenuated by either the modulator or the digital filter. This noise will alias back inband and reduce the overall SNR performance unless it is filtered out prior to the ADS1610. To prevent this, place an anti-alias filter in front of the ADS1610 that rolls off before 55MHz. Figure 35 shows the passband ripple from DC to 4.4MHz (fCLK = 60MHz). Figure 36 shows a closer view of the passband transition by plotting the response from 4.0MHz to 5.0MHz (fCLK = 60MHz). 0 −20 Magnitude (dB) 0.00020 0.00015 0.00010 Magnitude (dB) 4.3 0.00005 −40 −60 −80 −100 0 −120 −0.00005 0 −0.00010 20 40 60 80 100 120 140 160 180 Frequency (MHz) −0.00015 Figure 37. Frequency Response Out to 120MHz −0.00020 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 Frequency (MHz) Figure 35. Passband Ripple Submit Documentation Feedback 17 ADS1610 www.ti.com SBAS344C – AUGUST 2005 – REVISED OCTOBER 2006 NOISE FLOOR two samples is more than 3dB. Figure 38 below shows the typical in-band noise spectral density of the ADS1610. The numbers in the bottom of the figure represent the noise distribution with respect to a full-scale signal in different bandwidths of interest. The shaded area represents the signal bandwidth in the default mode of operation (10MHz output data rate). Power Spectral Density The ADS1610 is a delta sigma ADC and it uses noise shaping to achieve superior SNR performance. The noise floor of a typical successive approximation (SAR) or a pipeline ADC remains flat until the nyquist frequency occurs. A gain of 3dB in SNR can be achieved by averaging two samples, thereby having a tradeoff between output data rate and achievable SNR. In contrast, the noise floor of the ADS1610 inside the bandwidth of interest is shaped. Hence, the gain in SNR that can be achieved by averaging In band Frequency (MHz) 1 2 3 4 5 10 30 96dBFS 93dBFS 91dBFS 88.5dBFS 86dBFS - 74dBFS 55dBFS Figure 38. Typical Filter Bypass Mode Noise Spectral Density By using appropriate filtering the user can achieve a tradeoff between speed and SNR. For ease of use, the ADS1610 provides four filtering modes as explained in the next section. Figure 39 shows a conceptual diagram of the available filtering modes. Custom filtering is achieved by taking the modulator output data and adding a filter externally. AIN ADS1610 Modulator 60M Decimation by 3 20M Decimation by 2 10M Decimation by 2 5M Mux DOUT MODE[1:0] Figure 39. Conceptual Diagram of the ADS1610 Filtering Modes MODE SELECTION ADS1610 offers four different modes of operation each with different output data rates. This gives users the flexibility to choose the best output rate for their application. The outputs of all modes are MSB-aligned. 18 Submit Documentation Feedback ADS1610 www.ti.com SBAS344C – AUGUST 2005 – REVISED OCTOBER 2006 Table 4. Four Modes of Operation (1) Mode 1 Mode 0 0 0 0 1 1 1 (1) OUTPUT RATE OSR SNR (TYP) BITS SETTLING TIME (DRDY cycles) Default 10MHz mode 6 86dBFS 16 55 20MHz 3 74dBFS 14 25 0 5MHz 12 91dBFS 16 55 1 60MHz bypass mode 1 55dBFS 12 NA There is a pull-down resistor of 170kΩ on both mode pins; however, it is recommended that this pin be reduced to either high or low. 20MHz MODE In this mode, the oversampling ratio is three. Decreasing the OSR from 6 to 3 doubles the data rate, at the same time the performance is reduced from 16 bits to 14 bits. Note that all 16 bits of DOUT remain active in this mode. For fclk = 60MHz, the data rate is 20MSPS. In addition, the group delay becomes 1 µs or 13 DRDY cycles. In this mode the noise increases. Typical SNR performance degrades by 14dB. THD remains approximately the same. Table 5. Recommended RBIAS Resistor Values for Different CLK Frequencies fCLK DATA RATE RBIAS TYPICAL POWER DISSIPATION 42MHz 7MHz 45kΩ 550mW 48MHz 8MHz 37kΩ 640mW 54MHz 9MHz 31kΩ 720mW 60MHz 10MHz 19kΩ 960mW POWER-DOWN (PD) 5MHz MODE In this mode the OSR is 12 for fclk = 60MHz and the data rate in 5MSPS. Typical SNR performance increases by 4dB. THD remains approximately the same. 60MHz MODE In this mode, decimation filters are bypassed. This data output can be filtered externally by the user. For fclk = 60MHz, the data rate is 60MSPS. ANALOG POWER DISSIPATION An external resistor connected between the RBIAS pin and the analog ground sets the analog current level, as shown in Figure 40. The current is inversely proportional to the resistor value. Table 5 shows the recommended values of RBIAS for different CLK frequencies. Notice that the analog current can be reduced when using a slower frequency CLK input because the modulator has more time to settle. Avoid adding any capacitance in parallel to RBIAS, since this will interfere with the internal circuitry used to set the biasing. When not in use, the ADS1610 can be powered down by taking the PD pin low. There is an internal pull-up resistor of 170kΩ on the PD pin, but it is recommended that this pin be connected to DVDD if not used. Once the PD pin is pulled high, allow at least t11 (see Timing Specification Table) DRDY cycles for the modulator and the digital filter to settle before retrieving data. POWER SUPPLIES Two supplies are used on the ADS1610: analog (AVDD), and digital (DVDD). Each supply (other than DVDD pins 49 and 50) must be suitably bypassed to achieve the best performance. It is recommended that a 1µF and 0.1µF ceramic capacitor be placed as close to each supply pin as possible. Connect each supply-pin bypass capacitor to the associated ground, as shown in Figure 41. Each main supply bus should also be bypassed with a bank of capacitors from 47µF to 0.1µF, as shown in Figure 41. For optimum performance, insert a 10Ω resistor in series with the AVDD2 supply (pin 58); the modulator clocking circuitry. This resistor decouples switching. ADS1610 RBIAS RBIAS AGND Figure 40. External Resistor Used to Set Analog Power Dissipation Submit Documentation Feedback 19 ADS1610 www.ti.com SBAS344C – AUGUST 2005 – REVISED OCTOBER 2006 DVDD 47mF 4.7 mF 1 mF 0.1 mF CP(1) CP(1) CP(1) 10Ω AGND 6 AGND 7 AVDD 9 AGND 52 51 50 49 DVDD(2) 3 53 DVDD(2) AVDD 54 DGND 2 55 DVDD AGND 57 DVDD 1 58 DGND 0.1mF 1 mF AGND 4.7mF AGND2 47 mF AVDD2 AVDD CP(1) If using separate analog and digital ground planes, connect together on the ADS1610 PCB. CP(1) DGND AGND ADS1610 CP(1) 10 AVDD 11 AGND CP 19 25 (1) CP DVDD DGND 18 DGND 12 AVDD DVDD CP(1) 26 (1) NOTES: (1) CP = 1mF 0.1mF (2) Bypass capacitors not required at pins 49 and 50. Figure 41. Recommended Power-Supply Bypassing LAYOUT ISSUES The ADS1610 is a very high-speed, high-resolution data converter. In order to achieve the maximum performance, careful attention must be given to the printed circuit board (PCB) layout. Use good high-speed techniques for all circuitry. Critical capacitors should be placed close to pins as possible. These include capacitors directly connected to the analog and reference inputs and the power supplies. Make sure to also properly bypass all circuitry driving the inputs and references. planes, one for the analog grounds and one for the digital grounds. When using only one common plane, isolate the flow of current on AGND2 (pin 57) from pin 1; use breaks on the ground plane to accomplish this. AGND2 carries the switching current from the analog clocking for the modulator and can corrupt the quiet analog ground on pin 1. When using two planes, it is recommended that they be tied together right at the PCB. Do not try to connect the ground planes together after running separately through edge connectors or cables as this reduces performance and increases the likelihood of latch-up. Two approaches can be used for the ground planes: either a single common plane; or two separate 20 Submit Documentation Feedback ADS1610 www.ti.com SBAS344C – AUGUST 2005 – REVISED OCTOBER 2006 In general, keep the resistances used in the driving circuits for the inputs and reference low to prevent excess thermal noise from degrading overall performance. Avoid having the ADS1610 digital outputs drive heavy loads. Buffers on the outputs are recommended unless the ADS1610 is connected directly to a DSP or controller situated nearby. Additionally, make sure the digital inputs are driven with clean signals as ringing on the inputs can introduce noise. The ADS1610 uses TI PowerPAD™ technology. The PowerPAD is physically connected to the substrate of the silicon inside the package and must be soldered to the analog ground plane on the PCB using the exposed metal pad underneath the package for proper heat dissipation. See application report SLMA002, located at www.ti.com, for more details on the PowerPAD package. APPLICATION INFORMATION INTERFACING THE ADS1610 TO THE TMS320C6000 Figure 42 illustrates how to directly connect the ADS1610 to the TMS320C6000 DSP. The processor controls reading using output ARE. The ADS1610 is selected using the DSP control output, CE2. The ADS1610 16-bit data output bus is directly connected to the TMS320C6000 data bus. The data ready output (DRDY) from the ADS1610 drives interrupt EXT_INT7 on the TMS320C6000. ADS1610 16 DOUT[15:0] DRDY TMS320C6000 spaces (address or data). This can help reduce the possibility of digital noise coupling into the ADS1610. When not using this signal, replace NAND gate U1 with an inverter between R/W and RD. Two signals, IOSTRB and A15, combine using NAND gate U2 to select the ADS1610. If there are no additional devices connected to the TMS320C5400 I/O space, U2 can be eliminated. Simply connect IOSTRB directly to CS. The ADS1610 16-bit data output bus is directly connected to the TMS320C5400 data bus. The data ready output (DRDY) from the ADS1610 drives interrupt INT3 on the TMS320C5400. ADS1610 DOUT[15:0] XD[15:0] CE2 RD ARE Figure 42. ADS1610 – TMS320C6000 Interface Connection INTERFACING THE ADS1610 TO THE TMS320C5400 Figure 43 illustrates how to connect the ADS1610 to the TMS320C5400 DSP. The processor controls the reading using the outputs R/W and IS. The I/O space-select signal (IS) is optional and is used to prevent the ADS1610 RD input from being strobed when the DSP is accessing other external memory TMS320C5400 D[15:0] DRDY EXT_INT7 CS 16 INT3 CS U2 RD U1 IOSTRB A15 R/W IS Figure 43. ADS1610 – TMS320C5400 Interface Connection Code Composer Studio, available from TI, provides support for interfacing TI DSPs through a collection of data converter plug-ins. Check the TI website, located at www.ti.com/sc/dcplug-in, for the latest information on ADS1610 support. Submit Documentation Feedback 21 PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish (2) MSL Peak Temp Op Temp (°C) Top-Side Markings (3) (4) ADS1610IPAPR ACTIVE HTQFP PAP 64 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 85 ADS1610I ADS1610IPAPRG4 ACTIVE HTQFP PAP 64 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 85 ADS1610I ADS1610IPAPT ACTIVE HTQFP PAP 64 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 85 ADS1610I ADS1610IPAPTG4 ACTIVE HTQFP PAP 64 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 85 ADS1610I (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Top-Side Marking for that device. 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Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 11-Feb-2014 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant ADS1610IPAPR HTQFP PAP 64 1000 330.0 24.4 13.0 13.0 1.4 16.0 24.0 Q2 ADS1610IPAPT HTQFP PAP 64 250 330.0 24.4 13.0 13.0 1.4 16.0 24.0 Q2 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 11-Feb-2014 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) ADS1610IPAPR HTQFP PAP 64 1000 333.2 345.9 31.8 ADS1610IPAPT HTQFP PAP 64 250 333.2 345.9 31.8 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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