Intersil ISL62386HRTZ-T High-efficiency, quad output system power supply controller for notebook computer Datasheet

ISL62386
®
Data Sheet
February 4, 2009
High-Efficiency, Quad Output System
Power Supply Controller for Notebook
Computers
FN6831.0
Features
• High Performance R3 Technology
• Fast Transient Response
The ISL62386 controller generates supply voltages for
battery-powered systems. The ISL62386 includes two
pulse-width modulation (PWM) controllers, adjustable from
0.6V to 5.5V, and two linear regulators, LDO5 and LDO3,
that generate a fixed 5V output and a fixed 3.3V output
respectively. Each can deliver up to 100mA. The Channel 2
switching regulator will automatically take over the LDO5
load when programmed to 5V output. This provides a large
power saving and boosts efficiency. The ISL62386 includes
on-board power-up sequencing, one power-good (PGOOD)
output, digital soft-start, and an internal soft-stop output
discharge that prevents negative voltages on shutdown.
The patented R3 PWM control scheme provides a low jitter
system with fast response to load transients. Light-load
efficiency is improved with period-stretching discontinuous
conduction mode (DCM) operation. To eliminate noise in
audio frequency applications, an ultrasonic DCM mode is
included, which limits the minimum switching frequency to
approximately 28kHz.
The ISL62386 is available in a 32 Ld 5x5 TQFN package,
and can operate over the extended temperature range
(-10°C to +100°C).
• ±1% Output Voltage Accuracy: -10°C to +100°C
• Two Fully Programmable Switch-Mode Power Supplies
with Independent Operation
• Programmable Switching Frequency
• Integrated MOSFET Drivers and Bootstrap Diode
• Fixed +3.3V LDO Output with Enable Control
• Fixed +5V LDO with Automatic Switchover to SMPS2
• Internal Soft-Start and Soft-Stop Output Discharge
• Wide Input Voltage Range: +5.5V to +25V
• Full and Ultrasonic Pulse-Skipping Mode
• Power-Good Indicator
• Overvoltage, Undervoltage and Overcurrent Protection
• Thermal Monitor and Protection
• Pb-Free (RoHS Compliant)
Applications
• Notebook and Sub-Notebook Computers
• PDAs and Mobile Communication Devices
Ordering Information
• General Purpose Switching Buck Regulators
Pinout
62386 HRTZ -10 to +100 32 Ld 5x5 TQFN L32.5x5A
1
UGATE2
PHASE2
ISEN2
VOUT2
32 31 30
29 28 27 26 25
PGOOD
1
24 BOOT2
FSET2
2
23 LGATE2
FCCM
3
22 PGND
AGND2
4
21 LDO5
THERMAL PAD
(AGND)
20 VIN
VCC
5
AGND1
6
19 LDO3
LDO3EN
7
18 LGATE1
FSET1
8
UGATE1
12 13 14 15 16
NC
ISEN1
10 11
FB1
17 BOOT1
9
VOUT1
NOTE: These Intersil Pb-free plastic packaged products employ special
Pb-free material sets, molding compounds/die attach materials, and 100%
matte tin plate plus anneal (e3 termination finish, which is RoHS compliant
and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures
that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
FB2
*Please refer to TB347 for details on reel specifications.
NC
ISL62386
(32 LD 5X5 TQFN)
TOP VIEW
ISL62386HRTZ-T* 62386 HRTZ -10 to +100 32 Ld 5x5 TQFN L32.5x5A
PHASE1
PKG.
DWG. #
EN2
PACKAGE
(Pb-Free)
OCSET2
TEMP
RANGE
(°C)
EN1
ISL62386HRTZ
PART
MARKING
OCSET1
PART
NUMBER
(Note)
• 3-Cell and 4-Cell Li+ Battery-Powered Devices
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2009. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
ISL62386
Absolute Maximum Ratings
Thermal Information
VIN to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +28V
VCC, PGOOD, LDO3, LDO5 to GND. . . . . . . . . . . . . -0.3V to +7.0V
EN1,2, LDO3EN . . . . . . . . . . . . . . . . . . . . -0.3V to GND, VCC + 0.3V
VOUT1,2, FB1,2, FSET1,2 . . . . . . . . . . . . -0.3V to GND, VCC + 0.3V
PHASE1,2 to GND . . . . . . . . . . . . . . . . . . . . . . . (DC) -0.3V to +28V
(<100ns Pulse Width, 10µJ) . . . . . . . . . . . . . . . . . . . . . . . . . -5.0V
BOOT1,2 to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +33V
BOOT1,2 to PHASE1,2 . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +7V
UGATE1,2 . . . . . . . . . . . (DC) -0.3V to PHASE1,2, BOOT1,2 + 0.3V
(<200ns Pulse Width, 20µJ) . . . . . . . . . . . . . . . . . . . . . . . . -4.0V
LGATE1,2 . . . . . . . . . . . . . . . . . . . . (DC) -0.3V to GND, VCC + 0.3V
(<100ns Pulse Width, 4µJ) . . . . . . . . . . . . . . . . . . . . . . . . . . -2.0V
LDO3, LDO5 Output Continuous Current . . . . . . . . . . . . . . +100mA
Thermal Resistance (Typical, Notes 1, 2) θJA (°C/W) θJC (°C/W)
TQFN Package . . . . . . . . . . . . . . . . . .
32
2
Junction Temperature Range. . . . . . . . . . . . . . . . . .-55°C to +150°C
Operating Temperature Range . . . . . . . . . . . . . . . .-10°C to +100°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Recommended Operating Conditions
Ambient Temperature Range. . . . . . . . . . . . . . . . . .-10°C to +100°C
Supply Voltage (VIN to GND). . . . . . . . . . . . . . . . . . . . . 5.5V to 25V
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTES:
1. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See
Tech Brief TB379.
2. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside.
Electrical Specifications
These specifications apply for TA = -10°C to +100°C, unless otherwise noted. Typical values are at TA = +25°C,
VIN = 12V; Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified.
Temperature limits established by characterization and are not production tested.
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Rising Threshold
5.3
5.4
5.5
V
Hysteresis
20
80
150
mV
VIN
VIN Power-on Reset (POR)
VIN Shutdown Supply Current
EN1 = EN2 = GND or Floating, LDO3EN = GND
-
6
15
µA
VIN Standby Supply Current
EN1 = EN2 = GND or Floating, LDO3EN = VCC
-
150
250
µA
I_LDO5 = 0
4.9
5.0
5.1
V
I_LDO5 = 100mA (Note 3)
4.9
5.0
5.1
V
LINEAR REGULATOR
LDO5 Output Voltage
LDO5 Short-Circuit Current (Note 3)
LDO5 = GND
-
190
-
mA
LDO5 UVLO Threshold Voltage (Note 3)
Rising edge of LDO5
-
4.35
-
V
Falling edge of LDO5
-
4.15
-
V
4.63
4.80
4.93
V
-
2.5
3.2
Ω
I_LDO3 = 0
3.25
3.3
3.35
V
I_LDO3 = 100mA (Note 3)
3.25
3.3
3.35
V
-
180
-
mA
SMPS2 to LDO5 Switchover Threshold
SMPS2 to LDO5 Switchover Resistance (Note 3) VOUT2 to LDO5, VOUT2 = 5V
LDO3 Output Voltage
LDO3 Short-Circuit Current (Note 3)
LDO3 = GND
LDO3EN Input Voltage
Rising edge
1.1
-
2.5
V
Falling edge
0.94
-
1.06
V
LDO3EN Input Leakage Current
LDO3EN = GND or VCC
-1
-
1
µA
LDO3 Discharge ON-Resistance
LDO3EN = GND
-
36
60
Ω
VCC Input Bias Current (Note 3)
EN1 = EN2 = VCC, FB1 = FB2 = 0.65V
-
2
-
mA
VCC Start-up Voltage
EN1 = EN2 = LDO3EN = GND
3.45
3.6
3.75
V
VCC
PWM
2
FN6831.0
February 4, 2009
ISL62386
Electrical Specifications
These specifications apply for TA = -10°C to +100°C, unless otherwise noted. Typical values are at TA = +25°C,
VIN = 12V; Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified.
Temperature limits established by characterization and are not production tested. (Continued)
PARAMETER
CONDITIONS
Reference Voltage (Note 3)
MIN
TYP
MAX
UNITS
-
0.6
-
V
Regulation Accuracy
VOUT regulated to 0.6V
-1
-
1
%
FB Input Bias Current
FB = 0.6V
-10
-
30
nA
200
-
600
kHz
Frequency Range
Frequency Set Accuracy (Note 4)
FSW = 300kHz
-12
-
12
%
VOUT Voltage Regulation Range
VIN > 6V for VOUT = 5.5V
0.6
-
5.5
V
-
14
50
Ω
VOUT Soft-Discharge Resistance
POWER-GOOD
PGOOD Pull-Down Impedance
(Note 3)
-
32
50
Ω
PGOOD Leakage Current
PGOOD = VCC
-
0
1
µA
-
5
-
mA
From EN1(2) = High, then from EN2(1) High to
PGOOD High
2.20
2.75
3.70
ms
From EN1(2) = Floating, then from EN2(1) High
to PGOOD High
4.50
5.60
7.50
ms
Maximum PGOOD Sink Current (Note 3)
PGOOD Soft-start Delay
GATE DRIVER
UGATE Pull-Up ON-Resistance (Note 3)
200mA source current
-
1.0
1.5
Ω
UGATE Source Current (Note 3)
UGATE-PHASE = 2.5V
-
2.0
-
A
UGATE Pull-Down ON-Resistance (Note 3)
250mA source current
-
1.0
1.5
Ω
UGATE Sink Current (Note 3)
UGATE-PHASE = 2.5V
-
2.0
-
A
LGATE Pull-Up ON-Resistance (Note 3)
250mA source current
-
1.0
1.5
Ω
LGATE Source Current (Note 3)
LGATE-PGND = 2.5V
-
2.0
-
A
LGATE Pull-Down ON-Resistance (Note 3)
250mA source current
-
0.5
0.9
Ω
LGATE Sink Current (Note 3)
LGATE-PGND = 2.5V
-
4.0
-
A
UGATE to LGATE Deadtime (Note 3)
UG falling to LG rising, no load
-
21
-
ns
LGATE to UGATE Deadtime (Note 3)
LG falling to UG rising, no load
-
21
-
ns
Bootstrap Diode Forward Voltage (Note 3)
2mA forward diode current
-
0.58
-
V
Bootstrap Diode Reverse Leakage Current
VR = 25V
-
0.2
1
µA
Low level (DCM enabled)
-
-
0.8
V
Float level (DCM with audio filter)
1.9
-
2.1
V
High level (Forced CCM)
2.4
-
-
V
FCCM Input Leakage Current
FCCM = GND or VCC
-2
-
2
µA
Audio Filter Switching Frequency (Note 3)
FCCM floating
-
28
-
kHz
EN Input Voltage
Clear fault level/SMPS OFF level
-
-
0.8
V
Delay start level
1.9
-
2.1
V
SMPS ON level
2.4
-
-
V
EN Input Leakage Current
EN = GND or VCC
-3.5
-
3.5
µA
ISEN Input Impedance (Note 3)
EN = VCC
-
600
-
kΩ
CONTROL
FCCM Input Voltage
3
FN6831.0
February 4, 2009
ISL62386
Electrical Specifications
These specifications apply for TA = -10°C to +100°C, unless otherwise noted. Typical values are at TA = +25°C,
VIN = 12V; Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified.
Temperature limits established by characterization and are not production tested. (Continued)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
EN = GND
-
0.1
-
µA
OCSET Input Impedance (Note 3)
EN = VCC
-
600
-
kΩ
OCSET Input Leakage Current (Note 3)
EN = GND
-
0.1
-
µA
OCSET Current Source
EN = VCC
9
10.0
10.5
µA
-1.75
0.0
1.75
mV
ISEN Input Leakage Current (Note 3)
PROTECTION
OCP (VOCSET-VISEN) Threshold
UVP Threshold
Falling edge, referenced to FB
81
84
87
%
OVP Threshold
Rising edge, referenced to FB
113
116
120
%
Falling edge, referenced to FB
99.5
103
106
%
Rising edge
-
150
-
°C
Falling edge
-
135
-
°C
OTP Threshold (Note 3)
NOTES:
3. Limits established by characterization and are not production tested.
4. FSW accuracy reflects IC tolerance only; it does not include frequency variation due to VIN, VOUT, LOUT, ESRCOUT, or other application specific
parameters.
4
FN6831.0
February 4, 2009
ISL62386
Typical Application Circuits
The following typical application circuits generate the 5V/8A and 3.3V/8A main supplies in a
notebook computer. The input supply (VBAT) range is 5.5V to 25V.
VBAT
4x10µF
BO O T1
V IN
BOOT2
0.22µF
0.22µF
IRF7821
4.7µH
3 .3 V
330µF
UGATE1
UG ATE2
PHASE1
PHASE2
LG ATE1
LG ATE2
IRF7821
0.022µF 14k
4.7µH
5V
0.022µF
330µF
14k
IRF7832
IRF7832
ISL62386
14k
14k
750
45.3k
VO UT1
1200pF
VOUT2
FB1
10k
68.1k
IS E N 2
IS E N 1
1200pF
750
OCSET2
OCSET1
FB2
9.09k
AGND1
AGND2
3 .3 V
LDO3
4.7µF
PGOOD
5V
LDO5
4.7µF
LDO5
100k
EN1
EN2
LD O 3EN
FCCM
FSET1
FSET2
VCC
1µF
PGND
0.01µF
24.3k
19.6k
0.01µF
A G N D 1 /2
AGND2
AGND1
FIGURE 1. TYPICAL APPLICATION CIRCUIT WITH INDUCTOR DCR CURRENT SENSE
VBAT
BOOT1
4x10µF
4.7µH
3 .3 V
0.001
330µF
V IN
BOOT2
IRF7821
IRF7821
0.22µF
1k
UG ATE1
UGATE2
PHASE1
PHASE2
LG ATE1
LGATE2
IRF7832
1k
0.22µF
4.7µH
5V
0.001
330µF
IRF7832
1k
1k
ISL62386
750
750
1200pF
OCSET1
45.3k
OCSET2
IS E N 1
IS E N 2
VO UT1
VOUT2
FB1
68.1k
FB2
9.09k
AGND1
10k
3 .3 V
LDO3
4.7µF
AGND2
LDO5
PGOOD
5V
LDO 5
4.7µF
1200pF
EN1
EN2
100k
LD O 3EN
VCC
1µF
FCCM
FSET1
FSET2
PGND
24.3k
19.6k
A G N D 1 /2
0.01µF
0.01µF
AGND2
AGND1
FIGURE 2. TYPICAL APPLICATION CIRCUIT WITH RESISTOR CURRENT SENSE
5
FN6831.0
February 4, 2009
ISL62386
Typical Application Circuits
The below typical application circuits generate the 1.05V/15A and 1.5V/15A main supplies in a
notebook computer. The input supply (VBAT) range is 5.5V to 25V.
VBAT
6x10µF
BO O T1
V IN
BOOT2
0.22µF
0.22µF
IRF7821x2
2.2µH
1 .0 5 V
330µF
UGATE1
UG ATE2
PHASE1
PHASE2
LG ATE1
LG ATE2
IRF7821x2
2.2µH
1 .5 V
330µF
16.2k 0.022µF
0.022µF 16.2k
IRF7832x2
IRF7832x2
ISL62386
590
16.2k
36.5k
VO UT1
1800pF
VOUT2
FB1
48.7k
36.5k
IS E N 2
IS E N 1
1800pF
590
16.2k
OCSET2
OCSET1
FB2
24.3k
AGND1
AGND2
3 .3 V
LDO3
PGOOD
5V
4.7µF
LDO5
4.7µF
LDO 5
100k
EN1
EN2
LD O 3EN
FCCM
FSET1
FSET2
VCC
1µF
PGND
0.01µF
17.4k
14k
0.01µF
A G N D 1 /2
AGND2
AGND1
FIGURE 3. TYPICAL APPLICATION CIRCUIT WITH INDUCTOR DCR CURRENT SENSE
VBAT
IRF7821x2
6x10µF
BO O T1
V IN
IRF7821x2
BOOT2
0.22µF
0.22µF
2.2µH
1 .0 5 V
0.001
330µF
UGATE1
UGATE2
PHASE1
PHASE2
LG ATE1
LG ATE2
2.2µH
IRF7832x2
2k
2k
1 .5 V
0.001
330µF
IRF7832x2
2k
2k
ISL62386
590
1800pF
O CSET1
36.5k
590
OCSET2
IS E N 1
IS E N 2
VOUT1
VOUT2
FB1
36.5k
FB2
24.3k
AGND1
48.7k
1800pF
AGND2
3 .3 V
LDO3
4.7µF
PGOOD
5V
LDO5
4.7µF
LDO 5
100k
EN1
EN2
LDO 3EN
VCC
1µF
FCCM
FSET1
FSET2
PGND
17.4k
14k
A G N D 1 /2
AGND2
0.01µF
0.01µF
AGND1
FIGURE 4. TYPICAL APPLICATION CIRCUIT WITH RESISTOR CURRENT SENSE WITH VCC AS ENABLE POWER SUPPLY
6
FN6831.0
February 4, 2009
ISL62386
Pin Descriptions
PIN
NAME
FUNCTION
1
PGOOD
Open-drain power-good status output. Connect to LDO5 through a 100k resistor. Output will be high when both the SMPSs outputs
are within the regulation window with no faults detected.
2
FSET2
Frequency control input for SMPS2. Connect a resistor to ground to program the switching frequency. A small ceramic capacitor
such as 10nF is necessary to parallel with this resistor to smooth the voltage.
3
FCCM
Logic input to control efficiency mode. Logic high forces continuous conduction mode (CCM). Logic low allows full discontinuous
conduction mode (DCM). Float this pin for ultrasonic DCM operation.
4
AGND2
Analog ground of the SMPS2.
5
VCC
6
AGND1
Analog ground of the SMPS1. AGND1 and AGND2 are connected together internally.
7
LDO3EN
Logic input for enabling and disabling the LDO3 linear regulator. Positive logic input.
8
FSET1
9
FB1
10
VOUT1
11
ISEN1
12
OCSET1
13
EN1
Logic input to enable and disable SMPS1. A logic high will enable SMPS1 immediately. A logic low will disable SMPS1. Floating this
input will delay SMPS1 start-up until after SMPS2 achieves regulation.
14, 27
NC
No connection.
15
PHASE1
SMPS1 switching node for high-side gate drive return and synthetic ripple modulation. Connect to the switching NMOS source, the
synchronous NMOS drain, and the output inductor for SMPS1.
16
UGATE1
High-side NMOS gate drive output for SMPS1. Connect to the gate of the SMPS1 switching FET.
17
BOOT1
SMPS1 bootstrap input for the switching NMOS gate drivers. Connect to PHASE1 with a 0.22µF ceramic capacitor.
18
LGATE1
Low-side NMOS gate drive output for SMPS1. Connect to the gate of the SMPS1 synchronous FET.
19
LDO3
20
VIN
21
LDO5
5V linear regulator output, providing up to 100mA before switchover to SMPS2. Bypass to ground with a 4.7µF ceramic capacitor.
22
PGND
Power ground for SMPS1 and SMPS2. This provides a return path for synchronous FET switching currents.
23
LGATE2
Low-side NMOS gate drive output for SMPS2. Connect to the gate of the SMPS2 synchronous FET.
24
BOOT2
SMPS2 bootstrap input for the switching NMOS gate drivers. Connect to PHASE2 with a 0.22µF ceramic capacitor.
25
UGATE2
High-side NMOS gate drive output for SMPS2. Connect to the gate of the SMPS2 switching FET.
26
PHASE2
SMPS2 switching node for high-side gate drive return and synthetic ripple modulation. Connect to the switching NMOS source, the
synchronous NMOS drain, and the output inductor for SMPS2.
28
EN2
Logic input to enable and disable SMPS2. A logic high will enable SMPS2 immediately. A logic low will disable SMPS2. Floating this
input will delay SMPS2 start-up until after SMPS1 achieves regulation.
29
OCSET2
30
ISEN2
SMPS2 current sense input. Used for overcurrent protection and R3 regulation.
31
VOUT2
SMPS2 output voltage sense input. Used for soft-discharge and switchover to LDO5 output.
32
FB2
Bottom
Pad
Analog power supply input for reference voltages and currents. It is internally connected to the LDO5 output. Bypass to AGND1 or
AGND2 with a 1µF ceramic capacitor near the IC.
Frequency control input for SMPS1. Connect a resistor to ground to program the switching frequency. A small ceramic capacitor
such as 10nF is necessary to parallel with this resistor to smooth the voltage.
SMPS1 feedback input used for output voltage programming and regulation.
SMPS1 output voltage sense input. Used for soft-discharge.
SMPS1 current sense input. Used for overcurrent protection and R3 regulation.
Input from current-sensing network, used to program the overcurrent shutdown threshold for SMPS1.
LDO3 linear regulator output, providing up to 100mA. Bypass to ground with a 4.7µF ceramic capacitor.
Feed-forward input for line voltage transient compensation. Connect to the power train input voltage.
Input from current-sensing network, used to program the over-current shutdown threshold for SMPS2.
SMPS2 feedback input used for output voltage programming and regulation.
Thermal pad. Connected to AGND internally.
7
FN6831.0
February 4, 2009
ISL62386
100
100
95
95
90
90
85
85
EFFICIENCY (%)
EFFICIENCY (%)
Typical Performance
80
VIN = 7V
75
VIN = 12V
70
65
VIN = 19V
70
65
60
55
55
1.00
IOUT (A)
10.00
FIGURE 5. CHANNEL 1 EFFICIENCY AT VO1 = 3.3V, DEM
OPERATION. HIGH-SIDE 1xIRF7821,
rDS(ON) = 9.1mΩ; LOW-SIDE 1xIRF7832,
rDS(ON) = 4mΩ; L = 4.7µH, DCR = 14.3mΩ; CCM
FSW = 270kHz
1) CH1: 2V 1ms
2) CH2: 500mV 1ms
3) CH3: 5V 1ms
4) CH4: 10V 1ms
VIN = 12V
75
60
50
0.10
VIN = 7V
80
VIN = 19V
50
0.01
0.10
10.00
FIGURE 6. CHANNEL 2 EFFICIENCY AT VO2 = 5V, DEM
OPERATION. HIGH-SIDE 1xIRF7821,
rDS(ON) = 9.1mΩ; LOW-SIDE 1xIRF7832,
rDS(ON) = 4mΩ; L = 4.7µH, DCR = 14.3mΩ; CCM
FSW = 330kHz
1) CH1: 2V 200µs
2) CH2: 500mV 200µs
3) CH3: 5V 200µs
4) CH4: 10V 200µs
VO1
1.00
IOUT (A)
FB1
VO1
FB1
PGOOD
PGOOD
PHASE1
PHASE1
FIGURE 7. POWER-ON, VIN = 12V, IO1 = 5A, VO1 = 3.3V
1) CH1: 2V 500µs
2) CH2: 500mV 500µs
3) CH3: 5V 500µs
4) CH4: 10V 500µs
FIGURE 8. POWER-OFF, VIN = 12V, IO1 = 5A, VO1 = 3.3V
1) CH1: 2V 1ms
2) CH2: 500mV 1ms
3) CH3: 5V 1ms
4) CH4: 5V 1ms
VO1
VO1
FB1
FB1
PGOOD
PGOOD
EN1
EN1
FIGURE 9. ENABLE CONTROL, EN1 = HIGH, VIN = 12V,
VO1 = 3.3V, IO1 = 5A
8
FIGURE 10. ENABLE CONTROL, EN1 = LOW, VIN = 12V,
VO1 = 3.3V, IO1 = 5A
FN6831.0
February 4, 2009
ISL62386
Typical Performance (Continued)
1) CH1: 50mV 2V 2µs
2) CH2: 10V 2µs
3) CH3: 50mV 2µs
4) CH4: 10V 2µs
1) CH1: 50mV 10µs
2) CH2: 10V 10µs
3) CH3: 50mV 10µs
4) CH4: 10V 10µs
VO1
VO1
PHASE1
PHASE1
VO2
VO2
PHASE2
PHASE2
FIGURE 11. CCM STEADY-STATE OPERATION,VIN = 12V,
VO1 = 3.3V, IO1 = 5A, VO2 = 5V, IO2 = 5A
1) CH1: 50mV 20µs
2) CH2: 10mV 20µs
3) CH3: 50mV 20µs
4) CH4: 10V 20µs
FIGURE 12. DCM STEADY-STATE OPERATION,VIN = 12V,
VO1 = 3.3V, IO1 = 0. 2A, VO2 = 5V, IO2 = 0. 2A
1) CH1: 50mV 100µs
2) CH2: 10V 100µs
4) CH4: 5A 100µs
VO1
VO1
PHASE1
PHASE1
VO2
PHASE2
FIGURE 13. AUDIO FILTER OPERATION, VIN = 12V,
VO1 = 3.3V, VO2 = 5V, NO LOAD
IO1
FIGURE 14. TRANSIENT RESPONSE, VIN = 12V, VO1 = 3.3V,
IO1 = 0.1A/8.1A @ 2.5A/µs
1) CH1: 50mV 20µs
2) CH2: 10V 20µs
4) CH4: 5A 20µs
1) CH1: 50mV 20µs
2) CH2: 10V 20µs
4) CH4: 5A 20µs
VO1
VO1
PHASE1
PHASE1
IO1
IO1
FIGURE 15. LOAD INSERTION RESPONSE, VIN = 12V,
VO1 = 3.3V, IO1 = 0.1A/8.1A @ 2.5A/µs
9
FIGURE 16. LOAD RELEASE RESPONSE, VIN = 12V,
VO1 = 3.3V, IO1 = 0.1A/8.1A @ 2.5A/µs
FN6831.0
February 4, 2009
ISL62386
Typical Performance (Continued)
1) CH1: 5V 1ms
2) CH2: 2V 1ms
3) CH3: 5V 1ms
EN1
1) CH1: 5V 1ms
2) CH2: 2V 1ms
3) CH3: 5V 1ms
EN2
VO1
VO1
VO2
VO2
FIGURE 17. DELAYED START, VIN = 12V, VO1 = 3.3V, VO2 = 5V,
EN2 = FLOAT, NO LOAD
1) CH1: 5V 1ms
2) CH2: 5V 1ms
3) CH3: 2V 1µs
4) CH4: 5V 1µs
VO1
FIGURE 18. DELAYED START, VIN = 12V, VO1 = 3.3V, VO2 = 5V,
EN1 = FLOAT, NO LOAD
1) CH1: 2V 100µs
2) CH2: 5V 100µs
3) CH3: 5A 100µs
VO1
PGOOD
VO2
IO1
PGOOD
LDO3
FIGURE 19. DELAYED START , VIN = 12V, VO1 = 3.3V,
VO2 = 5V, EN1 = 1, EN2 = FLOAT, NO LOAD
1) CH1: 5V 200µs
2) CH2: 5V 200µs
3) CH3: 500mV 200µs
4) CH4: 5V 200µs
VO1
FIGURE 20. OVERCURRENT PROTECTION, VIN = 12V,
VO1 = 3.3V
1) CH1: 1V 10µs
2) CH2: 5V 10µs
3) CH3: 10V 10µs
4) CH4: 5V 10µs
VO1
VO2
LGATE1
FB1
PGOOD
FIGURE 21. UNDERVOLTAGE PROTECTION, FAULT ON
SMPS1, VIN = 12V, VO1 = 3.3V, VO2 = 5V, NO
LOAD
10
PHASE1
PGOOD
FIGURE 22. OVERVOLTAGE PROTECTION, AUTO-RESTART
WHEN FAULT IS CLEARED. VIN = 12V, NOMINAL
VO1 = 3.3V, NO LOAD, DEM OPERATION
FN6831.0
February 4, 2009
ISL62386
Block Diagram
VIN
VOUT2
FSET 1, 2
4 .8V
5V
LDO
FB 1, 2
R3
MODULATOR
VREF
LDO5
0.6V
BOOT1, 2
AGND1, 2
FCCM
PWM
UGATE
DRIVER
VOUT1, 2
UGATE1, 2
PHASE1, 2
SOFT DISCHARGE
LGATE
DRIVER
LGATE1, 2
PGND
EN1, 2
PGOOD
START-UP
AND
SHUTDOWN
LOGIC
LDO3EN
BIAS AND
REFERENCE
10µA
OCSET1, 2
OCP
PROTECTION LOGIC
OVP/ UVP/ OCP/ OTP
ISEN1, 2
VIN
VCC
START- UP
3.6V
VCC
LDO5
V REF + 16%
UVP
3.3V
LDO
FB1/2
LDO3
OVP
V REF - 16%
THERMAL
MONITOR
SOFT DISCHARGE
11
FN6831.0
February 4, 2009
ISL62386
Theory of Operation
Four Output Controller
The ISL62386 generates four regulated output voltages,
including two PWM controllers and two LDOs. The two PWM
channels are identical and almost entirely independent.
Unless otherwise stated, only one individual channel is
discussed, and the conclusion applies to both channels.
PWM Modulator
The ISL62386 modulator features Intersil’s R3 technology, a
hybrid of fixed frequency PWM control and variable
frequency hysteretic control. Intersil’s R3 technology can
simultaneously affect the PWM switching frequency and
PWM duty cycle in response to input voltage and output load
transients. The R3 modulator synthesizes an AC signal VR,
which is an analog representation of the output inductor
ripple current. The duty-cycle of VR is the result of charge
and discharge current through a ripple capacitor CR. The
current through CR is provided by a transconductance
amplifier gm that measures the VIN and VO pin voltages.
The positive slope of VR can be written as Equation 1:
V RPOS = g m ⋅ ( V IN – V OUT ) ⁄ C R
(EQ. 1)
frequency is proportional to the slew rates of the positive and
negative slopes of VR; it is inversely proportional to the
voltage between VW and VCOMP. Equation 3 illustrates how
to calculate the window size based on output voltage and
frequency set resistor RW.
V W = g m ⋅ V OUT ⋅ ( 1 – D ) ⋅ R W
(EQ. 3)
Programming the PWM Switching Frequency
The ISL62386 does not use a clock signal to produce
PWMs. The PWM switching frequency FSW is programmed
by the resistor RW that is connected from the FSET pin to
the GND pin. The approximate PWM switching frequency
can be expressed as written in Equation 4:
1
F SW = --------------------------------10 ⋅ C R ⋅ R W
(EQ. 4)
For a desired FSW, the RW can be selected by Equation 5.
1
R W = -----------------------------------10 ⋅ C R ⋅ F SW
(EQ. 5)
where CR = 17pF with ±20% error range. To smooth the
FSET pin voltage, a ceramic capacitor such as 10nF is
necessary to parallel with RW.
The negative slope of VR can be written as Equation 2:
It is recommended that whenever the control loop
compensation network is modified, FSW should be checked
for the correct frequency and if necessary, adjust RW .
V RNEG = g m ⋅ V OUT ⁄ C R
Power-On Reset
(EQ. 2)
Where gm is the gain of the transconductance amplifier.
WINDOW VOLTAGE VW
(WRT VCOMP)
RIPPLE CAPACITOR VOLTAGE VR
The ISL62386 is disabled until the voltage at the VIN pin has
increased above the rising power-on reset (POR) threshold
voltage. The controller will be disabled when the voltage at
the VIN pin decreases below the falling POR threshold.
In addition to VIN POR, the LDO5 pin is also monitored. If its
voltage falls below 4.2V, the SMPS outputs will be shut
down. This ensures that there is sufficient BOOT voltage to
enhance the upper MOSFET.
EN, Soft-Start and PGOOD
ERROR AMPLIFIER
VOLTAGE VCOMP
PWM
FIGURE 23. MODULATOR WAVEFORMS DURING LOAD
TRANSIENT
A window voltage VW is referenced with respect to the error
amplifier output voltage VCOMP, creating an envelope into
which the ripple voltage VR is compared. The amplitude of
VW is set by a resistor connected across the FSET and GND
pins. The VR, VCOMP, and VW signals feed into a window
comparator in which VCOMP is the lower threshold voltage
and VCOMP + VW is the higher threshold voltage. Figure 23
shows PWM pulses being generated as VR traverses the
VCOMP and VCOMP + VW thresholds. The PWM switching
12
The ISL62386 uses a digital soft-start circuit to ramp the
output voltage of each SMPS to the programmed regulation
setpoint at a predictable slew rate. The slew rate of the
soft-start sequence has been selected to limit the in-rush
current through the output capacitors as they charge to the
desired regulation voltage. When the EN pins are pulled
above their rising thresholds, the PGOOD Soft-Start Delay,
tSS, starts and the output voltage begins to rise. The FB pin
ramps to 0.6V in approximately 1.5ms and the PGOOD pin
goes to high impedance approximately 1.25ms after the FB
pin voltage reaches 0.6V.
The PGOOD pin indicates when the converter is capable of
supplying regulated voltage. It is an undefined impedance if
VIN is not above the rising POR threshold or below the POR
falling threshold. When a fault is detected, the ISL62386 will
turn on the open-drain NMOS, which will pull PGOOD low
with a nominal impedance of 32Ω. This will flag the system
that one of the output voltages is out of regulation.
FN6831.0
February 4, 2009
ISL62386
1.5ms
VOUT
tSOFT-START
VCC and LDO5
EN
FB
PGOOD
2.75ms
PGOOD Delay
FIGURE 24. SOFT-START SEQUENCE FOR ONE SMPS
Separate enable pins allow for full soft-start sequencing.
Because low shutdown quiescent current is necessary to
prolong battery life in notebook applications, the LDO5 5V
LDO is held off until any of the three enable signals (EN1,
EN2 or LDO3EN) is pulled high. Soft-start of all outputs will
only start until after LDO5 is above the 4.2V POR threshold.
In addition to user-programmable sequencing, the ISL62386
includes a pre-programmed sequential SMPS soft-start
feature. Table 1 shows the SMPS enable truth table.
resistance is small in order to clamp the gate of the MOSFET
below the VGS(th) at turnoff. The current transient through
the gate at turn-off can be considerable because the gate
charge of a low r DS(ON) MOSFET can be large. Adaptive
shoot-through protection prevents a gate-driver output from
turning on until the opposite gate-driver output has fallen
below approximately 1V. The dead-time shown in Figure 25
is extended by the additional period that the falling gate
voltage stays above the 1V threshold. The typical dead-time
is 21ns. The high-side gate-driver output voltage is
measured across the UGATE and PHASE pins while the
low-side gate-driver output voltage is measured across the
LGATE and PGND pins. The power for the LGATE
gate-driver is sourced directly from the LDO5 pin. The power
for the UGATE gate-driver is sourced from a “boot” capacitor
connected across the BOOT and PHASE pins. The boot
capacitor is charged from the 5V LDO5 supply through a
“boot diode” each time the low-side MOSFET turns on,
pulling the PHASE pin low. The ISL62386 has integrated
boot diodes connected from the LDO5 pins to BOOT pins.
tLGFUGR
tUGFLGR
TABLE 1. SMPS ENABLE SEQUENCE LOGIC
EN1
EN2
START-UP SEQUENCE
0
0
Both SMPS outputs OFF simultaneously
0
Float
Both SMPS outputs OFF simultaneously
Float
0
Both SMPS outputs OFF simultaneously
Float
Float
Both SMPS outputs OFF simultaneously
0
1
SMPS1 OFF, SMPS2 ON
1
0
SMPS1 ON, SMPS2 OFF
1
1
Both SMPS outputs ON simultaneously
Float
1
SMPS1 enabled after SMPS2 is in regulation
1
Float
SMPS2 enabled after SMPS1 is in regulation
50%
UGATE
LGATE
50%
FIGURE 25. LGATE AND UGATE DEAD-TIME
Diode Emulation
VCC
The VCC nominal operation voltage is 5V. If EN1, EN2 and
LDO3EN are all logic low, the VCC start-up voltage is 3.6V
when VIN is applied on ISL62386. As described before, the
LDO5 5V LDO is held off until any of the three enable signals
(EN1, EN2 or LDO3EN) is pulled high. When LDO5 is above
the 4.2V VCC POR threshold, VCC will switchover to LDO5.
After VIN is applied, the VCC start-up 3.6V voltage can be used
as the logic high signal of any of EN1, EN2 and LDO3EN to
enable LDO5 if there is no other power supply on the board.
MOSFET Gate-Drive Outputs LGATE and UGATE
The ISL62386 has internal gate-drivers for the high-side and
low-side N-Channel MOSFETs. The low-side gate-drivers
are optimized for low duty-cycle applications where the
low-side MOSFET conduction losses are dominant,
requiring a low r DS(ON) MOSFET. The LGATE pull-down
13
FCCM is a logic input that controls the power state of the
ISL62386. If forced high, the ISL62386 will operate in forced
continuous-conduction-mode (CCM) over the entire load
range. This will produce the best transient response to all
load conditions, but will have increased light-load power
loss. If FCCM is forced low, the ISL62386 will automatically
operate in diode-emulation-mode (DEM) at light load to
optimize efficiency in the entire load range. The transition is
automatically achieved by detecting the load current and
turning off LGATE when the inductor current reaches 0A.
Positive-going inductor current flows from either the source
of the high-side MOSFET, or the drain of the low-side
MOSFET. Negative-going inductor current flows into the
drain of the low-side MOSFET. When the low-side MOSFET
conducts positive inductor current, the phase voltage will be
negative with respect to the GND and PGND pins.
Conversely, when the low-side MOSFET conducts negative
FN6831.0
February 4, 2009
ISL62386
inductor current, the phase voltage will be positive with
respect to the GND and PGND pins. The ISL62386 monitors
the phase voltage when the low-side MOSFET is conducting
inductor current to determine its direction.
When the output load current is greater than or equal to ½
the inductor ripple current, the inductor current is always
positive, and the converter is always in CCM. The ISL62386
minimizes the conduction loss in this condition by forcing the
low-side MOSFET to operate as a synchronous rectifier.
When the output load current is less than ½ the inductor
ripple current, negative inductor current occurs. Sinking
negative inductor current through the low-side MOSFET
lowers efficiency through unnecessary conduction losses.
The ISL62386 automatically enters DEM after the PHASE
pin has detected positive voltage and LGATE was allowed to
go high for eight consecutive PWM switching cycles. The
ISL62386 will turn off the low-side MOSFET once the phase
voltage turns positive, indicating negative inductor current.
The ISL62386 will return to CCM on the following cycle after
the PHASE pin detects negative voltage, indicating that the
body diode of the low-side MOSFET is conducting positive
inductor current.
Efficiency can be further improved with a reduction of
unnecessary switching losses by reducing the PWM
frequency. It is characteristic of the R3 architecture for the
PWM frequency to decrease while in diode emulation. The
extent of the frequency reduction is proportional to the
reduction of load current. Upon entering DEM, the PWM
frequency makes an initial step-reduction because of a 33%
step-increase of the window voltage V W.
Because the switching frequency in DEM is a function of
load current, very light load conditions can produce
frequencies well into the audio band. This can be
problematic if audible noise is coupled into audio amplifier
circuits. To prevent this from occurring, the ISL62386 allows
the user to float the FCCM input. This will allow DEM at light
loads, but will prevent the switching frequency from going
below ~28kHz to prevent noise injection into the audio band.
A timer is reset each PWM pulse. If the timer exceeds 30µs,
LGATE is turned on, causing the ramp voltage to reduce until
another UGATE is commanded by the voltage loop.
Overcurrent Protection
The overcurrent protection (OCP) setpoint is programmed
with resistor, ROCSET, that is connected across the OCSET
and PHASE pins.
Figure 26 shows the overcurrent-set circuit for SMPS1. The
inductor consists of inductance L and the DC resistance
(DCR). The inductor DC current IL creates a voltage drop
across DCR, given by Equation 6:
(EQ. 6)
V DCR = I L • DCR
L
DCR
+
ROCSET
ISL62386
10µF
OCSET1
+ VROCSET
VO
IL
PHASE1
VDCR
CSEN
_
CO
_
RO
ISEN1
FIGURE 26. OVERCURRENT-SET CIRCUIT
The ISL62386 sinks a 10µA current into the OCSET1 pin,
creating a DC voltage drop across the resistor ROCSET,
given by Equation 7:
V ROCSET = 10μA • R OCSET
(EQ. 7)
Resistor RO is connected between the ISEN1 pin and the
actual output of the converter. During normal operation, the
ISEN1 pin is a high impedance path, therefore there is no
voltage drop across RO. The DC voltage difference between
the OCSET1 pin and the ISEN1 pin can be established using
Equation 8:
V OCSET1 – V ISEN1 = I L • DCR – 10μA • R OCSET
(EQ. 8)
The ISL62386 monitors the OCSET1 pin and the ISEN1 pin
voltages. Once the OCSET1 pin voltage is higher than the
ISEN1 pin voltage for more than 10µs, the ISL62386 declares
an OCP fault. The value of ROCSET is then written as
Equation 9:
I OC • DCR
R OCSET = --------------------------10μA
(EQ. 9)
Where:
- ROCSET (Ω) is the resistor used to program the
overcurrent setpoint
- IOC is the output current threshold that will activate the
OCP circuit
- DCR is the inductor DC resistance
For example, if IOC is 20A and DCR is 4.5mΩ, the choice of
ROCSET is ROCSET = 20Ax4.5mΩ/10µA = 9kΩ.
Resistor ROCSET and capacitor CSEN form an RC network
to sense the inductor current. To sense the inductor current
correctly, not only in DC operation but also during dynamic
operation, the RC network time constant ROCSETCSEN
needs to match the inductor time constant L/DCR. The value
of CSEN is then written as Equation 10:
L
C SEN = ----------------------------------------R OCSET • DCR
(EQ. 10)
For example, if L is 1.5µH, DCR is 4.5mΩ, and ROCSET is
9kΩ, the choice of CSEN = 1.5µH/(9kΩ x 4.5mΩ) = 0.037µF.
Upon converter start-up, the CSEN capacitor bias is 0V. To
prevent false OCP during this time, a 10µA current source
14
FN6831.0
February 4, 2009
ISL62386
flows out of the ISEN1 pin, generating a voltage drop on the
RO resistor, which should be chosen to have the same
resistance as ROCSET. When PGOOD pin goes high, the
ISEN1 pin current source will be removed.
When an OCP fault is detected in one SMPS channel, the
PGOOD pin will pull down to 32Ω. The ISL62386 turns the
faulted channel UGATE and LGATE off and latches off the
faulted channel.
The fault will remain latched until either of the EN pins has
been pulled below the falling EN threshold voltage, or until
VIN has decayed below the falling POR threshold.
When using a discrete current sense resistor, inductor
time-constant matching is not required. Equation 7 remains
unchanged, but Equation 8 is modified in Equation 11:
V OCSET1 – V ISEN1 = I L • R SENSE – 10μA • R OCSET
(EQ. 11)
Furthermore, Equation 9 is changed in Equation 12:
I OC • R SENSE
R OCSET = ------------------------------------10μA
(EQ. 12)
Where RSENSE is the series power resistor for sensing
inductor current. For example, with an RSENSE = 1mΩ and
an OCP target of 10A, ROCSET = 1kΩ.
Overvoltage Protection
The OVP fault detection circuit triggers after the FB pin
voltage is above the rising overvoltage threshold for more
than 2µs. The FB pin voltage is 0.6V in normal operation.
The rising overvoltage threshold is typically 116% of that
value, or 1.16*0.6V = 0.696V.
If an OVP is detected in one SMPS channel, the PGOOD pin
will pull-down to 32Ω, and the LGATE gate-driver will turn on
the low-side MOSFET to discharge the output voltage, thus
protecting the load from potentially damaging voltage levels.
Once the FB pin voltage falls to 106% of the reference
voltage, or 1.06*0.6V = 0.636V, the faulted channel will
resume the normal switching, and PGOOD will go high when
the output voltage is in regulation. This process repeats as
long as the OVP fault is present.
Programming the Output Voltage
When the converter is in regulation there will be 0.6V
between the FB and GND pins. Connect a two-resistor
voltage divider across the OUT and GND pins with the
output node connected to the FB pin as shown in Figure 27.
Scale the voltage-divider network such that the FB pin is
0.6V with respect to the GND pin when the converter is
regulating at the desired output voltage. The output voltage
can be programmed from 0.6V to 5.5V.
Programming the output voltage is written as Equation 13:
R TOP ⎞
⎛
V OUT = V REF • ⎜ 1 + -----------------------------⎟
R BOTTOM⎠
⎝
(EQ. 13)
Where:
- VOUT is the desired output voltage of the converter
- The voltage to which the converter regulates the FB pin
is the VREF (0.6V)
- RTOP is the voltage-programming resistor that connects
from the FB pin to the converter output. In addition to
setting the output voltage, this resistor is part of the loop
compensation network
- RBOTTOM is the voltage-programming resistor that
connects from the FB pin to the GND pin
Choose RTOP first when compensating the control loop, and
then calculate RBOTTOM according to Equation 14:
V REF • R
TOP
R BOTTOM = ------------------------------------V OUT – V REF
(EQ. 14)
Compensation Design
Figure 27 shows the recommended Type-II compensation
circuit. The FB pin is the inverting input of the error amplifier.
The COMP signal, the output of the error amplifier, is inside the
chip and unavailable to users. CINT is a 100pF capacitor
integrated inside the IC that connects across the FB pin and the
COMP signal. RTOP, RFB, CFB and CINT form the Type-II
compensator. The frequency domain transfer function is given
by Equation15:
1 + s • ( R TOP + R FB ) • C
FB
G COMP ( s ) = ------------------------------------------------------------------------------------------s • R TOP • C INT • ( 1 + s • R FB • C )
(EQ. 15)
FB
Undervoltage Protection
CINT = 100pF
The UVP fault detection circuit triggers after the FB pin
voltage is below the undervoltage threshold for more than
2µs. The undervoltage threshold is typically 86% of the
reference voltage, or 0.86*0.6V = 0.516V.
RTOP
-
If a UVP fault is detected in one SMPS channel, the PGOOD
pin will pull-down to 32Ω. The ISL62386 turns the faulted
channel UGATE and LGATE off and latches off the faulted
channel.
The fault will remain latched until either of the EN pins has
been pulled below the falling EN threshold voltage, or until
VIN has decayed below the falling POR threshold.
15
CFB
RFB
VO
FB
EA
RBOTTOM
COMP
+
REF
ISL62386
FIGURE 27. COMPENSATION REFERENCE CIRCUIT
FN6831.0
February 4, 2009
ISL62386
The LC output filter has a double pole at its resonant frequency
that causes rapid phase change. The R3 modulator used in the
ISL62386 makes the LC output filter resemble a first order
system in which the closed loop stability can be achieved with
the recommended Type-II compensation network. Intersil
provides a PC-based tool that can be used to calculate
compensation network component values and help simulate
the loop frequency response.
Selecting the LC Output Filter
LDO5 Linear Regulator
V OUT • ( 1 – D )
I PP = -------------------------------------F SW • L
In addition to the two SMPS outputs, the ISL62386 also
provides two linear regulator outputs. LDO5 is fixed 5V LDO
output capable of sourcing 100mA continuous current.
When the output of SMPS2 is programmed to 5V, SMPS2 will
automatically take over the load of LDO5. This provides a
large power savings and boosts the efficiency. After
switchover to SMPS2, the LDO5 output current plus the
MOSFET drive current should not exceed 100mA in order to
guarantee the LDO5 output voltage in the range of 5V ±5%.
The total MOSFET drive current can be estimated by
Equation 16.
I DRIVE = Q g ⋅ F SW
(EQ. 16)
where Qg is the total gate charge of all the power MOSFET
in two SMPS regulators. Then the LDO5 output load current
should be less than (100mA - IDRIVE).
LDO3 Linear Regulator
ISL62386 includes LDO3 linear regulator whose output is fixed
3.3V. It can be independently enabled from both SMPS
channels. Logic high of LDO3EN will enable LDO3. LDO3 is
capable of sourcing 100mA continuous current. Currents in
excess of the limit will cause the LDO3 voltage to drop
dramatically, limiting the power dissipation.
Thermal Monitor and Protection
LDO3 and LDO5 can dissipate non-trivial power inside the
ISL62386 at high input-to-output voltage ratios and full load
conditions. To protect the silicon, ISL62386 continually
monitors the die temperature. If the temperature exceeds
+150°C, all outputs will be turned off to sharply curtail power
dissipation. The outputs will remain off until the junction
temperature has fallen below +135°C.
General Application Design Guide
This design guide is intended to provide a high-level
explanation of the steps necessary to design a single-phase
power converter. It is assumed that the reader is familiar with
many of the basic skills and techniques referenced in the
following section. In addition to this guide, Intersil provides
complete reference designs that include schematics, bills of
materials, and example board layouts.
16
The duty cycle of an ideal buck converter is a function of the
input and the output voltage. This relationship is written as
Equation 17:
V OUT
D = --------------V IN
(EQ. 17)
The output inductor peak-to-peak ripple current is written as
Equation 18:
(EQ. 18)
A typical step-down DC/DC converter will have an IP-P of
20% to 40% of the maximum DC output load current. The
value of IP-P is selected based upon several criteria such as
MOSFET switching loss, inductor core loss, and the resistive
loss of the inductor winding. The DC copper loss of the
inductor can be estimated by Equation 19:
P COPPER = I LOAD
2
•
(EQ. 19)
DCR
Where ILOAD is the converter output DC current.
The copper loss can be significant so attention has to be given
to the DCR selection. Another factor to consider when choosing
the inductor is its saturation characteristics at elevated
temperatures. A saturated inductor could cause destruction of
circuit components, as well as nuisance OCP faults.
A DC/DC buck regulator must have output capacitance CO
into which ripple current IP-P can flow. Current IP-P develops
out of the capacitor. These two voltages are written as
Equation 20:
ΔV ESR = I P – P • E SR
(EQ. 20)
and Equation 21:
IP – P
ΔV C = ------------------------------8 • CO • F
(EQ. 21)
SW
If the output of the converter has to support a load with high
pulsating current, several capacitors will need to be paralleled
to reduce the total ESR until the required VP-P is achieved.
The inductance of the capacitor can cause a brief voltage dip
if the load transient has an extremely high slew rate. Low
inductance capacitors should be considered in this scenario.
A capacitor dissipates heat as a function of RMS current and
frequency. Be sure that IP-P is shared by a sufficient quantity
of paralleled capacitors so that they operate below the
maximum rated RMS current at FSW. Take into account that
the rated value of a capacitor can fade as much as 50% as
the DC voltage across it increases.
Selection of the Input Capacitor
The important parameters for the bulk input capacitance are
the voltage rating and the RMS current rating. For reliable
operation, select bulk capacitors with voltage and current
ratings above the maximum input voltage and capable of
supplying the RMS current required by the switching circuit.
Their voltage rating should be at least 1.25x greater than the
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ISL62386
maximum input voltage, while a voltage rating of 1.5x is a
preferred rating. Figure 28 is a graph of the input capacitor
RMS ripple current, normalized relative to output load current,
as a function of duty cycle and is adjusted for converter
efficiency. The normalized RMS ripple current calculation is
written as Equation 22:
2
D⋅k
I MAX ⋅ D ⋅ ( 1 – D ) + -------------12
I C ( RMS ,NORMALIZED ) = ----------------------------------------------------------------------I MAX
IN
(EQ. 22)
Where:
- IMAX is the maximum continuous ILOAD of the converter
- k is a multiplier (0 to 1) corresponding to the inductor
peak-to-peak ripple amplitude expressed as a
percentage of IMAX (0% to 100%)
- D is the duty cycle that is adjusted to take into account
the efficiency of the converter which is written as:
Equation 23.
V OUT
D = -------------------------V IN ⋅ EFF
(EQ. 23)
NORMALIZED INPUT RMS RIPPLE CURRENT
In addition to the bulk capacitance, some low ESL ceramic
capacitance is recommended to decouple between the drain
of the high-side MOSFET and the source of the low-side
MOSFET.
off, the high-side MOSFET turns off with a VDS of
approximately VIN - VOUT, plus the spike across it. The
preferred low-side MOSFET emphasizes low r DS(ON) when
fully saturated to minimize conduction loss. It should be
noted that this is an optimal configuration of MOSFET
selection for low duty cycle applications (D < 50%). For
higher output, low input voltage solutions, a more balanced
MOSFET selection for high- and low-side devices may be
warranted.
For the low-side (LS) MOSFET, the power loss can be
assumed to be conductive only and is written as Equation 24:
2
P CON_LS ≈ I LOAD ⋅ r DS ( ON )_LS • ( 1 – D )
(EQ. 24)
For the high-side (HS) MOSFET, the conduction loss is
written as Equation 25:
P CON_HS = I LOAD
2
•
r DS ( ON )_HS • D
(EQ. 25)
For the high-side MOSFET, the switching loss is written as
Equation 26:
V IN • I PEAK • t OFF • f
V IN • I VALLEY • t ON • f
SW
SW
P SW_HS = ----------------------------------------------------------------- + ------------------------------------------------------------2
2
(EQ. 26)
0.60
Where:
- IVALLEY is the difference of the DC component of the
inductor current minus 1/2 of the inductor ripple current
- IPEAK is the sum of the DC component of the inductor
current plus 1/2 of the inductor ripple current
- tON is the time required to drive the device into
saturation
- tOFF is the time required to drive the device into cut-off
0.48
k=1
k = 0.75
k = 0.5
k = 0.25
k=0
0.36
0.24
Selecting The Bootstrap Capacitor
0.12
0
The selection of the bootstrap capacitor is written as
Equation 27:
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
DUTY CYCLE
FIGURE 28. NORMALIZED RMS INPUT CURRENT @ EFF = 1
MOSFET Selection and Considerations
Typically, a MOSFET cannot tolerate even brief excursions
beyond their maximum drain to source voltage rating. The
MOSFETs used in the power stage of the converter should
have a maximum VDS rating that exceeds the sum of the
upper voltage tolerance of the input power source and the
voltage spike that occurs when the MOSFET switches off.
There are several power MOSFETs readily available that are
optimized for DC/DC converter applications. The preferred
high-side MOSFET emphasizes low gate charge so that the
device spends the least amount of time dissipating power in
the linear region. Unlike the low-side MOSFET which has the
drain-source voltage clamped by its body diode during turn
17
Qg
C BOOT = -----------------------ΔV BOOT
(EQ. 27)
Where:
- Qg is the total gate charge required to turn on the
high-side MOSFET
- ΔVBOOT, is the maximum allowed voltage decay across
the boot capacitor each time the high-side MOSFET is
switched on
As an example, suppose the high-side MOSFET has a total
gate charge Qg, of 25nC at VGS = 5V, and a ΔVBOOT of
200mV. The calculated bootstrap capacitance is 0.125µF; for
a comfortable margin, select a capacitor that is double the
calculated capacitance. In this example, 0.22µF will suffice.
Use an X7R or X5R ceramic capacitor.
Layout Considerations
As a general rule, power should be on the bottom layer of
the PCB and weak analog or logic signals are on the top
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ISL62386
layer of the PCB. The ground-plane layer should be adjacent
to the top layer to provide shielding. The ground plane layer
should have an island located under the IC, the
compensation components, and the FSET components. The
island should be connected to the rest of the ground plane
layer at one point.
VIAS TO
VIAS
GROUND
GROUND
PLANE
GND
VOUT
INDUCTOR
INDUCTOR
HIGH-SIDE
HIGH-SIDE
MOSFETS
MOSFETS
The VIN pin should be connected close to the drain of the
high-side MOSFET, using a low resistance and low
inductance path.
For best performance, place the decoupling capacitor very
close to the VCC and AGND1 or AGND2 pin.
LOW-SIDE
LOW-SIDE
MOSFETS
MOSFETS
LDO3 (Pin 19) and LDO5 (Pin 21)
INPUT
INPUT
CAPACITORS
CAPACITORS
VIN
VIN (Pin 20)
VCC (Pin 5)
OUTPUT
CAPACITORS
CAPACITORS
SCHOTTKY
SCHOTTKY
DIODE
DIODE
PHASE
NODE
connected to the source of the low-side MOSFET with a
low-resistance, low-inductance path.
FIGURE 29. TYPICAL POWER COMPONENT PLACEMENT
For best performance, place the decoupling capacitors very
close to LDO3 pin and PGND pin, LDO5 pin and PGND pin,
respectively, preferably on the same side of the PCB as the
ISL62386 IC.
EN (Pins 13 and 28) and PGOOD (Pin 1)
Because there are two SMPS outputs and only one PGND
pin, the power train of both channels should be laid out
symmetrically. The line of bilateral symmetry should be
drawn through pins 4 and 21. This layout approach ensures
that the controller does not favor one channel over another
during critical switching decisions. Figure 30 illustrates one
example of how to achieve proper bilateral symmetry.
Co
L2
PIN 20 (VIN)
PIN 5 (VCC)
L2
ISL62386
U2
LINE OF SYMMETRY
Ci
PGND PLANE
PHASE PLANES
VOUT PLANES
VIN PLANE
OCSET (Pins 12 and 29) and ISEN (Pins 11 and 30)
For DCR current sensing, current-sense network, consisting
of ROCSET and CSEN, needs to be connected to the
inductor pads for accurate measurement. Connect ROCSET
to the phase-node side pad of the inductor, and connect
CSEN to the output side pad of the inductor. The ISEN
resistor should also be connected to the output pad of the
inductor with a separate trace. Connect the OCSET pin to
the common node of node of ROCSET and CSEN.
For resistive current sensing, connect ROCSET from the
OCSET pin to the inductor side of the resistor pad. The ISEN
resistor should be connected to the VOUT side of the resistor
pad.
Ci
L1
These are logic signals that are referenced to the AGND pin.
Treat them as typical logic signals.
U1
L1
Co
FIGURE 30. SYMMETRIC LAYOUT GUIDE
Signal Ground and Power Ground
The bottom of the ISL62386 TQFN package is the signal
ground (AGND) terminal for analog and logic signals of the
IC. The bottom pad is connected to AGND1 pin and AGND2
pin internally. Connect the AGND pad of the ISL62386 to the
island of ground plane under the IC using several vias for a
robust thermal and electrical conduction path. Connect the
input capacitors, the output capacitors, and the source of the
lower MOSFETs to the power ground (PGND) plane.
PGND (Pin 22)
In both current-sense configurations, the resistor and
capacitor sensing elements, with the exclusion of the current
sense power resistor, should be placed near the
corresponding IC pin. The trace connections to the inductor
or sensing resistor should be treated as Kelvin connections.
FB (Pins 9 and 32), and VOUT (Pins 10 and 31)
The VOUT pin is used to generate the R3 synthetic ramp
voltage and for soft-discharge of the output voltage during
shutdown events. This signal should be routed as close to
the regulation point as possible. The input impedance of the
FB pin is high, so place the voltage programming and loop
compensation components close to the VOUT, FB, and
AGND pins keeping the high impedance trace short.
FSET (Pins 2 and 8)
These pins require a quiet environment. The resistor RFSET
and capacitor CFSET should be placed directly adjacent to
these pins. Keep fast moving nodes away from these pins.
This is the return path for the pull-down of the LGATE
low-side MOSFET gate driver. Ideally, PGND should be
18
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ISL62386
LGATE (Pins 18 and 23)
The signal going through these traces are both high dv/dt
and high di/dt, with high peak charging and discharging
current. Route these traces in parallel with the trace from the
PGND pin. These two traces should be short, wide, and
away from other traces. There should be no other weak
signal traces in proximity with these traces on any layer.
BOOT (Pins 17 and 24), UGATE (Pins 16 and 25), and
PHASE (Pins 15 and 26)
The signals going through these traces are both high dv/dt
and high di/dt, with high peak charging and discharging
current. Route the UGATE and PHASE pins in parallel with
short and wide traces. There should be no other weak signal
traces in proximity with these traces on any layer.
Copper Size for the Phase Node
The parasitic capacitance and parasitic inductance of the
phase node should be kept very low to minimize ringing. It is
best to limit the size of the PHASE node copper in strict
accordance with the current and thermal management of the
application. An MLCC should be connected directly across
the drain of the upper MOSFET and the source of the lower
MOSFET to suppress the turn-off voltage spike.
19
FN6831.0
February 4, 2009
ISL62386
Thin Quad Flat No-Lead Plastic Package (TQFN)
Thin Micro Lead Frame Plastic Package (TMLFP)
L32.5x5A
2X
0.15 C A
D
A
32 LEAD THIN QUAD FLAT NO-LEAD PLASTIC PACKAGE
(COMPLIANT TO JEDEC MO-220WJJD-1 ISSUE C)
D/2
MILLIMETERS
2X
6
INDEX
AREA
N
0.15 C B
1
2
3
SYMBOL
MIN
NOMINAL
MAX
NOTES
A
0.70
0.75
0.80
-
A1
-
-
0.05
-
0.30
5, 8
3.55
7, 8
A3
E/2
b
E
D
D2
B
TOP VIEW
0.20 REF
0.18
5.00 BSC
3.30
C
0.08 C
SEATING PLANE
A3
SIDE VIEW
A1
3.45
-
E
5.00 BSC
-
5.75 BSC
9
3.30
e
/ / 0.10 C
-
E1
E2
A
0.25
3.45
3.55
0.50 BSC
7, 8
-
k
0.20
-
-
-
L
0.30
0.40
0.50
8
N
32
2
Nd
8
3
Ne
8
3
Rev. 2 05/06
NX b
5
0.10 M C A B
D2
NX k
D2
2
(DATUM B)
8
7
N
(DATUM A)
6
INDEX
AREA
E2
E2/2
3
2
1
NX L
N
7
(Ne-1)Xe
REF.
8
NOTES:
1. Dimensioning and tolerancing conform to ASME Y14.5m-1994.
2. N is the number of terminals.
3. Nd and Ne refer to the number of terminals on each D and E.
4. All dimensions are in millimeters. Angles are in degrees.
5. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
7. Dimensions D2 and E2 are for the exposed pads which provide
improved electrical and thermal performance.
8. Nominal dimensions are provided to assist with PCB Land Pattern
Design efforts, see Intersil Technical Brief TB389.
e
8
(Nd-1)Xe
REF.
BOTTOM VIEW
A1
NX b
5
SECTION "C-C"
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
20
FN6831.0
February 4, 2009
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