Am29PL320D Data Sheet RETIRED PRODUCT This product has been retired and is not recommended for designs. For new and current designs, S29GL032M supersedes Am29PL320D and is the factory-recommended migration path. Please refer to the S29GL032M datasheet for specifications and ordering information. Availability of this document is retained for reference and historical purposes only. June 2005 The following document specifies Spansion memory products that are now offered by both Advanced Micro Devices and Fujitsu. Although the document is marked with the name of the company that originally developed the specification, these products will be offered to customers of both AMD and Fujitsu. Continuity of Specifications There is no change to this datasheet as a result of offering the device as a Spansion product. Any changes that have been made are the result of normal datasheet improvement and are noted in the document revision summary, where supported. Future routine revisions will occur when appropriate, and changes will be noted in a revision summary. For More Information Please contact your local AMD or Fujitsu sales office for additional information about Spansion memory solutions. Publication Number 24075 Revision C Amendment +3 Issue Date June 13, 2005 THIS PAGE LEFT INTENTIONALLY BLANK. Am29PL320D 32 Megabit (2 M x 16-Bit/1 M x 32-Bit) CMOS 3.0 Volt-only High Performance Page Mode Flash Memory This product has been retired and is not recommended for designs. For new and current designs, S29GL032M supersedes Am29PL320D and is the factory-recommended migration path. Please refer to the S29GL032M datasheet for specifications and ordering information. Availability of this document is retained for reference and historical purposes only. DISTINCTIVE CHARACTERISTICS ARCHITECTURAL ADVANTAGES ■ 32 Mbit Page Mode device — Word (16-bit) or double word (32-bit) mode selectable via WORD# input — Page size of 8 words/4 double words: Fast page read access from random locations within the page ■ Single power supply operation — Full voltage range: 2.7 to 3.6 volt read and write operations for battery-powered applications — Regulated voltage range: 3.0 to 3.6 volt read and write operations and for compatibility with high performance 3.3 volt microprocessors ■ Flexible sector architecture — Sector sizes (x16 configuration): One 16 Kword, two 8 Kword, one 96 Kword and fifteen 128 Kword sectors — Supports full chip erase ■ SecSi™ (Secured Silicon) Sector region — Current version of device has 512 words (256 double words); future versions will have 128 words (64 double words) ■ Top or bottom boot block configuration ■ Manufactured on 0.23 µm process technology ■ 20-year data retention at 125°C ■ Minimum 1 million erase cycles guarantee per sector PERFORMANCE CHARACTERISTICS ■ High performance read access times — Page access times as fast as 20 ns — Random access times as fast as 60 ns ■ Power consumption (typical values) — Initial page read current: 4 mA (1 MHz), 40 mA (10 MHz) — Intra-page read current: 15 mA (10 MHz), 50 mA (33 MHz) — Standby mode current: 2 µA SOFTWARE FEATURES ■ Software command-set compatible with JEDEC standard — Backward compatible with Am29F and Am29LV families ■ CFI (Common Flash Interface) compliant — Provides device-specific information to the system, allowing host software to easily reconfigure for different Flash devices ■ Unlock Bypass Program Command — Reduces overall programming time when issuing multiple program command sequences ■ Erase Suspend/Erase Resume — Suspends an erase operation to read data from, or program data to, a sector that is not being erased, then resumes the erase operation HARDWARE FEATURES ■ Sector Protection — A hardware method of locking a sector to prevent any program or erase operations within that sector — Sectors can be locked via programming equipment — Temporary Sector Unprotect command sequence allows code changes in previously locked sectors ■ ACC (Acceleration) input provides faster programming times ■ WP# (Write Protect) input — At VIL, protects the first or last 32 Kword sector, regardless of sector protect/unprotect status — At VIH, allows removal of sector protection — An internal pull up to VCC is provided ■ Package Options — 84-ball FBGA — Program/erase current: 25 mA Publication# 24075 Rev: C Amendment/+3 Issue Date: June 13, 2005 Refer to AMD’s Website (www.amd.com/flash) for the latest information. GENERAL DESCRIPTION The Am29PL320D is a 32 Mbit, 3.0 Volt-only page mode Flash memory device organized as 2,097,152 words or 1,048,576 double words. The device is offered in an 84-ball FBGA package. The word-wide data (x16) appears on DQ15–DQ0; the double wordwide (x32) data appears on DQ31–DQ0. The device is available in both top and bottom boot versions. This device can be programmed in-system or with in standard EPROM programmers. A 12.0 V VPP or 5.0 VCC are not required for write or erase operations. The device offers fast page access times of 20, 25, and 35 ns, with corresponding random access times of 60, 70, 90 ns, respectively, allowing high speed microprocessors to operate without wait states. To eliminate bus contention the device has separate chip enable (CE#), write enable (WE#), and output enable (OE#) controls. Page Mode Features The device is AC timing, input, output, and package compatible with 16 Mbit x 16 page mode Mask ROM. The page size is 8 words or 4 double words. After initial page access is accomplished, the page mode operation provides fast read access speed of random locations within that page. Standard Flash Memory Features The device requires only a single 3.0 volt power supply for both read and write functions. Inter nally generated and regulated voltages are provided for the program and erase operations. The device is entirely command set compatible with the JEDEC single-power-supply Flash standard. Commands are written to the command register using standard microprocessor write timings. Register contents serve as input to an internal state-machine that controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming and erase operations. Reading data out of the device is similar to reading from other Flash or EPROM devices. Device programming occurs by executing the program command sequence. This initiates the Embedded Program algor ithm—an inter nal algorithm that automatically times the program pulse widths and verifies proper cell margin. The Unlock Bypass mode facilitates faster programming times by requiring only two write cycles to program data instead of four. Device erasure occurs by executing the erase command sequence. This initiates the Embedded Erase algorithm—an internal algorithm that automatically preprograms the array (if it is not already programmed) 2 before executing the erase operation. During erase, the device automatically times the erase pulse widths and verifies proper cell margin. The host system can detect whether a program or erase operation is complete by reading the DQ7 (Data# Polling) and DQ6 (toggle) status bits. After a program or erase cycle has been completed, the device is ready to read array data or accept another command. The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data contents of other sectors. The device is fully erased when shipped from the factory. Hardware data protection measures include a low VCC detector that automatically inhibits write operations during power transitions. The hardware sector protection feature disables both program and erase operations in any combination of the sectors of memo r y. T h i s c a n b e a c h i ev e d i n - s y s t e m o r v i a programming equipment. The Erase Suspend/Erase Resume feature enables the user to put erase on hold for any period of time to read data from, or program data to, any sector that is not selected for erasure. True background erase can thus be achieved. The device offers two power-saving features. When addresses have been stable for a specified amount of time, the device enters the automatic sleep mode. The system can also place the device into the standby mode. Power consumption is greatly reduced in both these modes. The SecSi™ Sector (Secured Silicon) is an extra sector capable of being permanently locked by AMD or customers. The SecSi Indicator Bit (DQ7) is permanently set to a 1 if the part is factory locked, and set to a 0 if customer lockable. This way, customer lockable parts can never be used to replace a factory locked par t. Current version of device has 512 words (256 double words); future versions will have only 128 words (64 double words). This should be considered during system design. Factory locked parts can store a secure, random 16 byte ESN (Electronic Serial Number), customer code (programmed through AMD’s ExpressFlash service), or both. Customer Lockable parts may be programmed after being shipped from AMD. AMD’s Flash technology combines years of Flash memory manufacturing experience to produce the highest levels of quality, reliability and cost effectiveness. The device electrically erases all bits within a sector simultaneously via Fowler-Nordheim tunneling. The data is programmed using hot electron injection. Am29PL320D June 13, 2005 TABLE OF CONTENTS Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 5 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Input Configuration . . . . . . . . . . . . . . . . . . . . . . . . 7 Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 8 Standard Products .................................................................... 8 Device Bus Operations . . . . . . . . . . . . . . . . . . . . . . 9 Table 1. Am29PL320D Device Bus Operations ................................9 Word/Double Word Configuration ............................................. 9 Requirements for Reading Array Data ..................................... 9 Read Mode ............................................................................... 9 Random Read (Non-Page Mode Read) ............................................9 Page Mode Read .................................................................... 10 Table 2. Double Word Mode ...........................................................10 Table 3. Word Mode ........................................................................10 Writing Commands/Command Sequences ............................ 11 Figure 3. Erase Operation.............................................................. 23 Temporary Sector Unprotect Enable/Disable Command Sequence .............................................................. 24 Figure 4. Temporary Sector Unprotect Algorithm .......................... 24 Command Definitions ............................................................. 25 Table 13. Command Definitions (Double Word Mode) .................. 25 Table 14. Command Definitions (Word Mode) ............................... 26 Write Operation Status . . . . . . . . . . . . . . . . . . . . . 27 DQ7: Data# Polling ................................................................. 27 Figure 5. Data# Polling Algorithm .................................................. 27 DQ6: Toggle Bit ...................................................................... 28 DQ2: Toggle Bit ...................................................................... 28 Reading Toggle Bits DQ6/DQ2 ............................................... 28 DQ5: Exceeded Timing Limits ................................................ 28 Figure 6. Toggle Bit Algorithm........................................................ 29 DQ3: Sector Erase Timer ....................................................... 29 Accelerated Program Operation ......................................................11 Table 15. Write Operation Status ................................................... 30 Program and Erase Operation Status .................................... 11 Standby Mode ........................................................................ 11 Automatic Sleep Mode ........................................................... 11 Output Disable Mode .............................................................. 11 Absolute Maximum Ratings. . . . . . . . . . . . . . . . . 31 Table 4. Sector Address Table, Top Boot (Am29PL320DT) ...........12 Table 5. SecSi™ Sector Addresses for Top Boot Devices .............12 Table 6. Sector Address Table, Bottom Boot (Am29PL320DB) ......13 Table 7. SecSi™ Sector Addresses for Bottom Boot Devices .......................................................................13 Autoselect Mode ..................................................................... 14 Table 8. Am29PL320D Autoselect Codes (High Voltage Method) ..14 Sector Protection/Unprotection ............................................... 14 Common Flash Memory Interface (CFI) . . . . . . . 15 Table 9. CFI Query Identification String ..........................................15 Table 10. System Interface String ...................................................16 Table 11. Device Geometry Definition ............................................16 Table 12. Primary Vendor-Specific Extended Query ......................17 Figure 7. Maximum Negative Overshoot Waveform ...................... 31 Figure 8. Maximum Positive Overshoot Waveform........................ 31 Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . 31 Commercial (C) Devices ......................................................... 31 Industrial (I) Devices ............................................................... 31 VCC Supply Voltages .............................................................. 31 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 32 CMOS Compatible .................................................................. 32 Zero Power Flash ................................................................... 33 Figure 9. ICC1 Current vs. Time (Showing Active and Automatic Sleep Currents) ........................................................................................ 33 Figure 10. Typical ICC1 vs. Frequency ........................................... 33 Figure 11. Test Setup..................................................................... 34 Table 16. Test Specifications ......................................................... 34 Key to Switching Waveforms. . . . . . . . . . . . . . . . 34 Figure 12. Input Waveforms and Measurement Levels ................. 34 SecSi™ (Secured Silicon) Sector Flash Memory Region ....... 18 Read Operations .................................................................... 35 Factory Locked: SecSi Sector Programmed and Protected At the Factory .................................................................18 Customer Lockable: SecSi Sector NOT Programmed or Locked At the Factory .................................................................................18 Figure 1. SecSi Sector Protect Verify.............................................. 19 Figure 13. Conventional Read Operations Timings ....................... 36 Figure 14. Page Read Timings ...................................................... 36 Write Protect (WP#) ................................................................ 19 Hardware Data Protection ...................................................... 19 Low VCC Write Inhibit ......................................................................19 Write Pulse “Glitch” Protection ........................................................19 Logical Inhibit ..................................................................................19 Power-Up Write Inhibit ....................................................................19 Command Definitions . . . . . . . . . . . . . . . . . . . . . . 19 Reading Array Data ................................................................ 19 Reset Command ..................................................................... 20 Autoselect Command Sequence ............................................ 20 Enter SecSi™ Sector/Exit SecSi Sector Command Sequence .............................................................. 20 Word/Double Word Program Command Sequence ............... 20 Double Word/Word Configuration (WORD#) ........................ 37 Figure 15. WORD# Timings for Read Operations.......................... 37 Figure 16. WORD# Timings for Write Operations.......................... 37 Program/Erase Operations .................................................... 38 Figure 17. Program Operation Timings.......................................... Figure 18. AC Waveforms for Chip/Sector Erase Operations........ Figure 19. Data# Polling Timings (During Embedded Algorithms). Figure 20. Toggle Bit Timings (During Embedded Algorithms)...... Figure 21. DQ2 vs. DQ6 for Erase and Erase Suspend Operations ............................................................ 39 40 40 41 41 Alternate CE# Controlled Erase/Program Operations ..................................................... 42 Figure 22. Alternate CE# Controlled Write Operation Timings ...... 43 Unlock Bypass Command Sequence ..............................................21 Figure 2. Program Operation .......................................................... 21 Erase and Programming Performance . . . . . . . 44 Latchup Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Data Retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 BGA Package Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 46 Chip Erase Command Sequence ........................................... 22 Sector Erase Command Sequence ........................................ 22 Erase Suspend/Erase Resume Commands ........................... 22 Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 47 Revision A (March 7, 2001) .................................................... 47 June 13, 2005 FBF084—84-Ball Fine Pitch Ball Grid Array (FBGA) 11 x 12 mm ..... 46 Am29PL320D 3 Revision B (June 12, 2001) .................................................... 47 Revision B+1 (August 30, 2001) ............................................. 47 Revision C (October 22, 2002) ............................................... 47 4 Revision C+1 (July 21, 2003) ................................................. 47 Revision C+2 (October 2, 2003) ............................................. 47 Am29PL320D June 13, 2005 PRODUCT SELECTOR GUIDE Family Part Number Speed Option Am29PL320D Regulated Voltage Range: VCC =3.0–3.6 V 60R 70R Full Voltage Range: VCC = 2.7–3.6 V 70 90 Max access time, ns (tACC) 60 70 90 Max CE# access time, ns (tCE) 60 70 90 Max page access time, ns (tPACC) 20 25 30 Max OE# access time, ns (tOE) 20 25 30 Note: See “AC Characteristics” for full specifications. BLOCK DIAGRAM DQ31–DQ0 VCC VSS Erase Voltage Generator WE# WORD# ACC Input/Output Buffers State Control Command Register WP# PGM Voltage Generator Chip Enable Output Enable Logic CE# OE# VCC Detector Address Latch STB Timer A19–A0 STB Data Latch Y-Decoder Y-Gating X-Decoder Cell Matrix A1, A0, A-1 June 13, 2005 Am29PL320D 5 CONNECTION DIAGRAMS 84-Ball FBGA Top View, Balls Facing Down B9 C9 D9 E9 F9 G9 H9 J9 DQ30 VCC DQ13 DQ12 DQ27 DQ26 VCC DQ9 A8 B8 C8 D8 E8 F8 G8 H8 J8 K8 CE# VSS DQ15 DQ29 DQ28 DQ11 VSS DQ24 VCC A19 A7 B7 C7 D7 E7 F7 G7 H7 J7 K7 NC WORD# OE# DQ14 VSS DQ10 DQ25 A18 A17 A16 A6 B6 C6 D6 E6 F6 G6 H6 J6 K6 WE# NC NC DQ31/A-1 NC NC DQ8 A15 A14 A13 A5 B5 C5 D5 E5 F5 G5 H5 J5 K5 NC ACC WP# NC NC NC NC NC NC NC A4 B4 C4 D4 E4 F4 G4 H4 J4 K4 A1 A2 A3 A0 DQ2 NC A12 A11 A9 A10 A3 B3 C3 D3 E3 F3 G3 H3 J3 K3 A4 A5 DQ0 DQ16 DQ18 DQ5 DQ21 A8 A6 A7 B2 C2 D2 E2 F2 G2 H2 J2 K2 VCC DQ1 VSS DQ19 DQ4 DQ6 DQ7 DQ23 VSS C1 D1 E1 F1 G1 J1 DQ17 VCC DQ3 DQ20 VSS H1 VCC Special Handling Instructions for FBGA Package Special handling is required for Flash Memory products in FBGA packages. 6 DQ22 Flash memory devices in FBGA packages may be damaged if exposed to ultrasonic cleaning methods. The package and/or data integrity may be compromised if the package body is exposed to temperatures above 150°C for prolonged periods of time. Am29PL320D June 13, 2005 INPUT CONFIGURATION A19–A0 LOGIC SYMBOL = 20 address inputs 20 DQ30–DQ0 = 31 data inputs/outputs A19–A0 DQ31/A-1 = In double word mode, functions as DQ31. In word mode, functions as A-1 (LSB address input) WORD# = Word enable input When low, enables word mode When high, enables double word mode WP# = Hardware Write Protect input ACC = Acceleration input CE# = Chip Enable input OE# = Output Enable input WE# = Write Enable input VCC = 3.0 volt-only single power supply (see Product Selector Guide for speed options and voltage supply tolerances) VSS = Device ground NC = input not connected internally June 13, 2005 16 or 32 DQ31–DQ0 (A-1) CE# OE# WE# WORD# WP# ACC Am29PL320D 7 ORDERING INFORMATION Standard Products AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of the elements below. Am29PL320D B 60R WP I TEMPERATURE RANGE I = Industrial (–40°C to +85°C) PACKAGE TYPE WP = 84-Ball Fine Pitch Ball Grid Array (FBGA) 0.8 mm pitch (FBF084) SPEED OPTION See Product Selector Guide and Valid Combinations BOOT CODE SECTOR ARCHITECTURE T = Top Boot Sector B = Bottom Boot Sector DEVICE NUMBER/DESCRIPTION Am29PL320D 32 Megabit (2 M x 16-Bit/1 M x 32-Bit) CMOS 3.0 Volt-only High Performance Page Mode Flash Memory Valid Combinations Package Marking AM29PL320DT60R, AM29PL320DB60R P320DT60RI, P320DB60RI AM29PL320DT70R, AM29PL320DB70R P320DT70RI, P320DB70RI Voltage Range VCC = 3.0–3.6 V WPI AM29PL320DT70, AM29PL320DB70 P320DT70VI, P320DB70VI AM29PL320DT90, AM29PL320DB90 P320DT90VI, P320DB90VI VCC = 2.7–3.6 V Valid Combinations Valid Combinations list configurations planned to be supported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly released combinations. 8 Am29PL320D June 13, 2005 DEVICE BUS OPERATIONS This section describes the requirements and use of the device bus operations, which are initiated through the internal command register. The command register itself does not occupy any addressable memor y location. The register is composed of latches that store the commands, along with the address and data information needed to execute the command. The contents Table 1. of the register serve as inputs to the internal state machine. The state machine outputs dictate the function of the device. Table 1 lists the device bus operations, the inputs and control levels they require, and the resulting output. The following subsections describe each of these operations in further detail. Am29PL320D Device Bus Operations DQ31–DQ8 CE# OE# WE# WP# Addresses (Note 1) Read L L H X AIN DOUT DOUT Write L H L X AIN DIN DIN DQ30–DQ16 = High-Z, DQ31 = A-1 VCC ± 0.3 V X X X X High-Z High-Z High-Z L H H X X High-Z High-Z High-Z Operation Standby Output Disable DQ7– DQ0 WORD# = VIH WORD# = VIL Legend: L = Logic Low = VIL, H = Logic High = VIH, VID = 12.0 ± 0.5 V, X = Don’t Care, AIN = Address In, DIN = Data In, DOUT = Data Out Notes: 1. Addresses are A19–A0 in double word mode (WORD# = VIH), A19–A-1 in word mode (WORD# = VIL). 2. The sector protect and sector unprotect functions must be implemented via programming equipment. See the “Sector Protection/Unprotection” section. Word/Double Word Configuration The WORD# input controls whether the device data I/Os DQ31–DQ0 operate in the word or double word configuration. If the WORD# input is set at VIH, the device is in double word configuration; DQ31–DQ0 are active and controlled by CE# and OE#. If the WORD# input is set at logic ‘0’, the device is in word configuration, and only data I/Os DQ15–DQ0 are active and controlled by CE# and OE#. The data I/Os DQ30–DQ16 are tri-stated, and the DQ31 input is used as an input for the LSB (A-1) address function. Requirements for Reading Array Data To read array data from the outputs, the system must drive the CE# and OE# inputs to VIL. CE# is the power control and selects the device. OE# is the output control and gates array data to the output inputs. WE# should remain at VIH. The WORD# input determines whether the device outputs array data in words or bytes. The internal state machine is set for reading array data upon device power-up. This ensures that no spurious alteration of the memory content occurs during the power transition. No command is necessary in this mode to obtain array data. Standard microprocessor read cycles that assert valid addresses on the device June 13, 2005 address inputs produce valid data on the device data outputs. The device remains enabled for read access until the command register contents are altered. See “Reading Array Data” for more information. Refer to the AC Read Operations table for timing specifications and to Figure 13 for the timing diagram. ICC1 in the DC Characteristics table represents the active current specification for reading array data. Read Mode Random Read (Non-Page Mode Read) The device has two control functions which must be satisfied in order to obtain data at the outputs. CE# is the power control and should be used for device selection. OE# is the output control and should be used to gate data to the output inputs if the device is selected. Address access time (tACC) is equal to the delay from stable addresses to valid output data. The chip enable access time (t CE ) is the delay from the stable addresses and stable CE# to valid data at the output inputs. The output enable access time is the delay from the falling edge of OE# to valid data at the output inputs (assuming the addresses have been stable for at least tACC–tOE time). Am29PL320D 9 Page Mode Read The Am29PL320D is capable of fast page mode read and is compatible with the page mode Mask ROM read operation. This mode provides faster read access speed for random locations within a page. The page size of the Am29PL320D device is 8 words, or 4 double words, with the appropriate page being selected by the higher address bits A19–A2 and the LSB bits A1– A0 (in the double word mode) and A1 to A-1 (in the word mode) determining the specific word/double word within that page. This is an asynchronous operation with the microprocessor supplying the specific word or double word location. The following tables determine the specific word and double word within the selected page: The random or initial page access is equal to tACC or tCE and subsequent page read accesses (as long as the locations specified by the microprocessor falls within that page) is equivalent to tPACC. When CE# is deasserted and reasserted for a subsequent access, the access time is tACC or tCE. Here again, CE# selects the device and OE# is the output control and should be used to gate data to the output inputs if the device is selected. Fast page mode accesses are obtained by keeping A19–A2 constant and changing A1 to A0 to select the specific double word, or changing A1 to A-1 to select the specific word, within that page. 10 Am29PL320D Table 2. Double Word Mode Word A1 A0 Double Word 0 0 0 Double Word 1 0 1 Double Word 2 1 0 Double Word 3 1 1 Table 3. Word Mode Word A1 A0 A-1 Word 0 0 0 0 Word 1 0 0 1 Word 2 0 1 0 Word 3 0 1 1 Word 4 1 0 0 Word 5 1 0 1 Word 6 1 1 0 Word 7 1 1 1 June 13, 2005 Writing Commands/Command Sequences To write a command or command sequence (which includes programming data to the device and erasing sectors of memory), the system must drive WE# and CE# to VIL, and OE# to VIH. For program operations, the WORD# input determines whether the device accepts program data in double words or words. Refer to “Word/Double Word Configuration” for more information. The device features an Unlock Bypass mode to facilitate faster programming. Once the device enters the Unlock Bypass mode, only two write cycles are required to program a word or double word, instead of four. The “Word/Double Word Program Command Sequence” section has details on programming data to the device using both standard and Unlock Bypass command sequences. An erase operation can erase one sector, multiple sectors, or the entire device. Table 4 indicates the address space that each sector occupies. A “sector address” consists of the address bits required to uniquely select a sector. The “Command Definitions” section has details on eras ing a s ector or the entire chip, or suspending/resuming the erase operation. After the system writes the autoselect command sequence, the device enters the autoselect mode. The system can then read autoselect codes from the internal register (which is separate from the memory array) on DQ7–DQ0. Standard read cycle timings apply in this mode. Refer to the “Autoselect Mode” and “Autoselect Command Sequence” sections for more information. ICC2 in the DC Characteristics table represents the active current specification for the write mode. The “AC Characteristics” section contains timing specification tables and timing diagrams for write operations. Accelerated Program Operation The device offers accelerated program operations through the ACC function. This function is primarily intended to allow faster manufacturing throughput during system production. If the system asserts VHH (11.5 to 12.5 V) on this input, the device automatically enters the aforementioned Unlock Bypass mode, temporarily unprotects any protected sectors, and uses the higher voltage on the pin to reduce the time required for program operations. The system would use a two-cycle program command sequence as required by the Unlock Bypass mode. Removing V HH from the ACC pin returns the June 13, 2005 device to normal operation. Note that the ACC pin must not be at VHH for operations other than accelerated programming, or device damage may result. In addition, the ACC pin must not be left floating or unconnected; inconsistent behavior of the device may result. Program and Erase Operation Status During an erase or program operation, the system may check the status of the operation by reading the status bits on DQ7–DQ0. Standard read cycle timings and ICC read specifications apply. Refer to “Write Operation Status” for more information, and to “AC Characteristics” for timing diagrams. Standby Mode When the system is not reading or writing to the device, it can place the device in the standby mode. In this mode, current consumption is greatly reduced, and the outputs are placed in the high impedance state, independent of the OE# input. The device enters the CMOS standby mode when the CE# input is both held at VCC ± 0.3 V. (Note that this is a more restricted voltage range than VIH .) If CE# is held at VIH, but not within VCC ± 0.3 V, the device will be in the standby mode, but the standby current will be greater. The device requires standard access time (tCE) for read access when the device is in either of these standby modes, before it is ready to read data. If the device is deselected during erasure or programming, the device draws active current until the operation is completed. Automatic Sleep Mode The automatic sleep mode minimizes Flash device energy consumption. The device automatically enables this mode when addresses remain stable for tACC + 30 ns. The automatic sleep mode is independent of the CE#, WE#, and OE# control signals. Standard address access timings provide new data when addresses are changed. While in sleep mode, output data is latched and always available to the system. Note that during Automatic Sleep mode, OE# must be at VIH before the device reduces current to the stated sleep mode specification. Output Disable Mode When the OE# input is at VIH, output from the device is disabled. The output inputs are placed in the high impedance state. Am29PL320D 11 Table 4. Sector A19 A18 Sector Address Table, Top Boot (Am29PL320DT) A17 A16 A15 A14 A13 A12 Sector Size (Kwords/ Kdouble words) Address Range (in hexadecimal) Word Mode (x16) Double Word Mode (x32) SA0 0 0 0 0 X X X X 128/64 000000–01FFFF 00000–0FFFF SA1 0 0 0 1 X X X X 128/64 020000–03FFFF 10000–1FFFF SA2 0 0 1 0 X X X X 128/64 040000–05FFFF 20000–2FFFF SA3 0 0 1 1 X X X X 128/64 060000–07FFFF 30000–3FFFF SA4 0 1 0 0 X X X X 128/64 080000–09FFFF 40000–4FFFF SA5 0 1 0 1 X X X X 128/64 0A0000–0BFFFF 50000–5FFFF SA6 0 1 1 0 X X X X 128/64 0C0000–0DFFFF 60000–6FFFF SA7 0 1 1 1 X X X X 128/64 0E0000–0FFFFF 70000–7FFFF SA8 1 0 0 0 X X X X 128/64 100000–11FFFF 80000–8FFFF SA9 1 0 0 1 X X X X 128/64 120000–13FFFF 90000–9FFFF SA10 1 0 1 0 X X X X 128/64 140000–15FFFF A0000–AFFFF SA11 1 0 1 1 X X X X 128/64 160000–17FFFF B0000–BFFFF SA12 1 1 0 0 X X X X 128/64 180000–19FFFF C0000–CFFFF SA13 1 1 0 1 X X X X 128/64 1A0000–1BFFFF D0000–DFFFF SA14 1 1 1 0 X X X X 128/64 1C0000–1DFFFF E0000–EFFFF SA15 1 1 1 1 96/48 1E0000–1F7FFF F0000–FBFFF SA16 1 1 1 1 1 1 0 0 8/4 1F8000–1F9FFF FC000–FCFFF SA17 1 1 1 1 1 1 0 1 8/4 1FA000–1FBFFF FD000–FDFFF SA18 1 1 1 1 1 1 1 X 16/8 1FC000–1FFFFF FE000–FFFFF 0000–1011 Note: Address range is A19–A-1 if device is in word mode (WORD# = VIL). Address range is A19–A0 if device is in double word mode (WORD# = VIH). Table 5. 12 SecSi™ Sector Addresses for Top Boot Devices Device Sector Address A7–A0 Sector Size (x16) Address Range (x32) Address Range Am29PL320DT 00000000 512 words/256 double words 000000h–0001FFh 00000h–000FFh Am29PL320D June 13, 2005 Table 6. Sector Address Table, Bottom Boot (Am29PL320DB) Sector A19 A18 A17 A16 A15 A14 A13 A12 Sector Size (Kwords/ Kdouble words) SA0 0 0 0 0 0 0 0 X 16/8 000000–003FFF 00000–001FF SA1 0 0 0 0 0 0 1 0 8/4 004000–005FFF 02000–02FFF SA2 0 0 0 0 0 0 1 1 8/4 006000–007FFF 03000–03FFF SA3 0 0 0 0 96/48 008000–01FFFF 04000–0FFFF SA4 0 0 0 1 X X X X 128/64 020000–03FFFF 10000–1FFFF SA5 0 0 1 0 X X X X 128/64 040000–05FFFF 20000–2FFFF SA6 0 0 1 1 X X X X 128/64 060000–07FFFF 30000–3FFFF SA7 0 1 0 0 X X X X 128/64 080000–09FFFF 40000–4FFFF SA8 0 1 0 1 X X X X 128/64 0A0000–0BFFFF 50000–5FFFF SA9 0 1 1 0 X X X X 128/64 0C0000–0DFFFF 60000–6FFFF SA10 0 1 1 1 X X X X 128/64 0E0000–0FFFFF 70000–7FFFF SA11 1 0 0 0 X X X X 128/64 100000–11FFFF 80000–8FFFF SA12 1 0 0 1 X X X X 128/64 120000–13FFFF 90000–9FFFF SA13 1 0 1 0 X X X X 128/64 140000–15FFFF A0000–AFFFF SA14 1 0 1 1 X X X X 128/64 160000–17FFFF B0000–BFFFF SA15 1 1 0 0 X X X X 128/64 180000–19FFFF C0000–CFFFF SA16 1 1 0 1 X X X X 128/64 1A0000–1BFFFF D0000–DFFFF SA17 1 1 1 0 X X X X 128/64 1C0000–1DFFFF E0000–EFFFF SA18 1 1 1 1 X X X X 128/64 1E0000–1FFFFF F0000–FFFFF 01000–11111 Address Range (in hexadecimal) Word Mode (x16) Double Word Mode (x32) Note: Address range is A19–A-1 if device is in word mode (WORD# = VIL). Address range is A19–A0 if device is in double word mode (WORD# = VIH). Table 7. SecSi™ Sector Addresses for Bottom Boot Devices Device Sector Address A7–A0 Sector Size (x16) Address Range (x32) Address Range Am29PL320DB 00000000 512 words/256 double words 000000h–0001FFh 00000h–000FFh June 13, 2005 Am29PL320D 13 Autoselect Mode dition, when verifying sector protection, the sector address must appear on the appropriate highest order address bits (Table 4). Table 8 shows the remaining address bits that are don’t care. When all necessary bits have been set as required, the programming equipment may then read the corresponding identifier code on DQ7-DQ0. The autoselect mode provides manufacturer and device identification, and sector protection verification, through identifier codes output on DQ7–DQ0. This mode is primarily intended for programming equipment to automatically match a device to be programmed with its corresponding programming algorithm. However, the autoselect codes can also be accessed insystem through the command register. To access the autoselect codes in-system, the host system can issue the autoselect command via the command register, as shown in Table 13. This method does not require VID. See “Command Definitions” for details on using the autoselect mode. When using programming equipment, the autoselect mode requires VID (11.5 V to 12.5 V) on address input A9. Address inputs must be as shown in Table 8. In ad- A8–A7 A6 A5–A4 A3 A2 A1 A0 Read Cycle 3 A9 Read Cycle 2 Word A11–A10 Device ID Read Cycle 1 A19–12 Manufacturer ID: AMD WE# Mode DQ31– DQ8 H X X VID X L X X X L L X X X VID X L X L L L H VID X VID X OE# Description Am29PL320D Autoselect Codes (High Voltage Method) CE# Table 8. L L L L H Dbl. Word L L H Word L L H L L H Word L L H 7Eh 222222h 22h X Dbl. Word 01h 22h X Dbl. Word DQ7–DQ0 X X L X H H H L 03h 222222h L X H H H 22h 00h (bottom boot) 222222h 01h (top boot) 80h (factory locked) 00h (not factory locked) H L L H SecSi™ Sector Indicator Bit L L H X X VID X L X L L H H X Sector Protection Verification L L H SA X VID X L X L L H L X 01h (protected) 00h (unprotected) L = Logic Low = VIL, H = Logic High = VIH, SA = Sector Address, X = Don’t care. Note: The autoselect codes may also be accessed in-system via command sequences. See Table 13. Sector Protection/Unprotection The hardware sector protection feature disables both p r o g ra m a n d e r a s e o p e r a ti o n s i n a ny s e ct o r. The hardware sector unprotection feature re-enables both program and erase operations in previously protected sectors. The device is shipped with all sectors unprotected. AMD offers the option of programming and protecting sectors at its factory prior to shipping the device through AMD’s ExpressFlash™ Service. Contact an AMD representative for details. It is possible to determine whether a sector is protected or unprotected. See “Autoselect Mode” for details. 14 Sector protection and unprotection must be implemented via programming equipment. The procedure requires high voltage (VID ) to be placed on address input A9 and control input OE#. This method is compatible with programmer routines written for earlier AMD 3.0 volt devices. Publication number 24136 contains further details; contact an AMD representative to request a copy. For sector unprotect, all unprotected sectors must first be protected prior to the first sector unprotect write cycle. Note that after the sector unprotect operation, all previously protected sectors must be re-protected using the sector protect algorithm. The device features a temporary unprotect command sequence to allow changing array data in-system. See “ Tem p o rar y S e cto r U n p r ote ct E n able /D i sa bl e Command Sequence” for more information. Am29PL320D June 13, 2005 COMMON FLASH MEMORY INTERFACE (CFI) The Common Flash Interface (CFI) specification outlines device and host system software interrogation handshake, which allows specific vendor-specified software algorithms to be used for entire families of dev i c e s . S o f tw a r e s u p p o r t c a n t h e n b e d ev i c e independent, JEDEC ID-independent, and forwardand backward-compatible for the specified flash device families. Flash vendors can standardize their existing interfaces for long-term compatibility. This device enters the CFI Query mode when the system writes the CFI Query command, 98h, to address 55h in double word mode (or address AAh in word mode), any time the device is ready to read array data. Table 9. The system can read CFI information at the addresses given in Tables 9–12. To terminate reading CFI data, the system must write the reset command. The system can also write the CFI query command when the device is in the autoselect mode. The device enters the CFI query mode, and the system can read CFI data at the addresses given in Tables 9–12. The system must write the reset command to return the device to the autoselect mode. For further information, please refer to the CFI Specification and CFI Publication 100, available via the World Wide Web at http://www.amd.com/flash/cfi. Alternatively, contact an AMD representative for copies of these documents. CFI Query Identification String Addresses (Double Word Mode) Addresses (Word Mode) Data 10h 11h 12h 20h 22h 24h 0051h 0052h 0059h Query Unique ASCII string “QRY” 13h 14h 26h 28h 0002h 0000h Primary OEM Command Set 15h 16h 2Ah 2Ch 0040h 0000h Address for Primary Extended Table 17h 18h 2Eh 30h 0000h 0000h Alternate OEM Command Set (00h = none exists) 19h 1Ah 32h 34h 0000h 0000h Address for Alternate OEM Extended Table (00h = none exists) June 13, 2005 Description Am29PL320D 15 Table 10. System Interface String Addresses (Double Word Mode) Addresses (Word Mode) Data 1Bh 36h 0027h VCC Min. (write/erase) D7–D4: volt, D3–D0: 100 millivolt 1Ch 38h 0036h VCC Max. (write/erase), D7–D4: volt, D3–D0: 100 millivolt 1Dh 3Ah 0000h VPP Min. voltage (00h = no VPP input present) 1Eh 3Ch 0000h VPP Max. voltage (00h = no VPP input present) 1Fh 3Eh 0004h Typical timeout per single word/double word write 2N µs 20h 40h 0000h Typical timeout for Min. size buffer write 2N µs (00h = not supported) 21h 42h 000Ah Typical timeout per individual block erase 2N ms 22h 44h 0000h Typical timeout for full chip erase 2N ms (00h = not supported) 23h 46h 0005h Max. timeout for word/ double word write 2N times typical 24h 48h 0000h Max. timeout for buffer write 2N times typical 25h 4Ah 0006h Max. timeout per individual block erase 2N times typical 26h 4Ch 0000h Max. timeout for full chip erase 2N times typical (00h = not supported) Table 11. Description Device Geometry Definition Addresses (Double Word Mode) Addresses (Word Mode) Data 27h 4Eh 0016h Device Size = 2N byte 28h 29h 50h 52h 0005h 0000h Flash Device Interface description (refer to CFI publication 100) 2Ah 2Bh 54h 56h 0000h 0000h Max. number of bytes in multi-byte write = 2N (00h = not supported) 2Ch 58h 0004h Number of Erase Block Regions within device 2Dh 2Eh 2Fh 30h 5Ah 5Ch 5Eh 60h 0000h 0000h 0080h 0000h Erase Block Region 1 Information (refer to the CFI specification or CFI publication 100) 31h 32h 33h 34h 62h 64h 66h 68h 0001h 0000h 0040h 0000h Erase Block Region 2 Information 35h 36h 37h 38h 6Ah 6Ch 6Eh 70h 0000h 0000h 0000h 0003h Erase Block Region 3 Information 39h 3Ah 3Bh 3Ch 72h 74h 76h 78h 000Eh 0000h 0000h 0004h Erase Block Region 4 Information 16 Description Am29PL320D June 13, 2005 Table 12. Primary Vendor-Specific Extended Query Addresses (Double Word Mode) Addresses (Word Mode) Data 40h 41h 42h 80h 82h 84h 0050h 0052h 0049h Query-unique ASCII string “PRI” 43h 86h 0031h Major version number, ASCII 44h 88h 0032h Minor version number, ASCII 45h 8Ah 0000h Address Sensitive Unlock 0 = Required, 1 = Not Required 46h 8Ch 0002h Erase Suspend 0 = Not Supported, 1 = To Read Only, 2 = To Read & Write 47h 8Eh 0001h Sector Protect 0 = Not Supported, X = Number of sectors in per group 48h 90h 0001h Sector Temporary Unprotect 00 = Not Supported, 01 = Supported 49h 92h 0001h Sector Protect/Unprotect scheme 01 = 29F040 mode, 02 = 29F016 mode, 03 = 29F400 mode, 04 = 29LV800A mode 4Ah 94h 0000h Simultaneous Operation 00 = Not Supported, 01 = Supported 4Bh 96h 0000h Burst Mode Type 00 = Not Supported, 01 = 4 Word Linear Burst, 02 = 8 Word Linear Burst, 03 = 32 Linear Burst, 04 = 4 Word Interleave Burst 4Ch 98h 0002h Page Mode Type 00 = Not Supported, 01 = 4 Word Page, 02 = 8 Word Page 4Dh 9Ah 00B5h ACC (Acceleration) Supply Minimum 00h = not supported, D7–D4: volt; D3–D0: 100 millivolt. 4Eh 9Ch 00C5h ACC (Acceleration) Supply Maximum 00h = not supported, D7–D4: volt; D3–D0: 100 millivolt. 50h A0h 0000h Program Suspend 00h = not supported, 01h = supported Description SecSi™ (Secured Silicon) Sector Flash Memory Region 128 words. This should be considered during system design. The SecSi (Secured Silicon) Sector feature provides a Flash memory region that enables permanent part identification through an Electronic Serial Number (ESN). The SecSi Sector is a minimum of 128 words (64 double words) in length, and uses a SecSi Sector Indicator Bit (DQ7) to indicate whether or not the SecSi Sector is locked when shipped from the factory. This bit is permanently set at the factory and cannot be changed, which prevents cloning of a factory locked part. This ensures the security of the ESN once the product is shipped to the field. Current version of device has 512 words; future versions will have only AMD offers the device with the SecSi Sector either factory locked or customer lockable. The factorylocked version is always protected when shipped from the factory, and has the SecSi (Secured Silicon) Sector Indicator Bit permanently set to a “1.” The customer-lockable version is shipped with the SecSi Sector unprotected, allowing customers to utilize the that sector in any manner they choose. The customerlockable version has the SecSi (Secured Silicon) Sector Indicator Bit permanently set to a “0.” Thus, the SecSi Sector Indicator Bit prevents customer-lockable June 13, 2005 Am29PL320D 17 devices from being used to replace devices that are factory locked. bypass functions are not available when programming the SecSi Sector. The system accesses the SecSi Sector through a command sequence (see “Enter SecSi ™ Sector/Exit SecSi Sector Command Sequence”). After the system has written the Enter SecSi Sector command sequence, it may read the SecSi Sector by using the addresses normally occupied by the boot sectors. This mode of operation continues until the system issues the Exit SecSi Sector command sequence, or until power is removed from the device. On power-up the device reverts to sending commands to the boot sectors. The SecSi Sector can be locked in-system by performing the following steps: Factory Locked: SecSi Sector Programmed and Protected At the Factory In a factory locked device, the SecSi Sector is protected when the device is shipped from the factory. The SecSi Sector cannot be modified in any way. The device is available preprogrammed with one of the following: ■ A random, secure ESN only ■ Write the three-cycle Enter SecSi Sector Region command sequence. ■ Write 60h to any address (protect command). ■ Wait 150 µs, and then write 40h to address 01h (verify command). ■ Read from address 02h. The data should be 01h. ■ Write the reset command (F0h to any address). ■ Write the four-cycle Exit SecSi Sector command sequence to return to reading from the array. To verify the protect/unprotect status of the SecSi Sector, follow the algorithm shown in Figure 1. The SecSi Sector lock must be used with caution since, once locked, there is no procedure available for unlocking the SecSi Sector area and none of the bits in the SecSi Sector memory space can be modified in any way. ■ Customer code through the ExpressFlash service ■ Both a random, secure ESN and customer code through the ExpressFlash service. START In devices that have an ESN, a Bottom Boot device will have the 8-word (4-double word) ESN in the lowest addressable memor y area at addresses 000000h– 000003h in double word mode (or 000000h–000007h in word mode). In the Top Boot device the starting address of the ESN will be at the bottom of the lowest 8 Kbyte boot sector at addresses 1F8000h–1F8003h in double word mode (or addresses FC0000h–FC0007h in word mode). RESET# = VIH or VID Wait 1 μs Write 60h to any address Write 40h to SecSi Sector address with A6 = 0, A1 = 1, A0 = 0 Customers may opt to have their code programmed by AMD through the AMD ExpressFlash service. AMD programs the customer’s code, with or without the random ESN. The devices are then shipped from AMD’s factory with the SecSi Sector permanently locked. Contact an AMD representative for details on using AMD’s ExpressFlash service. Read from SecSi Sector address with A6 = 0, A1 = 1, A0 = 0 If data = 00h, SecSi Sector is unprotected. If data = 01h, SecSi Sector is protected. Remove VIH or VID from RESET# Write reset command SecSi Sector Protect Verify complete Customer Lockable: SecSi Sector NOT Programmed or Locked At the Factory If the security feature is not required, the SecSi Sector can be treated as an additional Flash memory space, expanding the size of the available Flash array. Current version of device has 512 words; future versions will have only 128 words. This should be considered during system design. The SecSi Sector can be read, programmed, and erased as often as required. (In upcoming versions of this device, the SecSi Sector erase function will not be available.) Note that the accelerated programming (ACC) and unlock 18 Figure 1. SecSi Sector Protect Verify Write Protect (WP#) The Write Protect function provides a hardware method of protecting certain boot sectors without using VID. If the system asserts VIL on the WP# input, the device disables program and erase functions in Sector 0 (for bottom boot) or Sector 18 (for top boot) independently of whether those sectors were protected or unpro- Am29PL320D June 13, 2005 tected using the method described in “Sector Protection/Unprotection”. If the system asserts VIH on the WP# input, the device reverts to whether Sector 0 or 18 was last set to be protected or unprotected. That is, sector protection or unprotection for that sector depends on whether they were last protected or unprotected using the method described in “Sector Protection/Unprotection”. Note that the WP# input must not be left floating or unconnected; inconsistent behavior of the device may result. Hardware Data Protection The command sequence requirement of unlock cycles for programming or erasing provides data protection against inadvertent writes (refer to Table 13 for command definitions). In addition, the following hardware data protection measures prevent accidental erasure or programming, which might otherwise be caused by spurious system level signals during V CC power-up and power-down transitions, or from system noise. Low VCC Write Inhibit When VCC is less than VLKO, the device does not accept any write cycles. This protects data during VCC power-up and power-down. The command register and all internal program/erase circuits are disabled, and the device resets. Subsequent writes are ignored until VCC is greater than VLKO. The system must provide the proper signals to the control inputs to prevent unintentional writes when VCC is greater than VLKO. Write Pulse “Glitch” Protection Noise pulses of less than 5 ns (typical) on OE#, CE# or WE# do not initiate a write cycle. Logical Inhibit Write cycles are inhibited by holding any one of OE# = VIL, CE# = VIH or WE# = VIH. To initiate a write cycle, CE# and WE# must be a logical zero while OE# is a logical one. Power-Up Write Inhibit If WE# = CE# = VIL and OE# = VIH during power up, the device does not accept commands on the rising edge of WE#. The internal state machine is automatically reset to reading array data on power-up. COMMAND DEFINITIONS Writing specific address and data commands or sequences into the command register initiates device operations. Table 13 defines the valid register command sequences. Note that writing incorrect address and data values or writing them in the improper sequence may place the device in an unknown state. A reset command is required to return the device to normal operation. All addresses are latched on the falling edge of WE# or CE#, whichever happens later. All data is latched on the rising edge of WE# or CE#, whichever happens first. Refer to the appropriate timing diagrams in the “AC Characteristics” section. Reading Array Data The device is automatically set to reading array data after device power-up. No commands are required to retrieve data. The device is also ready to read array data after completing an Embedded Program or Embedded Erase algorithm. After the device accepts an Erase Suspend command, the device enters the Erase Suspend mode. The system can read array data using the standard read timings, except that if it reads at an address within erase-suspended sectors, the device outputs status data. After completing a programming operation in the Erase Suspend mode, the system may once again read array data with the same exception. See “Erase June 13, 2005 Suspend/Erase Resume Commands” for more information on this mode. The system must issue the reset command to re-enable the device for reading array data if DQ5 goes high, or while in the autoselect mode. See the “Reset Command” section, next. See also “Requirements for Reading Array Data” in the “Device Bus Operations” section for more information. The Read Operations table provides the read parameters, and Figure 13 shows the timing diagram. Reset Command Writing the reset command to the device resets the device to reading array data. Address bits are don’t care for this command. The reset command may be written between the sequence cycles in an erase command sequence before erasing begins. This resets the device to reading array data. Once erasure begins, however, the device ignores reset commands until the operation is complete. The reset command may be written between the sequence cycles in a program command sequence before programming begins. This resets the device to reading array data (also applies to programming in Erase Suspend mode). Once programming begins, however, the device ignores reset commands until the operation is complete. Am29PL320D 19 The reset command may be written between the sequence cycles in an autoselect command sequence. Once in the autoselect mode, the reset command must be written to return to reading array data (also applies to autoselect during Erase Suspend). If DQ5 goes high during a program or erase operation, writing the reset command returns the device to reading array data (also applies during Erase Suspend). Autoselect Command Sequence The autoselect command sequence allows the host system to access the manufacturer and devices codes, and determine whether or not a sector is protected. Table 13 shows the address and data requirements. The autoselect command sequence is initiated by writing two unlock cycles, followed by the autoselect command. The device then enters the autoselect mode, and the system may read any number of autoselect codes without reinitiating the command sequence. Tables 13 and 14 show the address and data requirements for the command sequence. To determine sector protection information, the system must write to the appropriate sector address (SA). Tables 4 and 6 show the address range associated with each sector. The system must write the reset command to exit the autoselect mode and return to reading array data. Enter SecSi™ Sector/Exit SecSi Sector Command Sequence The SecSi Sector region provides a secured data area containing a random, eight-word (or four double word) electronic serial number (ESN). The system can access the SecSi Sector region by issuing the threecycle Enter SecSi Sector command sequence. The device continues to access the SecSi Sector region until the system issues the four-cycle Exit SecSi Sector command sequence. The Exit SecSi Sector comm a n d s e q ue n c e r e tu r ns t h e d ev ic e t o n o r m a l operation. Table 13 shows the address and data requirements for both command sequences. See also “SecSi™ (Secured Silicon) Sector Flash Memory Region” for further information. Word/Double Word Program Command Sequence The system may program the device by word or double word, depending on the state of the WORD# input. Programming is a four-bus-cycle operation. The program command sequence is initiated by writing two unlock write cycles, followed by the program set-up command. The program address and data are written next, which in turn initiate the Embedded Program algorithm. The system is not required to provide further 20 controls or timings. The device automatically generates the program pulses and verifies the programmed cell margin. Table 13 shows the address and data requirements for the program command sequence. When the Embedded Program algorithm is complete, the device then returns to reading array data and addresses are no longer latched. The system can determine the status of the program operation by using DQ7 or DQ6. See “Write Operation Status” for information on these status bits. Any commands written to the device during the Embedded Program Algorithm are ignored. The Program command sequence should be reinitiated once the device has reset to reading array data, to ensure data integrity. Programming is allowed in any sequence and across sector boundaries. A bit cannot be programmed from a “0” back to a “1”. Attempting to do so may halt the operation and set DQ5 to “1,” or cause the Data# Polling algorithm to indicate the operation was successful. However, a succeeding read will show that the data is still “0”. Only erase operations can convert a “0” to a “1”. Unlock Bypass Command Sequence The unlock bypass feature allows the system to program bytes or words to the device faster than using the standard program command sequence. The unlock bypass command sequence is initiated by first writing two unlock cycles. This is followed by a third write cycle containing the unlock bypass command, 20h. The device then enters the unlock bypass mode. A two-cycle unlock bypass program command sequence is all that is required to program in this mode. The first cycle in this sequence contains the unlock bypass program command, A0h; the second cycle contains the program address and data. Additional data is programmed in the same manner. This mode dispenses with the initial two unlock cycles required in the standard program command sequence, resulting in faster total programming time. Table 13 shows the requirements for the command sequence. During the unlock bypass mode, only the Unlock Bypass Program and Unlock Bypass Reset commands are valid. To exit the unlock bypass mode, the system must issue the two-cycle unlock bypass reset command sequence. The first cycle must contain the data 90h; the second cycle the data 00h. Addresses are don’t care for both cycles. The device then returns to reading array data. Figure 2 illustrates the algorithm for the program operation. See the Program/Erase Operations table in “AC Characteristics” for parameters, and to Figure 17 for timing diagrams. Am29PL320D June 13, 2005 START Write Program Command Sequence Data Poll from System Embedded Program algorithm in progress Verify Data? No Yes Increment Address No Last Address? Yes Programming Completed Note: See Table 13 for program command sequence Figure 2. June 13, 2005 Program Operation Am29PL320D 21 Chip Erase Command Sequence Chip erase is a six bus cycle operation. The chip erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. Two additional unlock write cycles are then followed by the chip erase command, which in turn invokes the Embedded Erase algorithm. The device does not require the system to preprogram prior to erase. The Embedded Erase algorithm automatically preprograms and verifies the entire memory for an all zero data pattern prior to electrical erase. The system is not required to provide any controls or timings during these operations. Table 13 shows the address and data requirements for the chip erase command sequence. this time to ensure all commands are accepted. The interrupts can be re-enabled after the last Sector Erase command is written. If the time between additional sector erase commands can be assumed to be less than 50 µs, the system need not monitor DQ3. Any command other than Sector Erase or Erase Suspend during the time-out period resets the device to reading array data. The system must rewrite the command sequence and any additional sector addresses and commands. The system can monitor DQ3 to determine if the sector erase timer has timed out. (See the “DQ3: Sector Erase Timer” section.) The time-out begins from the rising edge of the final WE# pulse in the command sequence. Any commands written to the chip during the Embedded Erase algorithm are ignored. The Chip Erase command sequence should be reinitiated once the device has returned to reading array data, to ensure data integrity. Once the sector erase operation has begun, only the Erase Suspend command is valid. All other commands are ignored. The Sector Erase command sequence should be reinitiated once the device has returned to reading array data, to ensure data integrity. The system can determine the status of the erase operation by using DQ7, DQ6, or DQ2. See “Write Operation Status” for information on these status bits. When the Embedded Erase algorithm is complete, the device returns to reading array data and addresses are no longer latched. When the Embedded Erase algorithm is complete, the device returns to reading array data and addresses are no longer latched. The system can determine the status of the erase operation by using DQ7, DQ6, or DQ2. (Refer to “Write Operation Status” for information on these status bits.) Figure 3 illustrates the algorithm for the erase operation. See the Program/Erase Operations tables in “AC Characteristics” for parameters, and to Figure 18 for timing diagrams. Figure 3 illustrates the algorithm for the erase operation. Refer to the Program/Erase Operations tables in the “AC Characteristics” section for parameters, and to Figure 18 for timing diagrams. Sector Erase Command Sequence Erase Suspend/Erase Resume Commands Sector erase is a six bus cycle operation. The sector erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. Two additional unlock write cycles are then followed by the address of the sector to be erased, and the sector erase command. Table 13 shows the address and data requirements for the sector erase command sequence. The Erase Suspend command allows the system to interrupt a sector erase operation and then read data from, or program data to, any sector not selected for erasure. This command is valid only during the sector erase operation, including the 50 µs time-out period during the sector erase command sequence. The Erase Suspend command is ignored if written during the chip erase operation or Embedded Program algorithm. Writing the Erase Suspend command during the Sector Erase time-out immediately terminates the time-out period and suspends the erase operation. Addresses are “don’t-cares” when writing the Erase Suspend command. The device does not require the system to preprogram the memory prior to erase. The Embedded Erase algorithm automatically programs and verifies the sector for an all zero data pattern prior to electrical erase. The system is not required to provide any controls or timings during these operations. After the command sequence is written, a sector erase time-out of 50 µs begins. During the time-out period, additional sector addresses and sector erase commands may be written. Loading the sector erase buffer may be done in any sequence, and the number of sectors may be from one sector to all sectors. The time between these additional cycles must be less than 50 µs, otherwise the last address and command might not be accepted, and erasure may begin. It is recommended that processor interrupts be disabled during 22 When the Erase Suspend command is written during a sector erase operation, the device requires a maximum of 20 µs to suspend the erase operation. However, when the Erase Suspend command is written during the sector erase time-out, the device immediately terminates the time-out period and suspends the erase operation. After the erase operation has been suspended, the system can read array data from or program data to any sector not selected for erasure. (The device “erase Am29PL320D June 13, 2005 suspends” all sectors selected for erasure.) Note that unlock bypass programming is not allowed when the device is erase-suspended. Another Erase Suspend command can be written after the device has resumed erasing. Reading at any address within erase-suspended sectors produces status data on DQ7–DQ0. The system can use DQ7, or DQ6 and DQ2 together, to determine if a sector is actively erasing or is erase-suspended. See “Write Operation Status” for information on these status bits. START Write Erase Command Sequence After an erase-suspended program operation is complete, the system can once again read array data within non-suspended sectors. The system can determine the status of the program operation using the DQ7 or DQ6 status bits, just as in the standard program operation. See “Write Operation Status” for more information. Data Poll from System The system may also write the autoselect command sequence when the device is in the Erase Suspend mode. The device allows reading autoselect codes even at addresses within erasing sectors, since the codes are not stored in the memory array. When the device exits the autoselect mode, the device reverts to the Erase Suspend mode, and is ready for another valid operation. See “Autoselect Command Sequence” for more information. The system must write the Erase Resume command (address bits are “don’t care”) to exit the erase suspend mode and continue the sector erase operation. Further writes of the Resume command are ignored. No Data = FFh? Yes Erasure Completed Notes: 1. See Table 13 for erase command sequence. 2. See “DQ3: Sector Erase Timer” for more information. Figure 3. June 13, 2005 Embedded Erase algorithm in progress Am29PL320D Erase Operation 23 Temporary Sector Unprotect Enable/Disable Command Sequence The temporary unprotect command sequence is a four-bus-cycle operation. The sequence is initiated by writing two unlock write cycles. A third write cycle sets up the command. The fourth and final write cycle enables or disables the temporary unprotect feature. If the temporary unprotect feature is enabled, all sectors are temporarily unprotected. The system may program or erase data as needed. When the system writes the temporary unprotect disable command sequence, all sectors return to their previous protected or unprotected settings. See Table 13 and Figure 4 for more information. START Write Temporary Sector Unprotect Enable Command Sequence (Note 1) Perform Erase or Program Operations Write Temporary Sector Unprotect Disable Command Sequence Procedure Complete (Note 2) Notes: 1. All protected sectors are unprotected. If WP# = VIL, the first or last 64 KByte sector will remain protected. 2. All previously protected sectors are protected once again. Figure 4. 24 Am29PL320D Temporary Sector Unprotect Algorithm June 13, 2005 Command Definitions Command Sequence (Note 1) Cycles Table 13. Command Definitions (Double Word Mode) First Addr Data Second Addr Data Bus Cycles (Notes 2–5) Third Fourth Addr Data Addr Data 1 RA Reset (Note 7) 1 XXX F0 Manufacturer ID 4 555 AA 2AA 55 555 90 00 01 Device ID (Note 9) 6 555 AA 2AA 55 555 90 01 227E 90 (BA) X03 (Note 10) 90 (SA) X02 (Note 11) Autoselect (Note 8) Read (Note 6) Fifth Addr Data Addr Sixth Data RD 0E 2203 0F 2200 2201 AA 2AA 55 555 10 AA 2AA 55 SA 30 SecSi™ Sector Factory Protect (Note 10) 4 555 AA 2AA 55 (BA) 555 Sector Protect Verify (Note 11) 4 555 AA 2AA 55 555 Enter SecSi Sector Region 3 555 AA 2AA 55 555 88 Exit SecSi Sector Region 4 555 AA 2AA 55 555 90 XXX 00 CFI Query (Note 12) 1 55 98 Program 4 555 AA 2AA 55 555 A0 PA PD Unlock Bypass 3 555 AA 2AA 55 555 20 Unlock Bypass Program (Note 13) 2 XXX A0 PA PD Unlock Bypass Reset (Note 14) 2 XXX 90 XXX 00 Chip Erase 6 555 AA 2AA 55 555 80 555 Sector Erase 6 555 AA 2AA 55 555 80 555 Erase Suspend (Note 15) 1 XXX B0 Erase Resume (Note 16) 1 XXX 30 Temporary Sector Unprotect Enable 4 555 AA 2AA 55 555 E0 XXX 01 Temporary Sector Unprotect Disable 4 555 AA 2AA 55 555 E0 XXX 00 Legend: X = Don’t care RA = Address of the memory location to be read. RD = Data read from location RA during read operation. PA = Address of the memory location to be programmed. Addresses latch on the falling edge of the WE# or CE# pulse, whichever happens later. PD = Data to be programmed at location PA. Data latches on the rising edge of WE# or CE# pulse, whichever happens first. SA = Address of the sector to be verified (in autoselect mode) or erased. Address bits A19–A12 uniquely select any sector. Notes: 11. The data is 00h for an unprotected sector and 01h for a protected sector. See “Autoselect Command Sequence” for more information. 12. Command is valid when device is ready to read array data or when device is in autoselect mode. 13. The Unlock Bypass command is required prior to the Unlock Bypass Program command. 14. The Unlock Bypass Reset command is required to return to reading array data when the device is in the unlock bypass mode. 15. The system may read and program in non-erasing sectors, or enter the autoselect mode, when in the Erase Suspend mode. The Erase Suspend command is valid only during a sector erase operation. 16. The Erase Resume command is valid only during the Erase Suspend mode. 1. 2. 3. See Table 1 for description of bus operations. All values are in hexadecimal. Except for the read cycle and the fourth cycle of the autoselect command sequence, all bus cycles are write cycles. 4. Data bits DQ31–DQ8 are don’t cares for unlock and command cycles. 5. Address bits A19–A11 are don’t cares for unlock and command cycles, unless SA or PA required. 6. No unlock or command cycles required when reading array data. 7. The Reset command is required to return to reading array data when device is in the autoselect mode, or if DQ5 goes high (while the device is providing status data). 8. The fourth cycle of the autoselect command sequence is a read cycle. 9. DQ31–DQ16 output 2222h for device ID reads. The device ID must be read across the fourth, fifth, and sixth cycles. The sixth cycle specifies 22222200h for bottom boot devices and 22222201h for top boot devices. 10. The data is 80h for factory locked and 00h for not factory locked. June 13, 2005 Am29PL320D 25 Command Sequence (Note 1) Cycles Table 14. Command Definitions (Word Mode) Bus Cycles (Notes 2–5) First Addr Data Second Addr Data Third Fourth Addr Data Addr Data 1 RA Reset (Note 7) 1 XXX F0 Manufacturer ID 4 AAA AA 555 55 AAA 90 00 01 Device ID (Note 9) 6 AAA AA 555 55 AAA 90 02 227E 90 (BA) X06 (Note 10) 90 (SA) X04 (Note 11) Autoselect (Note 8) Read (Note 6) Fifth Sixth Addr Data Addr Data RD SecSi™ Sector Factory Protect (Note 10) 4 AAA AA 555 55 (BA) AAA Sector Protect Verify (Note 11) 4 AAA AA 555 55 AAA Enter SecSi Sector Region 3 AAA AA 555 55 AAA 88 Exit SecSi Sector Region 4 AAA AA 555 55 AAA 90 XXX 00 CFI Query (Note 12) 1 55 98 PA PD 1C 2203 1E 2200 2201 Program 4 AAA AA 555 55 AAA A0 Unlock Bypass 3 AAA AA 555 55 AAA 20 Unlock Bypass Program (Note 13) 2 XXX A0 PA PD Unlock Bypass Reset (Note 14) 2 XXX 90 XXX 00 Chip Erase 6 AAA AA 555 55 AAA 80 AAA AA 555 55 AAA 10 Sector Erase 6 AAA AA 555 55 AAA 80 AAA AA 555 55 SA 30 Erase Suspend (Note 15) 1 XXX B0 Erase Resume (Note 16) 1 XXX 30 Temporary Sector Unprotect Enable 4 AAA AA 555 55 AAA E0 XXX 01 Temporary Sector Unprotect Disable 4 AAA AA 555 55 AAA E0 XXX 00 Legend: X = Don’t care RA = Address of the memory location to be read. RD = Data read from location RA during read operation. PA = Address of the memory location to be programmed. Addresses latch on the falling edge of the WE# or CE# pulse, whichever happens later. PD = Data to be programmed at location PA. Data latches on the rising edge of WE# or CE# pulse, whichever happens first. SA = Address of the sector to be verified (in autoselect mode) or erased. Address bits A19–A12 uniquely select any sector. Notes: 10. The data is 80h for factory locked and 00h for not factory locked. 11. The data is 00h for an unprotected sector and 01h for a protected sector. See “Autoselect Command Sequence” for more information. 12. Command is valid when device is ready to read array data or when device is in autoselect mode. 13. The Unlock Bypass command is required prior to the Unlock Bypass Program command. 14. The Unlock Bypass Reset command is required to return to reading array data when the device is in the unlock bypass mode. 15. The system may read and program in non-erasing sectors, or enter the autoselect mode, when in the Erase Suspend mode. The Erase Suspend command is valid only during a sector erase operation. 16. The Erase Resume command is valid only during the Erase Suspend mode. 1. 2. 3. 4. 5. 6. 7. 8. 9. 26 See Table 1 for description of bus operations. All values are in hexadecimal. Except for the read cycle and the fourth cycle of the autoselect command sequence, all bus cycles are write cycles. Data bits DQ31–DQ8 are don’t cares for unlock and command cycles. Address bits A19–A11 are don’t cares for unlock and command cycles, unless SA or PA required. No unlock or command cycles required when reading array data. The Reset command is required to return to reading array data when device is in the autoselect mode, or if DQ5 goes high (while the device is providing status data). The fourth cycle of the autoselect command sequence is a read cycle. The device ID must be read across the fourth, fifth, and sixth cycles. The sixth cycle specifies 2200h for bottom boot devices and 2201h for top boot devices. Am29PL320D June 13, 2005 WRITE OPERATION STATUS The device provides several bits to determine the status of a write operation: DQ2, DQ3, DQ5, DQ6, and DQ7. Table 15 and the following subsections describe the functions of these bits. DQ7 and DQ6 each offer a method for determining whether a program or erase operation is complete or in progress. These three bits are discussed first. DQ6 while Output Enable (OE#) is asserted low. See Figure 18 in the “AC Characteristics” section. Table 15 shows the outputs for Data# Polling on DQ7. Figure 5 shows the Data# Polling algorithm. START DQ7: Data# Polling The Data# Polling bit, DQ7, indicates to the host system whether an Embedded Algorithm is in progress or completed, or whether the device is in Erase Suspend. Data# Polling is valid after the rising edge of the final WE# pulse in the program or erase command sequence. During the Embedded Program algorithm, the device outputs on DQ7 the complement of the datum programmed to DQ7. This DQ7 status also applies to programming during Erase Suspend. When the Embedded Program algorithm is complete, the device outputs the datum programmed to DQ7. The system must provide the program address to read valid status information on DQ7. If a program address falls within a protected sector, Data# Polling on DQ7 is active for approximately 1 µs, then the device returns to reading array data. Read DQ7–DQ0 Addr = VA DQ7 = Data? No No When the system detects DQ7 has changed from the complement to true data, it can read valid data at DQ7–DQ0 on the following read cycles. This is because DQ7 may change asynchronously with DQ0– DQ5 = 1? Yes During the Embedded Erase algorithm, Data# Polling produces a “0” on DQ7. When the Embedded Erase algorithm is complete, or if the device enters the Erase Suspend mode, Data# Polling produces a “1” on DQ7. This is analogous to the complement/true datum output described for the Embedded Program algorithm: the erase function changes all the bits in a sector to “1”; prior to this, the device outputs the “complement,” or “0.” The system must provide an address within any of the sectors selected for erasure to read valid status information on DQ7. After an erase command sequence is written, if all sectors selected for erasing are protected, Data# Polling on DQ7 is active for approximately 100 µs, then the device returns to reading array data. If not all selected sectors are protected, the Embedded Erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. Read DQ7–DQ0 Addr = VA DQ7 = Data? Yes No FAIL PASS Notes: 1. VA = Valid address for programming. During a sector erase operation, a valid address is an address within any sector selected for erasure. During chip erase, a valid address is any non-protected sector address. 2. DQ7 should be rechecked even if DQ5 = “1” because DQ7 may change simultaneously with DQ5 Figure 5. June 13, 2005 Yes Am29PL320D Data# Polling Algorithm 27 DQ6: Toggle Bit Toggle Bit I on DQ6 indicates whether an Embedded Program or Erase algorithm is in progress or complete, or whether the device has entered the Erase Suspend mode. Toggle Bit I may be read at any address, and is valid after the rising edge of the final WE# pulse in the command sequence (prior to the program or erase operation), and during the sector erase time-out. During an Embedded Program or Erase algorithm operation, successive read cycles to any address cause DQ6 to toggle. (The system may use either OE# or CE# to control the read cycles.) When the operation is complete, DQ6 stops toggling. After an erase command sequence is written, if all sectors selected for erasing are protected, DQ6 toggles for approximately 100 µs, then returns to reading array data. If not all selected sectors are protected, the Embedded Erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. The system can use DQ6 and DQ2 together to determine whether a sector is actively erasing or is erasesuspended. When the device is actively erasing (that is, the Embedded Erase algorithm is in progress), DQ6 toggles. When the device enters the Erase Suspend mode, DQ6 stops toggling. However, the system must also use DQ2 to determine which sectors are erasing or erase-suspended. Alternatively, the system can use DQ7 (see the subsection on “DQ7: Data# Polling”). If a program address falls within a protected sector, DQ6 toggles for approximately 1 µs after the program command sequence is written, then returns to reading array data. DQ6 also toggles during the erase-suspend-program mode, and stops toggling once the Embedded Program algorithm is complete. Table 15 shows the outputs for Toggle Bit I on DQ6. Figure 6 shows the toggle bit algorithm in flowchart form, and the section “Reading Toggle Bits DQ6/DQ2” explains the algorithm. Figure 20 in the “AC Characteristics” section shows the toggle bit timing diagrams. Figure 21 shows the differences between DQ2 and DQ6 in graphical form. See also the subsection on “DQ2: Toggle Bit”. DQ2: Toggle Bit The “Toggle Bit II” on DQ2, when used with DQ6, indicates whether a particular sector is actively erasing (that is, the Embedded Erase algorithm is in progress), or whether that sector is erase-suspended. Toggle Bit II is valid after the rising edge of the final WE# pulse in the command sequence. 28 DQ2 toggles when the system reads at addresses within those sectors that have been selected for erasure. (The system may use either OE# or CE# to control the read cycles.) But DQ2 cannot distinguish whether the sector is actively erasing or is erase-suspended. DQ6, by comparison, indicates whether the device is actively erasing, or is in Erase Suspend, but cannot distinguish which sectors are selected for erasure. Thus, both status bits are required for sector and mode information. Refer to Table 15 to compare outputs for DQ2 and DQ6. Figure 6 shows the toggle bit algorithm in flowchart form, and the section “Reading Toggle Bits DQ6/DQ2” explains the algorithm. See also the DQ6: Toggle Bit subsection. Figure 20 shows the toggle bit timing diagram. Figure 21 shows the differences between DQ2 and DQ6 in graphical form. Reading Toggle Bits DQ6/DQ2 Refer to Figure 6 for the following discussion. Whenever the system initially begins reading toggle bit status, it must read DQ7–DQ0 at least twice in a row to determine whether a toggle bit is toggling. Typically, the system would note and store the value of the toggle bit after the first read. After the second read, the system would compare the new value of the toggle bit with the first. If the toggle bit is not toggling, the device has completed the program or erase operation. The system can read array data on DQ7–DQ0 on the following read cycle. However, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the system also should note whether the value of DQ5 is high (see the section on DQ5). If it is, the system should then determine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as DQ5 went high. If the toggle bit is no longer toggling, the device has successfully completed the program or erase operation. If it is still toggling, the device did not complete the operation successfully, and the system must write the reset command to return to reading array data. The remaining scenario is that the system initially determines that the toggle bit is toggling and DQ5 has not gone high. The system may continue to monitor the toggle bit and DQ5 through successive read cycles, determining the status as described in the previous paragraph. Alternatively, it may choose to perform other system tasks. In this case, the system must start at the beginning of the algorithm when it returns to determine the status of the operation (top of Figure 6). DQ5: Exceeded Timing Limits DQ5 indicates whether the program or erase time has exceeded a specified internal pulse count limit. Under these conditions DQ5 produces a “1.” This is a failure Am29PL320D June 13, 2005 condition that indicates the program or erase cycle was not successfully completed. The DQ5 failure condition may appear if the system tries to program a “1” to a location that is previously programmed to “0.” Only an erase operation can change a “0” back to a “1.” Under this condition, the device halts the operation, and when the operation has exceeded the timing limits, DQ5 produces a “1.” START Read DQ7–DQ0 Read DQ7–DQ0 Under both these conditions, the system must issue the reset command to return the device to reading array data. (Note 1) DQ3: Sector Erase Timer Toggle Bit = Toggle? After writing a sector erase command sequence, the system may read DQ3 to determine whether or not an erase operation has begun. (The sector erase timer does not apply to the chip erase command.) If additional sectors are selected for erasure, the entire timeout also applies after each additional sector erase command. When the time-out is complete, DQ3 switches from “0” to “1.” The system may ignore DQ3 if the system can guarantee that the time between additional sector erase commands will always be less than 50 μs. See also the “Write Operation Status” section. No Yes No DQ5 = 1? Yes Read DQ7–DQ0 Twice Toggle Bit = Toggle? (Notes 1, 2) No Yes Program/Erase Operation Not Complete, Write Reset Command Program/Erase Operation Complete After the sector erase command sequence is written, the system should read the status on DQ7 (Data# Polling) or DQ6 (Toggle Bit I) to ensure the device has accepted the command sequence, and then read DQ3. If DQ3 is “1”, the internally controlled erase cycle has begun; all further commands (other than Erase Suspend) are ignored until the erase operation is complete. If DQ3 is “0”, the device will accept additional sector erase commands. To ensure the command has been accepted, the system software should check the status of DQ3 prior to and following each subsequent sector erase command. If DQ3 is high on the second status check, the last command might not have been accepted. Table 15 shows the outputs for DQ3. Notes: 1. Read toggle bit twice to determine whether or not it is toggling. See text. 2. Recheck toggle bit because it may stop toggling as DQ5 changes to “1”. See text. Figure 6. June 13, 2005 Toggle Bit Algorithm Am29PL320D 29 Table 15. Operation Standard Mode Erase Suspend Mode Embedded Program Algorithm Write Operation Status DQ7 (Note 2) DQ6 DQ5 (Note 1) DQ3 DQ2 (Note 2) DQ7# Toggle 0 N/A No toggle Embedded Erase Algorithm 0 Toggle 0 1 Toggle Reading within Erase Suspended Sector 1 No toggle 0 N/A Toggle Reading within Non-Erase Suspended Sector Data Data Data Data Data Erase-Suspend-Program DQ7# Toggle 0 N/A N/A Notes: 1. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits. See “DQ5: Exceeded Timing Limits” for more information. 2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details. 30 Am29PL320D June 13, 2005 ABSOLUTE MAXIMUM RATINGS Storage Temperature Plastic Packages . . . . . . . . . . . . . . . -65°C to +150°C Ambient Temperature with Power Applied. . . . . . . . . . . . . . -65°C to +125°C 20 ns 20 ns +0.8 V –0.5 V Voltage with Respect to Ground VCC (Note 1) . . . . . . . . . . . . . . . . . .–0.5 V to +4.0 V –2.0 V A9, OE#, ACC (Note 2) . . . . . . . . –0.5 V to +13.0 V 20 ns All other inputs (Note 1) . . . . . . . . . –0.5 V to +5.5 V Output Short Circuit Current (Note 3) . . . . . . 200 mA Notes: 1. Minimum DC voltage on input or I/Os is –0.5 V. During voltage transitions, voltages on inputs or I/Os may overshoot VSS to –2.0 V for periods of up to 20 ns. Maximum DC voltage on output and I/Os is VCC + 0.5 V. During voltage transitions I/Os may overshoot to VCC + 2.0 V for periods up to 20 ns. 2. Minimum DC input voltage on inputs A9, OE#, and ACC is –0.5 V. During voltage transitions, A9 and OE# may overshoot VSS to -2.0 V for periods of up to 20 ns. Maximum DC input voltage on input A9, OE#, and ACC is +13.0 V which may overshoot to 14.0 V for periods up to 20 ns. 3. No more than one output may be shorted to ground at a time. Duration of the short circuit should not be greater than one second. Figure 7. Maximum Negative Overshoot Waveform 20 ns VCC +2.0 V VCC +0.5 V 2.0 V 20 ns Figure 8. 20 ns Maximum Positive Overshoot Waveform 4. Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this data sheet is not implied. Exposure of the device to absolute maximum rating conditions for extended periods may affect device reliability. OPERATING RANGES Commercial (C) Devices Ambient Temperature (TA) . . . . . . . . . . . 0°C to +70°C Industrial (I) Devices Ambient Temperature (TA) . . . . . . . . . –40°C to +85°C VCC Supply Voltages VCC for regulated voltage range. . . . . . . 3.0 V to 3.6 V VCC for full voltage range . . . . . . . . . . . . 2.7 V to 3.6 V Operating ranges define those limits between which the functionality of the device is guaranteed. June 13, 2005 Am29PL320D 31 DC CHARACTERISTICS CMOS Compatible Parameter Symbol Description Test Conditions Min ILI Input Load Current VIN = VSS to VCC, VCC = VCC max ILIT A9 Input Load Current VCC = VCC max; A9 = 12.5 V ILO Output Leakage Current VOUT = VSS to VCC, VCC = VCC max ICC1 VCC Active Inter-Page Read Current (Notes 1, 2) CE# = VIL, OE# = VIH ICC2 VCC Active Write Current (Notes 2, 4) ICC3 Typ Max Unit ±1.0 µA 35 µA ±1.0 µA 1 MHz 4 50 mA 10 MHz 40 80 mA CE# = VIL, OE# = VIH 25 80 mA VCC Standby Current (Note 2) CE# = VCC±0.3 V 2 5 µA Automatic Sleep Mode (Notes 2, 3, 6) VIH = VCC ± 0.3 V; VIL = VSS ± 0.3 V OE# = VIH 1 5 ICC4 OE# = VIL 2 20 VCC Active Intra-Page Read Current (Note 2) 10 MHz 15 50 mA ICC5 CE# = VIL, OE# = VIH 33 MHz 50 80 mA VIL Input Low Voltage –0.5 0.8 V VIH Input High Voltage 2.0 VCC + 0.3 V VHH Voltage for Accelerated Programming on ACC 11.5 12.5 V VID Voltage for Autoselect and Temporary Sector Unprotect VCC = 3.0 ± 0.3 V 11.5 12.5 V VOL Output Low Voltage IOL = 4.0 mA, VCC = VCC min 0.45 V VOH1 Output High Voltage VOH2 VLKO µA IOH = –2.0 mA, VCC = VCC min 0.85 x VCC IOH = –100 µA, VCC = VCC min VCC–0.4 Low VCC Lock-Out Voltage (Note 6) 2.3 V 2.5 V Notes: 1. The ICC current listed is typically less than 4 mA/MHz, with OE# at VIH. Typical VCC is 3.0 V. 2. Maximum ICC specifications are tested with VCC = VCCmax. 3. The Automatic Sleep Mode current is dependent on the state of OE#. 4. ICC active while Embedded Erase or Embedded Program is in progress. 5. Automatic sleep mode enables the low power mode when addresses remain stable for tACC + 30 ns. 6. Not 100% tested. 32 Am29PL320D June 13, 2005 DC CHARACTERISTICS (Continued) Zero Power Flash Supply Current in mA 25 20 15 10 5 0 0 500 1000 1500 2000 2500 3000 3500 4000 Time in ns Note: Addresses are switching at 1 MHz. Figure 9. ICC1 Current vs. Time (Showing Active and Automatic Sleep Currents) 20 3.6 V Supply Current in mA 16 2.7 V 12 8 4 0 1 2 3 4 5 Frequency in MHz Note: T = 25 °C Figure 10. June 13, 2005 Typical ICC1 vs. Frequency Am29PL320D 33 TEST CONDITIONS Table 16. Test Specifications 3.3 V Test Condition 2.7 kΩ Device Under Test CL 6.2 kΩ All speeds Output Load 1 TTL gate Output Load Capacitance, CL (including jig capacitance) 30 pF Input Rise and Fall Times 5 ns 0.0–3.0 V Input timing measurement reference levels 1.5 V Output timing measurement reference levels 1.5 V Input Pulse Levels Note: Diodes are IN3064 or equivalent Figure 11. Unit Test Setup KEY TO SWITCHING WAVEFORMS WAVEFORM INPUTS OUTPUTS Steady Changing from H to L Changing from L to H 3.0 V Input Don’t Care, Any Change Permitted Changing, State Unknown Does Not Apply Center Line is High Impedance State (High Z) 1.5 V Measurement Level 1.5 V Output 0.0 V Figure 12. 34 Input Waveforms and Measurement Levels Am29PL320D June 13, 2005 AC CHARACTERISTICS Read Operations Parameter Speed Options JEDEC Std Description tAVAV tRC Read Cycle Time tAVQV tACC Address Access Time tELQV tCE Chip Enable to Output Delay tPACC Test Setup 60R 70R, 70 90 Unit Min 60 70 90 ns CE#=VIL, OE#=VIL Max 60 70 90 ns OE#=VIL Max 60 70 90 ns Page Access Time Max 20 25 35 ns 20 25 35 ns tGLQV tOE Output Enable to Output Valid Max tEHQZ tDF Chip Enable to Output High Z Max 16 ns tGHQZ tDF Output Enable to Output High Z Max 16 ns Read 0 ns Toggle and Data# Polling 10 ns 0 ns tAXQX tOEH Output Enable Hold Time (Note 1) tOH Output Hold Time From Addresses, OE# or CE#, Whichever Occurs First (Note 1) Min Notes: 1. Not 100% tested. 2. See Figure 11 and Table 16 for test specifications. June 13, 2005 Am29PL320D 35 AC CHARACTERISTICS tRC Addresses Stable Addresses tACC CE# tDF tOE OE# tOEH WE# tCE tOH HIGH Z HIGH Z Output Valid Outputs 0V Figure 13. Conventional Read Operations Timings Same Page A19-A3 A2-A-1 Aa Ab tPACC tACC Data Bus Qa Ad Ac tPACC Qb tPACC Qc Qd CE# Note: Double Word Configuration: Toggle A2, A1, A0. Word Configuration: Toggle A2, A1, A0, A-1. Figure 14. 36 Page Read Timings Am29PL320D June 13, 2005 AC CHARACTERISTICS Double Word/Word Configuration (WORD#) Parameter JEDEC Std Speed Options Description 60R 70R, 70 90 Unit tELFL/tELFH CE# to WORD# Switching Low or High Max 5 ns tFLQZ WORD# Switching Low to Output HIGH Z Max 16 ns tFHQV WORD# Switching High to Output Active Min 60 70 90 ns CE# OE# WORD# WORD# Switching from double word to word mode tELFL Data Output (DQ15–DQ0) Data Output (DQ30–DQ0) DQ30–DQ0 Address Input DQ31 Output DQ31/A-1 tFLQZ tELFH WORD# WORD# Switching from word to double word mode Data Output (DQ15–DQ0) DQ30–DQ0 Address Input DQ31/A-1 Data Output (DQ30–DQ0) DQ15 Output tFHQV Figure 15. WORD# Timings for Read Operations CE# The falling edge of the last WE# signal WE# WORD# tSET (tAS) tHOLD (tAH) Note: Refer to the Erase/Program Operations table for tAS and tAH specifications. Figure 16. June 13, 2005 WORD# Timings for Write Operations Am29PL320D 37 AC CHARACTERISTICS Program/Erase Operations Parameter Speed Options Unit JEDEC Std Description 60R 70R, 70 90 tAVAV tWC Write Cycle Time (Note 1) Min 60 70 90 tAVWL tAS Address Setup Time Min tWLAX tAH Address Hold Time Min 35 45 45 ns tDVWH tDS Data Setup Time Min 30 35 45 ns tWHDX tDH Data Hold Time Min 0 ns tOES Output Enable Setup Time Min 0 ns Read Recovery Time Before Write (OE# High to WE# Low) Min 0 ns 0 ns ns tGHWL tGHWL tELWL tCS CE# Setup Time Min 0 ns tWHEH tCH CE# Hold Time Min 0 ns tWLWH tWP Write Pulse Width Min 35 35 35 ns tWHWL tWPH Write Pulse Width High Min 25 30 30 ns tWHWH1 tWHWH1 Programming Operation (Note 2) tWHWH2 tWHWH2 tVCS Word Typ 14.3 µs Double Word Typ 18.3 Sector Erase Operation (Note 2) Typ 5 sec VCC Setup Time (Note 1) Min 50 µs Notes: 1. Not 100% tested. 2. See the “Erase and Programming Performance” section for more information. 38 Am29PL320D June 13, 2005 AC CHARACTERISTICS Program Command Sequence (last two cycles) tAS tWC Addresses 555h Read Status Data (last two cycles) PA PA PA tAH CE# tCH tGHWL OE# tWHWH1 tWP WE# tWPH tCS tDS tDH A0h Data PD Status DOUT tVCS VCC Notes: 1. PA = program address, PD = program data, DOUT is the true data at the program address. 2. Illustration shows device in word mode. Figure 17. June 13, 2005 Program Operation Timings Am29PL320D 39 AC CHARACTERISTICS Erase Command Sequence (last two cycles) tAS tWC 2AAh Addresses Read Status Data VA SA VA 555h for chip erase tAH CE# tGHWL tCH OE# tWP WE# tWPH tCS tWHWH2 tDS tDH Data 55h In Progress 30h Complete 10 for Chip Erase tVCS VCC Notes: 1. SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see “Write Operation Status”). 2. Illustration shows device in word mode. Figure 18. AC Waveforms for Chip/Sector Erase Operations tRC Addresses VA VA VA tACC tCE CE# tCH tOE OE# tOEH tDF WE# tOH High Z DQ7 Complement Complement DQ6–DQ0 Status Data Status Data True Valid Data High Z True Valid Data Note: VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data read cycle Figure 19. 40 Data# Polling Timings (During Embedded Algorithms) Am29PL320D June 13, 2005 AC CHARACTERISTICS tRC Addresses VA VA VA VA tACC tCE CE# tCH tOE OE# tOEH tDF WE# tOH DQ6/DQ2 High Z Valid Status Valid Status (first read) (second read) Valid Status Valid Data (stops toggling) Note: VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status read cycle, and array data read cycle Figure 20. Enter Embedded Erasing WE# Erase Suspend Erase Toggle Bit Timings (During Embedded Algorithms) Enter Erase Suspend Program Erase Suspend Read Erase Suspend Program Erase Resume Erase Suspend Read Erase Erase Complete DQ6 DQ2 Note: The system may use CE# or OE# to toggle DQ2 and DQ6. DQ2 toggles only when read at an address within an erase-suspended sector. Figure 21. DQ2 vs. DQ6 for Erase and Erase Suspend Operations June 13, 2005 Am29PL320D 41 AC CHARACTERISTICS Alternate CE# Controlled Erase/Program Operations Parameter Speed Options JEDEC Std Description tAVAV tWC Write Cycle Time (Note 1) Min tAVEL tAS Address Setup Time Min tELAX tAH Address Hold Time Min 35 45 45 ns tDVEH tDS Data Setup Time Min 30 35 45 ns tEHDX tDH Data Hold Time Min 0 ns tOES Output Enable Setup Time Min 0 ns tGHEL tGHEL Read Recovery Time Before Write (OE# High to WE# Low) Min 0 ns tWLEL tWS WE# Setup Time Min 0 ns tEHWH tWH WE# Hold Time Min 0 ns tELEH tCP CE# Pulse Width Min tEHEL tCPH CE# Pulse Width High Min 30 Word Typ 14.3 Double Word Typ 18.3 Typ 5 tWHWH1 tWHWH1 Programming Operation (Note 2) tWHWH2 tWHWH2 Sector Erase Operation (Note 2) 60R 70R, 70 90 Unit 60 70 90 ns 0 25 30 ns 35 ns ns µs sec Notes: 1. Not 100% tested. 2. See the “Erase and Programming Performance” section for more information. 42 Am29PL320D June 13, 2005 AC CHARACTERISTICS PA for program SA for sector erase 555 for chip erase 555 for program 2AA for erase Data# Polling Addresses PA tWC tAS tAH tWH WE# tGHEL OE# tWHWH1 or 2 tCP CE# tWS tCPH tDS tDH DQ7# Data A0 for program 55 for erase DOUT PD for program 30 for sector erase 10 for chip erase Notes: 1. PA = program address, PD = program data, DQ7# = complement of the data written to the device, DOUT = data written to the device. 2. Figure indicates the last two bus cycles of the command sequence. 3. Word mode address used as an example. Figure 22. June 13, 2005 Alternate CE# Controlled Write Operation Timings Am29PL320D 43 ERASE AND PROGRAMMING PERFORMANCE Typ (Note 1) Max (Note 2) Unit 2 60 s Sector Erase Time, 8 and 16 KByte sector 0.5 60 Chip Erase Time 33.5 Word Programming Time 14.3 300 µs Double Word Programming Time 18.3 360 µs Word Mode 28 84 s Double Word Mode 18 54 s Parameter Sector Erase Time, 96 and 128 KByte sector Chip Programming Time (Note 3) Comments Excludes 00h programming prior to erasure (Note 4) s Excludes system level overhead (Note 5) Notes: 1. Typical program and erase times assume the following conditions: 25°C, 3.0 V VCC, 1,000,000 cycles. Additionally, programming typicals assume checkerboard pattern. 2. Under worst case conditions of 90°C, VCC = 2.7 V, 1,000,000 cycles. 3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most words program faster than the maximum program times listed. 4. In the pre-programming step of the Embedded Erase algorithm, all words are programmed to 00h before erasure. 5. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See Table 13 for further information on command definitions. 6. The device has a minimum erase and program cycle endurance of 1,000,000 cycles. LATCHUP CHARACTERISTICS Description Min Max Input voltage with respect to VSS on all inputs except I/O inputs (including A9 and OE#) –1.0 V 12.5 V Input voltage with respect to VSS on all I/O inputs –1.0 V VCC + 1.0 V –100 mA +100 mA VCC Current Includes all inputs except VCC. Test conditions: VCC = 3.0 V, one input at a time. DATA RETENTION Parameter Test Conditions Min Unit 150°C 10 Years 125°C 20 Years Minimum Pattern Data Retention Time * For reference only. BSC is an ANSI standard for Basic Space Centering. BGA PACKAGE CAPACITANCE Parameter Symbol Parameter Description Test Setup Typ Max Unit CIN Input Capacitance VIN = 0 4.2 5.0 pF COUT Output Capacitance VOUT = 0 5.4 6.5 pF CIN2 Control Pin Capacitance VIN = 0 3.9 4.7 pF Notes: 1. Sampled, not 100% tested. 2. Test conditions TA = 25°C, f = 1.0 MHz. 44 Am29PL320D June 13, 2005 PHYSICAL DIMENSIONS FBF084—84-Ball Fine Pitch Ball Grid Array (FBGA) 11 x 12 mm Dwg. Rev. AB-01; 7/00 June 13, 2005 Am29PL320D 45 REVISION SUMMARY Revision A (March 7, 2001) Distinctive Characteristics Initial release. Clarified endurance specification from “write cycles” to “erase cycles.” Revision B (June 12, 2001) SecSi™ (Secured Silicon) Sector Flash Memory Region Global Added 70R speed option. Changed data sheet status from Advance Information to Preliminary. Added text and figure on SecSi Sector Protect Verify function. Command Definitions Modified first paragraph to indicate device behavior when incorrect data or commands are written. Distinctive Characteristics SecSi Sector: Added note to future compatibility. Power Consumption: Replaced stated maximum values with typical values. DC Characteristics General Description Changed VIL maximum specification. Changed V CC test condition for VID parameter. Added section on SecSi Sector. BGA Ball Capacitance SecSi™ (Secured Silicon) Sector Flash Memory Region Added table. Added note to indicate sector size and erase functionality for future devices. Revision C+1 (July 21, 2003) Common Flash Interface (CFI) Changed URL for CFI publications. DC Characteristics Added typical values for ICC1–ICC5 to table. Corrected VIN test condition specification to VCC. Figure 10, Typical ICC1 vs. Frequency Command Definitions Added the phrase “in the improper sequence” to cautionary text in first paragraph. Changed scale on Y-axis to 4 mA divisions. Erase and Programming Performance Revision B+1 (August 30, 2001) Autoselect Command Sequence Changed typical sector erase time and typical chip erase time. Added typical and maximum sector erase times pertaining to 8 and 16 Kword sectors. Modified section to point to appropriate tables for autoselect functions. Revision C+2 (October 2, 2003) Erase Suspend/Erase Resume Commands Accelerated Program Operation Modified text to “Note that unlock bypass programming is not allowed when the device is erase-suspended” in the third paragraph. Specified a voltage range for VHH. Table 13, Command Definitions Corrected the autoselect device ID command sequence. The device ID is read in cycles 4, 5, and 6 of a single command sequence, not as three separate command sequences as previously shown. Separated the word and double word command sequences into two tables for easier reference. DC Characteristics Added VHH parameter to table. Revision C (October 22, 2002) AC Characteristics - Double Word/Word Configuration (WORD#) diagram Modified all instances of DQ14 to DQ30, DQ7 to DQ15, and DQ15 to DQ31. Revision C+3 (June 13, 2005) Cover Page / Title Page Added Spansion EOL cover page and added EOL disclaimer to title page. Global Deleted preliminary status from data sheet. 46 Am29PL320D June 13, 2005 Trademarks Copyright © 2003 Advanced Micro Devices, Inc. All rights reserved. AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc. ExpressFlash is a trademark of Advanced Micro Devices, Inc. Product names used in this publication are for identification purposes only and may be trademarks of their respective companies. June 13, 2005 Am29PL320D 47