IDT ICS84427CMLF Crystal-to-lvds integrated frequency synthesizer/fanout buffer Datasheet

84427
Crystal-to-LVDS Integrated
Frequency Synthesizer/Fanout Buffer
DATASHEET
GENERAL DESCRIPTION
FEATURES
T h e 8 4 4 2 7 i s a C r y s t a l - t o - LV D S F r e q u e n c y
Synthesizer/Fanout Buffer. The output frequency can be
programmed using the frequency select pins. The low phase
noise characteristics of the 84427 make it an ideal clock source
for 10 Gigabit Ethernet, 10 Gigabit Fibre Channel, OC3 and
OC12 applications.
• Six LVDS outputs
• Crystal oscillator interface
• Output frequency range: 77.76MHz to 625MHz
• Crystal input frequency: 19.44MHz, 25MHz or 25.5MHz
• RMS phase jitter at 155.52MHz, using a 19.44MHz crystal
(12kHz to 20MHz): 3.4ps (typical)
Phase noise:
Offset
Noise Power
100Hz ..................-95 dBc/Hz
1kHz ................-110 dBc/Hz
10kHz ................-120 dBc/Hz
100kHz ................-121 dBc/Hz
FUNCTION TABLE
Output
Frequency
Inputs
F_XTAL
MR
F_SEL2
F_SEL1
F_SEL0
F_OUT
X
1
X
X
X
LOW
19.44MHz
0
1
0
0
77.76MHz
• 0°C to 70°C ambient operating temperature
19.44MHz
0
1
0
1
155.52MHz
• Available in lead-free RoHS-compliant package
19.44MHz
0
1
1
0
311.04MHz
• 3.3V supply voltage
19.44MHz
0
1
1
1
622.08MHz
25MHz
0
0
0
0
78.125MHz
25MHz
0
0
0
1
156.25MHz
25MHz
0
0
1
0
312.5 MHz
25MHz
0
0
1
1
625MHz
25.5MHz
0
0
0
1
159.375MHz
BLOCK DIAGRAM
PIN ASSIGNMENT
XTAL_IN
0
OSC
XTAL_OUT
1
Output
Divider
6
Q0:Q5
6
nQ0:nQ5
/
/
PLL
Feedback
Divider
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
Q4
nQ4
Q5
nQ5
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
VDD
F_SEL0
F_SEL1
MR
XTAL_IN
XTAL_OUT
F_SEL2
VDDA
VDD
PLL_SEL
GND
VDD
84427
F_SEL2
84427 REVISION B 5/6/15
MR
PLL_SEL
F_SEL1
F_SEL0
1
24-Lead, 300-MIL SOIC
7.5mm x 15.33mm x 2.3mm body package
M Package
Top View
©2015 Integrated Device Technology, Inc.
84427 DATA SHEET
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Description
1, 2
Q0, nQ0
Output
Differential output pair. LVDS interface levels.
3, 4
Q1, nQ1
Output
Differential output pair. LVDS interface levels.
5, 6
Q2, nQ2
Output
Differential output pair. LVDS interface levels.
7, 8
Q3, nQ3
Output
Differential output pair. LVDS interface levels.
9, 10
Q4, nQ4
Output
Differential output pair. LVDS interface levels.
11, 12
Q5, nQ5
Output
Differential output pair. LVDS interface levels.
13, 16, 24
VDD
Power
Core supply pins.
14
GND
15
PLL_SEL
Input
17
VDDA
Power
Input
Power supply ground.
18
F_SEL2
19,
20
XTAL_OUT,
XTAL_IN
Input
21
MR
Input
22
F_SEL1
Input
23
F_SEL0
Input
Pullup
Selects between the PLL and crystal inputs as the input to the dividers.
When HIGH, selects PLL. When LOW, selects XTAL_IN and XTAL_OUT.
LVCMOS / LVTTL interface levels.
Analog supply pin.
Pullup
Feedback frequency select pin. LVCMOS/LVTTL interface levels.
Crystal oscillator interface. XTAL_IN is the input,
XTAL_OUT is the output.
Active High Master Reset. When logic HIGH, the internal dividers are
reset causing the true outputs Qx to go low and the inverted outputs nQx
Pulldown
to go high. When logic LOW, the internal dividers and the outputs are
enabled. LVCMOS / LVTTL interface levels.
Pulldown Output frequency select pin. LVCMOS/LVTTL interface levels.
Pullup
Output frequency select pin. LVCMOS/LVTTL interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
CIN
Input Capacitance
4
pF
RPULLUP
Input Pullup Resistor
51
kΩ
RPULLDOWN
Input Pulldown Resistor
51
kΩ
CRYSTAL-TO-LVDS
INTEGRATED FREQUENCY SYNTHESIZER/FANOUT BUFFER
2
REVISION B 5/6/15
84427 DATA SHEET
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VDD
4.6V
Inputs, VI
-0.5V to VDD + 0.5V
Outputs, IO
Continuous Current
Surge Current
10mA
15mA
Package Thermal Impedance, θJA
50°C/W (0 lfpm)
Storage Temperature, TSTG
-65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions
beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = 3.3V±5%, TA = 0°C TO 70°C
Symbol
Parameter
VDD
Core Supply Voltage
Test Conditions
Minimum
Typical
Maximum
Units
3.135
3.3
3.465
V
VDD – 0.72
3.3
VDDA
Analog Supply Voltage
VDD
V
IDD
Power Supply Current
300
mA
IDDA
Analog Supply Current
30
mA
Maximum
Units
TABLE 3B. LVCMOS / LVTTL DC CHARACTERISTICS, VDD = VDDA = 3.3V±5%, TA = 0°C TO 70°C
Symbol
Parameter
Test Conditions
Minimum
Typical
VIH
Input High Voltage
2
VDD + 0.3
V
VIL
Input Low Voltage
-0.3
0.8
V
IIH
Input High Current
IIL
Input Low Current
MR, F_SEL1
VDD = VIN = 3.465V
150
µA
PLL_SEL,
F_SEL0, F_SEL2
VDD = VIN = 3.465V
5
µA
MR, F_SEL1
VDD = 3.465V, VIN = 0V
-5
µA
PLL_SEL,
F_SEL0, F_SEL2
VDD = 3.465V, VIN = 0V
-150
µA
TABLE 3C. LVDS DC CHARACTERISTICS, VDD = VDDA = 3.3V±5%, TA = 0°C TO 70°C
Symbol
Parameter
VOD
Differential Output Voltage
Δ VOD
VOD Magnitude Change
VOS
Offset Voltage
Δ VOS
VOS Magnitude Change
REVISION B 5/6/15
Test Conditions
3
Minimum
Typical
Maximum
Units
375
475
575
mV
50
mV
1.3
1.45
1.6
V
50
mV
CRYSTAL-TO-LVDS
INTEGRATED FREQUENCY SYNTHESIZER/FANOUT BUFFER
84427 DATA SHEET
TABLE 4. CRYSTAL CHARACTERISTICS
Parameter
Test Conditions
Minimum
Mode of Oscillation
Typical Maximum
Units
Fundamental
Frequency
25.5
MHz
Equivalent Series Resistance (ESR)
19.44
50
Ω
Shunt Capacitance
7
pF
Drive Level
1
mW
TABLE 5. AC CHARACTERISTICS, VDD = VDDA = 3.3V±5%, TA = 0°C TO 70°C
Symbol
Parameter
FOUT
Output Frequency
tjit(Ø)
tjit(cc)
RMS Phase Jitter (Random);
NOTE 1
Test Conditions
Minimum
Typical
77.76
155.52MHz,
(Integration Range: 12kHz-20MHz)
156.25MHz,
(Integration Range: 12kHz-20MHz)
Output Skew; NOTE 3, 4
tR / tF
Output Rise/Fall Time
odc
Output Duty Cycle
tLOCK
PLL Lock Time
20% to 80%
Units
625
MHz
3.4
ps
3.1
ps
Cycle-to-Cycle Jitter; NOTE 2
tsk(o)
Maximum
36
ps
85
ps
200
600
ps
47
52
%
1
ms
See Parameter Measurement Information section.
NOTE 1: See Phase Noise Plots.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential crossing points.
CRYSTAL-TO-LVDS
INTEGRATED FREQUENCY SYNTHESIZER/FANOUT BUFFER
4
REVISION B 5/6/15
84427 DATA SHEET
TYPICAL PHASE NOISE AT 155.52MHZ
➤
0
-10
-20
-30
-40
-50
155.52MHz
SONET Filter
RMS Phase Noise Jitter
12kHz to 20MHz = 3.4ps (typical)
Raw Phase Noise Data
➤
Z
H )
(dBc
-80
-90
-100
-110
-120
-130
-140
-150
➤
PHASE NOISE
-60
-70
-160
-170
-180
-190
10
100
1k
Phase Noise Result by adding a
SONET Filter to raw data
10k
100k
1M
10M
100M
OFFSET FREQUENCY (HZ)
➤
10Gb Ethernet Filter
Raw Phase Noise Data
➤
Z
H )
(dBc
156.25MHz
RMS Phase Noise Jitter
12kHz to 20MHz = 3.1ps (typical)
➤
PHASE NOISE
TYPICAL PHASE NOISE AT 156.25MHZ
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
10
100
1k
Phase Noise Result by adding
10Gb Ethernet Filter to raw data
10k
100k
1M
10M
100M
OFFSET FREQUENCY (HZ)
REVISION B 5/6/15
5
CRYSTAL-TO-LVDS
INTEGRATED FREQUENCY SYNTHESIZER/FANOUT BUFFER
84427 DATA SHEET
PARAMETER MEASUREMENT INFORMATION
3.3V OUTPUT LOAD AC TEST CIRCUIT
RMS PHASE JITTER
CYCLE-TO-CYCLE JITTER
OUTPUT SKEW
DIFFERENTIAL OUTPUT VOLTAGE SETUP
OFFSET VOLTAGE SETUP
OUTPUT RISE/FALL TIME
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
CRYSTAL-TO-LVDS
INTEGRATED FREQUENCY SYNTHESIZER/FANOUT BUFFER
6
REVISION B 5/6/15
84427 DATA SHEET
APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply
pins are vulnerable to random noise. The 84427 provides
separate power supplies to isolate any high switching
noise from the outputs to the internal PLL. VDD and VDDA should be
individually connected to the power supply plane through vias,
and bypass capacitors should be used for each pin. To achieve
optimum jitter performance, power supply isolation is required.
Figure 1 illustrates how a 24Ω resistor along with a 10μF and a
.01μF bypass capacitor should be connected to each VDDA pin.
3.3V
VDD
.01μF
24Ω
VDDA
.01μF
10 μF
FIGURE 1. POWER SUPPLY FILTERING
CRYSTAL INPUT INTERFACE
and were chosen to minimize the ppm error. The optimum C1
and C2 values can be slightly adjusted for different board layouts.
The 84427 has been characterized with 18pF parallel resonant
crystals. The capacitor values, C1 and C2, shown in Figure 2
below were determined using an 18pF parallel resonant crystal
XTAL_IN
C1
18p
X1
18pF Parallel Crystal
XTAL_OUT
C2
22p
Figure 2. CRYSTAL INPUt INTERFACE
REVISION B 5/6/15
7
CRYSTAL-TO-LVDS
INTEGRATED FREQUENCY SYNTHESIZER/FANOUT BUFFER
84427 DATA SHEET
LVCMOS TO XTAL INTERFACE
The XTAL_IN input can accept a single-ended LVCMOS signal
through an AC coupling capacitor. A general interface diagram is
shown in Figure 3. The XTAL_OUT pin can be left floating. The
input edge rate can be as slow as 10ns. For LVCMOS inputs,
it is recommended that the amplitude be reduced from full
swing to half swing in order to prevent signal interference with
the power rail and to reduce noise. This configuration requires
that the output impedance of the driver (Ro) plus the series
resistance (Rs) equals the transmission line impedance. In
addition, matched termination at the crystal input will attenuate
the signal in half. This can be done in one of two ways. First, R1
and R2 in parallel should equal the transmission line impedance.
For most 50Ω applications, R1 and R2 can be 100Ω. This can
also be accomplished by removing R1 and making R2 50Ω.
VDD
VDD
R1
Ro
.1uf
Rs
Zo = 50
XTAL_IN
R2
Zo = Ro + Rs
XTAL_OUT
FIGURE 3. GENERAL DIAGRAM FOR LVCMOS DRIVER TO XTAL INPUT INTERFACE
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS
OUTPUTS:
LVDS
All unused LVDS output pairs can be either left floating or
terminated with 100Ω across. If they are left floating, we
recommend that there is no trace attached.
CRYSTAL-TO-LVDS
INTEGRATED FREQUENCY SYNTHESIZER/FANOUT BUFFER
8
REVISION B 5/6/15
84427 DATA SHEET
LVDS DRIVER TERMINATION
A general LVDS interface is shown in Figure 4. In a 100Ω differential transmission line environment, LVDS drivers require
a matched load termination of 100Ω across near the receiver
input. For a multiple LVDS outputs buffer, if only partial outputs
are used, it is recommended to terminate the un-used outputs.
3.3V
3.3V
LVDS_Driv er
+
R1
100
-
100 Ohm Differiential Transmission Line
FIGURE 4. TYPICAL LVDS DRIVER TERMINATION
SCHEMATIC EXAMPLE
Figure 5A shows a schematic example of using an 84427. In
this example, the input is a 25MHz parallel resonant crystal with
load capacitor CL=18pF. The frequency fine tuning capacitors
C1 and C2 is 22pF and 18pF respectively. This example also
shows logic control input handling. The configuration is set at
F_SEL[2:0]=101, therefore, the output frequency is 156.25MHz.
It is recommended to have one decouple capacitor per power
pin. Each decoupling capacitor should be located as close as
possible to the power pin. The low pass filter R7, C11 and C16
for clean analog supply should also be located as close to the
VDDA pin as possible.
VDD
VDD
R4
1K
R7
24
VDDA
22p
C11
0.1u
C16
10u
F_SEL2
C1
X1
25MHz,18pF
U1
VDD
F_SEL1
R5 F_SEL0
1K
C2
Zo = 50
13
14
15
16
17
18
19
20
21
22
23
24
VDD
VEE
PLL_SEL
VDD
VDDA
F_SEL2
XTAL_OUT
XTAL_IN
MR
F_SEL1
F_SEL0
VDD
nQ5
Q5
nQ4
Q4
nQ3
Q3
nQ2
Q2
nQ1
Q1
nQ0
Q0
12
11
10
9
8
7
6
5
4
3
2
1
+
R1
100
-
Zo = 50
LVDS_input
VDD
18p
VDD
ICS84427
RU1
1K
RU2
SP
RU3
1K
VDD=3.3V
F_SEL2
F_SEL1
F_SEL0
RD1
SP
RD2
1K
RD3
SP
VDD
(U1,13)
(U1,16)
C6
0.1u
e.g. F_SEL[2:0]=101
(U1,24)
C5
0.1u
C3
0.1u
SP = Spare, Not Installed
FIGURE 5A. 84427 SCHEMATIC EXAMPLE
REVISION B 5/6/15
9
CRYSTAL-TO-LVDS
INTEGRATED FREQUENCY SYNTHESIZER/FANOUT BUFFER
84427 DATA SHEET
The following component footprints are used in this layout
example:
• The differential 100Ω output traces should have the
same length.
All the resistors and capacitors are size 0603.
• Avoid sharp angles on the clock trace. Sharp angle turns
cause the characteristic impedance to change on the
transmission lines.
POWER AND GROUNDING
Place the decoupling capacitors C3, C5 and C6, as close as
possible to the power pins. If space allows, placement of the
decoupling capacitor on the component side is preferred. This
can reduce unwanted inductance between the decoupling capacitor and the power pin caused by the via.
• Keep the clock traces on the same layer. Whenever possible, avoid placing vias on the clock traces. Placement
of vias on the traces can affect the trace characteristic
impedance and hence degrade signal integrity.
Maximize the power and ground pad sizes and number of vias
capacitors. This can reduce the inductance between the power
and ground planes and the component power and ground pins.
• To prevent cross talk, avoid routing other signal traces
in parallel with the clock traces. If running parallel traces
is unavoidable, allow a separation of at least three trace
widths between the differential clock trace and the other
signal trace.
The RC filter consisting of R7, C11, and C16 should be placed
as close to the VDDA pin as possible.
• Make sure no other signal traces are routed between
the clock trace pair.
CLOCK TRACES AND TERMINATION
• The matching termination resistors should be located
as close to the receiver input pins as possible.
Poor signal integrity can degrade the system performance or
cause system failure. In synchronous high-speed digital systems, the clock signal is less tolerant to poor signal integrity
than other signals. Any ringing on the rising or falling edge or
excessive ring back can cause system failure. The shape of the
trace and the trace delay might be restricted by the available
space on the board and the component location. While routing
the traces, the clock signal traces should be routed first and
should be locked prior to routing other signal traces.
CRYSTAL
The crystal X1 should be located as close as possible to the pins
20 (XTAL_IN) and 19 (XTAL_OUT). The trace length between
the X1 and U1 should be kept to a minimum to avoid unwanted
parasitic inductance and capacitance. Other signal traces should
not be routed near the crystal traces.
C6
GND
VDD
C1
C5
Signals
R7
VDDA
C16
VIA
C11
X1
C2
C3
U1
ICS84427
Pin1
50 Ohm Traces
FIGURE 5B. PCB BOARD LAYOUT FOR 84427
CRYSTAL-TO-LVDS
INTEGRATED FREQUENCY SYNTHESIZER/FANOUT BUFFER
10
REVISION B 5/6/15
84427 DATA SHEET
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the 84427.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the 84427 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results.
•
Power (core)MAX = VDD_MAX * (IDD_MAX + IDDA_MAX) = 3.465V * (300mA + 30mA) = 1143.45mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of
the device. The maximum recommended junction temperature for the devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θJA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a
moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 43°C/W per Table 6 below.
Therefore, Tj for an ambient temperature of 70°C with all outputs switching is:
70°C + 1.143W * 43°C/W = 119.1°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
TABLE 6. THERMAL RESISTANCE θJA FOR 24-PIN SOIC, FORCED CONVECTION
θJA by Velocity (Linear Feet per Minute)
Multi-Layer PCB, JEDEC Standard Test Boards
0
200
500
50°C/W
43°C/W
38°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
REVISION B 5/6/15
11
CRYSTAL-TO-LVDS
INTEGRATED FREQUENCY SYNTHESIZER/FANOUT BUFFER
84427 DATA SHEET
RELIABILITY INFORMATION
TABLE 7. θJAVS. AIR FLOW TABLE FOR 24 LEAD SOIC
θJA by Velocity (Linear Feet per Minute)
Multi-Layer PCB, JEDEC Standard Test Boards
0
200
500
50°C/W
43°C/W
38°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for 84427 is: 2804
CRYSTAL-TO-LVDS
INTEGRATED FREQUENCY SYNTHESIZER/FANOUT BUFFER
12
REVISION B 5/6/15
84427 DATA SHEET
PACKAGE OUTLINE - M SUFFIX FOR 24 LEAD SOIC
TABLE 8. PACKAGE DIMENSIONS
Millimeters
SYMBOL
Minimum
N
Maximum
24
A
--
2.65
A1
0.10
--
A2
2.05
2.55
B
0.33
0.51
C
0.18
0.32
D
15.20
15.85
E
7.40
e
7.60
1.27 BASIC
H
10.00
10.65
h
0.25
0.75
L
0.40
1.27
α
0°
8°
Reference Document: JEDEC Publication 95, MS-013, MO-119
REVISION B 5/6/15
13
CRYSTAL-TO-LVDS
INTEGRATED FREQUENCY SYNTHESIZER/FANOUT BUFFER
84427 DATA SHEET
TABLE 9. ORDERING INFORMATION
Part/Order Number
Marking
Package
Shipping Packaging
Temperature
84427CMLF
ICS84427CMLF
84427CMLFT
ICS84427CMLF
24 Lead “Lead-Free” SOIC
tube
0°C to 70°C
24 Lead “Lead-Free” SOIC
tape & reel
0°C to 70°C
NOTE: Parts that are ordered with an “LF” suffix to the part number are the Pb-Free configuration and are RoHS complaint.
CRYSTAL-TO-LVDS
INTEGRATED FREQUENCY SYNTHESIZER/FANOUT BUFFER
14
REVISION B 5/6/15
84427 DATA SHEET
REVISION HISTORY SHEET
Rev
Table
Page
B
T9
14
16
B
REVISION B 5/6/15
T9
1
14
Description of Change
Date
Updated datasheet’s header/footer with IDT from ICS.
Removed ICS prefix from Part/Order Number column.Added Contact Page.
7/27/10
Product Discontinuation Notice - PDN CQ-15-03.
Ordering Information - removed leaded devices.
5/6/15
15
CRYSTAL-TO-LVDS
INTEGRATED FREQUENCY SYNTHESIZER/FANOUT BUFFER
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email: [email protected]
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