CS42L50
Low Voltage, Stereo CODEC with Headphone Amp
Features
Description
l 28-Pin CASON package
l 1.8 to 3.3 Volt supply
l 24-Bit conversion / 96 kHz sample rate
l 96 dB ADC/DAC dynamic range at 3 V supply
l -88/-85 dB ADC/DAC THD+N
l 19 mW playback power consumption @ 1.8 V
l Microphone or Line input amplifier with up to
The CS42L50 is a highly integrated, 24-bit, 96 kHz audio
codec.
This device is based on delta-sigma modulation allowing
infinite adjustment of the sample rate between 8 kHz and
100 kHz simply by changing the master clock frequency.
The CS42L50 contains a 2:1 stereo mux, programmable
analog gain control, and digital attenuation on the analog
inputs. The output D/A converters include digital bass
and treble boost, dynamic range compression, limiting,
mixing, volume control and de-emphasis.
32dB of gain
l 2:1 stereo mux
l Digital volume control on inputs and outputs
– 96 dB attenuation, 1 dB step size
l Digital bass and treble boost on outputs
– Selectable corner frequencies
l Dynamic range compression and limiting
l De-emphasis for 32 kHz, 44.1 kHz, and 48 kHz
l Headphone amplifier
– 26 mW power output into 16 W load @ 3.0V
supply
– -80 dB THD+N
– 34 dB analog attenuation and mute
l ATAPI mixing functions
The CS42L50 operates from a +1.8 V to +3.3 V supply.
These features are ideal for portable MP3 and MD recorders, CD and DVD recorders, digital camcorders, and
other portable systems that require extremely low power
consumption in a minimal amount of space.
ORDERING INFORMATION
CS42L50-KN 28-pin CASON, -10 to 70 °C
CDB42L50
Evaluation Board
II
Analog
Volume
Control
Control Port
LRCK
SDIN
SDOUT
Serial Port
SCLK
Digital
Volume
Control
Bass/Treble
Boost
Compression
Limiting
Attenuator
0-96 dB
Digital Filters
De-emphasis
VL
∆Σ
DAC
Analog
Filter
Digital
Filters
Analog
Volume
Control
MUX
Gain
12 dB
ADC
MUX
Gain
12 dB
MCLK
P.O. Box 17847, Austin, Texas 78760
(512) 445 7222 FAX: (512) 445 7581
http://www.cirrus.com
Analog
Filter
ADC
Attenuator
0-96 dB
Preliminary Product Information
∆Σ
DAC
Headphone
Amplifier
VA
HP_A
Line
Amplifier
RST
SDA
Gain
Compensation
SCL
AOUT_A
HP_B
AOUT_B
AIN_L1
AIN_L2
AIN_R1
AIN_R2
MUTEC
This document contains information for a new product.
Cirrus Logic reserves the right to modify this product without notice.
Copyright ã Cirrus Logic, Inc. 2001
(All Rights Reserved)
AUG ‘01
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CS42L50
TABLE OF CONTENTS
1. CHARACTERISTICS/SPECIFICATIONS ................................................................................. 5
ANALOG INPUT CHARACTERISTICS .................................................................................... 5
ANALOG OUTPUT CHARACTERISTICS ................................................................................ 7
POWER AND THERMAL CHARACTERISTICS..................................................................... 10
DIGITAL CHARACTERISTICS ............................................................................................... 11
ABSOLUTE MAXIMUM RATINGS ......................................................................................... 11
RECOMMENDED OPERATING CONDITIONS ..................................................................... 11
SWITCHING CHARACTERISTICS ........................................................................................ 12
SWITCHING CHARACTERISTICS - CONTROL PORT......................................................... 14
2. TYPICAL CONNECTION DIAGRAM ....................................................................................... 15
3. REGISTER QUICK REFERENCE ........................................................................................... 16
4. REGISTER DESCRIPTION ..................................................................................................... 18
4.1 ADC (address 0010000) .................................................................................................. 18
4.1.1 I/O and Power Control (address 01h) .......................................................................... 18
4.1.2 20DB Gain Boost (BOOST) .......................................................................................... 18
4.1.3 Analog Input Multiplexer (AINMUX) ............................................................................... 18
4.1.4 Power Down (PDN)........................................................................................................ 18
4.1.5 Control Port Enable (CP_EN) ........................................................................................ 18
4.1.6 Interface Control (address 02h) .................................................................................... 19
4.1.7 Master Clock Divide (MCLKDIV)................................................................................... 19
4.1.8 Master Clock Ratio (RATIO) ......................................................................................... 19
4.1.9 Master Mode (MASTER)............................................................................................... 19
4.1.10 Digital Interface Format (DIF) ..................................................................................... 19
4.1.11 Analog I/O Control (address 03h) ............................................................................... 20
4.1.12 Left/Right Channel Mute (MUTE)............................................................................... 20
4.1.13 Soft Ramp and Zero Cross Enable (SOFT/ZC) ......................................................... 20
4.1.14 Independent Volume Control Enable (INDVC) .......................................................... 21
4.1.15 Left Channel Volume = Right Channel Volume (L=R) ............................................... 21
4.1.16 High-Pass Filter Freeze (HPFREEZE)....................................................................... 21
4.1.17 Volume Control: Left Channel (address 04h) & Right Channel (address 05h) ............ 22
4.1.18 Left/Right Analog Gain (address 06h) ........................................................................ 22
4.1.19 Clip Detection Status (address 07h) .......................................................................... 23
4.2 DAC (Address = 0010001) ............................................................................................... 23
4.2.1 Power and Muting Control (address 01h) .................................................................... 23
4.2.2 Auto-Mute (AMUTE) ..................................................................................................... 23
4.2.3 Soft Ramp and Zero Cross Control (SZC) ..................................................................... 23
4.2.4 Power Down Headphone Amplifier (PDNHP) ................................................................ 24
Contacting Cirrus Logic Support
For a complete listing of Direct Sales, Distributor, and Sales Representative contacts, visit the Cirrus Logic web site at:
http://www.cirrus.com/corporate/contacts/sales.cfm
Purchase of I2C components of Cirrus Logic, Inc., or one of its sublicensed Associated Companies conveys a license under the Philips I2C Patent Rights to use those
components in a standard I2C system.
Preliminary product information describes products which are in production, but for which full characterization data is not yet available. Advance product information describes products which are in development and subject to development changes. Cirrus Logic, Inc. has made best efforts to ensure that the information contained in this
document is accurate and reliable. However, the information is subject to change without notice and is provided “AS IS” without warranty of any kind (express or implied).
Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and
limitation of liability. No responsibility is assumed by Cirrus Logic, Inc. for the use of this information, including use of this information as the basis for manufacture or sale
of any items, nor for infringements of patents or other rights of third parties. This document is the property of Cirrus Logic, Inc. and by furnishing this information, Cirrus
Logic, Inc. grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights of Cirrus
Logic, Inc. Cirrus Logic, Inc., copyright owner of the information contained herein, gives consent for copies to be made of the information only for use within your organization
with respect to Cirrus Logic integrated circuits or other parts of Cirrus Logic, Inc. The same consent is given for similar information contained on any Cirrus Logic website
or disk. This consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale.
The names of products of Cirrus Logic, Inc. or other vendors and suppliers appearing in this document may be trademarks or service marks of their respective owners which
may be registered in some jurisdictions. A list of Cirrus Logic, Inc. trademarks and service marks can be found at http://www.cirrus.com.
2
DS544PP1
CS42L50
4.2.5 Power Down Line Amplifier (PDNLN) ............................................................................ 24
4.2.6 Power Down (PDN) ....................................................................................................... 24
4.2.7 Control Port Enable (CP_EN) ........................................................................................ 24
4.2.8 Channel A Analog Headphone Attenuation Control (address 02h) (HVOLA) .............. 25
4.2.9 Channel B Analog Headphone Attenuation Control (address 03h) (HVOLB) .............. 25
4.2.10 Channel A Digital Volume Control (address 04h) (DVOLA) ....................................... 25
4.2.11 Channel B Digital Volume Control (address 05h) (DVOLB) ....................................... 25
4.2.12 Tone Control (address 06h)........................................................................................ 26
4.2.13 Bass Boost Level (BB)................................................................................................. 26
4.2.14 Treble Boost Level (TB)............................................................................................... 26
4.2.15 Mode Control (address 07h)....................................................................................... 27
4.2.16 Bass Boost Corner Frequency (BBCF) ....................................................................... 27
4.2.17 Treble Boost Corner Frequency (TBCF) ..................................................................... 27
4.2.18 Channel A Volume = Channel B Volume (A=B) .......................................................... 27
4.2.19 De-Emphasis Control (DEM) ....................................................................................... 28
4.2.20 Digital Volume Control Bypass (VCBYP) .................................................................... 28
4.2.21 Volume and Mixing Control (address 0Ah)................................................................. 28
4.2.22 Tone Control Mode (TC).............................................................................................. 28
4.2.23 Tone Control Enable (TC_EN) .................................................................................... 28
4.2.24 ATAPI Channel Mixing and Muting (ATAPI)................................................................ 29
4.2.25 Mode Control 2 (address 0Bh) ................................................................................... 29
4.2.26 Master Clock Divide Enable (MCLKDIV) ..................................................................... 29
4.2.27 Line Amplifier Gain Compensation (LINE)................................................................... 29
4.2.28 Digital Interface Format (DIF) ...................................................................................... 30
5. PIN DESCRIPTIONS ............................................................................................................... 31
6. APPLICATIONS ...................................................................................................................... 33
6.1 Grounding and Power Supply Decoupling ....................................................................... 33
6.2 Clock Modes .................................................................................................................... 33
6.3 EP73xx Serial Port Interface ........................................................................................... 33
6.4 De-Emphasis ................................................................................................................... 33
6.5 Recommended Power-up Sequence ............................................................................... 33
6.6 Optional External Headphone Mute ................................................................................ 33
7. CONTROL PORT INTERFACE ............................................................................................... 33
7.1 Memory Address Pointer (MAP) ...................................................................................... 35
7.2 INCR (Auto Map Increment Enable) ................................................................................. 35
7.3 MAP0-3 (Memory Address Pointer).................................................................................. 35
8. PARAMETER DEFINITIONS ................................................................................................... 44
9. REFERENCES ......................................................................................................................... 44
10. PACKAGE DIMENSIONS ..................................................................................................... 45
LIST OF FIGURES
Figure 1. SCLK to LRCK and SDIN, Slave Mode .................................................... 13
Figure 2. SCLK to LRCK and SDIN, Master Mode .................................................. 13
Figure 3. Control Port Timing - I2C‚ ......................................................................... 14
Figure 4. CS42L50 Typical Connection Diagram .................................................... 15
Figure 5. Control Port Timing .................................................................................. 35
Figure 6. Decimation Filter Single Speed Stopband Rejection ............................... 36
Figure 7. Decimation Filter Single Speed Transition Band ...................................... 36
Figure 8. Decimation Filter Single Speed Transition Band (Detail) ......................... 36
Figure 9. Decimation Filter Single Speed Passband Ripple ................................... 36
Figure 10.Decimation Filter Double Speed Stopband Rejection .............................. 36
Figure 11.Decimation Filter Double Speed Transition Band .................................... 36
Figure 12.Decimation Filter Double Speed Transition Band (Detail) ........................ 37
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CS42L50
Figure 13.Decimation Filter Double Speed Passband Ripple .................................. 37
Figure 14.Interpolation Filter Single Speed Stopband Rejection .............................. 38
Figure 15.Interpolation Filter Single Speed Transition Band .................................... 38
Figure 16.Interpolation Filter Single Speed Transition Band (Detail) ....................... 38
Figure 17.Interpolation Filter Single Speed Passband Ripple .................................. 38
Figure 18.Interpolation Filter Double Speed Stopband Rejection ............................ 38
Figure 19.Interpolation Filter Double Speed Transition Band ................................... 38
Figure 20.Interpolation Filter Double Speed Transition Band (Detail) ...................... 39
Figure 21.Interpolation Filter Double Speed Passband Ripple ................................. 39
Figure 22.Line Input Test Circuit .............................................................................. 39
Figure 23.Line Output Test Load .............................................................................. 40
Figure 24.Headphone Output Test Load .................................................................. 40
Figure 25.Left Justified, up to 24-bit data ................................................................. 41
Figure 26.Right Justified, 16-bit data ........................................................................ 41
Figure 27.Right Justified, 24-bit data ........................................................................ 41
Figure 28.Right Justified, 18-bit data ........................................................................ 42
Figure 29.Right Justified, 20-bit data ........................................................................ 42
Figure 30.I2S, up to 24-bit data ................................................................................ 42
Figure 31.De-Emphasis Curve ................................................................................. 43
Figure 32.ATAPI Block Diagram ............................................................................... 43
Figure 33.Package Dimensions ................................................................................ 45
Figure 34.Package Top and Side Views .................................................................. 46
Figure 35.Package Bottom View .............................................................................. 47
LIST OF TABLES
Table 1. Example Analog Volume Settings ...................................................................................25
Table 2. Example Digital Volume Settings ....................................................................................26
Table 3. Example Bass Boost Settings .........................................................................................26
Table 4. Example Treble Boost Settings .......................................................................................27
Table 5. ATAPI Decode.................................................................................................................29
Table 6. Digital Interface Format ...................................................................................................30
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CS42L50
1.
CHARACTERISTICS/SPECIFICATIONS
ANALOG INPUT CHARACTERISTICS (TA = 25° C; GND = 0 V Logic "1" = VL = 1.8 V; Logic "0" =
GND = 0 V; MCLK = 12.288 MHz; Fs for Single Speed Mode = 48 kHz, SCLK = 3.072 MHz, Fs for Double Speed
Mode = 96 kHz, SCLK = 6.144 MHz; Measurement Bandwidth 10 Hz to 20 kHz, unless otherwise specified. Input is
997Hz sine wave.)
Single Speed Mode Double Speed Mode
Parameter
Symbol
Min
Typ
Max
Min
Typ
Max
Unit
TBD
TBD
93
90
-
TBD
TBD
94
91
-
dB
dB
-
-88
-70
-30
-86
-68
-28
TBD
-
-
-88
-71
-31
-86
-68
-28
TBD
-
dB
dB
dB
dB
dB
dB
-
90
87
85
82
-
-
89
86
86
83
-
dB
dB
dB
dB
-
85
83
-
-
84
82
-
dB
dB
TBD
TBD
96
93
-
TBD
TBD
98
95
-
dB
dB
-
-88
-73
-33
-86
-68
-28
TBD
-
-
-85
-75
-35
-83
-65
-28
TBD
-
dB
dB
dB
dB
dB
dB
-
93
90
88
85
-
-
92
89
89
86
-
dB
dB
dB
dB
-
78
73
-
-
77
76
-
dB
dB
Analog Input Characteristics for VA = 1.8 V
Dynamic Range
A-weighted
unweighted
Total Harmonic Distortion + Noise
(Note 1) THD+N
18 to 24-Bit
-1 dB
-20 dB
-60 dB
16-Bit
-1 dB
-20 dB
-60 dB
Dynamic Range (PGA on)*
0 dB Gain
A-weighted
unweighted
12 dB Gain A-weighted
unweighted
THD+N
Total Harmonic Distortion + Noise (PGA on)*
(Note 1)
0 dB Gain, 18 to 24-Bit -1 dB
12 dB Gain, 18 to 24-Bit -1 dB
Analog Input Characteristics for VA = 3.0 V
Dynamic Range
A-weighted
unweighted
Total Harmonic Distortion + Noise
(Note 1) THD+N
18 to 24-Bit
-1 dB
-20 dB
-60 dB
16-Bit
-1 dB
-20 dB
-60 dB
Dynamic Range (PGA on)*
0 dB Gain
A-weighted
unweighted
12 dB Gain A-weighted
unweighted
Total Harmonic Distortion + Noise (PGA on)*
THD+N
(Note 1)
0 dB Gain, 18 to 24-Bit -1 dB
12 dB Gain, 18 to 24-Bit -1 dB
*PGA : Programmable Gain Amplifier
DS544PP1
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CS42L50
Single Speed Mode Double Speed Mode
Parameter
Symbol
Min
Typ
Max
Min
Typ
Max
Unit
-
90
-
-
90
-
dB
-
0.1
-
-
0.1
-
dB
-
-
0
-
-
0
LSB
TBD
VA/3.6
TBD
TBD
-
100
-
-
100
-
ppm/°C
10
-
-
10
-
-
kΩ
-
-
15
-
-
15
pF
Gain Step Size
-
1.0
-
-
1.0
-
dB
Absolute Gain Step Error
-
-
TBD
-
-
TBD
dB
0
-
23.5
0
-
47.5
kHz
-0.08
-
-
0
dB
Analog Input Characteristics for VA = 1.8 - 3.3V
Interchannel Isolation
1 kHz
Interchannel Gain Mismatch
Offset Error
(with HPF Active)
Full Scale Input Voltage
Gain Drift
Input Resistance
Input Capacitance
VA/3.6 TBD
Vrms
Programmable Gain Characteristics
A/D Decimation Filter Characteristics (Note 2)
Passband
(Note 3)
Passband Ripple
+0.17 -0.09
Stopband
(Note 3)
27.5
-
-
64.1
-
-
kHz
Stopband Attenuation
(Note 4)
-60.3
-
-
-48.4
-
-
dB
tgd
-
10/Fs
-
-
2.7/Fs
-
s
∆tgd
-
-
0.03
-
-
0.007
µs
Group Delay (Fs = Output Sample Rate)(Note 5)
Group Delay Variation vs. Frequency
High Pass Filter Characteristics
Frequency Response
-3 dB
-0.1 dB
(Note 2)
-
3.7
24.2
-
-
3.7
24.2
-
Hz
Hz
Phase Deviation
@ 20 Hz
(Note 2)
-
10
-
-
10
-
Degree
(Note 2)
-
-
0.17
-
-
0.09
dB
Passband Ripple
*PGA : Programmable Gain Amplifier
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DS544PP1
CS42L50
ANALOG OUTPUT CHARACTERISTICS (TA = 25° C; Logic "1" = VL = 1.8 V; Logic "0" =
GND = 0 V; Full-Scale Output Sine Wave, 997 Hz; MCLK = 12.288 MHz; Measurement Bandwidth 10 Hz to
20 kHz, unless otherwise specified; Fs for Single Speed Mode = 48 kHz, SCLK = 3.072 MHz. Fs for Double Speed
Mode = 96 kHz, SCLK = 6.144 MHz. Test load RL = 10 kΩ, CL = 10 pF (see Figure 23) for line out, RL = 16 Ω,
CL = 10 pF (see Figure 24) for headphone out.
Parameter
Symbol
Single Speed Mode
Double Speed Mode
Min
Typ
Max
Min
Typ
Max
Unit
TBD
TBD
-
91
94
89
92
-
TBD
TBD
-
89
92
87
90
-
dB
dB
dB
dB
-
-80
-71
-31
-78
-69
-29
TBD
-
-
-80
-69
-29
-78
-67
-27
TBD
-
dB
dB
dB
dB
dB
dB
-
100
-
-
100
-
dB
Line Output Dynamic Performance for VA = 1.8 V
Dynamic Range
18 to 24-Bit
16-Bit
Total Harmonic Distortion + Noise
18 to 24-Bit
16-Bit
Interchannel Isolation
(Note 6)
unweighted
A-Weighted
unweighted
A-Weighted
(Note 6) THD+N
0 dB
-20 dB
-60 dB
0 dB
-20 dB
-60 dB
(1 kHz)
Headphone Output Dynamic Performance for VA = VA_HP = 1.8 V
Dynamic Range
18 to 24-Bit
16-Bit
Total Harmonic Distortion + Noise
18 to 24-Bit
16-Bit
Interchannel Isolation
(Note 6)
unweighted
A-Weighted
unweighted
A-Weighted
(Note 6) THD+N
0 dB
-20 dB
-60 dB
0 dB
-20 dB
-60 dB
(1 kHz)
TBD
TBD
-
88
91
86
89
-
TBD
TBD
-
88
91
86
89
-
dB
dB
dB
dB
-
-82
-68
-28
-80
-66
-26
TBD
-
-
-85
-68
-28
-83
-66
-26
TBD
-
dB
dB
dB
dB
dB
dB
-
66
-
-
66
-
dB
Notes: 1. Referenced to typical full-scale input voltage.
2. Filter response is not tested but is guaranteed by design.
3. Filter characteristics scale with output sample rate. For output sample rates, Fs, other than 48 kHz, the
0.01 dB passband edge is 0.4535x Fs and the stopband edge is 0.625x Fs.
4. The analog modulator samples the input at 6.144 MHz for an Fs equal to 48 kHz. There is no rejection
of input signals which are multiples of the sampling frequency ( n x 6.144 MHz ±21.8 kHz where
n = 0,1,2,3...).
5. Group delay for Fs = 48 kHz, tgd = 10/48 kHz = 208 µs.
6. One-half LSB of triangular PDF dither is added to data.
DS544PP1
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CS42L50
ANALOG OUTPUT CHARACTERISTICS (Continued)
Single Speed Mode
Double Speed Mode
Min
Typ
Max
Min
Typ
Max
Unit
TBD
TBD
-
93
96
91
94
-
TBD
TBD
-
93
96
91
94
-
dB
dB
dB
dB
(Note 6) THD+N
0dB
-20dB
-60dB
0dB
-20dB
-60dB
-
-85
-73
-33
-83
-71
-31
TBD
-
-
-85
-73
-33
-83
-71
-31
TBD
-
dB
dB
dB
dB
dB
dB
(1 kHz)
-
100
-
-
100
-
dB
Parameter
Symbol
Line Output Dynamic Performance for VA = 3.0 V
Dynamic Range
18 to 24-Bit
16-Bit
(Note 6)
unweighted
A-Weighted
unweighted
A-Weighted
Total Harmonic Distortion + Noise
18 to 24 Bit
16-Bit
Interchannel Isolation
Headphone Output Dynamic Performance for VA = VA_HP = 3.0 V
Dynamic Range
18 to 24-Bit
16-Bit
Total Harmonic Distortion + Noise
18 to 24 Bit
16-Bit
Interchannel Isolation
8
(Note 6)
unweighted
A-Weighted
unweighted
A-Weighted
(Note 6) THD+N
0dB
-20dB
-60dB
0dB
-20dB
-60dB
(1 kHz)
TBD
TBD
-
90
93
88
91
-
TBD
TBD
-
90
93
88
91
-
dB
dB
dB
dB
-
-76
-70
-30
-74
-68
-28
TBD
-
-
-73
-70
-30
-71
-68
-28
TBD
-
dB
dB
dB
dB
dB
dB
-
66
-
-
66
-
dB
DS544PP1
CS42L50
ANALOG OUTPUT CHARACTERISTICS (Continued)
Parameters
Analog Output
Full Scale Line Output Voltage
Line Output Quiescent Voltage
Full Scale Headphone Output Voltage
Headphone Output Quiescent Voltage
Interchannel Gain Mismatch
Gain Drift
Maximum Line Output AC-Current
Maximum Headphone Output
AC-Current
Symbol
Min
Typ
Max
Units
(Note 7) VFS_LINE
VQ_LINE
VFS_HP
VQ_HP
TBD
TBD
-
G x VA
0.5 x VA_LINE
0.55 x VA
0.5 x VA_HP
0.1
100
0.1
0.15
31
52
TBD
TBD
-
Vpp
VDC
Vpp
VDC
dB
ppm/°C
mA
mA
mA
mA
VA=1.8 V
VA=3.0 V
VA=VA_HP=1.8 V
VA=VA_HP=3.0 V
ILINE
IHP
Single Speed Mode
Parameter
Symbol
Min
Typ
Double Speed Mode
Max
Min
Typ
Max
Unit
Combined Digital and On-chip Analog Filter Response (Note 8)
Passband
(Note 9)
to -0.05 dB corner
to -0.1 dB corner
to -3 dB corner
0
0
-
.4535
.4998
0
0
-
.4426
.4984
Fs
Fs
Fs
-.02
-
+.08
0
-
+0.11
dB
.5465
-
-
.577
-
-
Fs
50
-
-
55
-
-
dB
-
9/Fs
-
-
4/Fs
-
s
Passband Group Delay Deviation 0 - 40 kHz
0 - 20 kHz
-
±0.36/Fs
-
-
±1.39/Fs
±0.23/Fs
-
s
s
De-emphasis Error
(Relative to 1 kHz)
-
-
+.2/-.1
+.05/-.14
+0/-.22
Frequency Response 10 Hz to 20 kHz
(Note 10)
StopBand
StopBand Attenuation
(Note 11)
Group Delay
tgd
Fs = 32 kHz
Fs = 44.1 kHz
Fs = 48 kHz
(Note 12)
dB
dB
dB
Notes: 7. See Section 4.2.7 for details.
8. Filter response is not tested but is guaranteed by design.
9. Response is clock dependent and will scale with Fs. Note that the response plots (Figures 14 through 21)
have been normalized to Fs and can be de-normalized by multiplying the X-axis scale by Fs.
10. Referenced to a 1 kHz, full-scale sine wave.
11. For Single Speed Mode, the measurement bandwidth is 0.5465 Fs to 3 Fs.
For Double Speed Mode, the measurement bandwidth is 0.577 Fs to 1.4 Fs.
12. De-emphasis is not available in Double Speed Mode.
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CS42L50
POWER AND THERMAL CHARACTERISTICS (GND = 0 V; All voltages with respect to
ground. All measurements taken with all zeros input and open outputs, unless otherwise specified.)
Parameters
Power Supplies
Power Supply CurrentNormal Operation
Power Supply CurrentNormal Operation
Power Supply CurrentPower Down Mode (Note 13)
Total Power DissipationNormal Operation
Maximum Headphone Power Dissipation
(1 kHz full-scale sine wave
into 16 ohm load)
Package Thermal Resistance
Power Supply Rejection Ratio (Note 14)
VA=1.8 V
VA_HP=1.8 V
VL=1.8 V
VA=3.0 V
VA_HP=3.0 V
VL=3.0 V
All Supplies=1.8 V
All Supplies =3.0V
All Supplies=1.8 V
All Supplies=3.0 V
Symbol
Min
Typ
Max
Units
IA
IA_HP
ID_L
IA
IA_HP
ID_L
-
13.3
1.5
154
20
1.5
270
150
350
27
65
TBD
TBD
mA
mA
µA
mA
mA
µA
µA
µA
mW
mW
-
15
26
55
60
40
-
mW
mW
°C/Watt
dB
dB
VA=1.8 V
VA=3.0 V
(1 kHz)
(60 Hz)
θJA
PSRR
Notes: 13. Power Down Mode is defined as RST = LO with all clocks and data lines held static.
14. Valid with the recommended capacitor values on FILT+_ADC, FILT+_DAC, VQ_DAC, and VQ_ADC as
shown in Figure 4. Increasing the capacitance will also increase the PSRR. Note that care should be
taken when selecting capacitor type, as any leakage current in excess of 1.0 µA will cause degradation
in analog performance. A small ceramic capacitor in parallel with a larger electrolytic is recommended.
10
DS544PP1
CS42L50
DIGITAL CHARACTERISTICS (TA = 25° C; VL =
Parameters
High-Level Input Voltage
Low-Level Input Voltage
Input Leakage Current
High-Level Output Voltage
Low-Level Output Voltage
Input Capacitance
Maximum MUTEC Drive Capability
VA=1.8 V
VA=3.0 V
MUTEC High-Level Output Voltage
MUTEC Low-Level Output Voltage
1.7 V - 3.3 V; GND = 0 V)
Symbol
VIH
Min
0.7 x VL
Typ
-
Max
-
Units
V
VIL
-
-
0.3 x VL
V
Iin
VOH
VOL
0.7 x VL
-
8
TBD
3
VA
0
±10
0.3 x VL
-
µA
V
V
pF
mA
mA
V
V
ABSOLUTE MAXIMUM RATINGS (GND = 0V; all voltages with respect to ground.)
Parameters
DC Power Supplies:
Analog&Headphone
Digital I/O
Input Current, Any Pin Except Supplies
Digital Input Voltage
Ambient Operating Temperature (power applied)
Storage Temperature
Symbol
VA&VA_HP
VL
Iin
VIND
TA
Tstg
Min
-0.3
-0.3
-0.3
-55
-65
Max
4.0
4.0
±10
VL+0.4
125
150
Units
V
V
mA
V
°C
°C
WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is
not guaranteed at these extremes.
RECOMMENDED OPERATING CONDITIONS (GND = 0V; all voltages with respect to ground.)
Parameters
Ambient Temperature
DC Power Supplies:
Analog&Headphone
Digital I/O
Symbol
TA
(Note 15) VA&VA_HP
VL
Min
-10
1.7
1.7
Typ
-
Max
70
3.6
3.6
Units
°C
V
V
Notes: 15. VA and VA_HP should be tied to the same supply as shown in Figure 4.
DS544PP1
11
CS42L50
SWITCHING CHARACTERISTICS (TA = -10 to 70° C; VA = 1.7 V - 3.3 V; Inputs: Logic 0 = GND,
Logic 1 = VL, CL = 20 pF)
Parameters
Symbol
Min
Typ
Max
Units
Fs
Fs
2
50
-
50
100
kHz
kHz
Input Sample Rate
Single Speed Mode
Double Speed Mode
MCLK Pulse Width High
MCLK/LRCK = 1024
8
-
-
ns
MCLK Pulse Width Low
MCLK/LRCK = 1024
8
-
-
ns
MCLK Pulse Width High
MCLK/LRCK = 768
10
-
-
ns
MCLK Pulse Width Low
MCLK/LRCK = 768
10
-
-
ns
MCLK Pulse Width High
MCLK/LRCK = 512
15
-
-
ns
MCLK Pulse Width Low
MCLK/LRCK = 512
15
-
-
ns
MCLK Pulse Width High
MCLK / LRCK = 384 or 192
25
-
-
ns
MCLK Pulse Width Low
MCLK / LRCK = 384 or 192
25
-
-
ns
MCLK Pulse Width High
MCLK / LRCK = 256 or 128
35
-
-
ns
MCLK Pulse Width Low
MCLK / LRCK = 256 or 128
35
-
-
ns
Master Mode
SCLK Falling to LRCK Edge
tslrd
-20
-
20
ns
SCLK Falling to SDOUT Valid
tsdo
0
-
20
ns
40
50
60
%
40
50
60
%
SCLK Duty Cycle
Slave Mode
LRCK Duty Cycle
Rise Time of Both LRCK and SCLK
tr
-
-
10
ns
Fall Time of Both LRCK and SCLK
tf
-
-
10
ns
Single Speed Mode
tsclkw
-
-
ns
Double Speed Mode
tsclkw
1
---------------------( 128 )Fs
1
-----------------( 64 )Fs
-
-
ns
-20
-
20
ns
ns
ns
SCLK Period (Note 16)
SCLK Falling to LRCK Edge
SCLK Falling to SDOUT Valid
16.
12
tslrd
Single Speed Mode
tdss
-
-
1
(512)Fs
Double Speed Mode
tdss
-
-
1
(256)Fs
There must be exactly 32, 48, 64, or 128 SCLK periods per LRCK transition.
DS544PP1
CS42L50
t sclkh
t sclkw
SCLK
t sclkl
t slrd
LRCK
t dss
MSB
SDIN
Figure 1. SCLK to LRCK and SDIN, Slave Mode
SCLK
LRCK
t slrd
t sdo
SDIN
MSB
MSB-1
Figure 2. SCLK to LRCK and SDIN, Master Mode
DS544PP1
13
CS42L50
SWITCHING CHARACTERISTICS - CONTROL PORT
(TA = 25° C; VL = 1.7 V - 3.3 V; Inputs: logic 0 = GND, logic 1 = VL, CL = 30 pF)
Parameter
Symbol
Min
Max
Unit
SCL Clock Frequency
fscl
-
100
KHz
RST Rising Edge to Start
tirs
500
-
ns
Bus Free Time Between Transmissions
tbuf
4.7
-
µs
Start Condition Hold Time (prior to first clock pulse)
thdst
4.0
-
µs
Clock Low time
tlow
4.7
-
µs
Clock High Time
thigh
4.0
-
µs
Setup Time for Repeated Start Condition
tsust
4.7
-
µs
thdd
0
-
µs
tsud
250
-
ns
Rise Time of SCL
trc
-
25
ns
Fall Time of SCL
tfc
-
25
ns
Rise Time of SDA
trd
-
1
µs
Fall Time of SDA
tfd
-
300
ns
tsusp
4.7
-
µs
SDA Hold Time from SCL Falling
(Note 17)
SDA Setup time to SCL Rising
Setup Time for Stop Condition
Note: 17. Data must be held for sufficient time to bridge the transition time, tfc, of SCL.
RST
t irs
Stop
R ep e a te d
S ta rt
S ta rt
Stop
SDA
t buf
t
t high
t hdst
tf
hdst
t susp
SC L
t
low
t
hdd
t sud
t sust
tr
Figure 3. Control Port Timing - I2Câ
14
DS544PP1
CS42L50
2. TYPICAL CONNECTION DIAGRAM
1.8 to 3.3 V
Supply
+
1.0 µF
0.1 µF
0.1 µF
23
VA
150 Ω
0.47 µF
8
13
+
0.1 µF
1.0 µF
21
VA_HP
VL
HP_A
AIN_L1
12
220 µF
+
4.7 µH
0.01 µF
150 Ω
0.47 µF
7
0.47 µF
5
AIN_R1
HP_B
14
220 µF
+
4.7 µH
1 kΩ
AIN_L2
AOUTL 16
0.01 µF
150 Ω
0.47 µF
4
18
Digital
Audio
Source
25
24
20
AOUTR
MCLK
560 Ω
3.3 µF
+
10 kΩ
AIN_R2
0.01 µF
19
15
10 kΩ
26
27
2
1.0 nF
1
1.0 nF
RL
C
RL
SCLK
LRCK
Mute
Circuit
MUTEC 17
SDOUT
SDIN
VQ_DAC
11
+
FILT+_DAC 10
µc
Configuration
C
560 Ω
3.3 µF
+
CS42L50
VL
28
16 Ω
Headphones
1 kΩ
0.01 µF
150 Ω
1.8 to 3.3 V
Supply
RST
REF_GND
SDA
SCL
AFLTR
6
0.1 µF
FILT+_ADC 3
AFLTL
1.0 µF
+ 1.0 µF
1.0 µF
+
0.1 µF
1.0 µF
+
VQ_ADC 9
GND
22
C=
RL + 560
4 π FS (RL560)
Figure 4. CS42L50 Typical Connection Diagram
DS544PP1
15
CS42L50
3. REGISTER QUICK REFERENCE
ADC (Address = 0010000)
Addr
0h
Function
Reserved
7
6
5
4
3
2
1
0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
0
0
0
0
0
0
0
0
Reserved
BOOST
PDN
CP_EN
0
0
default
1h
I/O and Power
Control
default
2h
Interface Control
Reserved MCLKDIV
Analog I/O Control
Clip Detection Status
0
MASTER
DIF2
DIF1
DIF0
0
0
0
0
0
MUTEL
MUTER
SZC1
SZC0
Reserved
INDVC
L=R
HPFREEZE
0
0
1
1
0
0
0
0
VOL7
VOL6
VOL5
VOL4
VOL3
VOL2
VOL1
VOL0
0
0
0
0
0
0
0
0
VOL7
VOL6
VOL5
VOL4
VOL3
VOL2
VOL1
VOL0
0
0
0
0
0
0
0
0
LVOL3
LVOL2
LVOL1
LVOL0
RVOL3
RVOL2
RVOL1
RVOL0
default
7h
1
RATIO0
Right Channel Digital
Volume Control
Analog Gain Control
0
0
Left Channel Digital
Volume Control
6h
0
RATIO1
default
5h
0
0
default
4h
0
0
default
3h
AINMUX1 AINMUX0 Reserved Reserved
0
0
0
0
0
0
0
0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
CLIP_L
CLIP_R
0
0
0
0
0
0
0
0
default
default
DAC (Address = 0010001)
Addr
Function
0h
Reserved
1h
Power and Muting
Control
2h
Channel A Analog
Headphone
Attenuation Control
default
default
default
3h
Channel B Analog
Headphone
Attenuation Control
default
4h
Channel A Digital
Volume Control
default
5h
Channel B Digital
Volume Control
default
16
7
6
5
4
3
2
1
0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
0
0
0
0
0
0
0
0
AMUTE
SZC1
SZC0
Reserved
PDNHP
PDNLN
PDN
CP_EN
1
1
0
1
0
0
1
0
HVOLA7
HVOLA6
HVOLA5
HVOLA4
HVOLA3
HVOLA2
HVOLA1
HVOLA0
0
0
0
0
0
0
0
0
HVOLB7
HVOLB6
HVOLB5
HVOLB4
HVOLB3
HVOLB2
HVOLB1
HVOLB0
0
0
0
0
0
0
0
0
DVOLA7
DVOLA6
DVOLA5
DVOLA4
DVOLA3
DVOLA2
DVOLA1
DVOLA0
0
0
0
0
0
0
0
0
DVOLB7
DVOLB6
DVOLB5
DVOLB4
DVOLB3
DVOLB2
DVOLB1
DVOLB0
0
0
0
0
0
0
0
0
DS544PP1
CS42L50
Addr
6h
Function
Tone Control
default
7h
Mode Control
default
8h
Reserved
default
9h
Reserved
Ah
Volume and Mixing
Control
Bh
Mode Control 2
default
default
default
DS544PP1
7
6
5
4
3
2
1
0
BB3
BB2
BB1
BB0
TB3
TB2
TB1
TB0
0
0
0
0
0
0
0
0
BBCF1
BBCF0
TBCF1
TBCF0
A=B
DEM1
DEM0
VCBYP
0
0
0
0
0
0
0
0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
0
0
0
1
0
0
0
0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
0
0
1
0
0
0
0
0
TC1
TC0
TC_EN
Reserved
ATAPI3
ATAPI2
ATAPI1
ATAPI0
0
0
0
0
1
0
0
1
MCLKDIV
LINE1
LINE0
Reserved
Reserved
DIF2
DIF1
DIF0
0
0
0
0
0
0
0
0
17
CS42L50
4. REGISTER DESCRIPTION
4.1
ADC (Address = 0010000)
4.1.1
I/O and Power Control (address 01h)
7
RESERVED
0
4.1.2
6
BOOST
0
5
AINMUX1
0
4
AINMUX0
0
3
RESERVED
0
2
RESERVED
0
1
PDN
1
0
CP_EN
0
20DB GAIN BOOST (BOOST)
Default = 0
0 - Disabled
1 - Enabled
Function:
Applies a 20dB digital gain to the input signal, regardless of the input path.
4.1.3
ANALOG INPUT MULTIPLEXER (AINMUX)
Default = 00
00 - Channel 1 direct to A/D
01 - Channel 2 direct to A/D
10 - Channel 2 through PGA to A/D
11 - Reserved
Function:
The analog input multiplexer selects the input channel as well as the input path associated with various
gain stages.
4.1.4
POWER DOWN (PDN)
Default - 1
0 - Disabled
1 - Enabled
Function:
The entire ADC device will enter a low-power state whenever this function is activated. The power-down
bit defaults to ‘enabled’ on power-up and must be disabled before normal operation will begin. The contents of the control registers are retained when this mode is enabled.
4.1.5
CONTROL PORT ENABLE (CP_EN)
Default = 0
0 - Disabled
1 - Enabled
Function:
The ADC will enter control port mode when this bit is enabled. This bit must be set prior to writing to the
control port.
18
DS544PP1
CS42L50
4.1.6
Interface Control (address 02h)
7
RESERVED
0
4.1.7
6
MCLKDIV
0
5
RATIO1
0
4
RATIO0
0
3
MASTER
0
2
DIF2
0
1
DIF1
0
0
DIF0
0
MASTER CLOCK DIVIDE (MCLKDIV)
Default = 0
0 - Disabled
1 - Enabled
Function:
Divides ADC MCLK by two prior to all other chip circuitry.
4.1.8
MASTER CLOCK RATIO (RATIO)
Default = 00
00 - 128x
01 - 192x
10 - 256x
11 - 384x
Function:
Sets the ratio of MCLK to LRCK for the ADC.
4.1.9
MASTER MODE (MASTER)
Default = 0
0 - Slave Mode
1 - Master Mode
Function:
Configures the CS42L50 for master or slave operation.
4.1.10 DIGITAL INTERFACE FORMAT (DIF)
Default = 000
000 - I2S, up to 24-bit data, data valid on positive edge of SCLK
001 - Left Justified, up to 24-bit data, data valid on positive edge of SCLK
010 - Reserved
011 - Right Justified, 16-bit data, data valid on positive edge of SCLK
100 - Right Justifed, 24-bit data, data valid on positive edge of SCLK
101 - Right Justified, 18-bit data, data valid on positive edge of SCLK
110 - Right Justified, 20-bit data, data valid on positive edge of SCLK
111 - Reserved
Function:
The required relationship between the Left/Right clock, serial clock and serial data is defined by the Digital
Interface Format and the options are detailed in Figures 25 through 30. It is recommended that the ADC
and the DAC are configured for the same Digital Interface Format.
DS544PP1
19
CS42L50
4.1.11 Analog I/O Control (address 03h)
7
MUTEL
0
6
MUTER
0
5
SZC1
1
4
SZC0
1
3
RESERVED
0
2
INDVC
0
1
L=R
0
0
HPFREEZE
0
4.1.12 LEFT/RIGHT CHANNEL MUTE (MUTE)
Default = 0
0 - Disabled
1 - Enabled
Function:
Digital mute of the left and right ADC channels.
4.1.13 SOFT RAMP AND ZERO CROSS ENABLE (SOFT/ZC)
Default = 11
00 - Change volume immediately
01 - Change volume at next zero cross time
10 - Change volume in 1dB steps
11 - Change volume in 1dB steps at every zero cross time
Function:
Soft Ramp Enable :
Soft Ramp allows level changes, both muting and attenuation, to be implemented via an incremental
ramp. Digital volume control is ramped from the current level to the new level at a rate of 1/8 dB per
left/right clock period. Analog volume control is ramped in 1 dB steps every 8 left/right clock periods in
Single Speed mode, and 1dB every 16 left/right clock periods in Double Speed mode.
Zero Cross Enable :
Zero Cross enable dictates that signal level changes, either by attenuation changes or muting, will occur
on a signal zero crossing to minimize audible artifacts. The requested level change will occur after a timeout period of 512 sample periods in Single Speed mode or 1024 sample periods in Double Speed mode
(approximately 10.7ms at 48kHz sample rate) if the signal does not encounter a zero crossing. The zero
cross function is independently monitored and implemented for each channel.
Soft Ramp and Zero Cross Enable :
Soft Ramp and Zero Cross enable dictates that signal level changes, either by attenuation changes or
muting, will occur in 1 dB steps and be implemented on a signal zero crossing. The level change will occur
after a timeout period of 512 sample periods in Single Speed mode or 1024 sample periods in Double
Speed mode (approximately 10.7 ms at 48kHz sample rate) if the signal does not encounter a zero crossing. The zero cross function is independently monitored and implemented for each channel.
20
DS544PP1
CS42L50
4.1.14 INDEPENDENT VOLUME CONTROL ENABLE (INDVC)
Default = 0
0 - Disabled
1 - Enabled
Function:
When this function is disabled, the AIN_L and AIN_R volume levels are controlled by the Left and Right
Volume Control registers and the Independent Analog Gain Control registers are ignored.
When this function is enabled, the volume levels are determined by both the Volume Control registers and
the Independent Analog Gain Control registers.
4.1.15 LEFT CHANNEL VOLUME = RIGHT CHANNEL VOLUME (L=R)
Default = 0
0 - Disabled
1 - Enabled
Function:
When this function is disabled, the left channel volume is determined by the left channel volume control
register and right channel volume is determined by the right channel volume control register.
When enabled, the left and right channel volumes are determined by the left channel volume control register and the right channel volume control register is ignored.
4.1.16 HIGH-PASS FILTER FREEZE (HPFREEZE)
Default = 0
0 - Frozen
1 - Enabled
Function:
The high-pass filter works by continuously subtracting a measure of the dc offset from the output of the
decimation filter. If the HPFREEZE bit is taken low during normal operation, the current value of the dc
offset is frozen and this dc offset will continue to be subtracted from the conversion result.
DS544PP1
21
CS42L50
4.1.17 Volume Control: Left Channel (address 04h) & Right Channel (address 05h)
7
VOL7
0
6
VOL6
0
5
VOL5
0
4
VOL4
0
3
VOL3
0
2
VOL2
0
1
VOL1
0
0
VOL0
0
Default = 0 (No attenuation)
Binary Code
00001010
00000111
00000000
11000100
10100110
Decimal Value
12
7
0
-60
-90
Volume Setting
+12 dB
+7 dB
0 dB
-60 dB
-90 dB
Function:
The volume control allows the user to alter the signal level in 1 dB increments from +12 to -96 dB, when
the INDVC bit is disabled. When INDVC is enabled, the volume control can be altered in 1 dB increments
from 0 to -96dB. Volume settings are decoded as shown above, using a 2’s complement code. The volume changes are implemented as dictated by the Soft and Zero Cross bits in the Analog I/O Control register. All volume settings less than -96dB are equivalent to muting the channel.
4.1.18 Left/Right Analog Gain (address 06h)
7
LVOL3
0
6
LVOL2
0
5
LVOL1
0
4
LVOL0
0
3
RVOL3
0
2
RVOL2
0
1
RVOL1
0
0
RVOL0
0
Default = 0 (No gain)
Binary Code
0000
0010
1010
1001
1100
Decimal Value
0
2
6
9
12
Volume Setting
0 dB
+2 dB
+6 dB
+9 dB
+12 dB
Function:
The level of the left and right analog channels can be adjusted in 1dB increments as dictated by the Soft
Ramp and Zero Cross bits from 0 to +12dB when routed through the PGA via the AINMUX bits. Levels
are decoded as shown above. Levels above +12dB are interpreted as +12dB.
22
DS544PP1
CS42L50
4.1.19 Clip Detection Status (address 07h)
7
RESERVED
0
6
RESERVED
0
5
RESERVED
0
4
RESERVED
0
3
RESERVED
0
2
RESERVED
0
1
CLIP_L
0
0
CLIP_R
0
Default = 0 (No clipping detected)
Function:
The Clip Flags indicate when there is an over-range condition anywhere in the CS42L50 internal signal
path. These bits are “sticky”. They constantly monitor the ADC signal path and are set to 1 when an overrange condition occurs. They are reset to 0 when read.
4.2
DAC (Address = 0010001)
4.2.1
Power and Muting Control (address 01h)
7
AMUTE
1
4.2.2
6
SZC1
1
5
SZC0
0
4
POR
1
3
PDNHP
0
2
PDNLN
0
1
PDN
1
0
CP_EN
0
AUTO-MUTE (AMUTE)
Default = 1
0 - Disabled
1 - Enabled
Function:
The Digital-to-Analog converter output will mute following the reception of 8192 consecutive audio samples of static 0 or -1. A single sample of non-static data will release the mute. Detection and muting is
done independently for each channel. The quiescent voltage on the output will be retained and the Mute
Control pin will go active during the mute period. The muting function is affected, similar to volume control
changes, by the Soft and Zero Cross bits in the Power and Muting Control register.
4.2.3
SOFT RAMP AND ZERO CROSS CONTROL (SZC)
Default = 10
00 - Immediate Change
01 - Zero Cross Digital and Analog
10 - Ramped Digital and Analog
11 - Reserved
Function:
Immediate Change
When Immediate Change is selected all level changes will take effect immediately in one step.
Zero Cross Digital and Analog
Zero Cross Enable dictates that signal level changes, either by attenuation changes or muting, will occur
on a signal zero crossing to minimize audible artifacts. The requested level change will occur after a
timeout period of 512 sample periods (10.7 ms at 48 kHz sample rate) if the signal does not encounter a
zero crossing. The zero cross function is independently monitored and implemented for each channel.
DS544PP1
23
CS42L50
Ramped Digital and Analog
Soft Ramp allows digital level changes, both muting and attenuation, to be implemented by incrementally
ramping, in 1/8 dB steps, from the current level to the new level at a rate of 1 dB per 8 left/right clock periods. Analog level changes will occur in 1 dB steps on a signal zero crossing. The analog level change
will occur after a timeout period of 512 sample periods (10.7 ms at 48 kHz sample rate) if the signal does
not encounter a zero crossing. The zero cross function is independently monitored and implemented for
each channel.
Note:
4.2.4
Ramped Digital and Analog is not available in Double Speed Mode.
POWER DOWN HEADPHONE AMPLIFIER (PDNHP)
Default = 0
0 - Disabled
1 - Enabled
Function:
The headphone amplifier will independently enter a low-power state when this function is enabled.
4.2.5
POWER DOWN LINE AMPLIFIER (PDNLN)
Default = 0
0 - Disabled
1 - Enabled
Function:
The line output amplifier will independently enter a low-power state when this function is enabled.
4.2.6
POWER DOWN (PDN)
Default = 1
0 - Disabled
1 - Enabled
Function:
The entire DAC device will enter a low-power state when this function is enabled, and the contents of the
control registers are retained in this mode. The power-down bit defaults to ‘enabled’ on power-up and
must be disabled before normal operation will begin.
4.2.7
CONTROL PORT ENABLE (CP_EN)
Default = 0
0 - Disabled
1 - Enabled
Function:
The DAC will enter control port mode when this bit is enabled. This bit must be set prior to writing to the
control port.
24
DS544PP1
CS42L50
4.2.8
Channel A Analog Headphone Attenuation Control (address 02h) (HVOLA)
4.2.9
Channel B Analog Headphone Attenuation Control (address 03h) (HVOLB)
7
HVOLx7
0
6
HVOLx6
0
5
HVOLx5
0
4
HVOLx4
0
3
HVOLx3
0
2
HVOLx2
0
1
HVOLx1
0
0
HVOLx0
0
Default = 0 dB (No attenuation)
Function:
The Analog Headphone Attenuation Control operates independently from the Digital Volume Control. The
Analog Headphone Attenuation Control registers allow attenuation of the headphone output signal for
each channel in 1 dB increments from 0 to -25 dB. Attenuation settings are decoded using a 2’s complement code, as shown in Table 1. The volume changes are implemented as dictated by the Soft and Zero
Cross bits in the Power and Muting Control register. All volume settings greater than zero are interpreted
as zero.
Note: The Analog Headphone Attenuation only affects the headphone outputs. When set for levels
greater than -10dB, the actual attenuation deviates from the register setting by more than 1 dB.
Binary Code
00000000
11110110
11110001
Decimal Value
0
-10
-15
Volume Setting
0 dB
-10 dB
-15 dB
Table 1. Example Analog Volume Settings
4.2.10 Channel A Digital Volume Control (address 04h) (DVOLA)
4.2.11 Channel B Digital Volume Control (address 05h) (DVOLB)
7
DVOLx7
0
6
DVOLx6
0
5
DVOLx5
0
4
DVOLx4
0
3
DVOLx3
0
2
DVOLx2
0
1
DVOLx1
0
0
DVOLx0
0
Default = 0 dB (No attenuation)
Function:
The Digital Volume Control registers allow independent control of the signal levels in 1 dB increments
from +18 to -96 dB. Volume settings are decoded using a 2’s complement code, as shown in Table 2.
The volume changes are implemented as dictated by the Soft and Zero Cross bits in the Power and Muting Control register. All volume settings less than -96 dB are equivalent to muting the channel via the
ATAPI bits (see Section 4.46).
Note:
DS544PP1
The digital volume control affects both the line outputs and the headphone outputs. Setting this
register to values greater than +18 dB will cause distortion in the audio outputs.
25
CS42L50
Binary Code
00001010
00000111
00000000
11000100
10100110
Decimal Value
12
7
0
-60
-90
Volume Setting
+12 dB
+7 dB
0 dB
-60 dB
-90 dB
Table 2. Example Digital Volume Settings
4.2.12 Tone Control (address 06h)
7
BB3
0
6
BB2
0
5
BB1
0
4
BB0
0
3
TB3
0
2
TB2
0
1
TB1
0
0
TB0
0
4.2.13 BASS BOOST LEVEL (BB)
Default = 0 dB (No Bass Boost)
Function:
The level of the shelving bass boost filter is set by Bass Boost Level. The level can be adjusted in 1 dB
increments from 0 to +12 dB of boost. Boost levels are decoded as shown in Table 3. Levels above
+12 dB are interpreted as +12 dB.
Binary Code
0000
0010
1010
1001
1100
Decimal Value
0
2
6
9
12
Boost Setting
0 dB
+2 dB
+6 dB
+9 dB
+12 dB
Table 3. Example Bass Boost Settings
4.2.14 TREBLE BOOST LEVEL (TB)
Default = 0 dB (No Treble Boost)
Function:
The level of the shelving treble boost filter is set by Treble Boost Level. The level can be adjusted in 1 dB
increments from 0 to +12 dB of boost. Boost levels are decoded as shown in Table 4. Levels above
+12 dB are interpreted as +12 dB.
Note:
26
Treble Boost is not available in Double Speed Mode.
DS544PP1
CS42L50
Binary Code
0000
0010
1010
1001
1100
Decimal Value
0
2
6
9
12
Boost Setting
0 dB
+2 dB
+6 dB
+9 dB
+12 dB
Table 4. Example Treble Boost Settings
4.2.15 Mode Control (address 07h)
7
BBCF1
0
6
BBCF0
0
5
TBCF1
0
4
TBCF0
0
3
A=B
0
2
DEM1
0
1
DEM0
0
0
VCBYP
0
4.2.16 BASS BOOST CORNER FREQUENCY (BBCF)
Default = 00
00 - 50 Hz
01 - 100 Hz
10 - 200 Hz
11 - Reserved
Function:
The bass boost corner frequency is user selectable as shown above.
4.2.17 TREBLE BOOST CORNER FREQUENCY (TBCF)
Default = 00
00 - 2 kHz
01 - 4 kHz
10 - 7 kHz
11 - Reserved
Function:
The treble boost corner frequency is user selectable as shown above.
Note:
Treble Boost is not available in Double Speed Mode.
4.2.18 CHANNEL A VOLUME = CHANNEL B VOLUME (A=B)
Default = 0
0 - Disabled
1 - Enabled
Function:
The AOUTA/HP_A and AOUTB/HP_B volume levels are independently controlled by the A and the B
Channel Volume Control Bytes when this function is disabled. The volume on both AOUTA/HP_A and
AOUTB/HP_B are determined by the A Channel Attenuation and Volume Control Bytes, and the B Channel Bytes are ignored when this function is enabled.
DS544PP1
27
CS42L50
4.2.19 DE-EMPHASIS CONTROL (DEM)
Default = 00
00 - Disabled
01 - 44.1 kHz
10 - 48 kHz
11 - 32 kHz
Function:
Selects the appropriate digital filter to maintain the standard 15 µs/50 µs digital de-emphasis filter response at 32, 44.1 or 48 kHz sample rates. (see Figure 31)
Note:
De-emphasis is not available in Double Speed Mode.
4.2.20 DIGITAL VOLUME CONTROL BYPASS (VCBYP)
Default = 0
0 - Disabled
1 - Enabled
Function:
The digital volume control section is bypassed when this function is enabled. This disables the digital volume control, muting, bass boost, treble boost, limiting and ATAPI functions. The analog headphone attenuation control will remain functional.
4.2.21 Volume and Mixing Control (address 0Ah)
7
TC1
0
6
TC0
0
5
TC_EN
0
4
LIM_EN
0
3
ATAPI3
1
2
ATAPI2
0
1
ATAPI1
0
0
ATAPI0
1
4.2.22 TONE CONTROL MODE (TC)
Default = 00
00 - All settings are taken from user registers
01 - 12 dB of Bass Boost at 100 Hz and 6 dB of Treble Boost at 7 kHz
10 - 8 dB of Bass Boost at 100 Hz and 4 dB of Treble Boost at 7 kHz
11 - 4 dB of Bass Boost at 100 Hz and 2 dB of Treble Boost at 7 kHz
Function:
The Tone Control Mode bits determine how the Bass Boost and Treble Boost features are configured.
The user defined settings from the Bass and Treble Boost Level and Corner Frequency registers are used
when these bits are set to ‘00’. Alternately, one of three pre-defined settings may be used.
4.2.23 TONE CONTROL ENABLE (TC_EN)
Default = 0
0 - Disabled
1 - Enabled
Function:
The Bass Boost and Treble Boost features are active when this function is enabled.
28
DS544PP1
CS42L50
4.2.24 ATAPI CHANNEL MIXING AND MUTING (ATAPI)
Default = 1001 - AOUTA/HP_A = L, AOUTB/HP_B = R (Stereo)
Function:
The CS42L50 implements the channel mixing functions of the ATAPI CD-ROM specification. Refer to
Table 5 and Figure 32 for additional information.
Note:
All mixing functions occur prior to the digital volume control.
ATAPI3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
ATAPI2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
ATAPI1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
ATAPI0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
AOUTA/HP_A
MUTE
MUTE
MUTE
MUTE
R
R
R
R
L
L
L
L
[(L+R)/2]
[(L+R)/2]
[(L+R)/2]
[(L+R)/2]
AOUTB/HP_B
MUTE
R
L
[(L+R)/2]
MUTE
R
L
[(L+R)/2]
MUTE
R
L
[(L+R)/2]
MUTE
R
L
[(L+R)/2]
Table 5. ATAPI Decode
4.2.25 Mode Control 2 (address 0Bh)
7
MCLKDIV
0
6
LINE1
0
5
LINE0
0
4
RESERVED
0
3
RESERVED
0
2
DIF2
0
1
DIF1
0
0
DIF0
0
4.2.26 MASTER CLOCK DIVIDE ENABLE (MCLKDIV)
Default = 0
0 - Disabled
1 - Enabled
Function:
The MCLKDIV bit enables a circuit which divides the externally applied MCLK signal by 2 prior to all other
DAC circuitry.
4.2.27 LINE AMPLIFIER GAIN COMPENSATION (LINE)
Default = 00
00 - 0.785 x VA
01 - 0.943 x VA
10 - Reserved
DS544PP1
29
CS42L50
11 - Line Mute
Function:
The Line Amplifier Gain Compensation bits allow the user to scale the full-scale line output level according
to the power supply voltage used. The full-scale line output level will be equal to {gain factor}xVA, where
{gain factor} is selected from options above.
The Line Mute option is available to allow muting of the line output when the headphone output is still in
use and the line amp is still powered up. To use this feature, first mute the outputs via the ATAPI bits.
Next, set the LINE GAIN to Line Mute. Finally, un-mute the outputs with the ATAPI bits. Following these
steps will ensure a click free mute.
4.2.28 DIGITAL INTERFACE FORMAT (DIF)
Default = 000 - Format 0 (I2S, up to 24-bit data)
Function:
The required relationship between the Left/Right clock, serial clock and serial data is defined by the Digital
Interface Format and the options are detailed in Figures 25-30. It is recommended that the ADC and the
DAC is configured for the same Digital Interface Format.
DIF2
0
0
0
0
1
1
1
1
DIF1
0
0
1
1
0
0
1
1
DIF0
0
1
0
1
0
1
0
1
DESCRIPTION
I2S, up to 24-bit data
Reserved
Left Justified, up to 24-bit data,
Right Justified, 24-bit data
Right Justified, 20-bit data
Right Justified, 16-bit data
Right Justified, 18-bit data
Identical to Format 0
Format
0
2
3
4
5
6
0
FIGURE
30
25
27
29
26
28
30
Table 6. Digital Interface Format
30
DS544PP1
CS42L50
5. PIN DESCRIPTIONS
Filter Capacitor
Filter Capacitor
Voltage Reference
Analog Input 2 Right
Analog Input 2 Left
Ground Reference
Analog Input 1 Right
Analog Input 1 Left
Quiescent Voltage
Voltage Reference
Quiescent Voltage
Headphone A Output
Headphone Amp Power
Headphone B Output
Pin Name
#
AFLTR
AFLTL
FILT+_ADC
AIN_R2
AIN_L2
REF_GND
AIN_R1
AIN_L1
VQ_ADC
FILT+_DAC
VQ_DAC
HP_A
VA_HP
HP_B
1
28
2
27
3
26
4
25
5
24
6
23
7
22
8
21
9
20
10
19
11
18
12
17
13
16
14
15
RST
SCL
SDA
LRCK
SDOUT
VA
GND
VL
SDIN
MCLK
SCLK
MUTEC
AOUTL
AOUTR
Reset
Control Port Clock
Control Port Data
Left/Right Clock
Serial Audio Data Output
Analog Power
Ground Reference
Interface Power
Serial Audio Data Input
Master Clock
Serial Clock
External Mute Control
Analog Output Left
Analog Output Right
Pin Description
VA
23
Analog Power (Input) - Positive power supply for the analog section. Refer to the Recommended Operating Conditions for appropriate voltages.
VL
21
Logic Power (Input) - Determines the required signal level for the digital input/output. Refer to the Recommended Operating Conditions for appropriate voltages.
VA_HP
13
Headphone Amp Power (Input) - Positive power supply for the headphone amplifier. Refer to the Recommended Operating Conditions for appropriate voltages.
VQ_ADC
VQ_DAC
REF_GND
9,11 Quiescent Voltage (Output) - Filter connection for internal quiescent voltage. VQ must be capacitively
coupled to analog ground, as shown in the Typical Connection Diagram. The nominal voltage level is
specified in the Analog Characteristics and Specifications section. VQ presents an appreciable source
impedance and any current drawn from this pin will alter device performance. However, VQ can be used
to bias the analog circuitry assuming there is no AC signal component and the DC current is less than
10uA.
6
Reference Ground (Input) - Ground reference for the internal sampling circuits and must be connected
to analog ground.
22
Ground (Input) - Ground reference. Should be connected to analog ground.
MCLK
19
Master Clock (Input) - Clock source for the delta-sigma modulator and digital filters.
SCLK
18
Serial Clock (Input/Output) - Serial clock for the serial audio interface.
LRCK
25
Left Right Clock (Input/Output) - Determines which channel, Left or Right, is currently active on the
serial audio data line. The frequency of the left/right clock must be at the audio sample rate, Fs.
SDIN
20
Serial Audio Data Input (Input) - Input for two’s complement serial audio data.
SDOUT
24
Serial Audio Data Output (Output) - Output for two’s complement serial audio data.
GND
Serial Audio
Interface
DS544PP1
31
CS42L50
Analog
Input/Output
AIN_Rx
AIN_Lx
4, 5, Analog Inputs (Input) - The full scale analog input level is specified in the Analog Input Characteristics
7,8 specification table.
AOUTL
AOUTR
15, Analog Outputs (Output) - The full scale analog line output level is specified in the Analog Output Char16 acteristics specifications table.
HP_A
12, Headphone Outputs (Output) - The full scale analog headphone output level is specified in the Analog
14 Output Characteristics specifications table.
HP_B
Control Port
Interface
SCL
27
Serial Control Port Clock (Input) - Serial clock for the serial control port. Requires an external pull-up
resistor to the logic interface voltage as shown in the Typical Connection Diagram.
SDA
26
Serial Control Data (Input/Output) - SDA is a data I/O line and requires an external pull-up resistor to
the logic interface voltage, as shown in the Typical Connection Diagram.
Control & Misc.
AFLTR
AFLTL
1,2 Anti-Aliasing Capacitors (Output) - Anti-aliasing capacitors for the left and right channels. An external
capacitor is required from AFLTR and AFLTL to ground, as shown in the Typical Connections Diagram.
AFLTR and AFLTL are not intended to supply external current, and any current drawn from these pins
will alter device performance.
FILT+_ADC
3
Positive Voltage Reference (Output) - Positive reference voltage for the internal sampling circuits.
Requires the capacitive decoupling to AGND as shown in the Typical Connection Diagram.
FILT+_DAC
10
Positive Voltage Reference (Output) - Positive reference voltage for the internal sampling circuits.
Requires the capacitive decoupling to AGND as shown in the Typical Connection Diagram.
MUTEC
17
Mute Control (Output) - The Mute Control pin goes low during power-up initialization, reset, muting,
power-down or if the master clock to left/right clock frequency ratio is incorrect. This pin is intended to be
used as a control for an external mute circuit to prevent the clicks and pops that can occur in any single
supply system. The use of an external mute circuit is not mandatory but may be desired for designs
requiring the absolute minimum in extraneous clicks and pops.
RST
28
Reset (Input) - The device enters a low power mode and all internal registers are reset to their default
settings when low. When high, the control port becomes operational and the CP_EN bits must be set and
the PDN bits must be cleared before normal operation will occur. The control port cannot be accessed
when Reset is low.
32
DS544PP1
CS42L50
6. APPLICATIONS
6.5
6.1
1) Hold RST low until the power supply, master
clock and left/right clock are stable. In this
state, the control port is reset to its default settings and VQ_ADC and VQ_DAC will remain
low.
Grounding and Power Supply
Decoupling
As with any high resolution converter, the
CS42L50 requires careful attention to power supply and grounding arrangements to optimize performance. Figure 4 shows the recommended power
arrangement with VA, VA_HP, and VL connected
to clean supplies. Decoupling capacitors should be
located as close to the device package as possible.
If desired, all supply pins may be connected to the
same supply, but a decoupling capacitor should still
be used on each supply pin.
6.2
Clock Modes
The CS42L50 operates in one of two clocking
modes. Single Speed Mode supports input sample
rates up to 50 kHz, and Double Speed Mode supports input sample rates up to 100 kHz. All clock
modes use 64x oversampling.
6.3
EP73xx Serial Port Interface
Special considerations must be made when interfacing the CS42L50 with the EP73xx series of
ARM processors. To receive stereo data from the
ADC, connect the MCLK pin (pin 19) of the
CS42L50 to the BUZ pin (pin 93) of the EP73xx,
and run the serial port in 64Fs mode with MCLK
generation enabled on the EP73xx. Any other configuration, either hardware or software modes, will
result in mono data being produced from the ADC
of the CS42L50.
6.4
De-Emphasis
The CS42L50 includes on-chip digital de-emphasis. Figure 31 shows the de-emphasis curve. The
frequency response of the de-emphasis curve will
scale proportionally with changes in sample rate,
Fs.
The de-emphasis feature is included to accommodate older audio recordings that utilize pre-emphasis equalization as a means of noise reduction.
DS544PP1
Recommended Power-up Sequence
2) Bring RST high. The device will remain in a
low power state and VQ_ADC and VQ_DAC
remain low. The control port will be accessible
at this time and the desired register settings can
be loaded after setting the CP_EN bits and
while keeping the PDN bits set to 1.
3) Once the registers are configured as desired, set
the PDN bits to 0, initiating the power-up sequence.
6.6
Optional External Headphone Mute
An external headphone mute circuit, as shown in
the CDB42L50 datasheet schematic, is recommended to minimize the effects of output transients
during power-up and power-down. This technique
minimizes the audio transients commonly produced by single-ended, single-supply converters
when it is implemented with external DC-blocking
capacitors connected in series with the audio outputs.
Use of the Mute Control function on the line outputs is recommended for designs requiring the absolute minimum in extraneous clicks and pops.
Also, use of the Mute Control function can enable
the system designer to achieve idle channel
noise/signal-to-noise ratios only limited by the external mute circuit. See the CDB42L50 datasheet
for a suggested mute circuit.
7. CONTROL PORT INTERFACE
The control port is used to load all the internal settings. The operation of the control port may be
completely asynchronous with the audio sample
rate. However, to avoid potential interference problems, the control port pins should remain static if
33
CS42L50
no operation is required. Please note that the internal registers are separated into two unique chip address blocks, one for the control of the ADC and
one for the control of the DAC portion of the codec.
SDA is a bidirectional data line. Data is clocked
into and out of the part by the clock, SCL, with the
clock to data relationship as shown in Figure 5.
The upper 6 bits of the 7 bit address field must be
001000. To communicate with the CS42L50, the
chip address should match that of the ADC
(0010000) or DAC (0010001) address. The eighth
bit of the address byte is the R/W bit (high for a
read, low for a write). If the operation is a write, the
34
next byte is the Memory Address Pointer, MAP,
which selects the register to be read or written. The
MAP is then followed by the data to be written. If
the operation is a read, the contents of the register
pointed to by the MAP will be output after the chip
address.
The CS42L50 has MAP auto increment capability,
enabled by the INCR bit in the MAP register. If
INCR is 0, then the MAP will stay constant for successive writes. If INCR is set to 1, then MAP will
auto increment after each byte is written, allowing
block reads or writes of successive registers.
DS544PP1
CS42L50
7.1
Memory Address Pointer (MAP)
7
INCR
0
7.2
6
Reserved
0
5
Reserved
0
4
Reserved
0
3
MAP3
0
2
MAP2
0
1
MAP1
0
0
MAP0
0
INCR (AUTO MAP INCREMENT ENABLE)
Default = ‘0’
0 - Disabled
1 - Enabled
7.3
MAP0-3 (MEMORY ADDRESS POINTER)
Default = ‘0000’
N o te 1
SDA
0 01 0 00
ADDR
AD 0
R /W
ACK
D AT A
1 -8
ACK
DATA
1-8
ACK
SCL
S ta rt
Stop
N o te: If o pe ration is a w rite, th is byte co nta in s the M em o ry A ddre ss P o inte r, M A P .
Figure 5. Control Port Timing
DS544PP1
35
0
0
-10
-10
-20
-20
-30
-30
Amplitude dB
Amplitude dB
CS42L50
-40
-50
-60
-70
-40
-50
-60
-70
-80
-80
-90
-90
-100
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
-100
0.4
0.42
0.44
0.46
Frequency (normalized to Fs)
Figure 6. Decimation Filter Single Speed Stopband
Rejection
-1
-3
Amplitude dB
Amplitude dB
-2
-4
-5
-6
-7
-8
-9
0.46
0.47
0.48
0.49
0.5
0.51
0.52
0.53
0.54
0
0.05
0.1
0.54
0.56
0.58
0.6
0.15
0.2
0.25
0.3
0.35
0.4
0.45
0.5
Frequency (normalized to Fs)
Frequency (normalized to Fs)
Figure 9. Decimation Filter Single Speed Passband
Ripple
0
0
-10
-10
-20
-20
-30
-30
Amplitude dB
Amplitude dB
0.52
0.3
0.25
0.2
0.15
0.1
0.05
0
-0.05
-0.1
-0.15
-0.2
-0.25
-0.3
0.55
Figure 8. Decimation Filter Single Speed Transition
Band (Detail)
-40
-50
-60
-70
-80
-40
-50
-60
-70
-80
-90
-90
-100
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
Frequency (normalized to Fs)
Figure 10. Decimation Filter Double Speed Stopband
Rejection
36
0.5
Figure 7. Decimation Filter Single Speed Transition
Band
0
-10
0.45
0.48
Frequency (normalized to Fs)
-100
0.4
0.43
0.46
0.49
0.52
0.55
0.58
0.61
0.64
0.67
Frequency (normalized to Fs)
Figure 11. Decimation Filter Double Speed Transition
Band
DS544PP1
CS42L50
0
-1
-3
Amplitude dB
Amplitude dB
-2
-4
-5
-6
-7
-8
-9
-10
0.45
0.46
0.47
0.48
0.49
0.5
0.51
0.52
0.53
0.54
0.55
Frequency (normalized to Fs)
Figure 12. Decimation Filter Double Speed Transition
Band (Detail)
DS544PP1
0.3
0.25
0.2
0.15
0.1
0.05
0
-0.05
-0.1
-0.15
-0.2
-0.25
-0.3
0
0.05
0.1
0.15
0.2
0.25
0.3
0.35
0.4
0.45
0.5
Frequency (normalized to Fs)
Figure 13. Decimation Filter Double Speed Passband
Ripple
37
CS42L50
Figure 15. Interpolation Filter Single Speed Transition
Band
Figure 16. Interpolation Filter Single Speed Transition
Band (Detail)
Figure 17. Interpolation Filter Single Speed Passband
Ripple
0
0
-10
-10
-20
-20
-30
-30
-40
-40
Amplitude dB
Amplitude dB
Figure 14. Interpolation Filter Single Speed Stopband
Rejection
-50
-60
-70
-60
-70
-80
-80
-90
-90
-100
-100
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
Frequency (normalized to Fs)
Figure 18. Interpolation Filter Double Speed Stopband
Rejection
38
-50
0.40
0.42
0.44
0.46
0.48
0.50
0.52
0.54
0.56
0.58
0.60
Frequency (normalized to Fs)
Figure 19. Interpolation Filter Double Speed Transition
Band
DS544PP1
CS42L50
0
0.30
-1
0.25
0.20
-2
0.15
0.10
-4
Amplitude dB
Amplitude dB
-3
-5
-6
-7
0.00
-0.05
-0.10
-0.15
-8
-0.20
-9
-0.25
-0.30
-10
0.45
0.05
0.46
0.47
0.48
0.49
0.50
0.51
0.52
0.53
0.54
0.55
0.00
0.05
0.10
Figure 20. Interpolation Filter Double Speed Transition
Band (Detail)
150 Ω
0.15
0.20
0.25
0.30
0.35
0.40
0.45
0.50
Frequency (normalized to Fs)
Frequency (normalized to Fs)
Figure 21. Interpolation Filter Double Speed Passband
Ripple
0.47 µF
AIN_xx
0.01 µF
GND
Figure 22. Line Input Test Circuit
DS544PP1
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CS42L50
3.3 µF
AOUTx
+
V
out
R
C
L
L
AGND
Figure 23. Line Output Test Load
220 µF
HP_x
+
V
out
R
L
C
L
AGND
Figure 24. Headphone Output Test Load
40
DS544PP1
CS42L50
L eft C ha nne l
LR C K
R ig h t C h an n el
SCLK
SDATA
M SB -1 -2 -3 -4 -5
+5 +4 +3 +2 +1 LS B
M SB -1 -2 -3 -4
+5 +4 +3 +2 +1 LS B
Left Justified, up to 24-Bit Data. Data Valid on Rising
Edge of SCLK.
Figure 25. Left Justified, up to 24-bit data
LRCK
R igh t C ha n ne l
L eft C ha nnel
SCLK
SDATA
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
32 cRight
lo cks
Justified, 16-Bit Data. Data Valid on Rising Edge of
SCLK. SCLK Must Have at Least 32 Cycles per LRCK
Period.
Figure 26. Right Justified, 16-bit data
LRCK
R ig ht C h a n n e l
L e ft C ha n ne l
SCLK
SDATA
0
23 22 21 20 19 18
7
6
5
4
3
2
1
0
23 22 21 20 19 18
7
6
5
4
3
2
1
0
3 2 c lo cks
Right Justified, 24-Bit Data. Data Valid on Rising Edge of
SCLK. SCLK Must Have at Least 48 Cycles per LRCK
Period.
Figure 27. Right Justified, 24-bit data
DS544PP1
41
CS42L50
LR C K
R igh t C h a nn el
Le ft C h an n el
SCLK
SDATA
1
0
17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
2
1
0
32 clocks
Right Justified, 18-Bit Data. Data Valid on Rising Edge of
SCLK. SCLK Must Have at Least 36 Cycles per LRCK
Period.
Figure 28. Right Justified, 18-bit data
LR C K
R ight C h anne l
Le ft C hann el
SCLK
SDATA
1
0
19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
32 clocks
Right Justified, 20-Bit Data. Data Valid on Rising Edge of
SCLK. SCLK Must Have at Least 40 Cycles per LRCK
Period.
Figure 29. Right Justified, 20-bit data
L eft C ha nne l
LR C K
R ig h t C h an n el
SCLK
SDATA
MSB -1 -2 -3 -4 -5
+5 +4 +3 +2 +1 LSB
MSB -1 -2 -3 -4
+5 +4 +3 +2 +1 LSB
I2S, up to 24-Bit Data. Data Valid on Rising Edge of
SCLK
Figure 30. I2S, up to 24-bit data
42
DS544PP1
CS42L50
Gain
dB
T1=50 µs
0dB
T2 = 15 µs
-10dB
F1
3.183 kHz
F2
Frequency
10.61 kHz
Figure 31. De-Emphasis Curve
Left Channel
Audio Data
A Channel
Digital
Volume
Control
EQ
MUTE
B Channel
Digital
Volume
Control
EQ
MUTE
AoutA/HP_A
Σ
Right Channel
Audio Data
AoutB/HP_B
Figure 32. ATAPI Block Diagram
DS544PP1
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CS42L50
8. PARAMETER DEFINITIONS
Total Harmonic Distortion + Noise (THD+N)
The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified
bandwidth (typically 10 Hz to 20 kHz), including distortion components. Expressed in decibels.
Dynamic Range
The ratio of the full scale rms value of the signal to the rms sum of all other spectral components over the
specified bandwidth. Dynamic range is a signal-to-noise measurement over the specified bandwidth
made with a -60 dBFS signal. 60 dB is then added to the resulting measurement to refer the measurement
to full scale. This technique ensures that the distortion components are below the noise level and do not
affect the measurement. This measurement technique has been accepted by the Audio Engineering Society, AES17-1991, and the Electronic Industries Association of Japan, EIAJ CP-307.
Interchannel Isolation
A measure of crosstalk between the left and right channels. Measured for each channel at the converter's
output with all zeros to the input under test and a full-scale signal applied to the other channel. Units in
decibels.
Interchannel Gain Mismatch
The gain difference between left and right channels. Units in decibels.
Gain Error
The deviation from the nominal full scale analog output for a full scale digital input.
Gain Drift
The change in gain value with temperature. Units in ppm/°C.
9. REFERENCES
1) "How to Achieve Optimum Performance from Delta-Sigma A/D & D/A Converters" by Steven Harris.
Paper presented at the 93rd Convention of the Audio Engineering Society, October 1992.
1) "The I2C-Bus Specification: Version 2.1" Philips Semiconductors, January 2000.
http://semiconductors.philips.com
44
DS544PP1
CS42L50
10. PACKAGE DIMENSIONS
Figure 33. Package Dimensions
DS544PP1
45
CS42L50
Figure 34. Package Top and Side Views
46
DS544PP1
CS42L50
Figure 35. Package Bottom View
DS544PP1
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