Panasonic MN655431SH Low power 8-bit cmos a/d converter for image processing Datasheet

A/D, D/C Converters for Image Signal Processing
MN655431SH
Low Power 8-Bit CMOS A/D Converter for Image Processing
Overview
The MN655431SH is an 8-bit CMOS analog-to-digital
converter with a maximum conversion rate of 15 MSPS.
It uses a half flash structure based on chopper comparators and achieves both high speed and low power consumption with multiplex processing.
It provides separate power supply pins for the circuits
driving the low-voltage digital output pins.
Features
Maximum conversion rate: 15 MSPS (min.)
Linearity error: ±0.5 LSB (typ.)
Differential linearity error: ±0.4 LSB (typ.)
Power supply voltage: 4.40 to 5.25 V
Power consumption: 90 mW (typ.)
Pin Assignment
DVDDL
DVSS
(LSB) D0
D1
D2
D3
D4
D5
D6
(MSB) D7
DVDD
CLK
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
DVSS
VRB
VRBS
AVSS
AVSS
VIN
AVDD
VRT
VRTS
AVDD
AVDD
DVDD
Applications
Digital television receivers
(TOP VIEW)
Digital video equipment
Digital image processing equipment
SSOP024-P-0300
1
MN655431SH
A/D, D/C Converters for Image Signal Processing
Lower comparator
(4 bits)
13
DVDD
AVDD
14
AVDD
15
VRTS
16
AVDD
VIN
VRT
17
18
19
AVSS
20
VRBS
AVSS
21
VRB
22
23
24
DVSS
Block Diagram
Lower comparator
(4 bits)
Reference
resistor
Encoder (4 bits)
Encoder (4 bits)
Lower comparator (4 bits)
Clock generator
Data latch
2
12
CLK
11
DVDD
10
D7(MSB)
9
D6
8
D5
D4
7
6
D3
5
D2
D1
4
3
D0(LSB)
DVSS
DVDDL
1
2
Encoder (4 bits)
A/D, D/C Converters for Image Signal Processing
MN655431SH
Pin Descriptions
Pin No.
1
Symbol
DVDDL
2
DVSS
3
D0
Digital output (LSB)
4
D1
Digital output
5
D2
Digital output
6
D3
Digital output
7
D4
Digital output
8
D5
Digital output
9
D6
Digital output
10
D7
11
DVDD
Function Description
Power supply for digital output circuits
Ground for digital circuits
Digital output (MSB)
Power supply for digital circuits
12
CLK
Sampling clock
13
DVDD
Power supply for digital circuits
14
AVDD
Power supply for analog circuits
15
AVDD
Power supply for analog circuits
16
VRTS
Power supply for reference voltage (TOP)
17
VRT
Reference voltage (TOP)
18
AVDD
19
VIN
20
AVSS
Ground for analog circuits
21
AVSS
Ground for analog circuits
22
VRBS
Power supply for reference voltage (BOTTOM)
23
VRB
Reference voltage (BOTTOM)
24
DVSS
Ground for digital circuits
Power supply for analog circuits
Analog input
Absolute Maximum Ratings
Ta=25˚C
Parameter
Power supply voltage
Symbol
VDD
Rating
– 0.3 to +7.0
Unit
V
Power supply voltage for digital outputs
DVDDL
– 0.3 to +VDD +0.3
V
VI
AVSS – 0.3 to VDD +0.3
V
Output voltage
VO
DVSS – 0.3 to VDD +0.3
V
Operating ambient temperature
Topr
–20 to +70
˚C
Storage temperature
Tstg
–55 to +125
˚C
Input voltage
3
MN655431SH
A/D, D/C Converters for Image Signal Processing
Recommended Operating Conditions
VDD=AVDD=DVDD=5.0V, DVDDL=3.5V, VSS=AVSS=DVSS=0V, Ta=25˚C
Parameter
Power supply voltage
Symbol
VDD
min
4.50
Power supply voltage for digital outputs
DVDDL
VIH
Digital input
"H" level
typ
5.00
max
5.25
Unit
V
3.4
3.6
V
2.4
VDD
V
voltage
"L" level
VIL
VSS
0.8
V
Reference voltage
"H" level
VRT
3.3
VDD
V
"L" level
VRB
VSS
1.5
"H" level pulse width
tWH
30
Clock
"L" level pulse width
Analog input voltage
Electrical Characteristics
Parameter
Power supply voltage
tWL
30
VAIN
VSS
ns
VDD
Symbol
IDD
Conditions
fCLK = 15 MHz
min
RES
typ
max
Unit
18
26
mA
8
bit
Linearity error
EL
fCLK=15MHz
±0.5
±1.3
LSB
Differential linearity error
ED
VRT=3.5V
±0.4
±0.7
LSB
Maximum conversion rate
Fc(max.)
15
fCLK
1
15
2
VRT –VRB
V
–2
mA
Clock frequency
4
V
VDD=AVDD=DVDD=5.0V, DVDDL=3.5V, AVSS=DVSS=0V, Ta=25˚C
(includes reference power supply)
Resolution
V
ns
VRB=1.5V
Analog input dynamic range
DR
Output
"H" level
IOH
VOH=DVDDL – 0.8V
current
"L" level
IOL
VOL= 0.4V
MSPS
2
MHz
mA
Output delay time
td
30
Analog input capacitance
CI
18
45
ns
pF
A/D, D/C Converters for Image Signal Processing
MN655431SH
Timing Chart
The chip samples the analog input at the falling edge of the clock signal and provides the corresponding digital
output 2.5 clock cycles later at the rising edge of the clock signal.
tWH
tWL
Clock
Analog input
Data output
N
N–3
N+1
N–2
N+2
N+3
N–1
N
N+4
N+1
td(30ns)
Note: The circles indicate analog signal sampling points.
5
MN655431SH
A/D, D/C Converters for Image Signal Processing
Package Dimensions (Unit:mm)
SSOP024-P-0300
6.5±0.2
24
13
+0.10
0.15 -0.05
7.5±0.2
5.5±0.2
1.0±0.2
(0.5)
0.5
0.2±0.1
1.6±0.3
12
0.1±0.1
1
1.5±0.2
0 to 10°
SEATING PLANE
6
0.5±0.2
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