LINER LTC5557 12-bit, 125msps/105msps/ 80msps low power dual adc Datasheet

Electrical Specifications Subject to Change
LTC2145-12/
LTC2144-12/LTC2143-12
12-Bit, 125Msps/105Msps/
80Msps Low Power Dual ADCs
FEATURES
DESCRIPTION
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The LTC®2145-12/LTC2144-12/LTC2143-12 are 2-channel
simultaneous sampling 12-bit A/D converters designed
for digitizing high frequency, wide dynamic range signals.
They are perfect for demanding communications applications with AC performance that includes 70.6dB SNR and
89dB spurious free dynamic range (SFDR). Ultralow jitter
of 0.08psRMS allows undersampling of IF frequencies with
excellent noise performance.
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2-Channel Simultaneously Sampling ADC
70.6dB SNR
89dB SFDR
Low Power: 183mW/144mW/109mW Total
92mW/72mW/55mW per Channel
Single 1.8V Supply
CMOS, DDR CMOS, or DDR LVDS Outputs
Selectable Input Ranges: 1VP-P to 2VP-P
800MHz Full Power Bandwidth S/H
Optional Data Output Randomizer
Optional Clock Duty Cycle Stabilizer
Shutdown and Nap Modes
Serial SPI Port for Configuration
64-Pin (9mm × 9mm) QFN Package
DC specs include ±0.3LSB INL (typ), ±0.1LSB DNL (typ)
and no missing codes over temperature. The transition
noise is 0.3LSBRMS.
The digital outputs can be either full rate CMOS, double
data rate CMOS, or double data rate LVDS. A separate
output power supply allows the CMOS output swing to
range from 1.2V to 1.8V.
APPLICATIONS
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The ENC+ and ENC– inputs may be driven differentially
or single-ended with a sine wave, PECL, LVDS, TTL, or
CMOS inputs. An optional clock duty cycle stabilizer allows high performance at full speed for a wide range of
clock duty cycles.
Communications
Cellular Base Stations
Software Defined Radios
Portable Medical Imaging
Multi-Channel Data Acquisition
Nondestructive Testing
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
TYPICAL APPLICATION
1.8V
VDD
2-Tone FFT, fIN = 70MHz and 69MHz
1.8V
OVDD
0
–10
–20
CH 2
ANALOG
INPUT
D1_11
•
•
•
D1_0
12-BIT
ADC CORE
S/H
12-BIT
ADC CORE
S/H
OUTPUT
DRIVERS
D2_11
•
•
•
D2_0
–30
CMOS
OR
LVDS
OUTPUTS
AMPLITUDE (dBFS)
CH 1
ANALOG
INPUT
–40
–50
–60
–70
–80
–90
–100
–110
–120
125MHz
0
CLOCK
CONTROL
CLOCK
10
30
20
40
FREQUENCY (MHz)
50
60
21854312 TA01b
21454312 TA01a
GND
OGND
21454312p
1
LTC2145-12/
LTC2144-12/LTC2143-12
ABSOLUTE MAXIMUM RATINGS
(Notes 1, 2)
Supply Voltages (VDD, OVDD) ....................... –0.3V to 2V
Analog Input Voltage (AIN+, AIN–,
PAR/SER, SENSE) (Note 3) .......... –0.3V to (VDD + 0.2V)
Digital Input Voltage (ENC+, ENC–, CS,
SDI, SCK) (Note 4) .................................... –0.3V to 3.9V
SDO (Note 4) ............................................ –0.3V to 3.9V
Digital Output Voltage ................ –0.3V to (OVDD + 0.3V)
Operating Temperature Range
LTC2145C, LTC2144C, LTC2143C............. 0°C to 70°C
LTC2145I, LTC2144I, LTC2143I ............ –40°C to 85°C
Storage Temperature Range................... –65°C to 150°C
PIN CONFIGURATIONS
FULL RATE CMOS OUTPUT MODE
DOUBLE DATA RATE CMOS OUTPUT MODE
TOP VIEW
64 VDD
63 SENSE
62 VREF
61 SDO
60 OF1
59 OF2
58 D1_11
57 D1_10
56 D1_9
55 D1_8
54 D1_7
53 D1_6
52 D1_5
51 D1_4
50 D1_3
49 D1_2
64 VDD
63 SENSE
62 VREF
61 SDO
60 OF2_1
59 DNC
58 D1_10_11
57 DNC
56 D1_8_9
55 DNC
54 D1_6_7
53 DNC
52 D1_4_5
51 DNC
50 D1_2_3
49 DNC
TOP VIEW
VDD 1
VCM1 2
GND 3
AIN1+ 4
AIN1– 5
GND 6
REFH 7
REFL 8
REFH 9
REFL 10
PAR/SER 11
AIN2+ 12
AIN2– 13
GND 14
VCM2 15
VDD 16
65
GND
48 D1_0_1
47 DNC
46 DNC
45 DNC
44 DNC
43 DNC
42 OVDD
41 OGND
40 CLKOUT+
39 CLKOUT–
38 D2_10_11
37 DNC
36 D2_8_9
35 DNC
34 D2_6_7
33 DNC
VDD 17
ENC+ 18
ENC– 19
CS 20
SCK 21
SDI 22
DNC 23
DNC 24
DNC 25
DNC 26
DNC 27
D2_0_1 28
DNC 29
D2_2_3 30
DNC 31
D2_4_5 32
65
GND
48 D1_1
47 D1_0
46 DNC
45 DNC
44 DNC
43 DNC
42 OVDD
41 OGND
40 CLKOUT+
39 CLKOUT–
38 D2_11
37 D2_10
36 D2_9
35 D2_8
34 D2_7
33 D2_6
VDD 17
ENC+ 18
ENC– 19
CS 20
SCK 21
SDI 22
DNC 23
DNC 24
DNC 25
DNC 26
D2_0 27
D2_1 28
D2_2 29
D2_3 30
D2_4 31
D2_5 32
VDD 1
VCM1 2
GND 3
AIN1+ 4
AIN1– 5
GND 6
REFH 7
REFL 8
REFH 9
REFL 10
PAR/SER 11
AIN2+ 12
AIN2– 13
GND 14
VCM2 15
VDD 16
UP PACKAGE
64-LEAD (9mm × 9mm) PLASTIC QFN
TJMAX = 150°C, θJA = 20°C/W
EXPOSED PAD (PIN 65) IS GND, MUST BE SOLDERED TO PCB
UP PACKAGE
64-LEAD (9mm s 9mm) PLASTIC QFN
TJMAX = 150°C, θJA = 20°C/W
EXPOSED PAD (PIN 65) IS GND, MUST BE SOLDERED TO PCB
21454312p
2
LTC2145-12/
LTC2144-12/LTC2143-12
PIN CONFIGURATIONS
DOUBLE DATA RATE LVDS OUTPUT MODE
64 VDD
63 SENSE
62 VREF
61 SDO
60 OF2_1+
59 OF2_1–
58 D1_10_11+
57 D1_10_11–
56 D1_8_9+
55 D1_8_9–
54 D1_6_7+
53 D1_6_7–
52 D1_4_5+
51 D1_4_5–
50 D1_2_3+
49 D1_2_3–
TOP VIEW
VDD 1
VCM1 2
GND 3
AIN1+ 4
AIN1– 5
GND 6
REFH 7
REFL 8
REFH 9
REFL 10
PAR/SER 11
AIN2+ 12
AIN2– 13
GND 14
VCM2 15
VDD 16
48 D1_0_1+
47 D1_0_1–
46 DNC
45 DNC
44 DNC
43 DNC
42 OVDD
41 OGND
40 CLKOUT+
39 CLKOUT–
38 D2_10_11+
37 D2_10_11–
36 D2_8_9+
35 D2_8_9–
34 D2_6_7+
33 D2_6_7–
VDD 17
ENC+ 18
ENC– 19
CS 20
SCK 21
SDI 22
DNC 23
DNC 24
DNC 25
DNC 26
D2_0_1– 27
D2_0_1+ 28
D2_2_3– 29
D2_2_3+ 30
D2_4_5– 31
D2_4_5+ 32
65
GND
UP PACKAGE
64-LEAD (9mm s 9mm) PLASTIC QFN
TJMAX = 150°C, θJA = 20°C/W
EXPOSED PAD (PIN 65) IS GND, MUST BE SOLDERED TO PCB
ORDER INFORMATION
LEAD FREE FINISH
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC2145CUP-12#PBF
LTC2145CUP-12#TRPBF
LTC2145UP-12
64-Lead (9mm × 9mm) Plastic QFN
0°C to 70°C
LTC2145IUP-12#PBF
LTC2145IUP-12#TRPBF
LTC2145UP-12
64-Lead (9mm × 9mm) Plastic QFN
–40°C to 85°C
LTC2144CUP-12#PBF
LTC2144CUP-12#TRPBF
LTC2144UP-12
64-Lead (9mm × 9mm) Plastic QFN
0°C to 70°C
LTC2144IUP-12#PBF
LTC2144IUP-12#TRPBF
LTC2144UP-12
64-Lead (9mm × 9mm) Plastic QFN
–40°C to 85°C
LTC2143CUP-12#PBF
LTC2143CUP-12#TRPBF
LTC2143UP-12
64-Lead (9mm × 9mm) Plastic QFN
0°C to 70°C
LTC2143IUP-12#PBF
LTC2143IUP-12#TRPBF
LTC2143UP-12
64-Lead (9mm × 9mm) Plastic QFN
–40°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
21454312p
3
LTC2145-12/
LTC2144-12/LTC2143-12
CONVERTER CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 5)
LTC2145-12
PARAMETER
CONDITIONS
Resolution (No Missing Codes)
Integral Linearity Error
MIN
l
Differential Analog Input (Note 6) l
LTC2144-12
TYP
MAX
MIN
TBD
±0.3
TBD
12
LTC2143-12
TYP
MAX
MIN
TYP
MAX
UNITS
TBD
±0.3
TBD
TBD
±0.3
TBD
LSB
12
12
Bits
Differential Linearity Error
Differential Analog Input
l
–1
±0.1
1
–1
±0.1
1
–1
±0.1
1
LSB
Offset Error
(Note 7)
l
–9
±1.5
9
–9
±1.5
9
–9
±1.5
9
mV
Gain Error
Internal Reference
External Reference
l
–2.1
±1.5
–0.6
0.9
–2.1
±1.5
–0.6
0.9
–2.1
±1.5
–0.6
0.9
%FS
%FS
Offset Drift
Full-Scale Drift
Internal Reference
External Reference
Gain Matching
±10
±10
±10
μV/°C
±30
±10
±30
±10
±30
±10
ppm/°C
ppm/°C
±0.3
±0.3
±0.3
%FS
Offset Matching
±1.5
±1.5
±1.5
mV
Transition Noise
0.31
0.32
0.30
LSBRMS
ANALOG INPUT
The l denotes the specifications which apply over the full operating temperature range, otherwise
specifications are at TA = 25°C. (Note 5)
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
VIN
Analog Input Range (AIN+ – AIN–)
VIN(CM)
Analog Input Common Mode (AIN+ + AIN–)/2
VSENSE
External Voltage Reference Applied to SENSE External Reference Mode
IINCM
Analog Input Common Mode Current
Per Pin, 125Msps
Per Pin, 105Msps
Per Pin, 80Msps
IIN1
Analog Input Leakage Current (No Encode)
0 < AIN+, AIN– < VDD
l
–1
1
μA
IIN2
PAR/SER Input Leakage Current
0 < PAR/SER < VDD
l
–3
3
μA
0.625 < SENSE < 1.3V
l
–6
6
μA
IIN3
SENSE Input Leakage Current
tAP
Sample-and-Hold Acquisition Delay Time
tJITTER
Sample-and-Hold Acquisition Delay Jitter
CMRR
Analog Input Common Mode Rejection Ratio
BW-3B
Full-Power Bandwidth
1.7V < VDD < 1.9V
l
Differential Analog Input (Note 8)
l
0.7
VCM
1.25
V
l
0.625
1.250
1.300
V
1 to 2
155
130
100
0
Single-Ended Encode
Differential Encode
Figure 6 Test Circuit
VP-P
0.08
0.10
μA
μA
μA
ns
psRMS
psRMS
80
dB
800
MHz
21454312p
4
LTC2145-12/
LTC2144-12/LTC2143-12
DYNAMIC ACCURACY
The l denotes the specifications which apply over the full operating temperature range,
otherwise specifications are at TA = 25°C. AIN = –1dBFS. (Note 5)
LTC2145-12
SYMBOL
PARAMETER
CONDITIONS
SNR
Signal-to-Noise Ratio
5MHz Input
70MHz Input
140MHz Input
SFDR
S/(N+D)
MIN
TYP
l
TBD
Spurious Free Dynamic Range 5MHz Input
2nd or 3rd Harmonic
70MHz Input
140MHz Input
l
Spurious Free Dynamic Range 5MHz Input
4th Harmonic or Higher
70MHz Input
140MHz Input
Signal-to-Noise Plus
Distortion Ratio
5MHz Input
70MHz Input
140MHz Input
Crosstalk
10MHz Input
MAX
LTC2144-12
MIN
TYP
70.6
70.5
70.3
TBD
TBD
89
88
84
l
TBD
l
TBD
LTC2143-12
MIN
TYP
70.5
70.4
70.2
TBD
70.8
70.7
70.5
dBFS
dBFS
dBFS
TBD
89
88
84
TBD
89
88
84
dBFS
dBFS
dBFS
95
95
95
TBD
95
95
95
TBD
95
95
95
dBFS
dBFS
dBFS
70.5
70.4
70
TBD
70.4
70.3
69.9
TBD
70.7
70.6
70.2
dBFS
dBFS
dBFS
–110
dBc
–110
MAX
–110
MAX
UNITS
INTERNAL REFERENCE CHARACTERISTICS
The l denotes the specifications which apply over the
full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5)
PARAMETER
CONDITIONS
VCM Output Voltage
IOUT = 0
MIN
TYP
MAX
0.5 • VDD – 25mV
0.5 • VDD
0.5 • VDD + 25mV
VCM Output Temperature Drift
±25
VCM Output Resistance
–600μA < IOUT < 1mA
VREF Output Voltage
IOUT = 0
VREF Output Temperature Drift
1.250
±25
VREF Output Resistance
–400μA < IOUT < 1mA
VREF Line Regulation
1.7V < VDD < 1.9V
7
0.6
V
ppm/°C
4
1.225
UNITS
Ω
1.275
V
ppm/°C
Ω
mV/V
21454312p
5
LTC2145-12/
LTC2144-12/LTC2143-12
DIGITAL INPUTS AND OUTPUTS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 5)
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
ENCODE INPUTS (ENC+, ENC– )
Differential Encode Mode (ENC– Not Tied to GND)
VID
Differential Input Voltage
(Note 8)
l
0.2
VICM
Common Mode Input Voltage
Internally Set
Externally Set (Note 8)
l
1.1
1.6
V
V
l
0.2
3.6
V
V
1.2
VIN
Input Voltage Range
ENC+, ENC– to GND
RIN
Input Resistance
(See Figure 10)
10
kΩ
CIN
Input Capacitance
(Note 8)
3.5
pF
Single-Ended Encode Mode (ENC– Tied to GND)
VIH
High Level Input Voltage
VDD = 1.8V
l
VIL
Low Level Input Voltage
VDD = 1.8V
l
VIN
Input Voltage Range
ENC+ to GND
l
RIN
Input Resistance
(See Figure 11)
30
kΩ
CIN
Input Capacitance
(Note 8)
3.5
pF
1.2
V
0.6
0
3.6
V
V
DIGITAL INPUTS (CS, SDI, SCK in Serial or Parallel Programming Mode. SDO in Parallel Programming Mode)
VIH
High Level Input Voltage
VDD = 1.8V
l
VIL
Low Level Input Voltage
VDD = 1.8V
l
l
IIN
Input Current
VIN = 0V to 3.6V
CIN
Input Capacitance
(Note 8)
1.3
V
–10
0.6
V
10
μA
3
pF
200
Ω
SDO OUTPUT (Serial Programming Mode. Open-Drain Output. Requires 2kΩ Pull-Up Resistor if SDO is Used)
ROL
Logic Low Output Resistance to GND
VDD = 1.8V, SDO = 0V
IOH
Logic High Output Leakage Current
SDO = 0V to 3.6V
COUT
Output Capacitance
(Note 8)
l
–10
10
μA
3
pF
1.790
V
DIGITAL DATA OUTPUTS (CMOS MODES: FULL DATA RATE AND DOUBLE DATA RATE)
OVDD = 1.8V
VOH
High Level Output Voltage
IO = –500μA
l
VOL
Low Level Output Voltage
IO = 500μA
l
1.750
0.010
0.050
V
OVDD = 1.5V
VOH
High Level Output Voltage
IO = –500μA
1.488
V
VOL
Low Level Output Voltage
IO = 500μA
0.010
V
OVDD = 1.2V
VOH
High Level Output Voltage
IO = –500μA
1.185
V
VOL
Low Level Output Voltage
IO = 500μA
0.010
V
DIGITAL DATA OUTPUTS (LVDS MODE)
VOD
Differential Output Voltage
100Ω Differential Load, 3.5mA Mode
100Ω Differential Load, 1.75mA Mode
l
247
350
175
454
VOS
Common Mode Output Voltage
100Ω Differential Load, 3.5mA Mode
100Ω Differential Load, 1.75mA Mode
l
1.125
1.250
1.250
1.375
RTERM
On-Chip Termination Resistance
Termination Enabled, OVDD = 1.8V
100
mV
mV
V
V
Ω
21454312p
6
LTC2145-12/
LTC2144-12/LTC2143-12
POWER REQUIREMENTS
The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 9)
LTC2145-12
SYMBOL PARAMETER
CONDITIONS
LTC2144-12
LTC2143-12
MIN
TYP
MAX
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
CMOS Output Modes: Full Data Rate and Double Data Rate
VDD
Analog Supply Voltage
(Note 10)
l
1.7
1.8
1.9
1.7
1.8
1.9
1.7
1.8
1.9
V
OVDD
Output Supply Voltage
(Note 10)
l
1.1
1.8
1.9
1.1
1.8
1.9
1.1
1.8
1.9
V
IVDD
Analog Supply Current
DC Input
Sine Wave Input
l
101.5
102.2
TBD
79.8
80.3
TBD
60.4
60.9
TBD
mA
mA
IOVDD
Digital Supply Current
Sine Wave Input, OVDD = 1.2V
7.3
PDISS
Power Dissipation
l
DC Input
Sine Wave Input, OVDD = 1.2V
183
193
TBD
6.2
4.7
144
152
TBD
mA
109
115
TBD
mW
mW
LVDS Output Mode
VDD
Analog Supply Voltage
(Note 10)
l
1.7
1.8
1.9
1.7
1.8
1.9
1.7
1.8
1.9
V
OVDD
Output Supply Voltage
(Note 10)
l
1.7
1.8
1.9
1.7
1.8
1.9
1.7
1.8
1.9
V
IVDD
Analog Supply Current
Sine Input, 1.75mA Mode
Sine Input, 3.5mA Mode
l
103.4
104.6
TBD
81.6
82.8
TBD
62.1
63.4
TBD
mA
mA
Digital Supply Current
(0VDD = 1.8V)
Sine Input, 1.75mA Mode
Sine Input, 3.5mA Mode
l
30.6
57.9
TBD
30.3
57.6
TBD
30.1
57.3
TBD
mA
mA
Power Dissipation
Sine Input, 1.75mA Mode
Sine Input, 3.5mA Mode
l
241
293
TBD
201
253
TBD
166
217
TBD
mW
mW
IOVDD
PDISS
All Output Modes
PSLEEP
Sleep Mode Power
1
1
1
mW
PNAP
Nap Mode Power
16
16
16
mW
PDIFFCLK
Power Increase with Differential Encode Mode Enabled
(No increase for Nap or Sleep Modes)
20
20
20
mW
TIMING CHARACTERISTICS
The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 5)
LTC2145-12
SYMBOL
PARAMETER
CONDITIONS
MIN
fS
Sampling Frequency
(Note 10)
l
1
3.8
2
3.8
2
tL
ENC Low Time (Note 8)
Duty Cycle Stabilizer Off
Duty Cycle Stabilizer On
l
l
tH
ENC High Time (Note 8)
Duty Cycle Stabilizer Off
Duty Cycle Stabilizer On
l
l
tAP
Sample-and-Hold
Acquisition Delay Time
SYMBOL
PARAMETER
TYP
LTC2144-12
MAX
MIN
125
1
4
4
500
500
4.52
2
4
4
500
500
4.52
2
0
TYP
LTC2143-12
MAX
MIN
105
1
4.76
4.76
500
500
5.93
2
4.76
4.76
500
500
5.93
2
0
CONDITIONS
TYP
MAX
UNITS
80
MHz
6.25
6.25
500
500
ns
ns
6.25
6.25
500
500
ns
ns
0
ns
MIN
TYP
MAX
UNITS
Digital Data Outputs (CMOS Modes: Full Data Rate and Double Data Rate)
tD
ENC to Data Delay
CL = 5pF (Note 8)
l
1.1
1.7
3.1
ns
1
1.4
2.6
ns
0
0.3
0.6
ns
tC
ENC to CLKOUT Delay
CL = 5pF (Note 8)
l
tSKEW
DATA to CLKOUT Skew
tD – tC (Note 8)
l
Pipeline Latency
Full Data Rate Mode
Double Data Rate Mode
6
6.5
Cycles
Cycles
21454312p
7
LTC2145-12/
LTC2144-12/LTC2143-12
TIMING CHARACTERISTICS
The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 5)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Digital Data Outputs (LVDS Mode)
tD
ENC to Data Delay
CL = 5pF (Note 8)
l
1.1
1.8
3.2
ns
tC
ENC to CLKOUT Delay
CL = 5pF (Note 8)
l
1
1.5
2.7
ns
tSKEW
DATA to CLKOUT Skew
tD – tC (Note 8)
l
0
0.3
0.6
ns
Pipeline Latency
6.5
Cycles
SPI Port Timing (Note 8)
l
l
40
250
ns
ns
CS to SCK Setup Time
l
5
ns
tH
SCK to CS Setup Time
l
5
ns
tDS
SDI Setup Time
l
5
ns
tDH
SDI Hold Time
l
5
tDO
SCK Falling to SDO Valid
tSCK
SCK Period
tS
Write Mode
Readback Mode, CSDO = 20pF, RPULLUP = 2k
Readback Mode, CSDO = 20pF, RPULLUP = 2k
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All voltage values are with respect to GND with GND and OGND
shorted (unless otherwise noted).
Note 3: When these pin voltages are taken below GND or above VDD, they
will be clamped by internal diodes. This product can handle input currents
of greater than 100mA below GND or above VDD without latchup.
Note 4: When these pin voltages are taken below GND they will be
clamped by internal diodes. When these pin voltages are taken above VDD
they will not be clamped by internal diodes. This product can handle input
currents of greater than 100mA below GND without latchup.
Note 5: VDD = OVDD = 1.8V, fSAMPLE = 125MHz (LTC2145), 105MHz
(LTC2144), or 80MHz (LTC2143), LVDS outputs, differential ENC+/ENC– =
2VP-P sine wave, input range = 2VP-P with differential drive, unless
otherwise noted.
l
ns
125
ns
Note 6: Integral nonlinearity is defined as the deviation of a code from a
best fit straight line to the transfer curve. The deviation is measured from
the center of the quantization band.
Note 7: Offset error is the offset voltage measured from –0.5 LSB when
the output code flickers between 0000 0000 0000 and 1111 1111 1111 in
2’s complement output mode.
Note 8: Guaranteed by design, not subject to test.
Note 9: VDD = 1.8V, fSAMPLE = 125MHz (LTC2145), 105MHz (LTC2144),
or 80MHz (LTC2143), CMOS outputs, ENC+ = single-ended 1.8V square
wave, ENC– = 0V, input range = 2VP-P with differential drive, 5pF load on
each digital output unless otherwise noted. The supply current and power
dissipation specifications are totals for the entire IC, not per channel.
Note 10: Recommended operating conditions.
21454312p
8
LTC2145-12/
LTC2144-12/LTC2143-12
TIMING DIAGRAMS
Full Rate CMOS Output Mode Timing
All Outputs Are Single-Ended and Have CMOS Levels
tAP
CH 1
ANALOG
INPUT
A+4
A+2
A
A+3
tAP
CH 2
ANALOG
INPUT
A+1
B+4
B+2
B
B+3
tH
B+1
tL
ENC–
ENC+
tD
D1_0 - D1_11, OF1
A–6
A–5
A–4
A–3
A–2
D2_0 - D2_11, OF2
B–6
B–5
B–4
B–3
B–2
tC
CLKOUT +
CLKOUT –
21454312 TD01
Double Data Rate CMOS Output Mode Timing
All Outputs Are Single-Ended and Have CMOS Levels
tAP
CH 1
ANALOG
INPUT
A+3
tAP
CH 2
ANALOG
INPUT
A+4
A+2
A
A+1
B+4
B+2
B
B+3
tH
B+1
tL
ENC–
ENC+
tD
tD
BIT 0
A-6
BIT 1
A-6
BIT 0
A-5
BIT 1
A-5
BIT 0
A-4
BIT 1
A-4
BIT 0
A-3
BIT 1
A-3
BIT 0
A-2
D1_10_11
BIT 10
A-6
BIT 11
A-6
BIT 10
A-5
BIT 11
A-5
BIT 10
A-4
BIT 11
A-4
BIT 10
A-3
BIT 11
A-3
BIT 10
A-2
D2_0_1
BIT 0
B-6
BIT 1
B-6
BIT 0
B-5
BIT 1
B-5
BIT 0
B-4
BIT 1
B-4
BIT 0
B-3
BIT 1
B-3
BIT 0
B-2
BIT 10
B-6
BIT 11
B-6
BIT 10
B-5
BIT 11
B-5
BIT 10
B-4
BIT 11
B-4
BIT 10
B-3
BIT 11
B-3
BIT 10
B-2
OF
B-6
OF
A-6
OF
B-5
OF
A-5
OF
B-4
OF
A-4
OF
B-3
OF
A-3
OF
B-2
D1_0_1
••
•
••
•
D2_10_11
OF2_1
CLKOUT+
CLKOUT –
tC
tC
21454312 TD02
21454312p
9
LTC2145-12/
LTC2144-12/LTC2143-12
TIMING DIAGRAMS
Double Data Rate LVDS Output Mode Timing
All Outputs Are Differential and Have LVDS Levels
tAP
CH 1
ANALOG
INPUT
A+4
A+2
A
A+3
tAP
CH 2
ANALOG
INPUT
A+1
B+4
B+2
B
B+3
tH
B+1
tL
ENC–
ENC+
tD
D1_0_1+
D1_0_1–
tD
BIT 0
A-6
BIT 1
A-6
BIT 0
A-5
BIT 1
A-5
BIT 0
A-4
BIT 1
A-4
BIT 0
A-3
BIT 1
A-3
BIT 0
A-2
BIT 10
A-6
BIT 11
A-6
BIT 10
A-5
BIT 11
A-5
BIT 10
A-4
BIT 11
A-4
BIT 10
A-3
BIT 11
A-3
BIT 10
A-2
BIT 0
B-6
BIT 1
B-6
BIT 0
B-5
BIT 1
B-5
BIT 0
B-4
BIT 1
B-4
BIT 0
B-3
BIT 1
B-3
BIT 0
B-2
BIT 10
B-6
BIT 11
B-6
BIT 10
B-5
BIT 11
B-5
BIT 10
B-4
BIT 11
B-4
BIT 10
B-3
BIT 11
B-3
BIT 10
B-2
OF
B-6
OF
A-6
OF
B-5
OF
A-5
OF
B-4
OF
A-4
OF
B-3
OF
A-3
OF
B-2
••
•
D1_10_11+
D1_10_11–
D2_0_1+
D2_0_1–
••
•
D2_10_11+
D2_10_11–
OF2_1+
OF2_1–
tC
tC
CLKOUT+
CLKOUT –
21454312 TD03
SPI Port Timing (Readback Mode)
tDS
tS
tDH
tSCK
tH
CS
SCK
tDO
SDI
R/W
A6
A5
A4
A3
A2
A1
A0
SDO
XX
D7
HIGH IMPEDANCE
XX
D6
XX
D5
XX
D4
XX
D3
XX
D2
XX
XX
D1
D0
SPI Port Timing (Write Mode)
CS
SCK
SDI
R/W
SDO
HIGH IMPEDANCE
A6
A5
A4
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
21454312 TD04
21454312p
10
LTC2145-12/
LTC2144-12/LTC2143-12
TYPICAL PERFORMANCE CHARACTERISTICS
LTC2145-12: Integral
Non-Linearity (INL)
LTC2145-12: Differential
Non-Linearity (DNL)
1.0
0
0.8
0.8
–10
0.6
0.6
0.4
0.4
0.2
0.0
–0.2
–0.4
0
–0.2
–0.4
–0.6
–0.8
–0.8
–1.0
–1.0
1024
2048
3072
OUTPUT CODE
4096
–30
0.2
–0.6
0
–20
AMPLITUDE (dBFS)
DNL ERROR (LSB)
INL ERROR (LSB)
1.0
LTC2145-12: 64k Point FFT, fIN =
5MHz, –1dBFS, 125Msps
–60
–70
–80
–90
–100
–110
–120
0
1024
2048
3072
OUTPUT CODE
21454312 G01
0
4096
0
–10
–20
–20
–20
–30
–30
–30
–70
–80
AMPLITUDE (dBFS)
0
–10
AMPLITUDE (dBFS)
0
–60
–40
–50
–60
–70
–80
–40
–60
–70
–80
–90
–100
–90
–100
–110
–120
–110
–120
–110
–120
10
20
30
40
FREQUENCY (MHz)
50
0
60
10
20
30
40
FREQUENCY (MHz)
50
0
60
10
20
30
40
FREQUENCY (MHz)
21454312 G05
21454312 G04
LTC2145-12: 64k Point 2-Tone
FFT, fIN = 69MHz, 70MHz,
–7dBFS, 125Msps
0
50
60
21454312 G06
LTC2145-12: Shorted Input
Histogram
LTC2145-12: SNR vs Input Frequency,
–1dBFS, 125Msps, 2V Range
18000
–10
60
–50
–90
–100
0
50
LTC2145-12: 64k Point FFT,
fIN = 140MHz, –1dBFS, 125Msps
–10
–50
20
30
40
FREQUENCY (MHz)
21454312 G03
LTC2145-12: 64k Point FFT,
fIN = 70MHz, –1dBFS, 125Msps
–40
10
21454312 G02
LTC2145-12: 64k Point FFT,
fIN = 30MHz, –1dBFS, 125Msps
AMPLITUDE (dBFS)
–40
–50
72
16000
–20
14000
71
SINGLE-ENDED
ENCODE
–50
–60
–70
SNR (dBFS)
12000
–40
COUNT
AMPLITUDE (dBFS)
–30
10000
8000
–80
6000
–90
–100
4000
70
DIFFERENTIAL
ENCODE
69
2000
–110
–120
0
10
20
40
30
FREQUENCY (MHz)
50
60
21454312 G07
0
2043
2044
2045
2046
OUTPUT CODE
2047
21454312 G08
68
0
50
100
150
200
250
INPUT FREQUENCY (MHz)
300
21454312 G09
21454312p
11
LTC2145-12/
LTC2144-12/LTC2143-12
TYPICAL PERFORMANCE CHARACTERISTICS
LTC2145-12: 2nd, 3rd Harmonic
vs Input Frequency, –1dBFS,
125Msps, 2V Range
LTC2145-12: 2nd, 3rd Harmonic
vs Input Frequency, –1dBFS,
125Msps, 1V Range
100
100
95
95
LTC2145-12: SFDR vs Input Level,
fIN = 70MHz, 125Msps, 2V Range
110
90
3RD
85
80
2ND
75
70
dBFS
90
3RD
80
SFDR (dBc AND dBFS)
2ND AND 3RD HARMONIC (dBFS)
2ND AND 3RD HARMONIC (dBFS)
100
90
85
2ND
80
75
70
dBc
60
50
40
30
20
70
10
65
0
50
100
150
200
250
INPUT FREQUENCY (MHz)
65
300
0
50
100
150
200
250
INPUT FREQUENCY (MHz)
21454312 G10
21454312 G11
LTC2145-12: IVDD vs Sample
Rate, 5MHz, –1dBFS Sine Wave
Input on Each Channel
LTC2145-12: SNR vs SENSE,
fIN = 5MHz, –1dBFS
72
60
3.5mA LVDS
105
71
50
100
LVDS OUTPUTS
70
IOVDD (mA)
90
CMOS OUTPUTS
85
SNR (dBFS)
40
95
1.75mA LVDS
30
20
70
1.8V CMOS
10
0
25
50
75
100
SAMPLE RATE (Msps)
0
125
68
66
1.2V CMOS
0
25
50
75
100
SAMPLE RATE (Msps)
21454312 G13
65
125
0
0.8
–10
0.6
0.6
0.4
0.4
–0.4
0
–0.2
–0.4
–0.6
–0.8
–0.8
–1.0
–1.0
1024
2048
3072
OUTPUT CODE
4096
21454312 G16
1.2
1.3
–30
0.2
–0.6
0
0.9
1
1.1
SENSE PIN (V)
–20
AMPLITUDE (dBFS)
DNL ERROR (LSB)
1.0
0.8
–0.2
0.8
LTC2144-12: 64k Point FFT,
fIN = 5MHz, –1dBFS, 105Msps
1.0
0.0
0.7
21454312 G15
LTC2144-12: Differential
Non-Linearity (DNL)
0.2
0.6
21454312 G14
LTC2144-12: Integral
Non-Linearity (INL)
INL ERROR (LSB)
69
67
80
75
0
21454312 G12
LTC2145-12: IOVDD vs Sample
Rate, 5MHz, –1dBFS, Sine Wave
on Each Input
110
IVDD (mA)
0
–80 –70 –60 –50 –40 –30 –20 –10
INPUT LEVEL (dBFS)
300
–40
–50
–60
–70
–80
–90
–100
–110
–120
0
1024
2048
3072
OUTPUT CODE
4096
21454312 G17
0
10
20
30
40
FREQUENCY (MHz)
50
21454312 G18
21454312p
21454312
12
LTC2145-12/
LTC2144-12/LTC2143-12
TYPICAL PERFORMANCE CHARACTERISTICS
LTC2144-12: 64k Point FFT,
fIN = 140MHz, –1dBFS, 105Msps
LTC2144-12: 64k Point FFT,
fIN = 70MHz, –1dBFS, 105Msps
0
0
–10
–10
–20
–20
–20
–30
–30
–30
–40
–50
–60
–70
–80
AMPLITUDE (dBFS)
0
–10
AMPLITUDE (dBFS)
AMPLITUDE (dBFS)
LTC2144-12: 64k Point FFT,
fIN = 30MHz, –1dBFS, 105Msps
–40
–50
–60
–70
–80
–40
–50
–60
–70
–80
–90
–100
–90
–100
–90
–100
–110
–120
–110
–120
–110
–120
0
10
20
30
40
FREQUENCY (MHz)
0
50
10
20
30
40
FREQUENCY (MHz)
21454312 G19
0
50
10
20
30
40
FREQUENCY (MHz)
21454312 G20
LTC2144-12: 64k Point 2-Tone
FFT, fIN = 69MHz, 70MHz,
–7dBFS, 105Msps
21454312 G21
LTC2144-12: SNR vs Input
Frequency, –1dBFS, 105Msps,
2V Range
LTC2144-12: Shorted Input
Histogram
0
72
18000
–10
50
16000
–20
14000
71
SINGLE-ENDED
ENCODE
–50
–60
–70
SNR (dBFS)
12000
–40
COUNT
AMPLITUDE (dBFS)
–30
10000
8000
70
DIFFERENTIAL
ENCODE
6000
–80
–90
–100
69
4000
2000
–110
–120
0
10
20
30
40
FREQUENCY (MHz)
0
2043
50
2044
2045
2046
OUTPUT CODE
21454312 G22
68
2047
0
50
100
150
200
250
INPUT FREQUENCY (MHz)
21454312 G24
21454312 G23
LTC2144-12: 2nd, 3rd Harmonic
vs Input Frequency, –1dBFS,
105Msps, 2V Range
LTC2144-12: 2nd, 3rd Harmonic
vs Input Frequency, –1dBFS,
105Msps, 1V Range
100
100
95
95
300
LTC2144-12: SFDR vs Input Level,
fIN = 70MHz, 105Msps, 2V Range
110
90
3RD
85
80
2ND
75
70
90
3RD
SFDR (dBc AND dBFS)
2ND AND 3RD HARMONIC (dBFS)
2ND AND 3RD HARMONIC (dBFS)
100
90
85
2ND
80
75
80
70
dBFS
dBc
60
50
40
30
20
70
10
65
0
50
100
150
200
250
INPUT FREQUENCY (MHz)
300
21454312 G25
65
0
50
100
150
200
250
INPUT FREQUENCY (MHz)
300
21454312 G26
0
–80 –70 –60 –50 –40 –30 –20 –10
INPUT LEVEL (dBFS)
0
21454312 G27
21454312p
13
LTC2145-12/
LTC2144-12/LTC2143-12
TYPICAL PERFORMANCE CHARACTERISTICS
LTC2144-12: IVDD vs Sample
Rate, 5MHz, –1dBFS Sine Wave
Input on Each Channel
LTC2144-12: IOVDD vs Sample
Rate, 5MHz, –1dBFS, Sine Wave
on Each Input
70
85
80
3.5mA LVDS
71
50
70
CMOS OUTPUTS
65
40
1.75mA LVDS
30
60
20
55
10
0
25
50
75
SAMPLE RATE (Msps)
0
100
70
SNR (dBFS)
IOVDD (mA)
IVDD (mA)
72
60
LVDS OUTPUTS
75
50
68
1.8V CMOS
66
1.2V CMOS
0
25
50
75
SAMPLE RATE (Msps)
65
100
0
0.8
–10
0.6
0.6
0.4
0.4
–0.4
0
–0.2
–0.4
–0.6
–0.8
–0.8
–1.0
–1.0
1024
2048
3072
OUTPUT CODE
4096
–40
–50
–60
–70
–80
–110
–120
0
1024
2048
3072
OUTPUT CODE
4096
0
–20
–20
–20
–30
–30
–30
–80
AMPLITUDE (dBFS)
0
–10
AMPLITUDE (dBFS)
0
–10
–70
–40
–50
–60
–70
–80
–40
–50
–60
–70
–80
–90
–100
–90
–100
–90
–100
–110
–120
–110
–120
–110
–120
0
10
20
30
FREQUENCY (MHz)
40
21454312 G34
0
10
20
30
FREQUENCY (MHz)
40
LTC2143-12: 64k Point FFT,
fIN = 140MHz, –1dBFS, 80Msps
0
–60
20
30
FREQUENCY (MHz)
21454312 G33
–10
–50
10
21454312 G32
LTC2143-12: 64k Point FFT,
fIN = 70MHz, –1dBFS, 80Msps
–40
1.3
–90
–100
21454312 G31
LTC2143-12: 64k Point FFT,
fIN = 30MHz, –1dBFS, 80Msps
1.2
–30
0.2
–0.6
0
0.9
1
1.1
SENSE PIN (V)
–20
AMPLITUDE (dBFS)
DNL ERROR (LSB)
1.0
0.8
0.2
0.8
LTC2143-12: 64k Point FFT,
fIN = 5MHz, –1dBFS, 80Msps
1.0
0.0
0.7
21454312 G30
LTC2143-12: Differential
Non-Linearity (DNL)
0.2
0.6
21454312 G29
LTC2143-12: Integral
Non-Linearity (INL)
INL ERROR (LSB)
69
67
21454312 G28
AMPLITUDE (dBFS)
LTC2144-12: SNR vs SENSE,
fIN = 5MHz, –1dBFS
40
21454312 G35
0
10
30
20
FREQUENCY (MHz)
40
21454312 G36
21454312p
21454312
14
LTC2145-12/
LTC2144-12/LTC2143-12
TYPICAL PERFORMANCE CHARACTERISTICS
LTC2143-12: 64k Point 2-Tone FFT,
fIN = 69MHz, 70MHz, –7dBFS,
80Msps
0
18000
–10
16000
–20
SINGLE-ENDED
ENCODE
71
–50
–60
SNR (dBFS)
12000
–40
COUNT
10000
–70
8000
–80
6000
–90
–100
4000
70
DIFFERENTIAL
ENCODE
69
2000
–110
–120
0
10
20
30
FREQUENCY (MHz)
0
2050
40
2051
2052
2053
OUTPUT CODE
LTC2143-12: 2nd, 3rd Harmonic vs
Input Frequency, –1dBFS, 80Msps,
2V Range
95
95
2ND AND 3RD HARMONIC (dBFS)
100
85
80
2ND
75
70
50
100
150
200
250
INPUT FREQUENCY (MHz)
300
21454312 G39
LTC2143-12: 2nd, 3rd Harmonic vs
Input Frequency, –1dBFS, 80Msps,
1V Range
100
3RD
0
21454312 G38
21454312 G37
90
68
2054
LTC2143-12: SFDR vs Input Level,
fIN = 70MHz, 80Msps, 2V Range
110
100
dBFS
90
3RD
SFDR (dBc AND dBFS)
AMPLITUDE (dBFS)
72
14000
–30
2ND AND 3RD HARMONIC (dBFS)
LTC2143-12: SNR vs Input
Frequency, –1dBFS, 80Msps,
2V Range
LTC2143-12: Shorted Input
Histogram
90
85
2ND
80
75
80
70
60
dBc
50
40
30
20
70
10
65
0
50
100
150
200
250
INPUT FREQUENCY (MHz)
65
300
0
50
100
150
200
250
INPUT FREQUENCY (MHz)
21454312 G40
0
–80 –70 –60 –50 –40 –30 –20 –10
INPUT LEVEL (dBFS)
300
21454312 G41
LTC2143-12: IVDD vs Sample
Rate, 5MHz, –1dBFS Sine Wave
Input on Each Input
21454312 G42
LTC2143-12: IOVDD vs Sample
Rate, 5MHz, –1dBFS, Sine Wave
on Each Channel
70
0
LTC2143-12: SNR vs SENSE,
fIN = 5MHz, –1dBFS
72
60
3.5mA LVDS
LVDS OUTPUTS
IOVDD (mA)
IVDD (mA)
60
55
50
71
40
70
1.75mA LVDS
30
10
0
20
40
60
SAMPLE RATE (Msps)
80
21454312 G43
0
69
68
20
CMOS OUTPUTS
45
40
50
SNR (dBFS)
65
67
1.8V CMOS
0
1.2V CMOS
20
40
60
80
SAMPLE RATE (Msps)
21454312 G44
66
0.6
0.7
0.8
0.9
1
1.1
SENSE PIN (V)
1.2
1.3
21454312 G45
21454312p
15
LTC2145-12/
LTC2144-12/LTC2143-12
PIN FUNCTIONS
PINS THAT ARE THE SAME FOR ALL DIGITAL
OUTPUT MODES
VDD (Pins 1, 16, 17, 64): Analog Power Supply, 1.7V to
1.9V. Bypass to ground with 0.1μF ceramic capacitors.
Adjacent pins can share a bypass capacitor.
VCM1 (Pin 2): Common Mode Bias Output, Nominally Equal
to VDD/2. VCM1 should be used to bias the common mode
of the analog inputs to channel 1. Bypass to ground with
a 0.1μF ceramic capacitor.
GND (Pins 3, 6, 14): ADC Power Ground.
AIN1+ (Pin 4): Channel 1 Positive Differential Analog
Input.
AIN1– (Pin 5): Channel 1 Negative Differential Analog
Input.
REFH (Pins 7, 9): ADC High Reference. See the Applications Information section for recommended bypassing
circuits for REFH and REFL.
REFL (Pins 8, 10): ADC Low Reference. See the Applications Information section for recommended bypassing
circuits for REFH and REFL.
PAR/SER (Pin 11): Programming Mode Selection Pin. Connect to ground to enable the serial programming mode. CS,
SCK, SDI, SDO become a serial interface that control the
A/D operating modes. Connect to VDD to enable the parallel
programming mode where CS, SCK, SDI, SDO become
parallel logic inputs that control a reduced set of the A/D
operating modes. PAR/SER should be connected directly
to ground or VDD and not be driven by a logic signal.
AIN2+ (Pin 12): Channel 2 Positive Differential Analog
Input.
AIN2– (Pin 13): Channel 2 Negative Differential Analog
Input.
VCM2 (Pin 15): Common Mode Bias Output, Nominally
Equal to VDD/2. VCM2 should be used to bias the common
mode of the analog inputs to channel 2. Bypass to ground
with a 0.1μF ceramic capacitor.
ENC+ (Pin 18): Encode Input. Conversion starts on the
rising edge.
ENC– (Pin 19): Encode Complement Input. Conversion
starts on the falling edge. Tie to GND for single-ended
encode mode.
CS (Pin 20): In Serial Programming Mode, (PAR/SER =
0V), CS Is the Serial Interface Chip Select Input. When
CS is low, SCK is enabled for shifting data on SDI into
the mode control registers. In the parallel programming
mode (PAR/SER = VDD), CS controls the clock duty cycle
stabilizer (See Table 2). CS can be driven with 1.8V to
3.3V logic.
SCK (Pin 21): In Serial Programming Mode, (PAR/SER =
0V), SCK Is the Serial Interface Clock Input. In the parallel
programming mode (PAR/SER = VDD), SCK controls the
digital output mode (see Table 2). SCK can be driven with
1.8V to 3.3V logic.
SDI (Pin 22): In Serial Programming Mode, (PAR/SER =
0V), SDI Is the Serial Interface Data Input. Data on SDI is
clocked into the mode control registers on the rising edge
of SCK. In the parallel programming mode (PAR/SER =
VDD), SDI can be used together with SDO to power down
the part (see Table 2). SDI can be driven with 1.8V to
3.3V logic.
OGND (Pin 41): Output Driver Ground. Must be shorted
to the ground plane by a very low inductance path. Use
multiple vias close to the pin.
OVDD (Pin 42): Output Driver Supply. Bypass to ground
with a 0.1μF ceramic capacitor.
SDO (Pin 61): In Serial Programming Mode, (PAR/SER
= 0V), SDO Is the Optional Serial Interface Data Output.
Data on SDO is read back from the mode control registers and can be latched on the falling edge of SCK. SDO
is an open-drain NMOS output that requires an external
2k pull-up resistor to 1.8V – 3.3V. If read back from the
mode control registers is not needed, the pull-up resistor
is not necessary and SDO can be left unconnected. In the
parallel programming mode (PAR/SER = VDD), SDO can
be used together with SDI to power down the part (see
Table 2). When used as an input, SDO can be driven with
1.8V to 3.3V logic through a 1k series resistor.
VREF (Pin 62): Reference Voltage Output. Bypass to
ground with a 2.2μF ceramic capacitor. The output voltage
is nominally 1.25V.
21454312p
16
LTC2145-12/
LTC2144-12/LTC2143-12
PIN FUNCTIONS
SENSE (Pin 63): Reference Programming Pin. Connecting
SENSE to VDD selects the internal reference and a ±1V input
range. Connecting SENSE to ground selects the internal
reference and a ±0.5V input range. An external reference
between 0.625V and 1.3V applied to SENSE selects an
input range of ±0.8 • VSENSE.
Ground (Exposed Pad Pin 65): The exposed pad must be
soldered to the PCB ground.
FULL RATE CMOS OUTPUT MODE
All Pins Below Have CMOS Output Levels
(OGND to OVDD)
D2_0 to D2_11 (Pins 27, 28, 29, 30, 31, 32, 33, 34,
35, 36, 37, 38): Channel 2 Digital Outputs. D2_11 is the
MSB.
DNC (Pins 23, 24, 25, 26, 43, 44, 45, 46): Do not connect
these pins.
CLKOUT– (Pin 39): Inverted Version of CLKOUT+.
CLKOUT+ (Pin 40): Data Output Clock. The digital outputs
normally transition at the same time as the falling edge
of CLKOUT+. The phase of CLKOUT+ can also be delayed
relative to the Digital Outputs by programming the mode
control registers.
D1_0 to D1_11 (Pins 47, 48, 49, 50, 51, 52, 53, 54,
55, 56, 57, 58): Channel 1 Digital Outputs. D1_11 is the
MSB.
OF2 (Pin 59): Channel 2 Over/Underflow Digital Output. OF2
is high when an overflow or underflow has occurred.
OF1 (Pin 60): Channel 1 Over/Underflow Digital Output. OF1
is high when an overflow or underflow has occurred.
DOUBLE DATA RATE CMOS OUTPUT MODE
All Pins Below Have CMOS Output Levels
(OGND to OVDD)
D2_0_1 to D2_10_11 (Pins 28, 30, 32, 34, 36, 38):
Channel 2 Double Data Rate Digital Outputs. Two data
bits are multiplexed onto each output pin. The even data
bits (D0, D2, D4, D6, D8, D10) appear when CLKOUT+ is
low. The odd data bits (D1, D3, D5, D7, D9, D11) appear
when CLKOUT+ is high.
DNC (Pins 23, 24, 25, 26, 27, 29, 31, 33, 35, 37, 43,
44, 45, 46, 47, 49, 51, 53, 55, 57, 59): Do not connect
these pins.
CLKOUT– (Pin 39): Inverted Version of CLKOUT+.
CLKOUT+ (Pin 40): Data Output Clock. The Digital Outputs
normally transition at the same time as the falling and
rising edges of CLKOUT+. The phase of CLKOUT+ can also
be delayed relative to the Digital Outputs by programming
the mode control registers.
D1_0_1 to D1_10_11 (Pins 48, 50, 52, 54, 56, 58):
Channel 1 Double Data Rate Digital Outputs. Two data
bits are multiplexed onto each output pin. The even data
bits (D0, D2, D4, D6, D8, D10) appear when CLKOUT+ is
low. The odd data bits (D1, D3, D5, D7, D9, D11) appear
when CLKOUT+ is high.
OF2_1 (Pin 60): Over/Underflow Digital Output. OF2_1 is
high when an overflow or underflow has occurred. The
over/under flow for both channels are multiplexed onto
this pin. Channel 2 appears when CLKOUT+ is low, and
Channel 1 appears when CLKOUT+ is high.
DOUBLE DATA RATE LVDS OUTPUT MODE
All Pins Below Have LVDS Output Levels. The Output
Current Level Is Programmable. There Is an Optional
Internal 100Ω Termination Resistor Between the Pins
of Each LVDS Output Pair.
D2_0_1–/D2_0_1+ to D2_10_11–/D2_10_11+ (Pins 27/28,
29/30, 31/32, 33/34, 35/36, 37/38): Channel 2 Double
Data Rate Digital Outputs. Two data bits are multiplexed
onto each differential output pair. The even data bits (D0,
D2, D4, D6, D8, D10) appear when CLKOUT+ is low. The
odd data bits (D1, D3, D5, D7, D9, D11) appear when
CLKOUT+ is high.
CLKOUT–/CLKOUT+ (Pins 39/40): Data Output Clock.
The digital outputs normally transition at the same time
as the falling and rising edges of CLKOUT+. The phase of
CLKOUT+ can also be delayed relative to the digital outputs
by programming the mode control registers.
DNC (Pins 23, 24, 25, 26, 43, 44, 45, 46): Do not connect
these pins.
21454312p
17
LTC2145-12/
LTC2144-12/LTC2143-12
PIN FUNCTIONS
D1_0_1–/D1_0_1+ to D1_10_11–/D1_10_11+ (Pins 47/48,
49/50, 51/52, 53/54, 55/56, 57/58): Channel 2 Double
Data Rate Digital Outputs. Two data bits are multiplexed
onto each differential output pair. The even data bits (D0,
D2, D4, D6, D8, D10) appear when CLKOUT+ is low. The
odd data bits (D1, D3, D5, D7, D9, D11) appear when
CLKOUT+ is high.
OF2_1–/OF2_1+ (Pins 59/60): Over/Underflow Digital
Output. OF2_1+ is high when an overflow or underflow
has occurred. The over/under flow for both channels
are multiplexed onto this pin. Channel 2 appears when
CLKOUT+ is low, and Channel 1 appears when CLKOUT+
is high.
FUNCTIONAL BLOCK DIAGRAM
OVDD
CH 1
ANALOG
INPUT
OF1
12-BIT
ADC CORE
S/H
OF2
CORRECTION
LOGIC
CH 2
ANALOG
INPUT
D1_11
•
•
•
D1_0
12-BIT
ADC CORE
S/H
OUTPUT
DRIVERS
CLKOUT +
CLKOUT –
VREF
2.2μF
D2_11
•
•
•
D2_0
1.25V
REFERENCE
RANGE
SELECT
OGND
REFH
SENSE
VCM1
REFL
INTERNAL CLOCK SIGNALS
REF
BUF
VDD/2
0.1μF
VDD
DIFF
REF
AMP
CLOCK/DUTY
CYCLE
CONTROL
MODE
CONTROL
REGISTERS
VCM2
0.1μF
GND
REFH
REFL
ENC+
PAR/SER CS SCK SDI SDO
21854312 F01
2.2μF
0.1μF
ENC–
0.1μF
Figure 1. Functional Block Diagram
21454312p
18
LTC2145-12/
LTC2144-12/LTC2143-12
APPLICATIONS INFORMATION
CONVERTER OPERATION
The two channels are simultaneously sampled by a shared
encode circuit (Figure 2).
The LTC2145-12/LTC2144-12/LTC2143-12 are low power,
two-channel, 12-bit, 125Msps/105Msps/80Msps A/D
converters that are powered by a single 1.8V supply. The
analog inputs should be driven differentially. The encode
input can be driven differentially, or single ended for lower
power consumption. The digital outputs can be CMOS,
double data rate CMOS (to halve the number of output
lines), or double data rate LVDS (to reduce digital noise
in the system.) Many additional features can be chosen
by programming the mode control registers through a
serial SPI port.
For applications less sensitive to harmonic distortion, the
AIN+ input can be driven single-ended with a 1VP-P signal
centered around VCM. The AIN– input should be connected
to VCM. With a single-ended input the harmonic distortion
and INL will degrade, but the noise and DNL will remain
unchanged.
ANALOG INPUT
Input Filtering
The analog inputs are differential CMOS sample-and-hold
circuits (Figure 2). The inputs should be driven differentially around a common mode voltage set by the VCM1 or
VCM2 output pins, which are nominally VDD/2. For the 2V
input range, the inputs should swing from VCM – 0.5V
to VCM + 0.5V. There should be 180° phase difference
between the inputs.
If possible, there should be an RC lowpass filter right at
the analog inputs. This lowpass filter isolates the drive
circuitry from the A/D sample-and-hold switching, and
also limits wideband noise from the drive circuitry. Figure 3
shows an example of an input RC filter. The RC component
values should be chosen based on the application’s input
frequency.
Single-Ended Input
INPUT DRIVE CIRCUITS
Transformer Coupled Circuits
LTC2145-12
VDD
AIN
+
RON
15Ω
10Ω
CPARASITIC
1.8pF
VDD
AIN–
CSAMPLE
5pF
RON
15Ω
10Ω
CSAMPLE
5pF
Figure 3 shows the analog input being driven by an RF
transformer with a center-tapped secondary. The center
tap is biased with VCM, setting the A/D input at its optimal
DC level. At higher input frequencies a transmission line
balun transformer (Figure 4 to Figure 6) has better balance,
resulting in lower A/D distortion.
CPARASITIC
1.8pF
50Ω
VDD
VCM
0.1μF
0.1μF
ANALOG
INPUT
1.2V
T1
1:1
25Ω
25Ω
10k
AIN+
LTC2145-12
0.1μF
12pF
ENC+
25Ω
25Ω
ENC–
T1: MA/COM MABAES0060
RESISTORS, CAPACITORS
ARE 0402 PACKAGE SIZE
10k
1.2V
21454312 F02
Figure 2. Equivalent Input Circuit. Only One of the Two
Analog Channels Is Shown
AIN–
21454312 F03
Figure 3. Analog Input Circuit Using a Transformer.
Recommended for Input Frequencies from 5MHz to 70MHz
21454312p
19
LTC2145-12/
LTC2144-12/LTC2143-12
APPLICATIONS INFORMATION
Amplifier Circuits
Reference
Figure 7 shows the analog input being driven by a high
speed differential amplifier. The output of the amplifier is ACcoupled to the A/D so the amplifier’s output common mode
voltage can be optimally set to minimize distortion.
The LTC2145-12/LTC2144-12/LTC2143-12 has an internal
1.25V voltage reference. For a 2V input range using the
internal reference, connect SENSE to VDD. For a 1V input
range using the internal reference, connect SENSE to
ground. For a 2V input range with an external reference,
apply a 1.25V reference voltage to SENSE (Figure 9).
At very high frequencies an RF gain block will often have
lower distortion than a differential amplifier. If the gain
block is single-ended, then a transformer circuit (Figure 4
to Figure 6) should convert the signal to differential before
driving the A/D.
50Ω
VCM
0.1μF
0.1μF
ANALOG
INPUT
12Ω
T2
T1
25Ω
AIN+
LTC2145-12
0.1μF
The input range can be adjusted by applying a voltage to
SENSE that is between 0.625V and 1.30V. The input range
will then be 1.6 • VSENSE.
The VREF, REFH and REFL pins should be bypassed as
shown in Figure 8. A low inductance 2.2μF interdigitated
capacitor is recommended for the bypass between REFH
and REFL. This type of capacitor is available at a low cost
from multiple suppliers.
8.2pF
0.1μF
25Ω
12Ω
AIN–
50Ω
VCM
0.1μF
21454312 F04
T1: MA/COM MABA-007159-000000
T2: COILCRAFT WBC1-1TL
RESISTORS, CAPACITORS ARE 0402 PACKAGE SIZE
0.1μF
4.7nH
ANALOG
INPUT
T1
25Ω
LTC2145-12
0.1μF
25Ω
0.1μF
Figure 4. Recommended Front-End Circuit for Input
Frequencies from 5MHz to 150MHz
AIN+
4.7nH
AIN–
T1: MA/COM ETC1-1-13
RESISTORS, CAPACITORS
ARE 0402 PACKAGE SIZE
50Ω
VCM
Figure 6. Recommended Front-End Circuit for Input
Frequencies Above 250MHz
0.1μF
0.1μF
ANALOG
INPUT
AIN+
T2
T1
21454312 F06
25Ω
LTC2145-12
0.1μF
1.8pF
0.1μF
25Ω
VCM
AIN–
HIGH SPEED
DIFFERENTIAL
0.1μF
AMPLIFIER
200Ω
200Ω
25Ω
21454312 F05
T1: MA/COM MABA-007159-000000
T2: COILCRAFT WBC1-1TL
RESISTORS, CAPACITORS ARE 0402 PACKAGE SIZE
Figure 5. Recommended Front-End Circuit for Input
Frequencies from 150MHz to 250MHz
ANALOG
INPUT
+
+
–
–
0.1μF
AIN+
12pF
0.1μF
25Ω
LTC2145-12
AIN–
12pF
21454312 F07
Figure 7. Front-End Circuit Using a High Speed
Differential Amplifier
21454312p
20
LTC2145-12/
LTC2144-12/LTC2143-12
APPLICATIONS INFORMATION
in some vendors’ capacitors. In Figure 8d the REFH and
REFL pins are connected by short jumpers in an internal
layer. To minimize the inductance of these jumpers they
can be placed in a small hole in the GND plane on the
second board layer.
LTC2145-12
VREF
1.25V
5Ω
1.25V BANDGAP
REFERENCE
2.2μF
0.625V
TIE TO VDD FOR 2V RANGE;
TIE TO GND FOR 1V RANGE;
3"/(&t7SENSE FOR
0.625V < VSENSE < 1.300V
RANGE
DETECT
AND
CONTROL
SENSE
BUFFER
INTERNAL ADC
HIGH REFERENCE
C2
0.1μF
–
+
+
–
REFH
Figure 8c. Recommended Layout for the REFH/REFL
Bypass Circuit in Figure 8a
REFL
0.8x
DIFF AMP
C1
C3
0.1μF
–
+
+
–
REFH
REFL
INTERNAL ADC
LOW REFERENCE
C1: 2.2μF LOW INDUCTANCE
INTERDIGITATED CAPACITOR
TDK CLLE1AX7S0G225M
MURATA LLA219C70G225M
AVX W2L14Z225M
OR EQUIVALENT
21454312 F08a
Figure 8d. Recommended Layout for the REFH/REFL
Bypass Circuit in Figure 8b
Figure 8a. Reference Circuit
Alternatively, C1 can be replaced by a standard 2.2μF
capacitor between REFH and REFL (see Figure 8b). The
capacitors should be as close to the pins as possible (not
on the back side of the circuit board).
VREF
2.2μF
LTC2145-12
1.25V
EXTERNAL
REFERENCE
SENSE
1μF
21454312 F09
Figure 8c and Figure 8d show the recommended circuit
board layout for the REFH/REFL bypass capacitors. Note
that in Figure 8c, every pin of the interdigitated capacitor
(C1) is connected since the pins are not internally connected
REFH
C3
0.1μF
LTC2145-12
REFL
C1
2.2μF
C2
0.1μF
REFH
REFL
21454312 F08b
CAPACITORS ARE 0402 PACKAGE SIZE
Figure 8b. Alternative REFH/REFL Bypass Circuit
Figure 9. Using an External 1.25V Reference
Encode Input
The signal quality of the encode inputs strongly affects
the A/D noise performance. The encode inputs should
be treated as analog signals – do not route them next to
digital traces on the circuit board. There are two modes
of operation for the encode inputs: the differential encode
mode (Figure 10), and the single-ended encode mode
(Figure 11).
The differential encode mode is recommended for sinusoidal, PECL, or LVDS encode inputs (Figure 12 and
Figure 13). The encode inputs are internally biased to 1.2V
21454312p
21
LTC2145-12/
LTC2144-12/LTC2143-12
APPLICATIONS INFORMATION
LTC2145-12
through 10kΩ equivalent resistance. The encode inputs
can be taken above VDD (up to 3.6V), and the common
mode range is from 1.1V to 1.6V. In the differential encode
mode, ENC– should stay at least 200mV above ground to
avoid falsely triggering the single ended encode mode.
For good jitter performance ENC+ and ENC– should have
fast rise and fall times.
VDD
DIFFERENTIAL
COMPARATOR
VDD
15k
ENC+
ENC–
The single-ended encode mode should be used with
CMOS encode inputs. To select this mode, ENC– is connected to ground and ENC+ is driven with a square wave
encode input. ENC+ can be taken above VDD (up to 3.6V)
so 1.8V to 3.3V CMOS logic levels can be used. The ENC+
threshold is 0.9V. For good jitter performance ENC+ should
have fast rise and fall times. If the encode signal is turned
off or drops below approximately 500kHz, the A/D enters
nap mode.
30k
21454312 F10
Figure 10. Equivalent Encode Input Circuit
for Differential Encode Mode
LTC2145-12
ENC+
1.8V TO 3.3V
0V
ENC–
30k
Clock Duty Cycle Stabilizer
CMOS LOGIC
BUFFER
21454312 F11
Figure 11. Equivalent Encode Input Circuit
for Single-Ended Encode Mode
0.1μF
ENC+
T1
50Ω
100Ω
LTC2145-12
50Ω
0.1μF
0.1μF
ENC–
21454312 F12
T1 = MA/COM ETC1-1-13
RESISTORS AND CAPACITORS
ARE 0402 PACKAGE SIZE
For good performance the encode signal should have a
50% (±5%) duty cycle. If the optional clock duty cycle
stabilizer circuit is enabled, the encode duty cycle can
vary from 30% to 70% and the duty cycle stabilizer will
maintain a constant 50% internal duty cycle. If the encode
signal changes frequency, the duty cycle stabilizer circuit
requires one hundred clock cycles to lock onto the input
clock. The duty cycle stabilizer is enabled by mode control
register A2 (serial programming mode), or by CS (parallel
programming mode).
For applications where the sample rate needs to be changed
quickly, the clock duty cycle stabilizer can be disabled. If
the duty cycle stabilizer is disabled, care should be taken to
make the sampling clock have a 50% (±5%) duty cycle. The
duty cycle stabilizer should not be used below 5Msps.
Figure 12. Sinusoidal Encode Drive
DIGITAL OUTPUTS
0.1μF
PECL OR
LVDS
CLOCK
Digital Output Modes
ENC+
LTC2145-12
0.1μF
ENC–
21454312 F13
The LTC2145-12/LTC2144-12/LTC2143-12 can operate in
three digital output modes: full rate CMOS, double data
rate CMOS (to halve the number of output lines), or double
data rate LVDS (to reduce digital noise in the system.) The
output mode is set by mode control register A3 (serial
Figure 13. PECL or LVDS Encode Drive
21454312p
22
LTC2145-12/
LTC2144-12/LTC2143-12
APPLICATIONS INFORMATION
programming mode), or by SCK (parallel programming
mode). Note that double data rate CMOS cannot be selected
in the parallel programming mode.
Full Rate CMOS Mode
In full rate CMOS mode the data outputs (D1_0 to D1_11
and D2_0 to D2_11), overflow (OF2, OF1), and the data
output clocks (CLKOUT+, CLKOUT–) have CMOS output
levels. The outputs are powered by OVDD and OGND which
are isolated from the A/D core power and ground. OVDD
can range from 1.1V to 1.9V, allowing 1.2V through 1.8V
CMOS logic outputs.
For good performance the digital outputs should drive
minimal capacitive loads. If the load capacitance is larger
than 10pF a digital buffer should be used.
Double Data Rate CMOS Mode
In double data rate CMOS mode, two data bits are
multiplexed and output on each data pin. This reduces
the number of digital lines by thirteen, simplifying
board routing and reducing the number of input pins
needed to receive the data. The data outputs (D1_0_1,
D1_2_3, D1_4_5, D1_6_7, D1_8_9, D1_10_11, D2_0_1,
D2_2_3, D2_4_5, D2_6_7, D2_8_9, D2_10_11,
overflow (OF2_1), and the data output clocks (CLKOUT+,
CLKOUT–) have CMOS output levels. The outputs are
powered by OVDD and OGND which are isolated from the
A/D core power and ground. OVDD can range from 1.1V
to 1.9V, allowing 1.2V through 1.8V CMOS logic outputs.
Note that the overflow for both ADC channels is multiplexed
onto the OF2_1 pin.
For good performance the digital outputs should drive
minimal capacitive loads. If the load capacitance is larger
than 10pF a digital buffer should be used.
When using double data rate CMOS at sample rates above
100Msps the SNR may degrade slightly, about 0.1dB to
0.3dB depending on load capacitance and board layout.
Double Data Rate LVDS Mode
In double data rate LVDS mode, two data bits are
multiplexed and output on each differential output
pair. There are six LVDS output pairs per ADC channel
(D1_0_1+/D1_0_1– through D1_10_11+/D1_10_11– and
D2_0_1+/D2_0_1– through D2_10_11+/D2_10_11–) for
the digital output data. Overflow (OF2_1+/OF2_1–) and the
data output clock (CLKOUT+/CLKOUT–) each have an LVDS
output pair. Note that the overflow for both ADC channels
is multiplexed onto the OF2_1+/OF2_1– output pair.
By default the outputs are standard LVDS levels: 3.5mA
output current and a 1.25V output common mode voltage. An external 100Ω differential termination resistor
is required for each LVDS output pair. The termination
resistors should be located as close as possible to the
LVDS receiver.
The outputs are powered by OVDD and OGND which are
isolated from the A/D core power and ground. In LVDS
mode, OVDD must be 1.8V.
Programmable LVDS Output Current
In LVDS mode, the default output driver current is 3.5mA.
This current can be adjusted by serially programming mode
control register A3. Available current levels are 1.75mA,
2.1mA, 2.5mA, 3mA, 3.5mA, 4mA and 4.5mA.
Optional LVDS Driver Internal Termination
In most cases using just an external 100Ω termination
resistor will give excellent LVDS signal integrity. In addition, an optional internal 100Ω termination resistor can
be enabled by serially programming mode control register
A3. The internal termination helps absorb any reflections
caused by imperfect termination at the receiver. When the
internal termination is enabled, the output driver current
is doubled to maintain the same output voltage swing.
Overflow Bit
The overflow output bit outputs a logic high when the analog
input is either overranged or underranged. The overflow
bit has the same pipeline latency as the data bits. In full
rate CMOS mode each ADC channel has its own overflow
pin (OF1 for channel 1, OF2 for channel 2). In DDR CMOS
or DDR LVDS mode the overflow for both ADC channels
is multiplexed onto the OF2_1 output.
21454312p
23
LTC2145-12/
LTC2144-12/LTC2143-12
APPLICATIONS INFORMATION
Phase Shifting the Output Clock
DATA FORMAT
In full rate CMOS mode the data output bits normally
change at the same time as the falling edge of CLKOUT+,
so the rising edge of CLKOUT+ can be used to latch the
output data. In double data rate CMOS and LVDS modes
the data output bits normally change at the same time as
the falling and rising edges of CLKOUT+. To allow adequate
set-up and hold time when latching the data, the CLKOUT+
signal may need to be phase shifted relative to the data
output bits. Most FPGAs have this feature; this is generally
the best place to adjust the timing.
Table 1 shows the relationship between the analog input
voltage, the digital data output bits and the overflow bit.
By default the output data format is offset binary. The 2’s
complement format can be selected by serially programming mode control register A4.
The LTC2145-12/LTC2144-12/LTC2143-12 can also
phase shift the CLKOUT+/CLKOUT– signals by serially
programming mode control register A2. The output
clock can be shifted by 0°, 45°, 90°, or 135°. To use the
phase shifting feature the clock duty cycle stabilizer must
be turned on. Another control register bit can invert the
polarity of CLKOUT+ and CLKOUT–, independently of the
phase shift. The combination of these two features enables
phase shifts of 45° up to 315° (Figure 14).
Table 1. Output Codes vs Input Voltage
AIN+ – AIN–
(2V RANGE)
OF
D11-D0
(OFFSET BINARY)
D11-D0
(2’s COMPLEMENT)
>+1.000000V
1
1111 1111 1111
0111 1111 1111
+0.999512V
0
1111 1111 1111
0111 1111 1111
+0.999024V
0
1111 1111 1110
0111 1111 1110
+0.000488V
0
1000 0000 0001
0000 0000 0001
0.000000V
0
1000 0000 0000
0000 0000 0000
–0.000488V
0
0111 1111 1111
1111 1111 1111
–0.000976V
0
0111 1111 1110
1111 1111 1110
–0.999512V
0
0000 0000 0001
1000 0000 0001
–1.000000V
0
0000 0000 0000
1000 0000 0000
≤–1.000000V
1
0000 0000 0000
1000 0000 0000
ENC+
D0-D11, OF
MODE CONTROL BITS
PHASE
SHIFT
CLKINV
CLKPHASE1
CLKPHASE0
0°
0
0
0
45°
0
0
1
90°
0
1
0
135°
0
1
1
180°
1
0
0
225°
1
0
1
270°
1
1
0
315°
1
1
1
CLKOUT+
21854312 F14
Figure 14. Phase Shifting CLKOUT
21454312p
24
LTC2145-12/
LTC2144-12/LTC2143-12
APPLICATIONS INFORMATION
Digital Output Randomizer
CLKOUT
Interference from the A/D digital outputs is sometimes
unavoidable. Digital interference may be from capacitive or
inductive coupling or coupling through the ground plane.
Even a tiny coupling factor can cause unwanted tones
in the ADC output spectrum. By randomizing the digital
output before it is transmitted off chip, these unwanted
tones can be randomized which reduces the unwanted
tone amplitude.
The digital output is randomized by applying an exclusiveOR logic operation between the LSB and all other data
output bits. To decode, the reverse operation is applied;
an exclusive-OR operation is applied between the LSB
and all other bits. The LSB, OF and CLKOUT outputs are
not affected. The output randomizer is enabled by serially
programming mode control register A4.
Alternate Bit Polarity
Another feature that reduces digital feedback on the circuit
board is the alternate bit polarity mode. When this mode
is enabled, all of the odd bits (D1, D3, D5, D7, D9, D11)
are inverted before the output buffers. The even bits (D0,
D2, D4, D6, D8, D10), OF and CLKOUT are not affected.
This can reduce digital currents in the circuit board ground
plane and reduce digital noise, particularly for very small
analog input signals.
When there is a very small signal at the input of the A/D
that is centered around mid-scale, the digital outputs toggle
between mostly 1’s and mostly 0’s. This simultaneous
switching of most of the bits will cause large currents in the
ground plane. By inverting every other bit, the alternate bit
polarity mode makes half of the bits transition high while
half of the bits transition low. This cancels current flow in
the ground plane, reducing the digital noise.
The digital output is decoded at the receiver by inverting
the odd bits (D1, D3, D5, D7, D9, D11). The alternate bit
polarity mode is independent of the digital output randomizer – either, both or neither function can be on at the same
time. The alternate bit polarity mode is enabled by serially
programming mode control register A4.
CLKOUT
OF
OF
D11
D11/D0
D10
D2
D10/D0
•
•
•
D2/D0
RANDOMIZER
ON
D1
D1/D0
D0
D0
21454312 F15
Figure 15. Functional Equivalent of Digital Output Randomizer
PC BOARD
CLKOUT FPGA
OF
D11/D0
D11
D10/D0
LTC2145-12
D10
D2/D0
t
t
t
D2
D1/D0
D1
D0
D0
21454312 F16
Figure 16. Unrandomizing a Randomized Digital
Output Signal
21454312p
25
LTC2145-12/
LTC2144-12/LTC2143-12
APPLICATIONS INFORMATION
Digital Output Test Patterns
To allow in-circuit testing of the digital interface to the
A/D, there are several test modes that force the A/D data
outputs (OF, D11-D0) to known values:
All 1s: All outputs are 1
All 0s: All outputs are 0
Alternating: Outputs change from all 1s to all 0s on
alternating samples.
Checkerboard: Outputs change from 1010101010101
to 0101010101010 on alternating samples.
The digital output test patterns are enabled by serially
programming mode control register A4. When enabled,
the Test Patterns override all other formatting modes: 2’s
complement, randomizer, alternate bit polarity.
Output Disable
The digital outputs may be disabled by serially programming mode control register A3. All digital outputs including
OF and CLKOUT are disabled. The high-impedance disabled
state is intended for in-circuit testing or long periods of
inactivity – it is too slow to multiplex a data bus between
multiple converters at full speed. When the outputs are
disabled both channels should be put into either sleep or
nap mode.
Sleep and Nap Modes
The A/D may be placed in sleep or nap modes to conserve
power. In sleep mode the entire device is powered down,
resulting in 1mW power consumption. The amount of
time required to recover from sleep mode depends on the
size of the bypass capacitors on VREF, REFH, and REFL.
For the suggested values in Fig. 8, the A/D will stabilize
after 2ms.
In nap mode the A/D core is powered down while the internal
reference circuits stay active, allowing faster wakeup than
from sleep mode. Recovering from nap mode requires at
least 100 clock cycles. If the application demands very
accurate DC settling then an additional 50μs should be
allowed so the on-chip references can settle from the
slight temperature shift caused by the change in supply
current as the A/D leaves nap mode. Either channel 2 or
both channels can be placed in nap mode; it is not possible
to have channel 1 in nap mode and channel 2 operating
normally.
Sleep mode and nap mode are enabled by mode control
register A1 (serial programming mode), or by SDI and
SDO (parallel programming mode).
DEVICE PROGRAMMING MODES
The operating modes of the LTC2145-12/LTC2144-12/
LTC2143-12 can be programmed by either a parallel
interface or a simple serial interface. The serial interface
has more flexibility and can program all available modes.
The parallel interface is more limited and can only program
some of the more commonly used modes.
Parallel Programming Mode
To use the parallel programming mode, PAR/SER should
be tied to VDD. The CS, SCK, SDI and SDO pins are binary
logic inputs that set certain operating modes. These pins
can be tied to VDD or ground, or driven by 1.8V, 2.5V, or
3.3V CMOS logic. When used as an input, SDO should
be driven through a 1k series resistor. Table 2 shows the
modes set by CS, SCK, SDI and SDO.
Table 2. Parallel Programming Mode Control Bits (PAR/SER = VDD)
PIN
DESCRIPTION
CS
Clock Duty Cycle Stabilizer Control Bit
0 = Clock Duty Cycle Stabilizer Off
1 = Clock Duty Cycle Stabilizer On
SCK
Digital Output Mode Control Bit
0 = Full Rate CMOS Output Mode
1 = Double Data Rate LVDS Output Mode
(3.5mA LVDS Current, Internal Termination Off)
SDI/SDO Power Down Control Bit
00 = Normal Operation
01 = Channel 1 in Normal Operation, Channel 2 in Nap Mode
10 = Channel 1 and Channel 2 in Nap Mode
11 = Sleep Mode (Entire Device Powered Down)
21454312p
26
LTC2145-12/
LTC2144-12/LTC2143-12
APPLICATIONS INFORMATION
Serial Programming Mode
GROUNDING AND BYPASSING
To use the serial programming mode, PAR/SER should be
tied to ground. The CS, SCK, SDI and SDO pins become
a serial interface that program the A/D mode control
registers. Data is written to a register with a 16-bit serial
word. Data can also be read back from a register to verify
its contents.
The LTC2145-12/LTC2144-12/LTC2143-12 requires a
printed circuit board with a clean unbroken ground plane.
A multilayer board with an internal ground plane in the
first layer beneath the ADC is recommended. Layout for
the printed circuit board should ensure that digital and
analog signal lines are separated as much as possible. In
particular, care should be taken not to run any digital track
alongside an analog signal track or underneath the ADC.
Serial data transfer starts when CS is taken low. The data
on the SDI pin is latched at the first 16 rising edges of
SCK. Any SCK rising edges after the first 16 are ignored.
The data transfer ends when CS is taken high again.
The first bit of the 16-bit input word is the R/W bit. The
next seven bits are the address of the register (A6:A0).
The final eight bits are the register data (D7:D0).
If the R/W bit is low, the serial data (D7:D0) will be written to the register set by the address bits (A6:A0). If the
R/W bit is high, data in the register set by the address bits
(A6:A0) will be read back on the SDO pin (see the timing
diagrams). During a read back command the register is
not updated and data on SDI is ignored.
The SDO pin is an open drain output that pulls to ground
with a 200Ω impedance. If register data is read back
through SDO, an external 2k pull-up resistor is required.
If serial data is only written and read back is not needed,
then SDO can be left floating and no pull-up resistor is
needed.
Table 3 shows a map of the mode control registers.
Software Reset
If serial programming is used, the mode control registers
should be programmed as soon as possible after the power
supplies turn on and are stable. The first serial command
must be a software reset which will reset all register data
bits to logic 0. To perform a software reset, bit D7 in the
reset register is written with a logic 1. After the reset is
complete, bit D7 is automatically set back to zero.
High quality ceramic bypass capacitors should be used at
the VDD, OVDD, VCM, VREF, REFH and REFL pins. Bypass
capacitors must be located as close to the pins as possible.
Size 0402 ceramic capacitors are recommended. The traces
connecting the pins and bypass capacitors must be kept
short and should be made as wide as possible.
Of particular importance is the capacitor between REFH
and REFL. This capacitor should be on the same side of
the circuit board as the A/D, and as close to the device
as possible.
The analog inputs, encode signals, and digital outputs
should not be routed next to each other. Ground fill and
grounded vias should be used as barriers to isolate these
signals from each other.
HEAT TRANSFER
Most of the heat generated by the LTC2145-12/LTC2144-12/
LTC2143-12 is transferred from the die through the bottomside exposed pad and package leads onto the printed circuit
board. For good electrical and thermal performance, the
exposed pad must be soldered to a large grounded pad
on the PC board. This pad should be connected to the
internal ground planes by an array of vias.
21454312p
27
LTC2145-12/
LTC2144-12/LTC2143-12
APPLICATIONS INFORMATION
Table 3. Serial Programming Mode Register Map (PAR/SER = GND)
REGISTER A0: RESET REGISTER (ADDRESS 00h)
D7
D6
D5
D4
D3
D2
D1
D0
RESET
X
X
X
X
X
X
X
Bit 7
RESET
Software Reset Bit
0 = Not Used
1 = Software Reset. All Mode Control Registers Are Reset to 00h. The ADC Is Momentarily Placed in SLEEP Mode. This Bit Is
Automatically Set Back to Zero After the Reset Is Complete
Bits 6-0
Unused, Don’t Care Bits.
REGISTER A1: POWER-DOWN REGISTER (ADDRESS 01h)
D7
D6
D5
D4
D3
D2
D1
D0
X
X
X
X
X
X
PWROFF1
PWROFF0
Bits 7-2
Unused, Don’t Care Bits.
Bits 1-0
PWROFF1:PWROFF0
Power Down Control Bits
00 = Normal Operation
01 = Channel 1 in Normal Operation, Channel 2 in Nap Mode
10 = Channel 1 and Channel 2 in Nap Mode
11 = Sleep Mode
REGISTER A2: TIMING REGISTER (ADDRESS 02h)
D7
D6
D5
D4
D3
D2
D1
D0
X
X
X
X
CLKINV
CLKPHASE1
CLKPHASE0
DCS
Bits 7-4
Unused, Don’t Care Bits.
Bit 3
CLKINV
Output Clock Invert Bit
0 = Normal CLKOUT Polarity (As Shown in the Timing Diagrams)
1 = Inverted CLKOUT Polarity
Bits 2-1
CLKPHASE1:CLKPHASE0
Output Clock Phase Delay Bits
00 = No CLKOUT Delay (As Shown in the Timing Diagrams)
01 = CLKOUT+/CLKOUT– Delayed by 45° (Clock Period • 1/8)
10 = CLKOUT+/CLKOUT– Delayed by 90° (Clock Period • 1/4)
11 = CLKOUT+/CLKOUT– Delayed by 135° (Clock Period • 3/8)
Note: If the CLKOUT Phase Delay Feature Is Used, the Clock Duty Cycle Stabilizer Must Also Be Turned On
Bit 0
DCS
Clock Duty Cycle Stabilizer Bit
0 = Clock Duty Cycle Stabilizer Off
1 = Clock Duty Cycle Stabilizer On
21454312p
28
LTC2145-12/
LTC2144-12/LTC2143-12
APPLICATIONS INFORMATION
REGISTER A3: OUTPUT MODE REGISTER (ADDRESS 03h)
D7
D6
D5
D4
D3
D2
D1
D0
X
ILVDS2
ILVDS1
ILVDS0
TERMON
OUTOFF
OUTMODE1
OUTMODE0
Bit 7
Unused, Don’t Care Bit.
Bits 6-4
ILVDS2:ILVDS0 LVDS Output Current Bits
000 = 3.5mA LVDS Output Driver Current
001 = 4.0mA LVDS Output Driver Current
010 = 4.5mA LVDS Output Driver Current
011 = Not Used
100 = 3.0mA LVDS Output Driver Current
101 = 2.5mA LVDS Output Driver Current
110 = 2.1mA LVDS Output Driver Current
111 = 1.75mA LVDS Output Driver Current
Bit 3
TERMON
LVDS Internal Termination Bit
0 = Internal Termination Off
1 = Internal Termination On. LVDS Output Driver Current is 2× the Current Set by ILVDS2:ILVDS0
Bit 2
OUTOFF
Output Disable Bit
0 = Digital Outputs Are Enabled
1 = Digital Outputs Are Disabled and Have High Output Impedance
Note: If the Digital Outputs Are Disabled the Part Should Also Be Put in Sleep or Nap Mode (Both Channels).
Bits 1-0
OUTMODE1:OUTMODE0
Digital Output Mode Control Bits
00 = Full Rate CMOS Output Mode
01 = Double Data Rate LVDS Output Mode
10 = Double Data Rate CMOS Output Mode
11 = Not Used
REGISTER A4: DATA FORMAT REGISTER (ADDRESS 04h)
D7
D6
D5
D4
D3
D2
D1
D0
X
X
OUTTEST2
OUTTEST1
OUTTEST0
ABP
RAND
TWOSCOMP
Bit 7-6
Unused, Don’t Care Bits.
Bits 5-3
OUTTEST2:OUTTEST0
Digital Output Test Pattern Bits
000 = Digital Output Test Patterns Off
001 = All Digital Outputs = 0
011 = All Digital Outputs = 1
101 = Checkerboard Output Pattern. OF, D11-D0 Alternate Between 1 0101 0101 0101 and 0 1010 1010 1010
111 = Alternating Output Pattern. OF, D11-D0 Alternate Between 0 0000 0000 0000 and 1 1111 1111 1111
Note: Other Bit Combinations Are not Used
Bit 2
ABP
Alternate Bit Polarity Mode Control Bit
0 = Alternate Bit Polarity Mode Off
1 = Alternate Bit Polarity Mode On. Forces the Output Format to Be Offset Binary
Bit 1
RAND
Data Output Randomizer Mode Control Bit
0 = Data Output Randomizer Mode Off
1 = Data Output Randomizer Mode On
Bit 0
TWOSCOMP
Two’s Complement Mode Control Bit
0 = Offset Binary Data Format
1 = Two’s Complement Data Format
21454312p
29
LTC2145-12/
LTC2144-12/LTC2143-12
TYPICAL APPLICATIONS
Silkscreen Top
Top Side
21454312p
30
LTC2145-12/
LTC2144-12/LTC2143-12
TYPICAL APPLICATIONS
Inner Layer 2 GND
Inner Layer 3
21454312p
31
LTC2145-12/
LTC2144-12/LTC2143-12
TYPICAL APPLICATIONS
Inner Layer 4
Inner Layer 5 Power
21454312p
32
LTC2145-12/
LTC2144-12/LTC2143-12
TYPICAL APPLICATIONS
Bottom Side
21454312p
33
LTC2145-12/
LTC2144-12/LTC2143-12
TYPICAL APPLICATIONS
SDO
C23
2.2μF
SENSE
C17
1μF
9
CN1
+
–
11
12
13
14
15
16
60
59
58
57
56
55
54
53
52
51
50
49
OF2_1–
D1_10_11+
D1_10_11–
D1_8_9+
D1_8_9–
D1_6_7+
D1_6_7–
D1_4_5+
D1_4_5–
D1_2_3+
D1_2_3–
OF2_1
61
SDO
62
VREF
REFH
OVDD
REFL
OGND
LTC2145-12
45
44
43
42
40
39
PAR/SER
D2_10_11+
38
+
D2_10_11–
37
AIN2–
D2_8_9+
36
GND
D2_8_9–
35
VCM2
D2_6_7+
34
VDD
D2_6_7–
33
AIN2
DNC
D2_0_1
27
DNC
DNC
DNC
26
25
24
23
SCK
CS
SDI
22
21
17
AIN2–
20
ENC–
19
VDD
AIN2+
PAD
C37
0.1μF
41
CLKOUT–
REFL
DIGITAL
OUTPUTS
46
CLKOUT+
REFH
–
PAR/SER
DNC
ENC+
C21
0.1μF
–
+
10
GND
D2_4_5+
8
DNC
32
+
–
–
+
DNC
AIN1–
D2_4_5–
7
AIN1
18
C15
0.1μF
6
DNC
+
31
AIN1
GND
D2_2_3+
5
47
30
–
AIN1
D1_0_1–
D2_2_3–
4
VCM1
VDD
29
+
48
D2_0_1+
3
D1_0_1+
28
2
+
1
SENSE
VDD
64
C19
C20 0.1μF
0.1μF
63
VDD
OVDD
DIGITAL
OUTPUTS
65
VDD
C67
0.1μF
C18
0.1μF
C78
0.1μF
C79
0.1μF
R51
100Ω
ENCODE
CLOCK
SPI BUS
21454312 TA02
LTC2145-12 Schematic
21454312p
34
LTC2145-12/
LTC2144-12/LTC2143-12
PACKAGE DESCRIPTION
UP Package
64-Lead Plastic QFN (9mm × 9mm)
(Reference LTC DWG # 05-08-1705 Rev C)
0.70 ±0.05
7.15 ±0.05
7.50 REF
8.10 ±0.05 9.50 ±0.05
(4 SIDES)
7.15 ±0.05
PACKAGE OUTLINE
0.25 ±0.05
0.50 BSC
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
9 .00 ± 0.10
(4 SIDES)
0.75 ± 0.05
R = 0.10
TYP
R = 0.115
TYP
63 64
0.40 ± 0.10
PIN 1 TOP MARK
(SEE NOTE 5)
1
2
PIN 1
CHAMFER
C = 0.35
7.15 ± 0.10
7.50 REF
(4-SIDES)
7.15 ± 0.10
(UP64) QFN 0406 REV C
0.25 ± 0.05
0.200 REF
0.00 – 0.05
NOTE:
1. DRAWING CONFORMS TO JEDEC PACKAGE OUTLINE MO-220 VARIATION WNJR-5
2. ALL DIMENSIONS ARE IN MILLIMETERS
3. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE, IF PRESENT
4. EXPOSED PAD SHALL BE SOLDER PLATED
5. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE
6. DRAWING NOT TO SCALE
0.50 BSC
BOTTOM VIEW—EXPOSED PAD
21454312p
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
35
LINEAR TECHNOLOGY CONFIDENTIAL
LTC2145-12/
LTC2144-12/LTC2143-12
TYPICAL APPLICATION
1.8V
2-Tone FFT, fIN = 70MHz and 69MHz
1.8V
VDD
OVDD
0
–10
CH 2
ANALOG
INPUT
D1_11
•
•
•
D1_0
12-BIT
ADC CORE
S/H
12-BIT
ADC CORE
S/H
125MHz
D2_11
•
•
•
D2_0
OUTPUT
DRIVERS
–30
CMOS
OR
LVDS
OUTPUTS
–40
–50
–60
–70
–80
–90
–100
–110
–120
CLOCK
CONTROL
CLOCK
–20
AMPLITUDE (dBFS)
CH 1
ANALOG
INPUT
0
10
20
30
40
FREQUENCY (MHz)
50
21854312 TA03
21454312 TA01a
GND
60
OGND
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
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370mW/308mW/200mW, 76.8dB SNR, 90dB SFDR, DDR LVDS/DDR CMOS/CMOS
Outputs, 9mm × 9mm QFN-64
ADCs
LTC2185/LTC2184/
LTC2183
LTC2145-14/LTC2144-14/ 14-Bit, 125Msps/105Msps/80Msps 1.8V/ 190mW/160mW/120mW, 73dB SNR, 90dB SFDR, DDR LVDS/DDR CMOS/CMOS
LTC2143-14
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LTC2259-14/LTC2260-14/ 14-Bit, 80Msps/105Msps/125Msps
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6mm × 6mm QFN-40
14-Bit, 150Msps 1.8V ADC, Ultralow
Power
LTC2266-14/LTC2267-14/ 14-Bit, 80Msps/105Msps/125Msps
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216mW/250mW/293mW, 73.4dB SNR, 85dB SFDR, Serial LVDS Outputs,
6mm × 6mm QFN-40
LTC2266-12/LTC2267-12/ 12-Bit, 80Msps/105Msps/125Msps
LTC2268-12
1.8V Dual ADCs, Ultralow Power
216mW/250mW/293mW, 70.5dB SNR, 85dB SFDR, Serial LVDS Outputs,
6mm × 6mm QFN-40
RF Mixers/Demodulators
LTC5517
40MHz to 900MHz Direct Conversion
Quadrature Demodulator
High IIP3: 21dBm at 800MHz, Integrated LO Quadrature Generator
LTC5557
400MHz to 3.8GHz High Linearity
Downconverting Mixer
23.7dBm IIP3 at 2.6GHz, 23.5dBm IIP3 at 3.5GHz, NF = 13.2dB, 3.3V Supply
Operation, Integrated Transformer
LTC5575
800MHz to 2.7GHz Direct Conversion
Quadrature Demodulator
High IIP3: 28dBm at 900MHz, Integrated LO Quadrature Generator, Integrated RF
and LO Transformer
Amplifiers/Filters
LTC6412
800MHz, 31dB Range, Analog-Controlled Continuously Adjustable Gain Control, 35dBm OIP3 at 240MHz, 10dB Noise Figure,
Variable Gain Amplifier
4mm × 4mm QFN-24
LTC6605-7/LTC6605-10/
LTC6605-14
Dual Matched 7MHz/10MHz/14MHz
Filters with ADC Drivers
Dual Matched 2nd Order Lowpass Filters with Differential Drivers,
Pin-Programmable Gain, 6mm × 3mm DFN-22
14-Bit Dual Channel IF/Baseband
Receiver Subsystem
Integrated High Speed ADC, Passive Filters and Fixed Gain Differential Amplifiers
Signal Chain Receivers
LTM9002
21454312p
36 Linear Technology Corporation
LT 0311 • PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507
●
www.linear.com
©LINEAR TECHNOLOGY CORPORATION 2011