CY2071A Single-PLL General-Purpose EPROM Programmable Clock Generator Features Benefits Single phase-locked loop architecture Generates a custom frequency from an external source EPROM programmability Easy customization and fast turnaround Factory-programmable (CY2071A, CY2071AI) or field- Programming support available for all opportunities programmable (CY2071AF, CY2071AFI) device options Up to three configurable outputs Generates three related frequencies from a single device Low-skew, low-jitter, high-accuracy outputs Meets critical industry standard timing requirements Internal loop filter Alleviates the need for external components Power management (OE) Supports low-power applications Frequency select options 3 outputs with 2 user selectable frequencies Configurable 5V or 3.3V operation Supports industry standard design platforms 8-pin 150-mil SOIC package Industry-standard packaging saves on board space i Selector Guide Part Number Outputs Input Frequency Range Output Frequency Range Specifics CY2071A 3 10 MHz–25 MHz (external crystal) 1 MHz–30 MHz (reference clock) 500 kHz–130 MHz (5V) 500 kHz–100 MHz (3.3V) Factory Programmable Commercial Temperature CY2071AI 3 10 MHz–25 MHz (external crystal) 1 MHz–30 MHz (reference clock) 500 kHz–100 MHz (5V) 500 kHz–80 MHz (3.3V) Factory Programmable Industrial Temperature CY2071AF 3 10 MHz–25 MHz (external crystal) 1 MHz–30 MHz (reference clock) 500 kHz–100 MHz (5V) 500 kHz–80 MHz (3.3V) Field Programmable Commercial Temperature CY2071AFI 3 10 MHz–25 MHz (external crystal) 1 MHz–30 MHz (reference clock) 500 kHz–90 MHz (5V) 500 kHz–66.6 MHz (3.3V) Field Programmable Industrial Temperature Logic Block Diagram for CY2071A XTALIN REFERENCE OSCILLATOR CLKA EPROMConfigurable Multiplexer and Divide Logic XTALOUT PLL Block CLKB CLKC OE / FS Pin Configuration 8-pin SOIC Top View 1 2 3 4 CLKA GND XTALIN XTALOUT Cypress Semiconductor Corporation Document #: 38-07139 Rev. *A • 8 7 6 5 OE/FS VDD CLKC CLKB 3901 North First Street • San Jose • CA 95134 • 408-943-2600 Revised December 14, 2002 CY2071A Pin Summary Name Number Description CLKA 1 Configurable Clock Output GND 2 Ground XTALIN[1] 3 Reference Crystal Input or External Reference Clock Input XTALOUT[1, 2] 4 Reference Crystal Feedback CLKB 5 Configurable Clock Output CLKC 6 Configurable Clock Output VDD 7 Voltage Supply OE / FS 8 Output Control Pin, either Output Enable or Frequency Select Input (Active-HIGH, internal pull-up resistor to VDD) Notes: 1. For best accuracy, use a parallel-resonant crystal, CL = 17 pF. 2. Float XTALOUT pin if XTALIN is driven by reference clock (as opposed to an external crystal). Functional Description The CY2071A is a general-purpose clock synthesizer designed for use in applications such as modems, disk drives, CD-ROM drives, video CD players, games, set-top boxes, and data/telecommunications. The device offers up to three configurable clock outputs in an 8-pin, 150-mil SOIC package and can operate off either a 3.3V or 5V power supply. The on-chip reference oscillator is designed for 10-MHz to 25-MHz crystals. Alternatively, an external reference clock of frequency between 1 MHz and 30 MHz can be used. The CY2071A has one PLL and outputs three factory-EPROM configurable clocks: CLKA, CLKB, and CLKC. The output clocks can originate either from the PLL or the reference, or selected dividers thereof. Additionally, pin 8 can be configured to be an Output Enable or a Select input. The CY2071A can replace multiple Metal Can Oscillators (MCO) in a synchronous system, providing cost and board space savings to the manufacturer. Hence, these devices are ideally suited for applications that require multiple, accurate, and stable clocks synthesized from low-cost generators in small packages. A hard-disk drive is an example of such an application. In this case, CLKA drives the PLL in the Read Controller, while CLKB and CLKC drive the MCU and associated sequencers. sheet when specifying them in CyClocks to ensure that you stay within the limits. You can download a copy of CyClocks free on the Cypress Semiconductor website at www.cypress.com. Consider using the CY2081 for applications that require unrelated output frequencies. Consider using the CY2291, CY2292, or CY2907 for applications that require more than three output clocks. Cypress FTG Programmer The Cypress Frequency Timing Generator (FTG) Programmer is a portable programmer designed to custom program our family of EPROM Field Programmable Clock Devices. The FTG programmers connect to a PC serial port and allow users of CyClocks software to quickly and easily program any of the CY2291F, CY2292F, CY2071AF, and CY2907F devices. The ordering code for the Cypress FTG Programmer is CY3670. Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Supply Voltage ...............................................–0.5V to +7.0V DC Input Voltage ..................................... –0.5V to VDD+0.5V CyClocks™ Software Storage Temperature ................................. –65°C to +150°C CyClocks is an easy-to-use software application that allows you to configure any one of the EPROM-Programmable Clocks offered by Cypress. You may specify the input frequency, PLL and output frequencies, and different functional options. Please note the output frequency ranges in this data Junction Temperature...................................................150°C Document #: 38-07139 Rev. *A Max. Soldering Temperature (10 sec) ..........................260°C Static Discharge Voltage............................................ >2000V (per MIL-STD-883, Method 3015) Page 2 of 8 CY2071A Operating Conditions[3] Parameter Description Min. Max. Unit VDD Supply Voltage, 5.0V Operation 4.5 5.5 V VDD Supply Voltage, 3.3V Operation 3.0 3.6 V TA Commercial Operating Temperature, Ambient 0 70 °C –40 85 °C Max. Load Capacitance per Output (5V Operation) 25 pF Max. Load Capacitance per Output (3.3V Operation) 15 pF Industrial Operating Temperature, Ambient CL fREF tPU External Reference Crystal 10.0 25.0 MHz External Reference Clock[4, 5] 1.0 30.0 MHz Power-up time for all VDD's to reach minimum specified voltage (power ramps must be monotonic) 0.05 50 ms Electrical Characteristics, Commercial 5.0V VDD = 5V ±10%, TA = 0°C to +70°C Parameter Description Conditions VOH HIGH-Level Output Voltage IOH = –4.0 mA VOL LOW-Level Output Voltage IOL = 4.0 mA VIH HIGH-Level Input Voltage[6] Voltage[6] VIL LOW-Level Output IIH Input HIGH Current IIL Input LOW Current IOZ Output Leakage Current IDD VDD Supply Current[7] Min. Typ. Max. 2.4 V 0.4 Except Crystal Pins Unit 2.0 V V Except Crystal Pins 0.8 V VIN = VDD – 0.5V 10 µA VIN = 0.5V 150 µA Three State Outputs 250 µA 40 60 mA Typ. Max. Unit VDD = VDD max. 5V operation, CL = 25 pF Electrical Characteristics, Commercial 3.3V VDD = 3.3V ±10%, TA = 0°C to +70°C Parameter Description Conditions VOH HIGH-Level Output Voltage IOH = –4.0 mA VOL LOW-Level Output Voltage IOL = 4.0 mA VIH HIGH-Level Input Voltage[6] Except Crystal Pins VIL LOW-Level Output IIH Voltage[6] Min. 2.4 V 0.4 2.0 V V Except Crystal Pins 0.8 V Input HIGH Current VIN = VDD – 0.5V 10 µA IIL Input LOW Current VIN = 0.5V 150 µA IOZ Output Leakage Current Three State Outputs 250 µA 40 mA IDD VDD Supply Current[7] VDD = VDD max. 3.3V operation, CL = 15 pF 24 Notes: 3. Electrical parameters are guaranteed with these operating conditions. Values for 3.3V operation are shown in parentheses. 4. External input reference clock must have a duty cycle between 40% and 60%, measured at VDD/2. 5. Please refer to application note “Crystal Oscillator Topics” for information on AC-coupling the external input reference clock. 6. Xtal inputs have CMOS thresholds. 7. Load = max, typical configuration, fREF = 14.318 MHz. Specific configurations may vary. A close approximation of IDD can be derived by the following formula: IDD(mA) = VDD*(6.25+(0.055*FREF) + (0.0017*CLOAD*(FCLKA+FCLKB+FCLKC))). CLOAD is specified in pF and F is specified in MHz. Document #: 38-07139 Rev. *A Page 3 of 8 CY2071A Electrical Characteristics, Industrial 5.0V VDD =5.0V ±10%, TA = –40°C to +85°C Parameter Description Conditions VOH HIGH-Level Output Voltage IOH = –4.0 mA VOL LOW-Level Output Voltage IOL = 4.0 mA [6] Min. Typ. Max. 2.4 V 0.4 Except Crystal Pins Unit 2.0 V VIH HIGH-Level Input Voltage VIL LOW-Level Output Voltage[6] Except Crystal Pins 0.8 V V IIH Input HIGH Current VIN = VDD – 0.5V 10 µA IIL Input LOW Current VIN = 0.5V 150 µA IOZ Output Leakage Current Three State Outputs IDD VDD Supply Current[7] VDD = VDD max. 5V operation, CL = 25 pF 250 µA 40 75 mA Typ. Max. Unit Electrical Characteristics, Industrial 3.3V VDD =3.3V ±10%, TA = –40°C to +85°C Parameter Description Conditions VOH HIGH-Level Output Voltage IOH = –4.0 mA VOL LOW-Level Output Voltage IOL = 4.0 mA VIH HIGH-Level Input Voltage[6] Voltage[6] VIL LOW-Level Output IIH Input HIGH Current IIL Input LOW Current IOZ Output Leakage Current IDD VDD Supply Current[7] Min. 2.4 V 0.4 Except Crystal Pins 2.0 V V Except Crystal Pins 0.8 V VIN = VDD – 0.5V 10 µA VIN = 0.5V 150 µA Three State Outputs 250 µA 50 mA VDD = VDD max. 3.3V operation, CL = 15 pF 24 Switching Characteristics, Commercial 5.0V[8] Parameter t1 Name Output Period Description Clock output range 5V operation 25-pF load Max. Unit CY2071A 7.692 [130 MHz] Min. Typ. 2000 [500 kHz] ns CY2071AF 10 [100 MHz] 2000 [500 kHz] ns t1A Clock Jitter Peak-to-peak period jitter (t1 max. – t1 min.), % of clock period, fOUT ≤ 16 MHz 0.8 1 % t1B Clock Jitter Peak-to-peak period jitter (16 MHz ≤ fOUT ≤ 50 MHz) 350 500 ps t1C Clock Jitter[9] Peak-to-peak period jitter (fOUT > 50 MHz) 250 350 ps 45% 50% 55% 40% 50% 60% Output clock rise time 1.5 2.5 ns Output clock fall time 1.5 2.5 ns 0.5 ns Output Duty Cycle cycle[10, 11] Duty fOUT ≤ 60 MHz for outputs, (t2 ÷ t1) Output Duty Cycle[9] Duty cycle[11] for outputs, (t2 ÷ t1), fOUT > 60 MHz t3 Rise Time[9] Time[9] t4 Fall t5 Skew Skew delay between any two outputs with identical frequencies (generated by the PLL) Notes: 8. Guaranteed by design, not 100% tested. 9. When the output clock frequency is between 100 MHz and 130 MHz at 5V, the maximum capacitive load for these measurements is 15 pF. 10. Reference Output duty cycle depends on XTALIN duty cycle. 11. Measured at 1.4V. Document #: 38-07139 Rev. *A Page 4 of 8 CY2071A Switching Characteristics, Commercial 3.3V[8] Parameter t1 Name Output Period Description Clock output range 3.3V operation 15-pF load Min. Typ. Max. Unit CY2071AS 10 [100 MHz] 2000 [500 kHz] ns CY2071AF 12.50 [80 MHz] 2000 [500 kHz] ns t1A Clock Jitter Peak-to-peak period jitter (t1 max. – t1 min.), % of clock period, fOUT ≤ 16 MHz 0.8 1 % t1B Clock Jitter Peak-to-peak period jitter (16 MHz ≤ fOUT ≤ 50 MHz) 350 500 ps t1C Clock Jitter[9] Peak-to-peak period jitter (fOUT > 50 MHz) 250 350 ps 45% 50% 55% 40% 50% 60% Output clock rise time 1.5 2.5 ns Output clock fall time 1.5 2.5 ns 0.5 ns Output Duty Cycle [10, 11] Duty cycle fOUT ≤ 60 MHz for outputs, (t2 ÷ t1) Output Duty Cycle[9] Duty cycle[11] for outputs, (t2 ÷ t1), fOUT > 60 MHz t3 Rise Time[9] t4 Fall Time t5 Skew [9] Skew delay between any two outputs with identical frequencies (generated by the PLL) Switching Characteristics, Industrial 5.0V[8] Parameter t1 Name Output Period Description Clock output range 5.0V operation 25-pF load Max. Unit CY2071AI Min. 10 [100 MHz] Typ. 2000 [500 kHz] ns CY2071AFI 11.1 [90 MHz] 2000 [500 kHz] ns t1A Clock Jitter Peak-to-peak period jitter (t1 max. – t1 min.), % of clock period, fOUT ≤ 16 MHz 0.8 1 % t1B Clock Jitter Peak-to-peak period jitter (16 MHz ≤ fOUT ≤ 50 MHz) 350 500 ps t1C Clock Jitter[9] Peak-to-peak period jitter (fOUT > 50 MHz) 250 350 ps Output Duty Cycle Duty cycle[10, 11] for outputs, (t2 ÷ t1) fOUT ≤ 60 MHz 45% 50% 55% 40% 50% 60% Output clock rise time 1.5 2.5 ns Output clock fall time 1.5 2.5 ns 0.5 ns Output Duty Cycle[9] Duty cycle[11] for outputs, (t2 ÷ t1), fOUT > 60 MHz t3 Rise time[9] time[9] t4 Fall t5 Skew Document #: 38-07139 Rev. *A Skew delay between any two outputs with identical frequencies (generated by the PLL) Page 5 of 8 CY2071A Switching Characteristics, Industrial 3.3V[8] Parameter t1 Name Description Output Period Clock output range 3.3V operation 15-pF load Min. CY2071AI CY2071AFI Typ. Max. Unit 12.50 [80 MHz] 2000 [500 kHz] ns 15.0 [66.6 MHz] 2000 [500 kHz] ns t1A Clock Jitter Peak-to-peak period jitter (t1 max. – t1 min.), % of clock period, fOUT ≤ 16 MHz 0.8 1 % t1B Clock Jitter Peak-to-peak period jitter (16 MHz ≤ fOUT ≤ 50 MHz) 350 500 ps t1C Clock Jitter[9] Peak-to-peak period jitter (fOUT > 50 MHz) 250 350 ps Output Duty Cycle Duty cycle[10, 11] for outputs, (t2 ÷ t1) fOUT ≤ 60 MHz 45% 50% 55% 40% 50% 60% Output Duty Cycle[9] Duty cycle[11] for outputs, (t2 ÷ t1), fOUT > 60 MHz t3 Rise time[9] Output clock rise time 1.5 2.5 ns t4 Fall time[9] Output clock fall time 1.5 2.5 ns t5 Skew Skew delay between any two outputs with identical frequencies (generated by the PLL) 0.5 ns Switching Waveforms All Outputs Duty Cycle and Rise/Fall Time t1 t2 OUTPUT 2.4V 0.4V t3 VDD 2.4V 0.4V 0V t4 2071A–3 Output-Output Clock Skew OUTPUT OUTPUT t5 Document #: 38-07139 Rev. *A 2071A–4 Page 6 of 8 CY2071A Test Circuit VDD 7 0.1 µF OUTPUTS CLK output CLOAD 2 GND 2071A–5 Ordering Information Ordering Code Package Name Package Type Operating Range CY2071ASC-XXX S8 8-Pin (150-Mil) SOIC 5.0V, Commercial, Factory Programmable CY2071ASL-XXX S8 8-Pin (150-Mil) SOIC 3.3V, Commercial, Factory Programmable CY2071ASI-XXX S8 8-Pin (150-Mil) SOIC 5V/3.3V, Industrial, Factory Programmable CY2071AF S8 8-Pin (150-Mil) SOIC 5V/3.3V, Commercial, Field Programmable CY2071AFI S8 8-Pin (150-Mil) SOIC 5V/3.3V, Industrial, Field Programmable FTG Programmer Custom programming for Field Programmable Clocks CY3670 Package Characteristics Package θJA (C/W) θJC (C/W) Transistor Count 170 35 5436 8 Pin SOIC Package Diagram 8-Lead (150-Mil) SOIC S8 51-85066-A Document #: 38-07139 Rev. *A Page 7 of 8 © Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. CY2071A Document Title: CY2071A Single-PLL General-Purpose EPROM Programmable Clock Generator Document Number: 38-07139 REV. ECN NO. Issue Date Orig. of Change ** 110248 12/17/01 SZV *A 121827 12/14/02 RBI Document #: 38-07139 Rev. *A Description of Change Change from Spec number: 38-00521 to 38-07139 Power up requirements added to Operating Conditions Information Page 8 of 8