LT1573 Low Dropout PNP Regulator Driver U FEATURES ■ ■ ■ ■ ■ ■ ■ ■ ■ DESCRIPTIO The LT ®1573 is a regulator driver IC designed to provide a low cost solution for applications requiring high current, low dropout and fast transient response. When combined with an external PNP power transistor, this device provides load current up to 5A with dropout voltages as low as 0.35V. The LT1573 circuitry is designed for extremely fast transient response. This greatly reduces bulk storage capacitance when the regulator is used in applications with fast, high current load transients. Low Cost Solution for High Current, Low Dropout Regulators Fast Transient Response Needs Much Less Bulk Capacitance Latching Overload Protection Minimizes Heat Sink Size Precision Output Voltage (1%) Single Supply Operation: VIN = 2.8V to 10V Small Surface Mount Package Capable of Very Low Dropout Voltage (<0.2V) Fixed or Adjustable Outputs Shutdown To keep cost and complexity low, the LT1573 uses a new time-delayed latching overcurrent protection technique that requires no external current sense resistor. Base drive is limited for instantaneous protection, and a time-delayed latch protects the regulator from continuous short circuits. U APPLICATIO S ■ ■ ■ ■ ■ ■ 3.3V to 2.5V Regulators Microprocessor Power Sources Post Regulator for Switching Supplies High Efficiency Linear Regulators Ultralow Dropout Regulators Low Voltage Linear Regulators The LT1573 is available as an adjustable regulator with an output range of 1.27V to 6.8V and with fixed output voltages of 2.5V, 2.8V and 3.3V. Output accuracy is better than 1% to meet the critical regulation requirement of fast microprocessors. A special 8-pin, fused-lead surface mount package is used to minimize regulator footprint and provide adequate heat sinking. , LTC and LT are registered trademarks of Linear Technology Corporation. U TYPICAL APPLICATIO CC 100pF FB COMP LATCH VOUT LT1573 + CTIME Transient Response for 0.2A to 5A Output Load Step RC 1k SHDN GND VIN RD 24Ω DRIVE VIN 5V CIN 100µF TANT + RB 50Ω COUT1 1µF CER × 24 50mV/DIV QOUT MOTOROLA D45H11 + COUT2 220µF TANT VOUT 3.3V R1 1.6k 2.5A/DIV LOAD R2 1k GND VOUT = 1.265V (1 + R1/R2) FOR T < 45°C, COUT1 = 24 × 1µF Y5V CERAMIC SURFACE MOUNT CAPACITORS. FOR T > 45°C, COUT1 = 24 × 1µF X7R CERAMIC SURFACE MOUNT CAPACITORS. PLACE COUT1 IN THE MICROPROCESSOR SOCKET CAVITY 10µs/DIV 1573 F01a 1573 F01 Figure 1. 3.3V, 5A Microprocessor Supply 1 LT1573 W W W AXI U U ABSOLUTE RATI GS U U W PACKAGE/ORDER I FOR ATIO (Note 1) ORDER PART NUMBER Input Pin Voltage (VIN to GND) ............................... 10V Drive Pin Voltage (VDRIVE to GND).......................... 10V Output Pin Voltage (VOUT to GND) .......................... 10V Shutdown Pin Voltage (VSHDN to GND) .................. 10V Operating Junction Temperature Range LT1573C ............................................... 0°C to 125°C LT1573I ............................................ –40°C to 125°C Storage Temperature Range ................ – 65°C to 150°C Lead Temperature (Soldering, 10 sec.)................ 300°C TOP VIEW FB 1 8 COMP LATCH 2 7 VOUT SHDN 3 6 VIN GND 4 5 DRIVE S8 PACKAGE 8-LEAD PLASTIC SO LT1573CS8 LT1573CS8-2.5 LT1573CS8-2.8 LT1573CS8-3.3 LT1573IS8 S8 PART MARKING 157333 1573 157325 1573I 157328 TJMAX = 125°C, θJA = 85°C/ W Consult factory for Military grade parts. ELECTRICAL CHARACTERISTICS The ● denotes specifications that apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VIN = 5V, VDRIVE = 3V, unless otherwise noted. PARAMETER CONDITIONS MIN TYP MAX UNITS DC Characteristics LT1573 Reference Voltage (Adjustable)(Note 2) IDRIVE = 20mA, TJ = 25°C 1.252 1.265 1.278 V ● 1.225 1.265 1.305 V 3.267 3.3 3.333 V ● 3.234 3.3 3.366 V 2.772 2.8 2.828 V ● 2.744 2.8 2.856 V 2.475 2.5 2.525 V 5mA < IDRIVE < 250mA, 3V < VIN < 7V, 1.5V < VDRIVE < 7V ● 2.450 2.5 2.550 V Line Regulation LT1573 (VFB) LT1573-3.3 (VOUT) LT1573-2.8 (VOUT) LT1573-2.5 (VOUT) IDRIVE = 20mA, 3V < VIN < 7V IDRIVE = 20mA, 3.5V < VIN < 7V IDRIVE = 20mA, 3V < VIN < 7V IDRIVE = 20mA, 3V < VIN < 7V ● ● ● ● 0.17 0.34 0.34 0.25 2 5 4 4 mV mV mV mV Load Regulation LT1573 (VFB) LT1573-3.3 (VOUT) LT1573-2.8 (VOUT) LT1573-2.5 (VOUT) ∆IDRIVE = 20mA to 250mA ∆IDRIVE = 20mA to 250mA ∆IDRIVE = 20mA to 250mA ∆IDRIVE = 20mA to 250mA ● ● ● ● 7 18 15 13 30 40 34 30 mV mV mV mV FB Pin Bias Current (Adjustable Only) VFB = 1.265V ● 0.8 5 µA DRIVE Pin Current VFB = 1.35V, VDRIVE = 7V VFB = 1.15V, VDRIVE = 1.5V ● ● 2 mA mA IDRIVE = 20mA, VFB = 1.15V IDRIVE = 250mA, VFB = 1.15V ● ● 5mA < IDRIVE < 250mA, 3V < VIN < 7V, 1.5V < VDRIVE < 7V LT1573-3.3 Output Voltage (Note 2) IDRIVE = 20mA. TJ = 25°C 5mA < IDRIVE < 250mA, 3.5V < VIN < 7V, 1.5V < VDRIVE < 7V LT1573-2.8 Output Voltage (Note 2) IDRIVE = 20mA, TJ = 25°C 5mA < IDRIVE < 250mA, 3V < VIN < 7V, 1.5V < VDRIVE < 7V LT1573-2.5 Output Voltage (Note 2) DRIVE Pin Saturation Voltage IDRIVE = 20mA, TJ = 25°C SHDN Pin Threshold Voltage SHDN Pin Current 2 ● VSHDN = 5V 250 1.0 440 0.12 0.73 0.3 1.4 V V 1.33 1.6 V 200 µA LT1573 ELECTRICAL CHARACTERISTICS The ● denotes specifications that apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VIN = 5V, VDRIVE = 3V, unless otherwise noted. PARAMETER CONDITIONS LATCH Pin Latch-Off Threshold Voltage ● MIN TYP MAX 0.8 1.4 2.2 UNITS V LATCH Pin Charging Current 7 µA LATCH Pin Latching Current 0.65 mA VIN – VOUT Differential Threshold for Latch Disable 0.4 ● Input Quiescent Current VIN = 7V ● Minimum Input Voltage for Bias Operation 1.0 V 3.5 mA 2.8 ● Note 1: Absolute Maximum Ratings are those values beyond which the life of the device may be impaired. Note 2: Operating conditions are limited by maximum junction temperature. The regulated feedback or output voltage specification will 0.7 1.7 V not apply for all possible combinations of input voltage, drive voltage and drive current. When operating at maximum drive current, the drive voltage range must be limited. When operating at maximum input and drive voltage, the drive current must be limited. U W TYPICAL PERFOR A CE CHARACTERISTICS LT1573-3.3V Output Voltage vs Temperature LT1573-2.8V Output Voltage vs Temperature 3.40 2.90 1.285 3.38 2.88 1.280 3.36 2.86 1.275 1.270 1.265 1.260 1.255 OUTPUT VOLTAGE (V) 1.290 OUTPUT VOLTAGE (V) FEEDBACK PIN VOLTAGE (V) LT1573 Feedback Pin Voltage vs Temperature 3.34 3.32 3.30 3.28 3.26 2.84 2.82 2.80 2.78 2.76 1.250 3.24 2.74 1.245 3.22 2.72 1.240 –50 –25 3.20 –50 0 25 50 75 100 125 150 TEMPERATURE (°C) 50 0 75 25 TEMPERATURE (°C) –25 100 2.70 –50 125 50 0 75 25 TEMPERATURE (°C) –25 1573 G02 1573 G01 2.60 125 1573 G03 Feedback Pin Bias Current vs Temperature LT1573-2.5V Output Voltage vs Temperature 100 Quiescent Current vs Temperature 2.5 3.0 2.58 2.54 2.52 2.50 2.48 2.46 2.44 2.0 QUIESCENT CURRENT (mA) FEEDBACK PIN CURRENT (µA) OUTPUT VOLTAGE (V) 2.56 1.5 1.0 0.5 2.5 2.0 1.5 1.0 0.5 2.42 2.40 –50 –25 50 0 75 25 TEMPERATURE (°C) 100 125 1573 G04 0 –50 –25 0 25 50 75 100 125 150 TEMPERATURE (°C) 1573 G05 0 –50 –25 0 25 50 75 100 125 150 TEMPERATURE (°C) 1573 G06 3 LT1573 U W TYPICAL PERFOR A CE CHARACTERISTICS Drive Pin Current vs Feedback Pin Voltage Drive Pin Saturation Voltage vs Drive Pin Current 450 TJ = 130°C 0.85 0.9 0.80 0.8 TJ = 25°C 300 1.0 TJ = –45°C 250 200 150 100 0.75 0.7 TJ = 130°C 0.6 0.5 TJ = –45°C 0.4 50 0.1 0 0 0.2 0.4 0.6 0.8 1.0 1.2 FEEDBACK PIN VOLTAGE (V) TJ = 25°C 50 TJ = 25°C 1.5 TJ = 125°C 1.0 0.5 3 4 5 6 INPUT VOLTAGE (V) 8 7 1.0 14 0.9 12 TJ = –45°C 10 TJ = 25°C 8 6 TJ = 125°C 4 2 2 3 5 4 6 INPUT VOLTAGE (V) 7 TJ = –45°C 0.7 0.5 0.4 0.3 0.2 8 0 2 3 4 5 6 INPUT VOLTAGE (V) 300 SHUTDOWN PIN CURRENT (µA) 1.4 1.3 1.2 1.1 TJ = 25°C 200 150 TJ = 125°C 100 50 0 25 50 75 100 125 150 TEMPERATURE (°C) TJ = –45°C 250 0 1 2 3 4 5 6 SHUTDOWN PIN VOLTAGE (V) 7 1573 G14 1573 G13 4 7 8 1573 G12 Shutdown Pin Current vs Shutdown Pin Voltage 1.5 0 TJ = 125°C 0.6 1573 G11 Shutdown Voltage Threshold vs Temperature SHUTDOWN THRESHOLD (V) TJ = 25°C 0.8 0.1 1573 G10 1.0 –50 –25 25 50 75 100 125 150 TEMPERATURE (°C) Latching Current vs Input Voltage 16 0 2 0 1573 G09 LATCHING CURRENT (mA) LATCH CHARGING CURRENT (µA) LATCH PIN LATCH-OFF THRESHOLD (V) 3.0 0 0.40 –50 –25 300 150 200 250 100 DRIVE PIN CURRENT (mA) Latch Charging Current vs Input Voltage 2.5 VIN = 5V LATCH DISABLED FOR (VIN – VOUT) < LATCH DISABLE THRESHOLD 1573 G08 Latch Pin Latch-Off Threshold vs Input Voltage TJ = –45°C 0.60 0.50 1573 G07 2.0 0.65 0.45 0 1.4 0.70 0.55 0.3 0.2 0 VIN – VOUT (V) 350 DRIVE PIN VOLTAGE (V) DRIVE PIN CURRENT (mA) 400 Latch-Disable Threshold (VIN – VOUT) vs Temperature LT1573 U U U PI FU CTIO S FB (Pin 1): The feedback pin is the inverting input of the error amplifier. The noninverting input of the error amplifier is internally connected to a 1.265V reference. The error amplifier will servo the drive to the output transistor, QOUT in Figure 1, to force the voltage at the feedback pin to be 1.265V. Output voltage is set by a resistor divider as shown in Figure 1. For adjustable devices an external resistor divider is used to set the output voltage. For fixed voltage devices the resistor divider is internal and the top of the resistor divider is connected to the VOUT pin. LATCH (Pin 2): The LT1573 provides overcurrent protection with a timed latch-off circuit. The latch-off time out is triggered when the DRIVE pin is pulled below the saturation voltage of the drive transistor. The saturation voltage is a function of the drive current and is equal to approximately 130mV at 20mA rising to 780mV at 250mA (see typical performance curves). The time out is set by the latch charging current and the value of a capacitor connected between the LATCH pin and ground. If the overcurrent condition persists at the end of the timing cycle the regulator will latch off until either the latch is reset or power is cycled off and back on. The latch can be reset by either pulling the SHDN pin high, pulling current out of the LATCH pin greater than latching current or grounding the LATCH pin. Exceeding the thermal limit temperature will trigger the latch with no timing delay. Under normal condition, the DC voltage at the LATCH pin is zero. When the system is latched off, the DC voltage at theLATCH pin is two VBE above ground. SHDN (Pin 3): The SHDN pin has two functions. It can be used to turn off the output voltage by disabling the drive to the output transistor. It can also be used to reset the current limit latch. The shutdown/reset functions are activated by applying a voltage > 1.3V to the SHDN pin. The output voltage will restart as soon as the SHDN pin is pulled below the shutdown threshold. If the shutdown/ reset function is not used, the pin should be grounded. The voltage applied to the SHDN pin can be higher than the input voltage. When the SHDN pin voltage is higher than 2V, the SHDN pin current increases and is limited by an internal 20k resistor. GND (Pin 4): Circuit Ground. DRIVE (Pin 5): The DRIVE pin is connected to the collector of the main drive transistor of the LT1573. This drive transistor sinks the base current of the external PNP output transistor. A resistor is normally inserted between the base of the external PNP output transistor and the DRIVE pin. This resistor is sized to allow the LT1573 to sink the appropriate amount of base current for a given application and to activate the overcurrent latch in a fault condition. VIN (Pin 6): This pin provides power to all internal circuitry of the LT1573 including bias, start-up, thermal limit, error amplifier and all overcurrent latch circuitry. VOUT (Pin 7): The VOUT pin is the input to comparator C1 shown in Block Diagram. This pin is normally connected to the output. The comparator C1 is used to disable the overcurrent latch during start-up when the output transistor is saturated. For fixed voltage devices the top of the internal resistor divider that sets the output voltage is connected to this pin. COMP (Pin 8): A compensation network is inserted between the VOUT and COMP pins to obtain optimal transient response. Under normal condition, the DC voltage of the COMP pin sits at one VBE above ground. 5 LT1573 W BLOCK DIAGRA VOUT VIN 6 + + + SHDN 3 NORMALLY OFF NORMALLY OFF C3 7 I2 I3 + C1 S2 S3 – GND 4 VIODTH – VIN COMP FB 6 8 1 VSHDNTH + + + ILATCH DRIVE 5 IDISCHRG ICHRG R1 – C2 NORMALLY ON + C4 VLATCHTH – Q1 Q4 + EXTERNAL CAPACITOR Q3 ERROR AMP Q2 + S1 R2 + 2 LATCH S4 – NORMALLY OFF Q5 VDRSAT 1.265V CEXT FOR FIXED VOLTAGE VERSION THERMAL SHUTDOWN 4 GND 1573 BD U U U FU CTIO AL DESCRIPTIO The basic block diagram of the LT1573 is shown above. The regulating loop consists of a 1.265V reference, an error amplifier, a Darlington driver and an external PNP pass transistor. The 1.265V reference feeds the noninverting input of the error amplifier. The error amplifier drives the Darlington connected transistor pair Q1 and Q2. The collector of Q1 comes out to the DRIVE pin and is used to drive the base of an external PNP power transistor as shown in Figure 1. The error amplifier will adjust the drive current to the external PNP power transistor to maintain the feedback pin voltage at 1.265V. The LT1573 provides overcurrent protection by means of a timed latch function. Base current to the external PNP transistor is limited by placing a resistor between the base of the transistor and the DRIVE pin. When the DRIVE pin drops below VDRSAT (the DRIVE pin saturation voltage) the output of the comparator C2 switches high; S1, which is normally closed, opens and the external capacitor connected to the LATCH pin is allowed to charge. Discharge current IDISCHRG is equal to approximately 28µA and charging current ICHRG is equal to approximately 7µA. If the fault condition goes 6 away before CEXT charges to the latch threshold, C2 will switch back low, S1 will close and Q4 will discharge CEXT. If the fault condition persists long enough for CEXT to charge up to the latch threshold (VLATCHTH), comparator C4 will switch high and S4 will close and latch the output off. The device will stay latched because latching current ILATCH is greater than the pull-down current of Q4. Thermal shutdown circuitry will close S4 and latch the device off with no timing delay. Comparator C1 is used to override the latching function during start-up. If the difference between the output voltage and the input voltage is less than the input-output differential threshold (VIODTH), comparator C1 output goes high which closes S2. Current source I2 then drives base of Q4 which prevents CEXT from charging. Comparator C3 is used for system shutdown and latch reset. If SHDN pin voltage is higher than shutdown threshold VSDTH, the comparator C3 output goes high, shutting down the regulator and closing switch S3. Current I3 will drive Q4 to discharge CEXT, resetting the latch. LT1573 U W U U APPLICATIO S I FOR ATIO The LT1573 is designed to be used in conjunction with an external PNP transistor. The overall specifications of a regulator circuit using the LT1573 and an external PNP will be heavily dependent on the specifications of the external PNP. While there are a wide variety of PNP transistors available that can be used with the LT1573, the specifications given in a typical transistor data sheet are of little use in determining overall circuit performance. In the following discussion the critical requirements of the PNP transistors are noted. Design equations are given and examples are shown using a readily available discrete PNP transistor. This device is inexpensive, available from multiple sources and can be used for a wide range of applications. For applications using other PNP transistors, the regulator specifications can be derived by the same method. on the regulator circuit under overload conditions. The resistor RD is chosen based on the operating requirements of the circuit, primarily the dropout voltage and the output current. The dropout voltage of an LT1573-based regulator circuit is determined by the VCE saturation voltage of the discrete external PNP transistor when it is driven with a base current equal to the available drive current of the LT1573. External PNP Transistor Selection Criteria The selection of an appropriate external PNP transistor depends on the regulator application specifications. The critical PNP transistor selection criteria include: 1. The maximum output current of the PNP transistor 2. The dropout voltage at the maximum output current 3. The gain-bandwidth product fT of the transistor Basic Regulator Circuit The PNP transistor must be able to supply the specified maximum regulator output current to be qualified for the regulator application. The VCE saturation voltage of the transistor at the maximum output current determines the dropout voltage of the circuit. The dropout voltage determines the minimum regulator input voltage for a certain specified output voltage. The gain-bandwidth product fT of the transistor determines how fast the voltage regulator can follow an output load change without losing voltage regulation. The basic regulator circuit is shown in Figure 2. The adjustable output LT1573 senses the regulator output voltage from its feedback pin via the output voltage divider, R1 and R2, and drives the base of the external PNP transistor to maintain the regulator output at the desired value. For fixed output versions of the LT1573, the regulator output voltage is sensed from the feedback pin via an internal voltage divider. The resistor RD is required for the overcurrent latch-off function. RD is also used to limit the drive current available to the external PNP transistor and to limit the power dissipation in the LT1573. Limiting the drive current to the external PNP transistor will limit the output current of the regulator which minimizes the stress The D45H11 from Motorola and the KSE45H11TU from Samsung can be used in all LT1573 regulator circuits with current ratings up to 5A. The D45H11 can supply 5A of CC FB LATCH VOUT LT1573 + CTIME RC COMP SHDN VIN RB RD GND DRIVE QOUT VIN VOUT R1 + CIN COUT1 + LOAD COUT2 R2 GND 1573 F02 Figure 2. Basic Regulator Circuit 7 LT1573 U W U U APPLICATIO S I FOR ATIO output current with dropout voltage as low as 0.35V. The gain-bandwidth product fT of the D45H11 is typically 40MHz which enables the regulator, composed of this PNP transistor and the LT1573, to handle the load changes of several amps in a few hundred nanoseconds with a minimum amount of output capacitance. The following sections describe how specifications can be determined for the basic regulator based on the LT1573 and D45H11 from Motorola. To determine the specifications for regulators formed by the LT1573 and other PNP transistors, a similar method can be used. Dropout Voltage The dropout voltage of an LT1573-based regulator circuit is determined by the VCE saturation voltage of the discrete external PNP transistor when it is driven with a base current equal to the available drive current of the LT1573. The LT1573 is guaranteed to sink 250mA of base current (440mA typ). The available drive current of the LT1573 can be reduced by adding a resistor (RD in Figure 2) in series with the DRIVE pin. Table 1 lists some useful operating points for the D45H11. These points were empirically determined using a sampling of devices. Table 1. D45H11 Dropout Voltage DRIVE CURRENT (mA) OUTPUT CURRENT (A) TYPICAL DROPOUT VOLTAGE (V) 20 1 0.20 20 2 0.50 40 2 0.25 40 3 0.50 60 3 0.25 60 4 0.70 80 4 0.45 100 4 0.35 100 5 0.70 150 5 0.40 200 5 0.35 150 6 0.65 200 6 0.45 250 7 0.50 8 Current Limit For regulator circuits using the LT1573, current limiting is achieved by limiting the base drive current to the external PNP pass transistor. This means that the actual system current limit will be a function of both the current limit of the LT1573 and the Beta of the external PNP. Motorola provides the following Beta information for the D45H11. The minimum Beta of the D45H11 is 60 when VCE = 1V and IC = 2A. The minimum Beta is 40 when VCE = 1V and IC = 4A. For other PNP transistors, the user should first find out the Beta information from the external PNP transistor manufacturer to determine the appropriate LT1573 base drive current limit. The current limit of the regulator system then can be achieved by selecting the appropriate amount of resistance RD in Figure 2. Selecting RD Resistor RD can be used to limit the available drive current to the external PNP transistor. In order to select RD, the user should first choose the value of the drive current that will give the required value of output current and dropout voltage. For a circuit using the D45H11 as a pass transistor this can be done using Table 1. For circuits using transistors other than D45H11, the user must characterize the transistor to determine the drive current requirements for the specified output current and dropout voltage. In general, it is recommended that the user choose the lowest value of drive current that will satisfy the output current requirements. This will minimize the stress on circuit components during overload conditions. The formula used to determine the resistor RD is: RD = (VIN – VBE – VDRIVE)/(IDRIVE + IRB) (1) where, VIN = the minimum input voltage to the circuit VBE = the maximum emitter/base voltage of the PNP pass transistor IDRIVE = the minimum PNP base current required IRB = the current through RB = VBE/RB VDRIVE = the DRIVE pin saturation voltage when the DRIVE pin current equals (IDRIVE + IRB) LT1573 U W U U APPLICATIO S I FOR ATIO Resistor RB helps to turn off the PNP (QOUT in Figure 2). Smaller values for RB turn off the PNP faster but will increase input current. The recommended value for RB is 50Ω. For circuits that do not require high output current or fast transient response, the value of RB can be increased up to 200Ω. For the D45H11, the emitter-base voltage is a function of base and collector current. Table 2 lists some useful operating points for the D45H11. These points were empirically determined using a sampling of devices. Table 2. D45H11 VBE IB (mA) IC (A) VBE AT 25°C (V) 1 0.2 0.65 7 1 0.75 23 2 0.80 45 3 0.85 66 4 0.90 100 5 0.95 Design Example Given the following operating requirements: 4.5V < VIN < 5.5V IOUT(MAX) = 5A VOUT = 3.3V 1. The first step is to determine the required drive current for the D45H11. Dropout voltage must be less than 1.2V at 5A output current. From Table 1, a drive current of 100mA will give 0.7V dropout voltage at an output current of 5A. This satisfies the operating requirements. 2. The next step is to determine the value of RD. Assume RB is 50Ω. From Table 2, the maximum emitter-base voltage for this design is 0.95V. The current through RB is: IRB = VBE/RB = 0.95/50 = 19mA VDRIVE is the DRIVE pin saturation voltage when the DRIVE pin current equals 119mA, which can be read from the typical performance characteristics curve to be 0.39V. Resistor RD now can be calculated from Eq (1): RD = (4.5 – 0.95 – 0.39)V/(100 + 19)mA = 26.6Ω The next lowest 5% value is 24Ω. Overcurrent Latch-Off In addition to limiting the base drive current, the resistor RD is included in the circuit for the overcurrent protection latch-off function. There is a minimum value for this resistance. It is calculated by Equation 1 with the drive current IDRIVE set to the minimum available drive current (= 250mA) from the LT1573. At high currents, RD also limits the power dissipation in the LT1573. In some conditions, resistor RD can be replaced with a short. This is possible in circuits where an overload is unlikely and the input voltage and drive requirements are low. If resistor RD is not included in the circuit, the regulator is protected against the overcurrent condition only by the thermal shutdown function. After the resistor RD is determined, a certain amount of base drive current is available to the external PNP transistor. An overcurrent or output short condition will demand a base drive current greater than the LT1573 can supply. The internal drive transistor will saturate. A time-out latch will be triggered by this overcurrent condition to turn off the regulator system. The time-out period is determined by an external capacitor connected between the LATCH and GND pins. The timeout period is equal to the time it takes for the capacitor to charge from 0V to the latch threshold which is equal to 2VBE. The latch charging current is set by an internal current source and is a function of input voltage and temperature as shown in the typical performance characteristics curve. At 25°C, the typical latch charging current ranges from 7.2µA with 3V input to 8µA with 7V input. If the overcurrent or output short condition persists longer than the time-out period, the regulator will be shut down. Otherwise, the regulator will function normally. In the latch-off mode, some extra current is drawn from the input to maintain the latch. The latching current is a function of input voltage and temperature as shown in the typical performance characteristic curve. At 25°C, the typical latching current ranges from 0.3mA with 3V input to 9.5mA with 7V input. The latch can be reset by recycling input power, by grounding the LATCH pin or by putting the device into shutdown. 9 LT1573 U W U U APPLICATIO S I FOR ATIO Thermal Considerations The thermal characteristics of several components need to be considered; the LT1573, the pass transistor and resistor RD. Power dissipation should be calculated based on the worst-case conditions seen by each component during normal operation. 1. Power Dissipation of the LT1573: The worst-case power dissipation in the LT1573 is a function of drive current, supply voltage and the value of RD. Worst-case dissipation for the LT1573 occurs when the drive current is equal to approximately one half of its maximum value. The worst-case power dissipation in the LT1573 can be calculated by the following formula: (VIN − VBE) PD = 2 4RD RD > minimum RD for latch - off function (2) where, VIN = the maximum input voltage to the circuit VBE = the minimum emitter/base voltage of the PNP pass transistor Following the previous design example for selecting resistor RD, the power dissipation of LT1573 is calculated from Eq (2): (5.5 − 0.65) 4(24) = 0.25W For some operating conditions RD may be replaced with a short. This is possible in applications where the operating requirements (input voltage and drive current) are at the low end and the output will not be shorted. For RD = 0, the following formula may be used to calculate the maximum power dissipation in the LT1573: PD = (VIN – VBE)(IDRIVE) (3) where, VIN = the maximum input voltage VBE = the minimum emitter/base voltage of the PNP IDRIVE = the required maximum drive current 10 (VIN − VBE − VDRIVE) PRD = 2 (4) RD where, VIN = the maximum input voltage VBE = the minimum emitter/base voltage of the PNP VDRIVE = the voltage at the LT1573 DRIVE pin = VSAT of the DRIVE pin in the worst case Following the previous design example, the power dissipation of resistor RD is calculated from Eq (4): (5.5 − 0.65 − 0.39) PRD = 2 24 = 0.83W 3. Power Dissipation of the PNP Transistor: The worstcase power dissipation in the PNP pass transistor is simply equal to: PPNP = (VIN – VOUT)(IOUT) 2 PD = 2. Power Dissipation of the Resistor RD: The worst-case power dissipation in resistor RD needs to be calculated so that the power rating of the resistor can be determined. The worst-case power dissipation in this resistor will occur when the drive current is at a maximum. The power dissipation can be calculated from the following formula: (5) where, VIN = the maximum input voltage IOUT = the maximum output current Following the previous design example, the power dissipation of PNP transistor is calculated from Eq (5): PPNP = (5.5 – 3.3)(5) = 11W The LT1573 series regulators have internal thermal limiting designed to protect the device during overload conditions. For continuous normal load conditions, the maximum junction temperature rating of 125°C must not be exceeded. It is important to give careful consideration to all sources of thermal resistance from junction to ambient. For surface mount devices, heat sinking is accomplished by using the heat spreading LT1573 U W U U APPLICATIO S I FOR ATIO capabilities of the PC board and its copper traces. Table 3 lists some typical values for the thermal resistance of the LT1573. Measured values of thermal resistance for a specific board size with different copper areas are listed. All measurements were taken in still air on 3/32" FR-4 board with 2oz copper. It is possible to achieve significantly lower values with thinner multilayer boards. Table 3. LT1573 Thermal Resistance COPPER AREA THERMAL RESISTANCE BOARD AREA (JUNCTION-TO-AMBIENT) TOPSIDE* BACKSIDE 2500mm2 2500mm2 2500mm2 80°C/W 1000mm2 2500mm2 2500mm2 80°C/W 225mm2 2500mm2 2500mm2 85°C/W *Device is mounted on topside. We can find out the maximum junction temperature of the LT1573 during normal load operation after we calculate the maximum power dissipation of the LT1573 from Eq (2). From the previous design example, the maximum power dissipation of the LT1573 is 0.2W. From Table 3, we know the thermal resistance from junction-to-ambient is around 85°C/W. The temperature difference between junction and ambient is: (0.25W)(85°C/W) = 21.25°C If the maximum ambient temperature is specified at 50°C, the maximum junction temperature will be: TJMAX = 50°C + 21.25°C = 71.25°C The maximum junction temperature must not exceed the specified 125°C for safe continuous regulator operation. Thermal Limiting The thermal shutdown temperature of the LT1573 is approximately 150°C. The thermal limit of the LT1573 can be used to protect both the LT1573 and the external PNP pass transistor. This is accomplished by thermally coupling the LT1573 to the PNP power transistor by locating the LT1573 as close to the PNP transistor as possible. In this case, the power dissipation of the power transistor must be considered in the LT1573 maximum junction temperature calculation. Compensation In order to improve the transient response to regulator output load variation, a capacitor in series with a resistor can be inserted between the VOUT and COMP pins. For the microprocessor power supply regulator system based on the LT1573 and the PNP transistor D45H11 with 24 1µF surface mount ceramic capacitors in parallel with one 220µF surface mount tantalum capacitor at the output as shown in Figure 1, a 100pF capacitor in series with a 1k resistor is recommended. In theory, the output capacitor forms the dominant pole of the regulator system. An internal compensation capacitor forms another pole. The external compensation capacitor and resistor form a zero which adds phase margin to the regulator system to prevent high frequency oscillation. The LT1573 has an internal pole at approximately 5kHz. An external compensation zero between 10kHz and 100kHz is usually required to stabilize the regulator. The zero frequency is primarily determined by the compensation capacitor and can be roughly calculated by the following equation: ( 30 pF ) CCOMP( (pF) ) ,10 ≤ CCOMP ≤ 100 fZERO = 40kHz A compensation resistor between 1k and 10k is suggested. A compensation resistor of 5k works for most cases. In some cases, a greater compensation resistor is needed to stop oscillation above 1MHz. In some cases, the output capacitor may have enough equivalent series resistance (ESR) to generate the required zero and the external compensation zero may not be needed. Output Capacitor The LT1573 is designed to be used with an external PNP transistor with a high gain-bandwidth product fT to make a regulator with a very fast transient response, which can minimize the size of the output capacitor. For a regulator made of an LT1573 and a D45H11, only one 10µF surface mount ceramic capacitor at the output is enough for the regulator to handle the output load varying up to 5A in a few hundred nanoseconds interval and to remain stable with a 30pF capacitor in series with a 7.5k resistor between the VOUT and COMP pins. If tighter voltage regulation is 11 LT1573 U W U U APPLICATIO S I FOR ATIO needed during output transients, more capacitance can be added to the regulator output. If more capacitance is added to the output, the bandwidth of the regulator is lowered. A large value compensation capacitor may be needed to lower the frequency of the compensation zero to avoid high frequency oscillation. Equal value output capacitors with different ESR can have different output transient response. High frequency performance will be strongly affected by parasitics in the output capacitor and board layout. Some experimentation with the external compensation will be required for optimum results. Shutdown Function The regulator can be shut down by pulling the SHDN pin voltage higher than the shutdown threshold (about 1.3V). The regulator will restart itself if the SHDN is pulled below the shutdown threshold.The SHDN pin should be tied to ground if it is not used. The SHDN pin voltage can be higher than the input voltage. When the SHDN pin voltage is higher than 2V, the SHDN pin current increases and is limited by a 20k resistor. Momentarily putting the device into shutdown also resets the overcurrent latch. CC FB Lower dropout voltage or higher output current capability can be achieved by paralleling several output PNP transistors as shown in Figure 3. By paralleling output PNP transistors, the equivalent resistance between the emitters (VIN) and collectors (VOUT) is lowered or each PNP transistor sharing the output current now runs at a lower collector current, which causes the dropout voltage to decrease. Because the PNP transistors are running at a lower collector current where the transistor beta is higher, much more output current can be obtained at a given base drive current. When paralleling two or more output transistors, a separate resistor is needed for RB and RD for each output transistor. This allows the base drive current to be split evenly between output transistors, which promotes equal output current sharing. In the specific example drawn in Figure 3 with two output transistors, the resistance of RB1 and RB2 is now twice the value of the resistance of RB in Figure 2, and the resistance of RD1 and RD2 is twice the value of the resistance of RD in Figure 2. In case of n PNP transistors in parallel, the resistance RB RC COMP LATCH VOUT LT1573 + CTIME Lower Dropout Voltage or Higher Output Current Capability SHDN VIN RB1 GND DRIVE RB2 QOUT2 QOUT1 RD1 RD2 VIN VOUT CIN + R1 LOAD COUT1 R2 GND 1573 F03 Figure 3. Reduced Dropout Voltage or Increased Output Current by Paralleling Output PNP Transistors 12 LT1573 U W U U APPLICATIO S I FOR ATIO Table 4. LT1573 Output Feedback Divider Resistance OUTPUT R1 (Ω) (NEAREST 1%) VOLTAGE (V) R2 (Ω) equals the resistance of RB1, RB2, ..., and RBn in parallel, and the resistance RD equals the resistance of RD1, RD2, ..., and RDn in parallel. Voltage Feedback Resistor Divider Table Voltage feedback resistor divider is provided for convenience for the most possibly used output voltages in Table 4. 1.5 1k 187 1.8 1k 422 2.0 1k 576 2.2 1k 732 2.5 1k 976 2.8 1k 1210 3.0 1k 1370 3.3 1k 1620 3.5 1k 1780 3.8 1k 2000 4.0 1k 2150 4.5 1k 2550 5.0 1k 2940 U TYPICAL APPLICATIO S 3.3V/5A Microprocessor Supply FB LATCH CTIME 0.5µF + SHDN GND RC 1k 1/8W CC 100pF LT1573 COMP VOUT VIN RD 24Ω 1/2W DRIVE RB 50Ω 1/8W QOUT MOTOROLA D45H11 VIN 5V CIN 5V + + + COUT1 VOUT 3.3V R1 1.6k 1/8W COUT2 LOAD R2 1k 1/8W GND COUT1 = 24 × 1µF SURFACE MOUNT CERAMIC CAPACITOR (FOR T < 45°C, COUT1 = 24 × 1µF Y5V CERAMIC SURFACE MOUNT CAPACITORS, FOR T > 45°C, COUT1 = 24 × 1µF X7R CERAMIC SURFACE MOUNT CAPACITORS) PLACE COUT1 IN THE MICROPROCESSOR SOCKET CAVITY CIN, COUT2 = 220µF SURFACE MOUNT TANTALUM CAPACITOR CTIME = 0.5µF FOR 100ms TIME OUT AT ROOM TEMPERATURE SHDN (ACTIVE HIGH) PIN SHOULD BE TIED TO GROUND IF IT IS NOT USED 1573 TA01 13 LT1573 U TYPICAL APPLICATIO S 3.3V to 2.5/2A Voltage Regulator FB COMP LATCH CTIME 0.5µF + RC 1k 1/8W CC 30pF LT1573 VOUT VIN SHDN RD 39Ω 1/2W DRIVE GND RB 200Ω 1/8W QOUT MOTOROLA D45H11 VIN 3.3V + + CIN VOUT 2.5V R1 976Ω 1/8W + COUT1 COUT2 LOAD R2 1k 1/8W GND CIN = 22µF SURFACE MOUNT TANTALUM CAPACITOR COUT1 = 10µF SURFACE MOUNT CERAMIC CAPACITOR COUT2 = 15µF SURFACE MOUNT TANTALUM CAPACITOR CTIME = 0.5µF FOR 100ms TIME OUT AT ROOM TEMPERATURE SHDN (ACTIVE HIGH) PIN SHOULD BE TIED TO GROUND IF IT IS NOT USED 1573 TA02 5V/2A Output from 6V to 9V Wall Adapter Input LT1573 FB LATCH CTIME 0.5µF + SHDN GND COMP VOUT VIN RD 130Ω 1/2W DRIVE RB 200Ω 1/8W MOTOROLA D45H11 VIN 6V to 9V + + CIN VOUT 5V R1 2.94k 1/8W COUT LOAD R2 1k 1/8W GND CIN = 150µF (SANYO SURFACE MOUNT ELECTROLYTIC, 10V, PART #10CV150BS) OR 10µF LOW ESR TANTALUM CAPACITOR COUT = 47µF (SANYO SURFACE MOUNT ELECTROLYTIC, 25V, PART #25CV47BS) OR 150µF (SANYO SURFACE MOUNT ELECTROLYTIC, 10V, PART #10CV150BS) CTIME = 0.5µF FOR 100ms TIME OUT AT ROOM TEMPERATURE SHDN (ACTIVE HIGH) PIN SHOULD BE TIED TO GROUND IF IT IS NOT USED 14 1573 TA03 LT1573 U TYPICAL APPLICATIO S 3.3V to 2.85V/1A Voltage Regulator LT1573 FB COMP LATCH CTIME 0.5µF + VOUT VIN SHDN RD 91Ω 1/2W DRIVE GND RB 200Ω 1/8W MOTOROLA D45H11 VIN 3.3V + + COUT CIN VOUT 2.85V R1 1.24k 1/8W LOAD R2 1k 1/8W GND 1573 TA04 CIN, COUT = AVX 100µF/10V SURFACE MOUNT TANTALUM CAPACITOR CTIME = 0.5µF FOR 100ms TIME OUT AT ROOM TEMPERATURE SHDN (ACTIVE HIGH) PIN SHOULD BE TIED TO GROUND IF IT IS NOT USED High Efficiency 2.5V to 1.5V Converter at 6A Output Current LT1573 FB LATCH CTIME 0.5µF + SHDN GND VIN1 2.5V + CIN1 COMP VOUT VIN RD 6Ω 1/2W DRIVE RB 200Ω 1/8W MOTOROLA D45H11 VIN2 3V TO 7V + + CIN2 VOUT 1.5V R1 186Ω 1/8W COUT LOAD R2 1k 1/8W GND CIN1, COUT = AVX 100µF/10V SURFACE MOUNT TANTALUM CAPACITOR CIN2 = AVX 15µF/10V SURFACE MOUNT TANTALUM CAPACITOR CTIME = 0.5µF FOR 100ms TIME OUT AT ROOM TEMPERATURE SHDN (ACTIVE HIGH) PIN SHOULD BE TIED TO GROUND IF IT IS NOT USED Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 1573 TA05 15 LT1573 U TYPICAL APPLICATIO S High Efficiency 2.5V to 1.8V Converter at 5A Output Current LT1573 FB CTIME 0.5µF CIN1 COMP LATCH + VIN1 2.5V + VOUT VIN SHDN RD 6.2Ω 1/2W DRIVE GND RB 200Ω 1/8W MOTOROLA D45H11 VIN2 3V TO 7V + VOUT 1.8V R1 420Ω 1/8W + CIN2 COUT LOAD R2 1k 1/8W GND 1573 TA06 CIN1, COUT = AVX 100µF/10V SURFACE MOUNT TANTALUM CAPACITOR CIN2 = AVX 15µF/10V SURFACE MOUNT TANTALUM CAPACITOR CTIME = 0.5µF FOR 100ms TIME OUT AT ROOM TEMPERATURE SHDN (ACTIVE HIGH) PIN SHOULD BE TIED TO GROUND IF IT IS NOT USED U PACKAGE DESCRIPTIO Dimensions in inches (millimeters) unless otherwise noted. S8 Package 8-Lead Plastic Small Outline (Narrow 0.150) (LTC DWG # 05-08-1610) 0.189 – 0.197* (4.801 – 5.004) 0.010 – 0.020 × 45° (0.254 – 0.508) 0.008 – 0.010 (0.203 – 0.254) 0.053 – 0.069 (1.346 – 1.752) 0°– 8° TYP 0.016 – 0.050 (0.406 – 1.270) 0.014 – 0.019 (0.355 – 0.483) TYP *DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE **DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE 8 7 6 5 0.004 – 0.010 (0.101 – 0.254) 0.050 (1.270) BSC 0.150 – 0.157** (3.810 – 3.988) 0.228 – 0.244 (5.791 – 6.197) SO8 1298 1 2 3 4 RELATED PARTS PART NUMBER LT1529 LT1575/LT1577 LT1580/LT1581 LT1584/LT1585/LT1587 LT1761/LT1762/LT1763 LT1764 16 DESCRIPTION 3A Micropower Low Dropout Regulator Low Dropout N-Channel MOSFET Regulator Driver 7A, 10A Very Low Dropout Linear Regulators 7A/4.6A/3A Low Dropout, Fast Response Regulators Low Noise LDO Micropower Regulators 3A Fast Transient Response Low Dropout Regulator Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417● (408) 432-1900 FAX: (408) 434-0507● TELEX: 499-3977 ● www.linear-tech.com COMMENTS 50µA Quiescent Current, 0.5V Dropout, Shutdown Ultrafast Transient, Adjustable/Fixed Output, Current Limiting For High Current 3.3V to 2.xV Applications For High Performance Microprocessors 20µA to 30µA Quiescent Current, 20µVRMS Noise 340mV Dropout Voltage 1573fa LT/TP 1299 2K REV A • PRINTED IN USA LINEAR TECHNOLOGY CORPORATION 1997