ADC1003S030/040/050 Single 10 bits ADC, up to 30 MHz, 40 MHz or 50 MHz, with voltage regulator Rev. 02 — 7 August 2008 Product data sheet 1. General description The ADC1003S030/040/050 are a family of 10-bit high-speed low-power Analog-to-Digital Converters (ADC) for professional video and other applications. They convert the analog input signal into 10-bit binary-coded digital words at a maximum sampling rate of 50 MHz. All digital inputs and outputs are Transistor-Transistor Logic (TTL) and CMOS compatible, although a low-level sine wave clock input signal is allowed. The device includes an internal voltage reference regulator. If the application requires that the reference is driven via external sources the recommendation is to use one of the ADC1004S030/040/050 family. 2. Features n n n n n n n n n n n n n n 10-bit resolution Sampling rate up to 50 MHz DC sampling allowed One clock cycle conversion only High signal-to-noise ratio over a large analog input frequency range (9.3 effective bits at 4.43 MHz full-scale input at fclk = 40 MHz) No missing codes guaranteed In-Range (IR) CMOS output Levels TTL and CMOS compatible digital inputs 3 V to 5 V CMOS digital outputs Low-level AC clock input signal allowed Internal reference voltage regulator Power dissipation only 235 mW (typical) Low analog input capacitance, no buffer amplifier required No sample-and-hold circuit required 3. Applications High-speed analog-to-digital conversion for: n Video data digitizing n Radar n Transient signal analysis n Global Positioning System (GPS) receiver n Σ∆ modulators ADC1003S030/040/050 NXP Semiconductors Single 10 bits ADC, up to 30 MHz, 40 Mhz or 50 MHz, with voltage regulator n Cellular based stations n Barcode scanner n Medical imaging 4. Quick reference data Table 1. Quick reference data VCCA = V3 to V4 = 4.75 V to 5.25 V; VCCD = V11 to V12 and V28 to V27 = 4.75 V to 5.25 V; VCCO = V13 to V14 = 3.0 V to 5.25 V; AGND and DGND shorted together; Tamb = 0 °C to 70 °C; typical values measured at VCCA = VCCD = 5 V and VCCO = 3.3 V; CL = 15 pF and Tamb = 25 °C; unless otherwise specified. Symbol Parameter Min Typ Max Unit VCCA analog supply voltage 4.75 5.0 5.25 V VCCD digital supply voltage 4.75 5.0 5.25 V VCCO output supply voltage 3.0 3.3 5.25 V ICCA analog supply current - 30 35 mA ICCD digital supply current - 16 21 mA ICCO output supply current fclk = 40 MHz; ramp input - 1 2 mA INL integral non-linearity fclk = 40 MHz; ramp input - ±0.8 ±2.0 LSB DNL differential non-linearity fclk = 40 MHz; ramp input - ±0.5 ±0.9 LSB fclk(max) maximum clock frequency ADC1003S030TS 30 - - MHz ADC1003S040TS 40 - - MHz ADC1003S050TS 50 - - MHz fclk = 40 MHz; ramp input - 235 305 mW Ptot Conditions total power dissipation 5. Ordering information Table 2. Ordering information Type number Package Sampling frequency (MHz) Name Description Version ADC1003S030TS SSOP28 plastic shrink small outline package; 28 leads; body width 5.3 mm SOT341-1 30 ADC1003S040TS SSOP28 plastic shrink small outline package; 28 leads; body width 5.3 mm SOT341-1 40 ADC1003S050TS SSOP28 plastic shrink small outline package; 28 leads; body width 5.3 mm SOT341-1 50 ADC1003S030_040_050_2 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 02 — 7 August 2008 2 of 20 ADC1003S030/040/050 NXP Semiconductors Single 10 bits ADC, up to 30 MHz, 40 Mhz or 50 MHz, with voltage regulator 6. Block diagram VCCA DEC CLK VCCD2 OE 3 5 1 11 10 REFERENCE VOLTAGE REGULATOR RT 2 CLOCK DRIVER TC 9 25 D9 MSB 24 D8 23 D7 22 D6 Rlad 21 D5 analog voltage input VI 8 RM 7 ANALOG - TO - DIGITAL CONVERTER CMOS OUTPUTS LATCHES 20 D4 data outputs 19 D3 18 D2 17 D1 16 D0 13 6 RB ADC1003S030/040/050 CMOS OUTPUT IN-RANGE LATCH 26 28 4 12 14 27 AGND DGND2 OGND DGND1 analog ground Fig 1. digital ground output ground digital ground LSB VCCO IR output VCCD1 014aaa321 Block diagram ADC1003S030_040_050_2 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 02 — 7 August 2008 3 of 20 ADC1003S030/040/050 NXP Semiconductors Single 10 bits ADC, up to 30 MHz, 40 Mhz or 50 MHz, with voltage regulator 7. Pinning information 7.1 Pinning CLK 1 28 VCCD1 TC 2 27 DGND1 VCCA 3 26 IR AGND 4 25 D9 DEC 5 24 D8 RB 6 23 D7 RM 7 VI 8 RT 9 20 D4 OE 10 19 D3 VCCD2 11 18 D2 DGND2 12 17 D1 VCCO 13 16 D0 OGND 14 15 n.c. ADC1003S 050TS 22 D6 21 D5 014aaa320 Fig 2. Pin configuration 7.2 Pin description Table 3. Pin description Symbol Pin Description CLK 1 clock input TC 2 two’s complement input (active LOW) VCCA 3 analog supply voltage (5 V) AGND 4 analog ground DEC 5 decoupling input RB 6 reference voltage BOTTOM input RM 7 reference voltage MIDDLE VI 8 analog input voltage RT 9 reference voltage TOP input OE 10 output enable input (CMOS level input, active LOW) VCCD2 11 digital supply voltage 2 (5 V) DGND2 12 digital ground 2 VCCO 13 supply voltage for output stages (3 V to 5 V) OGND 14 output ground n.c. 15 not connected D0 16 data output; bit 0 (Least Significant Bit (LSB)) D1 17 data output; bit 1 D2 18 data output; bit 2 D3 19 data output; bit 3 ADC1003S030_040_050_2 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 02 — 7 August 2008 4 of 20 ADC1003S030/040/050 NXP Semiconductors Single 10 bits ADC, up to 30 MHz, 40 Mhz or 50 MHz, with voltage regulator Table 3. Pin description …continued Symbol Pin Description D4 20 data output; bit 4 D5 21 data output; bit 5 D6 22 data output; bit 6 D7 23 data output; bit 7 D8 24 data output; bit 8 D9 25 data output; bit 9 (Most Significant Bit (MSB)) IR 26 in-range data output DGND1 27 digital ground 1 VCCD1 28 digital supply voltage 1 (5 V) 8. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Min Max Unit VCCA analog supply voltage [1] −0.3 +7.0 V VCCD digital supply voltage [1] −0.3 +7.0 V VCCO output supply voltage staged [1] −0.3 +7.0 V ∆VCC supply voltage difference VCCA − VCCD −1.0 +1.0 V VCCA − VCCO −1.0 +4.0 V VCCD −VCCO −1.0 +4.0 V VI input voltage referenced to AGND −0.3 +7.0 V Vi(clk)(p-p) peak-to-peak clock input voltage referenced to DGND - VCCD V IO output current - 10 mA Tstg storage temperature −55 +150 °C Tamb ambient temperature −40 +85 °C Tj junction temperature - 150 °C [1] The supply voltages VCCA, VCCD and VCCO may have any value between −0.3 V and +7.0 V provided that the supply voltage differences ∆VCC are respected. 9. Thermal characteristics Table 5. Thermal characteristics Symbol Parameter Conditions Typ Unit Rth(j-a) thermal resistance from junction to ambient in free air 110 K/W ADC1003S030_040_050_2 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 02 — 7 August 2008 5 of 20 ADC1003S030/040/050 NXP Semiconductors Single 10 bits ADC, up to 30 MHz, 40 Mhz or 50 MHz, with voltage regulator 10. Characteristics Table 6. Characteristics VCCA = V3 to V4 = 4.75 V to 5.25 V; VCCD = V11 to V12 and V28 to V27 = 4.75 V to 5.25 V; VCCO = V13 to V14 = 3.0 V to 5.25 V; AGND and DGND shorted together; Tamb = 0 °C to 70 °C; typical values measured at VCCA = VCCD = 5 V and VCCO = 3.3 V; CL = 15 pF and Tamb = 25 °C; unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit Supplies VCCA analog supply voltage 4.75 5.0 5.25 V VCCD digital supply voltage 4.75 5.0 5.25 V VCCO output supply voltage ∆VCC supply voltage difference 3.0 3.3 5.25 V VCCA − VCCD −0.2 - +0.20 V VCCA − VCCO −0.2 - +2.25 V VCCA − VCCO −0.2 - +2.25 V ICCA analog supply current - 30 35 mA ICCD digital supply current - 16 21 mA ICCO output supply current fclk = 40 MHz; ramp input - 1 2 mA Ptot total power dissipation fclk = 40 MHz; ramp input - 235 305 mW Inputs Clock input CLK (referenced to DGND)[1] VIL LOW-level input voltage 0 - 0.8 V VIH HIGH-level input voltage 2 - VCCD V IIL LOW-level input current Vclk = 0.8 V −1 0 +1 µA IIH HIGH-level input current Vclk = 2 V - 2 10 µA Zi input impedance fclk = 40 MHz Ci input capacitance - 2 - kΩ - 2 - pF 0 - 0.8 V Inputs OE and TC (referenced to DGND) VIL LOW-level input voltage VIH HIGH-level input voltage 2 - VCCD V IIL LOW-level input current VIL = 0.8 V −1 - - µA IIH HIGH-level input current VIH = 2 V - - 1 µA VI (Analog input voltage referenced to AGND) IIL LOW-level input current VI = VRB = 1.3 V - 0 - µA IIH HIGH-level input current VI = VRT = 3.67 V - 35 - µA Zi input impedance fi = 4.43 MHz - 8 - kΩ Ci input capacitance - 5 - pF Reference voltages for the resistor ladder using the internal voltage regulator see Table 7 VRB voltage on pin RB 1.1 1.3 1.5 V VRT voltage on pin RT 3.4 3.6 3.8 V Vref(dif) differential reference voltage 2.25 2.3 2.35 V Iref reference current - 9.39 - mA VRT − VRB ADC1003S030_040_050_2 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 02 — 7 August 2008 6 of 20 ADC1003S030/040/050 NXP Semiconductors Single 10 bits ADC, up to 30 MHz, 40 Mhz or 50 MHz, with voltage regulator Table 6. Characteristics …continued VCCA = V3 to V4 = 4.75 V to 5.25 V; VCCD = V11 to V12 and V28 to V27 = 4.75 V to 5.25 V; VCCO = V13 to V14 = 3.0 V to 5.25 V; AGND and DGND shorted together; Tamb = 0 °C to 70 °C; typical values measured at VCCA = VCCD = 5 V and VCCO = 3.3 V; CL = 15 pF and Tamb = 25 °C; unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit Rlad ladder resistance - 245 - Ω TCRlad ladder resistor temperature coefficient - 456 - mΩ/K Voffset offset voltage Vi(a)(p-p) BOTTOM [2] - 175 - mV TOP [2] - 175 - mV [3] 1.90 1.95 2.00 V - peak-to-peak analog input voltage Digital outputs D9 to D0 and IR (Referenced to OGND) VOL LOW-level output voltage IOL = 1 mA 0 0.5 V VOH HIGH-level output voltage IOH = −1 mA VCCO − 0.5 - VCCO V IOZ OFF-state output current 0.5 V < VO < VCCO −20 +20 µA Switching characteristics; clock input CLK see Figure fclk(max) - 4;[1] maximum clock frequency ADC1003S030TS 30 - - MHz ADC1003S040TS 40 - - MHz ADC1003S050TS 50 - - MHz tw(clk)H HIGH clock pulse width full effective bandwidth 8.5 - - ns tw(clk)L LOW clock pulse width full effective bandwidth 5.5 - - ns Analog signal processing Linearity INL integral non-linearity fclk = 40 MHz; ramp input - ±0.8 ±2.0 LSB DNL differential non-linearity fclk = 40 MHz; ramp input - ±0.5 ±0.9 LSB Eoffset offset error middle code EG gain error - ±1 - LSB from device to device, using internal reference voltage [4] - ±3 - % full-scale sine wave [5] - 15 - MHz 75 % full-scale sine wave [5] - 20 - MHz small signal at mid-scale; VI = ±10 LSB at code 512 [5] - 350 - MHz Bandwidth (fclk = 40 MHz) B bandwidth ts(LH) LOW to HIGH settling time full-scale square wave; see Figure 6 [6] - 1.5 3.0 ns ts(HL) HIGH to LOW settling time full-scale square wave; see Figure 6 [6] - 1.5 3.0 ns ADC1003S030_040_050_2 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 02 — 7 August 2008 7 of 20 ADC1003S030/040/050 NXP Semiconductors Single 10 bits ADC, up to 30 MHz, 40 Mhz or 50 MHz, with voltage regulator Table 6. Characteristics …continued VCCA = V3 to V4 = 4.75 V to 5.25 V; VCCD = V11 to V12 and V28 to V27 = 4.75 V to 5.25 V; VCCO = V13 to V14 = 3.0 V to 5.25 V; AGND and DGND shorted together; Tamb = 0 °C to 70 °C; typical values measured at VCCA = VCCD = 5 V and VCCO = 3.3 V; CL = 15 pF and Tamb = 25 °C; unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit Harmonics (fclk = 40 MHz); see Figure 7 and Figure 8 α1H first harmonic level fi = 4.43 MHz - - 0 dB α2H second harmonic level fi = 4.43 MHz - −70 −63 dB α3H third harmonic level fi = 4.43 MHz - −72 −63 dB THD total harmonic distortion fi = 4.43 MHz - −61 - dB 55 58 - dB Signal-to-noise ratio; see Figure 7 and Figure 8[7] S/N signal-to-noise ratio full-scale: without harmonics; fclk = 40 MHz; fi = 4.43 MHz Effective bits; see Figure 7 and Figure 8[7] ENOB effective number of bits ADC1003S030TS; fclk = 30 MHz fi = 4.43 MHz - 9.4 bit fi = 7.5 MHz - 9.1 bit ADC1003S040TS; fclk = 40 MHz; fi = 4.43 MHz - 9.3 - bit fi = 7.5 MHz - 9.0 - bit fi = 10 MHz - 8.9 - bit fi = 15 MHz - 8.1 - bit ADC1003S050TS; fclk = 50 MHz fi = 4.43 MHz - 9.3 - bit fi = 7.5 MHz - 8.9 - bit fi = 10 MHz - 8.8 - bit fi = 15 MHz - 8.0 - bit intermodulation suppression fclk = 40 MHz - −69 - dB bit error rate fclk = 50 MHz; fi = 4.43 MHz; VI = ±16 LSB at code 512 - 10−13 - times/sample fclk = 40 MHz; PAL modulated ramp - 0.8 - % Two-tone[8] αIM Bit error rate BER Differential gain[9] Gdif differential gain ADC1003S030_040_050_2 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 02 — 7 August 2008 8 of 20 ADC1003S030/040/050 NXP Semiconductors Single 10 bits ADC, up to 30 MHz, 40 Mhz or 50 MHz, with voltage regulator Table 6. Characteristics …continued VCCA = V3 to V4 = 4.75 V to 5.25 V; VCCD = V11 to V12 and V28 to V27 = 4.75 V to 5.25 V; VCCO = V13 to V14 = 3.0 V to 5.25 V; AGND and DGND shorted together; Tamb = 0 °C to 70 °C; typical values measured at VCCA = VCCD = 5 V and VCCO = 3.3 V; CL = 15 pF and Tamb = 25 °C; unless otherwise specified. Symbol Differential ϕdif Parameter Conditions Min Typ Max Unit fclk = 40 MHz; PAL modulated ramp - 0.4 - deg phase[9] differential phase Timing (fclk = 40 MHz; CL = 15 pF); see Figure 4[10] td(s) sampling delay time - 3 - ns th(o) output hold time 4 - - ns td(o) output delay time VCCO = 4.75 V - 10 13 ns VCCO = 3.15 V - 12 15 ns - - 15 pF CL load capacitance 3-state output delay times; see Figure 5 tdZH float to active HIGH delay time - 5.5 8.5 ns tdZL float to active LOW delay time - 12 15 ns tdHZ active HIGH to float delay time - 19 24 ns tdLZ active LOW to float delay time - 12 15 ns [1] In addition to a good layout of the digital and analog ground, it is recommended that the rise and fall times of the clock must not be less than 0.5 ns [2] Analog input voltages producing code 0 up to and including code 1023: a) Voffset BOTTOM is the difference between the analog input which produces data equal to 00 and the reference voltage on pin RB (VRB) at Tamb = 25 °C. b) Voffset TOP is the difference between reference voltage on pin RT (VRT) and the analog input which produces data outputs equal to code 1023 at Tamb = 25 °C. [3] In order to ensure the optimum linearity performance of such converter architecture the lower and upper extremities of the converter reference resistor ladder (corresponding to output codes 0 and 1023 respectively) are connected to pins RB and RT via offset resistors ROB and ROT as shown in Figure 3. V RT – V RB a) The current flowing into the resistor ladder is I L = ---------------------------------------- and the full-scale input range at the converter R +R +R OB L OT RL to cover code 0 to code 1023, is V I = R L × I L = ---------------------------------------- × ( V RT – V RB ) = 0.848 × ( V RT – V RB ) R OB + R L + R OT RL R OB + R L + R OT b) Since RL, ROB and ROT have similar behavior with respect to process and temperature variation, the ratio ---------------------------------------- will be kept reasonably constant from device to device. Consequently, variation of the output codes at a given input voltage depends mainly on the difference VRT − VRB and its variation with temperature and supply voltage. When several ADCs are connected in parallel and fed with the same reference source, the matching between each of them is optimized. [4] ( V 1023 – V 0 ) – V i ( P – P ) E G = --------------------------------------------------------- × 100 V i(P – P) [5] The analog bandwidth is defined as the maximum input sine wave frequency which can be applied to the device. No glitches greater than 2 LSB, neither any significant attenuation are observed in the reconstructed signal. [6] The analog input settling time is the minimum time required for the input signal to be stabilized after a sharp full-scale input (square wave signal) in order to sample the signal and obtain correct output data. ADC1003S030_040_050_2 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 02 — 7 August 2008 9 of 20 ADC1003S030/040/050 NXP Semiconductors Single 10 bits ADC, up to 30 MHz, 40 Mhz or 50 MHz, with voltage regulator [7] Effective bits are obtained via a Fast Fourier Transform (FFT) treatment taking 8000 acquisition points per equivalent fundamental period. The calculation takes into account all harmonics and noise up to half of the clock frequency (Nyquist frequency). Conversion to signal-to-noise ratio: SINAD = ENOB × 6.02 + 1.76 dB. [8] Intermodulation measured relative to either tone with analog input frequencies of 4.43 MHz and 4.53 MHz. The two input signals have the same amplitude and the total amplitude of both signals provides full-scale to the converter. [9] Measurement carried out using video analyzer VM700A, where the video analog signal is reconstructed through a digital-to-analog converter. [10] Output data acquisition: the output data is available after the maximum delay time of td(o). For the 50 MHz version it is recommended to have the lowest possible output load. RT ROT code 1023 RL RL RM IL RL Rlad RL code 0 ROB RB 014aaa325 Fig 3. Explanation of Table 6 Table note 3 11. Additional information relating to Table 6 Table 7. Output coding and input voltage (typical values; referenced to AGND) Code Vi(a)(p-p) (V) IR Binary outputs D9 to D0 Two’s complement outputs D9 to D0 Underflow < 1.455 0 00 0000 0000 10 0000 0000 0 1.455 1 00 0000 0000 10 0000 0000 1 - 1 00 0000 0001 10 0000 0001 ↓ - ↓ ↓ ↓ 511 2.43 ↓ 01 1111 1111 11 1111 1111 ↓ - ↓ ↓ ↓ 1022 - 11 11 1111 1110 01 1111 1110 1023 3.405 1 11 1111 1111 01 1111 1111 Overflow > 3.405 0 11 1111 1111 01 1111 1111 ADC1003S030_040_050_2 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 02 — 7 August 2008 10 of 20 ADC1003S030/040/050 NXP Semiconductors Single 10 bits ADC, up to 30 MHz, 40 Mhz or 50 MHz, with voltage regulator Table 8. Mode selection TC OE D9 to D0 IR X 1 high impedance high impedance 0 0 active; two’s complement active 1 0 active; binary active sample N + 1 sample N sample N + 2 tw(clk)L tw(clk)H VCCO CLK 50% 0V sample N sample N + 1 sample N + 2 VI td(s) th(o) VCCO DATA D0 to D9 DATA N−2 DATA N−1 DATA N DATA N+1 50% 0V td(o) Fig 4. Timing diagram ADC1003S030_040_050_2 Product data sheet 014aaa326 © NXP B.V. 2008. All rights reserved. Rev. 02 — 7 August 2008 11 of 20 ADC1003S030/040/050 NXP Semiconductors Single 10 bits ADC, up to 30 MHz, 40 Mhz or 50 MHz, with voltage regulator VCCD 50 % OE tdHZ tdZH HIGH 90 % output data 50 % tdLZ LOW tdZL HIGH output data 50 % LOW 10 % VCCD 3.3 kΩ ADC1003S050 S1 15 pF OE TEST S1 tdLZ VCCD tdZL VCCD tdHZ DGND tdZH DGND 014aaa334 frequency on pin OE = 100 kHz Fig 5. Timing diagram and test conditions of 3-state output delay time. ts(LH) ts(HL) code 1023 VI 50% 50% code 0 2 ns CLK 2 ns 50% 50% 0.5 ns 0.5 ns 014aaa327 Fig 6. Analog input settling-time diagram ADC1003S030_040_050_2 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 02 — 7 August 2008 12 of 20 ADC1003S030/040/050 NXP Semiconductors Single 10 bits ADC, up to 30 MHz, 40 Mhz or 50 MHz, with voltage regulator 014aaa328 +20 amplitude (dB) −20 −60 −100 −140 0 5.00 10.0 15.0 20.0 f (MHz) (1) Effective bits: 9.42; THD = −71.8 dB (2) Harmonic levels (dB): 2nd = −83.19; 3rd = −78.09; 4th = −78.72; 5th = −78.33; 6th = −77.55 Fig 7. Typical fast Fourier transform (fclk = 40 MHz; fi = 4.43 MHz) 014aaa329 +20 amplitude (dB) −20 −60 −100 −140 0 5.0 10.0 15.0 20.0 25.0 f (MHz) (1) Effective bits: 8.91; THD = −62.96 dB (2) Harmonic levels (dB): 2nd = −71.38; 3rd = −71.54; 4th = −74.14; 5th = −65.15; 6th = −77.16 Fig 8. Typical fast Fourier transform (fclk = 50 MHz; fi = 10 MHz) ADC1003S030_040_050_2 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 02 — 7 August 2008 13 of 20 ADC1003S030/040/050 NXP Semiconductors Single 10 bits ADC, up to 30 MHz, 40 Mhz or 50 MHz, with voltage regulator VCCA VCCO D9 to D0 IR VI OGND AGND 014aaa332 014aaa330 Fig 9. CMOS data and in-range outputs Fig 10. Analog inputs DEC VCCA RT Rlad VCCO Rlad RM REGULATOR Rlad Rlad OE TC RB OGND AGND 014aaa333 014aaa323 Fig 11. OE and TC input Fig 12. RB, RM and RT ADC1003S030_040_050_2 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 02 — 7 August 2008 14 of 20 ADC1003S030/040/050 NXP Semiconductors Single 10 bits ADC, up to 30 MHz, 40 Mhz or 50 MHz, with voltage regulator VCCD 1.5 V CLK DGND 014aaa324 Fig 13. CLK input 12. Application information 12.1 Application diagram CLK TC VCCA (3) 100 nF AGND DEC RB(1) 4.7 nF RM(1) 1 nF AGND 1 nF AGND VI RT(1) AGND OE 100 nF VCCD2 AGND (3) 100 nF DGND2 VCCO (3) 100 nF OGND 1 28 2 27 3 26 4 25 5 24 6 23 7 22 ADC1003S050 8 21 9 20 10 19 11 18 12 17 13 16 14 15 VCCD1 DGND1 (3) 100 nF IR D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 n.c.(2) 014aaa322 The analog and digital supplies should be separated and well decoupled. A user manual is available that describes the demonstration board that uses the ADC1003S030/040/050 family in an application environment. (1) RB, RM and RT are decoupled to AGND. (2) Pin 15 may be connected to DGND in order to prevent noise influence. (3) Decoupling capacitor for supplies: must be placed close to the device. Fig 14. Application diagram ADC1003S030_040_050_2 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 02 — 7 August 2008 15 of 20 ADC1003S030/040/050 NXP Semiconductors Single 10 bits ADC, up to 30 MHz, 40 Mhz or 50 MHz, with voltage regulator 12.2 Alternative parts The following alternative parts are also available: Table 9. Alternative parts Type number Description ADC1004S030 Single 10 bits ADC ADC1004S040 Single 10 bits ADC [1] 40 MHz Single 10 bits ADC [1] 50 MHz Single 10 bits ADC [1] 60 MHz ADC0804S030 Single 8 bits ADC [1] 30 MHz ADC0804S040 Single 8 bits ADC [1] 40 MHz Single 8 bits ADC [1] 50 MHz ADC1004S050 ADC1005S060 ADC0804S050 [1] 30 MHz Pin to pin compatible ADC1003S030_040_050_2 Product data sheet Sampling frequency [1] © NXP B.V. 2008. All rights reserved. Rev. 02 — 7 August 2008 16 of 20 ADC1003S030/040/050 NXP Semiconductors Single 10 bits ADC, up to 30 MHz, 40 Mhz or 50 MHz, with voltage regulator 13. Package outline SSOP28: plastic shrink small outline package; 28 leads; body width 5.3 mm D SOT341-1 E A X c HE y v M A Z 28 15 Q A2 A (A 3) A1 pin 1 index θ Lp L 1 14 w M bp e detail X 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) θ mm 2 0.21 0.05 1.80 1.65 0.25 0.38 0.25 0.20 0.09 10.4 10.0 5.4 5.2 0.65 7.9 7.6 1.25 1.03 0.63 0.9 0.7 0.2 0.13 0.1 1.1 0.7 8 o 0 o Note 1. Plastic or metal protrusions of 0.2 mm maximum per side are not included. OUTLINE VERSION SOT341-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 MO-150 Fig 15. Package outline SOT341-1 (SSOP28) ADC1003S030_040_050_2 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 02 — 7 August 2008 17 of 20 ADC1003S030/040/050 NXP Semiconductors Single 10 bits ADC, up to 30 MHz, 40 Mhz or 50 MHz, with voltage regulator 14. Revision history Table 10. Revision history Document ID Release date Data sheet status Change notice Supersedes ADC1003S030_040_050_2 20080807 - ADC1003S030_040_050_1 Modifications: ADC1003S030_040_050_1 Product data sheet • Corrections made to the values of ∆VCC and the cross reference in subhead Reference voltages for the resistor ladder in Table 6. • Corrections made to the table notes in Figure 14. 20080611 Product data sheet ADC1003S030_040_050_2 Product data sheet - - © NXP B.V. 2008. All rights reserved. Rev. 02 — 7 August 2008 18 of 20 ADC1003S030/040/050 NXP Semiconductors Single 10 bits ADC, up to 30 MHz, 40 Mhz or 50 MHz, with voltage regulator 15. Legal information 15.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 15.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. 15.3 Disclaimers General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Quick reference data — The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. 15.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 16. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] ADC1003S030_040_050_2 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 02 — 7 August 2008 19 of 20 ADC1003S030/040/050 NXP Semiconductors Single 10 bits ADC, up to 30 MHz, 40 Mhz or 50 MHz, with voltage regulator 17. Contents 1 2 3 4 5 6 7 7.1 7.2 8 9 10 11 12 12.1 12.2 13 14 15 15.1 15.2 15.3 15.4 16 17 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Quick reference data . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5 Thermal characteristics. . . . . . . . . . . . . . . . . . . 5 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Additional information relating to Table 6 . . . 10 Application information. . . . . . . . . . . . . . . . . . 15 Application diagram . . . . . . . . . . . . . . . . . . . . 15 Alternative parts . . . . . . . . . . . . . . . . . . . . . . . 16 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 17 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 18 Legal information. . . . . . . . . . . . . . . . . . . . . . . 19 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 19 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Contact information. . . . . . . . . . . . . . . . . . . . . 19 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2008. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 7 August 2008 Document identifier: ADC1003S030_040_050_2