Freescale DSP5685XUM 16-bit digital signal controller Datasheet

56857
Data Sheet
Technical Data
56800E
16-bit Digital Signal Controllers
DSP56857
Rev. 6
01/2007
freescale.com
56857 General Description
• 120 MIPS at 120MHz
• Four (4) dedicated GPIO
• 40K x 16-bit Program SRAM
• 8-bit Parallel Host Interface
• 24K x 16-bit Data SRAM
• General Purpose 16-bit Quad Timer
• 1K x 16-bit Boot ROM
• Six (6) independent channels of DMA
• JTAG/Enhanced On-Chip Emulation (OnCE™) for
unobtrusive, real-time debugging
• Two (2) Enhanced Synchronous Serial Interfaces
(ESSI)
• Computer Operating Properly (COP)/Watchdog Timer
• Time-of-Day (TOD)
• Two (2) Serial Communication Interfaces (SCI)
• 100 LQFP package
• Serial Port Interface (SPI)
• Up to 47 GPIO
6
VDDIO
VDD
12
8
JTAG/
Enhanced
OnCE
Program Controller
and
Hardware Looping Unit
VSSIO
12
VSS VDDA
5
VSSA
2
16-Bit
DSP56800E Core
Address
Generation Unit
Data ALU
16 x 16 + 36 Æ 36-Bit MAC
Three 16-bit Input Registers
Four 36-bit Accumulators
Bit
Manipulation
Unit
PAB
PDB
CDBR
CDBW
Boot ROM
1024 x 16 ROM
Data Memory
24,576 x 16 SRAM
XDB2
XAB1
System
Bus
Control
XAB2
PAB
PDB
CDBR
DMA
6 channel
Core CLK
CDBW
DMA Requests
Memory
Program Memory
40,960 x 16 SRAM
Decoding
Peripherals
IPRDB
IPAB
IPWDB
IPBus Bridge (IPBB)
IPBus CLK
POR
CS0-CS3[3:0]
used as GPIOA0-A3
GPIO Contol
2 SCI ESSI0
or
or
GPIOE GPIOC
4
6
ESSI1
or
GPIOD
6
Quad
Timer
or
GPIOG
4
SPI
Host
Interrupt
or
Interface Controller
GPIOF
or
GPIOB
4
16
COP/
Watchdog
Time
of
Day
CLKO
3
System
COP/TOD CLK Integration
Module
Clock
Generator
MODEA-C or
(GPIOH0-H2)
RSTO
RESET
EXTAL
XTAL
OSC PLL
IRQA
IRQB
56857 Block Diagram
56857 Technical Data, Rev. 6
Freescale Semiconductor
3
Part 1 Overview
1.1 56857 Features
1.1.1
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1.1.2
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Digital Signal Processing Core
Efficient 16-bit engine with dual Harvard architecture
120 Million Instructions Per Second (MIPS) at 120MHz core frequency
Single-cycle 16 × 16-bit parallel Multiplier-Accumulator (MAC)
Four (4) 36-bit accumulators including extension bits
16-bit bidirectional shifter
Parallel instruction set with unique DSP addressing modes
Hardware DO and REP loops
Three (3) internal address buses
Four (4) internal data buses
Instruction set supports both DSP and controller functions
Four (4) hardware interrupt levels
Five (5) software interrupt levels
Controller-style addressing modes and instructions for compact code
Efficient C Compiler and local variable support
Software subroutine and interrupt stack with depth limited only by memory
JTAG/Enhanced OnCE debug programming interface
Memory
Harvard architecture permits up to three (3) simultaneous accesses to program and data memory
On-Chip Memory
— 40K × 16-bit Program RAM
— 24K × 16-bit Data RAM
— 1K × 16-bit Boot ROM
— Chip Select Logic used as dedicated GPIO
1.1.3
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Peripheral Circuits for 56857
General Purpose 16-bit Quad Timer*
Two Serial Communication Interfaces (SCI)*
Serial Peripheral Interface (SPI) Port*
Two (2) Enhanced Synchronous Serial Interface (ESSI) modules*
Computer Operating Properly (COP)/Watchdog Timer
JTAG/Enhanced On-Chip Emulation (OnCE) for unobtrusive, real-time debugging
Six (6) independent channels of DMA
56857 Technical Data, Rev. 6
4
Freescale Semiconductor
56857 Description
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8-bit Parallel Host Interface*
Time of Day
Up to 47 GPIO
* Each peripheral I/O can be used alternately as a General Purpose I/O if not needed
1.1.4
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Energy Information
Fabricated in high-density CMOS with 3.3V, TTL-compatible digital inputs
Wait and Stop modes available
1.2 56857 Description
The 56857 is a member of the 56800E core-based family of controllers. It combines, on a single chip, the
processing power of a Digital Signal Processor (DSP) and the functionality of a microcontroller with a
flexible set of peripherals to create an extremely cost-effective solution. Because of its low cost,
configuration flexibility, and compact program code, the 56857 is well-suited for many applications. The
56857 includes many peripherals that are especially useful for low-end Internet appliance applications
and low-end client applications such as telephony; portable devices; Internet audio; and point-of-sale
systems, such as noise suppression; ID tag readers; sonic/subsonic detectors; security access devices;
remote metering; sonic alarms.
The 56800E core is based on a Harvard-style architecture consisting of three execution units operating in
parallel, allowing as many as six operations per instruction cycle. The microprocessor-style programming
model and optimized instruction set allow straightforward generation of efficient, compact DSP and
control code. The instruction set is also highly efficient for C Compilers, enabling rapid development of
optimized control applications.
The 56857 supports program execution from either internal or external memories. Two data operands can
be accessed from the on-chip Data RAM per instruction cycle. The 56857 also provides two external
dedicated interrupt lines, and up to 47 General Purpose Input/Output (GPIO) lines, depending on
peripheral configuration.
The 56857 controller includes 40K words of Program RAM, 24K words of Data RAM and 1K of Boot
ROM.
This controller also provides a full set of standard programmable peripherals that include 8-bit parallel
Host Interface, Two Enhanced Synchronous Serial Interfaces (ESSI), one Serial Peripheral Interface (SPI),
two Serial Communications Interfaces (SCI), and one Quad Timer. The ESSIs, SPI, SCIs IO and Quad
Timer can be used as General Purpose Input/Outputs when its primary function is not required.
56857 Technical Data, Rev. 6
Freescale Semiconductor
5
1.3 State of the Art Development Environment
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Processor ExpertTM (PE) provides a Rapid Application Design (RAD) tool that combines easy-to-use
component-based software application creation with an expert knowledge system.
The Code Warrior Integrated Development Environment is a sophisticated tool for code navigation,
compiling, and debugging. A complete set of evaluation modules (EVMs) and development system cards
will support concurrent engineering. Together, PE, Code Warrior and EVMs create a complete, scalable
tools solution for easy, fast, and efficient development.
1.4 Product Documentation
The four documents listed in Table 1-1 are required for a complete description of and proper design with
the 56857. Documentation is available from local Freescale distributors, Freescale Semiconductor sales
offices, Freescale Literature Distribution Centers, or online at www.freescale.com.
Table 1-1 56857 Chip Documentation
Topic
Description
Order Number
56800E
Reference Manual
Detailed description of the 56800E architecture, 16-bit
core processor and the instruction set
56800ERM
DSP56857
User’s Manual
Detailed description of memory, peripherals, and
interfaces of the 56857
DSP5685xUM
DSP56857
Technical Data Sheet
Electrical and timing specifications, pin descriptions,
and package descriptions (this document)
DSP56857
DSP56857
Errata
Details any chip issues that might be present
DSP56857E
1.5 Data Sheet Conventions
This data sheet uses the following conventions:
OVERBAR
This is used to indicate a signal that is active when pulled low. For example, the RESET pin is
active when low.
“asserted”
A high true (active high) signal is high or a low true (active low) signal is low.
“deasserted”
A high true (active high) signal is low or a low true (active low) signal is high.
Examples:
Signal/Symbol
Logic State
Signal State
Voltage1
PIN
True
Asserted
VIL/VOL
PIN
False
Deasserted
VIH/VOH
PIN
True
Asserted
VIH/VOH
PIN
False
Deasserted
VIL/VOL
1. Values for VIL, VOL, VIH, and VOH are defined by individual product specifications.
56857 Technical Data, Rev. 6
6
Freescale Semiconductor
Introduction
Part 2 Signal/Connection Descriptions
2.1 Introduction
The input and output signals of the 56857 are organized into functional groups, as shown in Table 2-1 and
as illustrated in Figure 2-1. In Table 3-1 each table row describes the package pin and the signal or signals
present.
Table 2-1 Functional Group Pin Allocations
Functional Group
Number of Pins
Power (VDD, VDDIO, or VDDA)
(8, 12, 1)1
Ground (VSS, VSSIO,or VSSA)
(5, 12, 2)1
PLL and Clock
3
Chip Select Logic used as dedicated GPIO
4
Interrupt and Program Control
72
Host Interface (HI)*
163
Enhanced Synchronous Serial Interface (ESSI0) Port*
6
Enhanced Synchronous Serial Interface (ESSI1) Port*
6
Serial Communications Interface (SCI0) Ports*
2
Serial Communications Interface (SCI1) Ports*
2
Serial Peripheral Interface (SPI) Port*
4
Quad Timer Module Port*
4
JTAG/Enhanced On-Chip Emulation (EOnCE)
6
*Alternately, GPIO pins
1. VDD = VDD CORE, VSS = VSS CORE, VDDIO= VDD IO, VSSIO = VSS IO, VDDA = VDD ANA, VSSA = VSS ANA
2. MODE A, MODE B and MODE C can be used as GPIO after the bootstrap process has completed.
3. The following Host Interface signals are multiplexed: HRWB to HRD, HDS to HWR, HREQ to HTRQ and HACK to HRRQ.
56857 Technical Data, Rev. 6
Freescale Semiconductor
7
Logic
Power
VDD
1
8
VSS
1
5
1
I/O
Power
VDDIO
1
12
VSSIO
12
1
Analog
Power1
VDDA
1
1
VSSA
1
2
1
1
56857
1
1
1
1
1
Chip
Select
CS0 - CS3 (GPIOA0 - A3)
4
1
1
HD0 - HD7 (GPIOB0 - B7)
8
HA0 - HA2 (GPIOB8 - B10)
3
HRWB (HRD) (GPIOB11)
Host
Interface
1
HDS (HWR) (GPIOB12)
1
HCS (GPIOB13)
1
HREQ (HTRQ) (GPIOB14)
1
1
1
1
1
TIO0 - TIO3 (GPIOG0 - G3)
4
IRQA
1
IRQB
Interrupt /
Program
Control
1
SCI 0
TXDO (GPIOE1)
RXD1 (GPIOE2)
SCI 2
TXD1 (GPIOE3)
STD0 (GPIOC0)
SRD0 (GPIOC1)
SCK0 (GPIOC2)
ESSI 0
SC00 (GPIOC3)
SC01 (GPIOC4)
SC02 (GPIOC5)
STD1 (GPIOD0)
SRD1 (GPIOD1)
SCK1 (GPIOD2)
ESSI 1
SC10 (GPIOD3)
SC11 (GPIOD4)
SC12 (GPIOD5)
MISO (GPIOF0)
MOSI (GPIOF1)
SPI
SCK (GPIOF2)
SS (GPIOF3)
1
HACK (HRRQ) (GPIOB15)
Timer
Module
1
RXDO (GPIOE0)
1
MODE A, MODE B, MODE C
(GPIOH0 - H2)
1
1
1
1
RESET
RSTO
3
1
1
1
1
1
XTAL
PLL /
Clock
EXTAL
CLKO
TCK
TDI
TDO
JTAG /
Enhanced
OnCE
TMS
TRST
DE
Figure 2-1 56857 Signals Identified by Functional Group2
1. Specifically for PLL, OSC, and POR.
2. Alternate pin functions are shown in parentheses.
56857 Technical Data, Rev. 6
8
Freescale Semiconductor
Introduction
Part 3 Signals and Package Information
All digital inputs have a weak internal pull-up circuit associated with them. These pull-up circuits are
enabled by default. Exceptions:
1. When a pin has GPIO functionality, the pull-up may be disabled under software control.
2. MODE A, MODE B, and MODE C pins have no pull-up.
3. TCK has a weak pull-down circuit always active.
4. Bidirectional I/O pullups automatically disable when the output is enabled.
This table is presented consistently with the Signals Identified by Functional Group figure.
1. BOLD entries in the Type column represents the state of the pin just out of reset.
2. Output(Z) means an output in a High-Z condition.
Table 3-1 56857 Signal and Package Information for the 100-pin LQFP
Pin No.
Signal Name
Type
Description
8
VDD
VDD
25
VDD
Power (VDD)—These pins provide power to the internal structures of the
chip, and should all be attached to VDD.
36
VDD
50
VDD
59
VDD
60
VDD
76
VDD
87
VDD
9
VSS
VSS
37
VSS
Ground (VSS)—These pins provide grounding for the internal structures
of the chip and should all be attached to VSS.
38
VSS
61
VSS
88
VSS
56857 Technical Data, Rev. 6
Freescale Semiconductor
9
Table 3-1 56857 Signal and Package Information for the 100-pin LQFP (Continued)
Pin No.
Signal Name
Type
Description
5
VDDIO
VDDIO
6
VDDIO
Power (VDDIO)—These pins provide power for all I/O and ESD structures
of the chip, and should all be attached to VDDIO (3.3V).
13
VDDIO
34
VDDIO
45
VDDIO
47
VDDIO
48
VDDIO
VDDIO
53
VDDIO
Power (VDDIO)—These pins provide power for all I/O and ESD structures
of the chip, and should all be attached to VDDIO (3.3V).
72
VDDIO
80
VDDIO
90
VDDIO
98
VDDIO
7
VSSIO
VSSIO
14
VSSIO
Ground (VSSIO)—These pins provide grounding for all I/O and ESD
structures of the chip and should all be attached to VSS.
35
VSSIO
46
VSSIO
49
VSSIO
54
VSSIO
73
VSSIO
82
VSSIO
89
VSSIO
91
VSSIO
99
VSSIO
100
VSSIO
17
VDDA
VDDA
Analog Power (VDDA)—These pins supply an analog power source.
56857 Technical Data, Rev. 6
10
Freescale Semiconductor
Introduction
Table 3-1 56857 Signal and Package Information for the 100-pin LQFP (Continued)
Pin No.
Signal Name
Type
18
VSSA
VSSA
19
VSSA
55
CS0
Output
GPIOA0
Input/Output
CS1
Output
GPIOA1
Input/Output
CS2
Output
GPIOA2
Input/Output
CS3
Output
GPIOA3
Input/Output
HD0
Input
56
57
58
22
Description
Analog Ground (VSSA)—This pin supplies an analog ground.
External Chip Select (CS0)—This pin is used as a dedicated GPIO.
Port A GPIO (0)—This pin is a General Purpose I/O (GPIO) pin when not
configured for host port usage.
External Chip Select (CS1)—This pin is used as a dedicated GPIO.
Port A GPIO (1)—This pin is a General Purpose I/O (GPIO) pin when not
configured for host port usage.
External Chip Select (CS2)—This pin is used as a dedicated GPIO.
Port A GPIO (2)—This pin is a General Purpose I/O (GPIO) pin when not
configured for host port usage.
External Chip Select (CS3)—This pin is used as a dedicated GPIO.
Port A GPIO (3)—This pin is a General Purpose I/O (GPIO) pin when not
configured for host port usage.
Host Address (HD0)—This input provides the address selection for HI
registers.
This pin is disconnected internally.
23
GPIOB0
Input/Output
HD1
Input
Port B GPIO (0)—This pin is a General Purpose I/O (GPIO) pin when not
configured for host port usage.
Host Address (HD1)—This input provides the address selection for HI
registers.
This pin is disconnected internally.
24
GPIOB1
Input/Output
Port B GPIO (1)—This pin is a General Purpose I/O (GPIO) pins when
not configured for host port usage.
HD2
Input
Host Address (HD2)—This input provides the address selection for HI
registers.
This pin is disconnected internally.
GPIOB2
Input/Output
Port B GPIO (2)—This pin is a General Purpose I/O (GPIO) pins when
not configured for host port usage.
56857 Technical Data, Rev. 6
Freescale Semiconductor
11
Table 3-1 56857 Signal and Package Information for the 100-pin LQFP (Continued)
Pin No.
Signal Name
Type
29
HD3
Input
Description
Host Address (HD3)—This input provides the address selection for HI
registers.
This pin is disconnected internally.
30
GPIOB3
Input/Output
Port B GPIO (3)—This pin is a General Purpose I/O (GPIO) pins when
not configured for host port usage.
HD4
Input
Host Address (HD4)—This input provides the address selection for HI
registers.
This pin is disconnected internally.
31
GPIOB4
Input/Output
Port B GPIO (4)—This pin is a General Purpose I/O (GPIO) pins when
not configured for host port usage.
HD5
Input
Host Address (HD5)—This input provides the address selection for HI
registers.
This pin is disconnected internally.
32
GPIOB5
Input/Output
Port B GPIO (5)—This pin is a General Purpose I/O (GPIO) pins when
not configured for host port usage.
HD6
Input
Host Address (HD6)—This input provides the address selection for HI
registers.
This pin is disconnected internally.
33
GPIOB6
Input/Output
Port B GPIO (6)—This pin is a General Purpose I/O (GPIO) pins when
not configured for host port usage.
HD7
Input
Host Address (HD7)—This input provides the address selection for HI
registers.
This pin is disconnected internally.
62
GPIOB7
Input/Output
Port B GPIO (7)—This pin is a General Purpose I/O (GPIO) pins when
not configured for host port usage.
HA0
Input
Host Address (HA0)—This input provides the address selection for HI
registers.
This pin is disconnected internally.
GPIOB8
Input/Output
Port B GPIO (8)—This pin is a General Purpose I/O (GPIO) pin when not
configured for host port usage.
56857 Technical Data, Rev. 6
12
Freescale Semiconductor
Introduction
Table 3-1 56857 Signal and Package Information for the 100-pin LQFP (Continued)
Pin No.
Signal Name
Type
63
HA1
Input
Description
Host Address (HA1)—This input provides the address selection for HI
registers.
This pin is disconnected internally.
64
GPIOB9
Input/Output
HA2
Input
Port B GPIO (9)—This pin is a General Purpose I/O (GPIO) pin when not
configured for host port usage.
Host Address (HA2)—This input provides the address selection for HI
registers.
This pin is disconnected internally.
65
GPIOB10
Input/Output
Port B GPIO (10)—This pin is a General Purpose I/O (GPIO) pin when
not configured for host port usage.
HRWB
Input
Host Read/Write (HRWB)—When the HI08 is programmed to interface
to a single-data-strobe host bus and the HI function is selected, this
signal is the Read/Write input.
These pins are disconnected internally.
83
HRD
Input
Host Read Data (HRD)—This signal is the Read Data input when the
HI08 is programmed to interface to a double-data-strobe host bus and the
HI function is selected.
GPIOB11
Input/Output
Port B GPIO (11) —This pin is a General Purpose I/O (GPIO) pin when
not configured for host port usage.
HDS
Input
Host Data Strobe (HDS)—When the HI08 is programmed to interface to
a single-data-strobe host bus and the HI function is selected, this input
enables a data transfer on the HI when HCS is asserted.
These pins are disconnected internally.
84
HWR
Input
GPIOB12
Input/Output
Port B GPIO (12)—This pin is a General Purpose I/O (GPIO) pin when
not configured for host port usage.
HCS
Input
Host Chip Select (HCS)—This input is the chip select input for the Host
Interface.
Host Write Enable (HWR)—This signal is the Write Data input when the
HI08 is programmed to interface to a double-data-strobe host bus and the
HI function is selected.
These pins are disconnected internally.
GPIOB13
Input/Output
Port B GPIO (13)—This pin is a General Purpose I/O (GPIO) pin when
not configured for host port usage.
56857 Technical Data, Rev. 6
Freescale Semiconductor
13
Table 3-1 56857 Signal and Package Information for the 100-pin LQFP (Continued)
Pin No.
Signal Name
Type
Description
85
HREQ
Open Drain
Output
Host Request (HREQ)—When the HI08 is programmed for HRMS=0
functionality (typically used on a single-data- strobe bus), this open drain
output is used by the HI to request service from the host processor. The
HREQ may be connected to an interrupt request pin of a host processor,
a transfer request of a DMA controller, or a control input of external
circuitry.
These pins are disconnected internally.
86
HTRQ
Open Drain
Output
Transmit Host Request (HTRQ)—This signal is the Transmit Host
Request output when the HI08 is programmed for HRMS=1 functionality
and is typically used on a double-data-strobe bus.
GPIOB14
Input/Output
Port B GPIO (14) —This pin is a General Purpose I/O (GPIO) pin when
not configured for host port usage.
HACK
Input
Host Acknowledge (HACK)—When the HI08 is programmed for
HRMS=0 functionality (typically used on a single-data-strobe bus), this
input has two functions: (1) provide a Host Acknowledge signal for DMA
transfers or (2) to control handshaking and provide a Host Interrupt
Acknowledge compatible with the MC68000 family processors.
These pins are disconnected internally during reset.
81
79
78
HRRQ
Open Drain
Output
Receive Host Request (HRRQ)—This signal is the Receive Host
Request output when the HI08 is programmed for HRMS=1 functionality
and is typically used on a double-data-strobe bus.
GPIOB15
Input/Output
Port B GPIO (15)—This pin is a General Purpose I/O (GPIO) pin when
not configured for host port usage.
TIO0
Input/Output
Timer Input/Output (TIO0)—This pin can be independently configured to
be either a timer input source or an output flag.
GPIOG0
Input/Output
Port G GPIO (0)—This pin is a General Purpose I/O (GPIO) pin that can
individually be programmed as an input or output pin.
TIO1
Input/Output
Timer Input/Output (TIO1)—This pin can be independently configured to
be either a timer input source or an output flag.
GPIOG1
Input/Output
Port G GPIO (1)—This pin is a General Purpose I/O (GPIO) pin that can
individually be programmed as an input or output pin.
TIO2
Input/Output
Timer Input/Output (TIO2)—This pin can be independently configured to
be either a timer input source or an output flag.
GPIOG2
Input/Output
Port G GPIO (2)—This pin is a General Purpose I/O (GPIO) pin that can
individually be programmed as an input or output pin.
56857 Technical Data, Rev. 6
14
Freescale Semiconductor
Introduction
Table 3-1 56857 Signal and Package Information for the 100-pin LQFP (Continued)
Pin No.
Signal Name
Type
Description
77
TIO3
Input/Output
Timer Input/Output (TIO3)—This pin can be independently configured to
be either a timer input source or an output flag.
GPIOG3
Input/Output
Port G GPIO (3)—This pin is a General Purpose I/O (GPIO) pin that can
individually be programmed as an input or output pin.
15
IRQA
Input
16
IRQB
External Interrupt Request A and B—The IRQA and IRQB inputs are
asynchronous external interrupt requests that indicate that an external
device is requesting service. A Schmitt trigger input is used for noise
immunity. They can be programmed to be level-sensitive or
negative-edge- triggered. If level-sensitive triggering is selected, an
external pull-up resistor is required for Wired-OR operation.
10
MODE A
Input
Mode Select (MODE A)—During the bootstrap process MODE A selects
one of the eight bootstrap modes.
GPIOH0
Input/Output
Port H GPIO (0)—This pin is a General Purpose I/O (GPIO) pin after the
bootstrap process has completed.
MODE B
Input
Mode Select (MODE B)—During the bootstrap process MODE B selects
one of the eight bootstrap modes.
GPIOH1
Input/Output
Port H GPIOH1—This pin is a General Purpose I/O (GPIO) pin after the
bootstrap process has completed.
MODE C
Input
Mode Select (MODE C)—During the bootstrap process MODE C selects
one of the eight bootstrap modes.
GPIOH2
Input/Output
Port H GPIO (2)—This pin is a General Purpose I/O (GPIO) pin after the
bootstrap process has completed.
RESET
Input
Reset (RESET)—This input is a direct hardware reset on the processor.
When RESET is asserted low, the controller is initialized and placed in
the Reset state. A Schmitt trigger input is used for noise immunity. When
the RESET pin is deasserted, the initial chip operating mode is latched
from the MODE A, MODE B, and MODE C pins.
11
12
28
To ensure complete hardware reset, RESET and TRST should be
asserted together. The only exception occurs in a debugging
environment when a hardware reset is required and it is necessary not to
reset the JTAG/Enhanced OnCE module. In this case, assert RESET, but
do not assert TRST.
27
RSTO
Output
Reset Output (RSTO)—This output is asserted on any reset condition
(external reset, low voltage, software or COP).
51
RXD0
Input
Serial Receive Data 0 (RXD0)—This input receives byte-oriented serial
data and transfers it to the SCI 0 receive shift register.
GPIOE0
Input/Output
Port E GPIO (0)—This pin is a General Purpose I/O (GPIO) pin that can
individually be programmed as input or output pin.
56857 Technical Data, Rev. 6
Freescale Semiconductor
15
Table 3-1 56857 Signal and Package Information for the 100-pin LQFP (Continued)
Pin No.
Signal Name
Type
Description
52
TXD0
Output(Z)
Serial Transmit Data 0 (TXD0)—This signal transmits data from the SCI
0 transmit data register.
GPIOE1
Input/Output
Port E GPIO (1)—This pin is a General Purpose I/O (GPIO) pin that can
individually be programmed as input or output pin.
RXD1
Input
Serial Receive Data 1 (RXD1)—This input receives byte-oriented serial
data and transfers it to the SCI 1 receive shift register.
GPIOE2
Input/Output
Port E GPIO (2)—This pin is a General Purpose I/O (GPIO) pin that can
individually be programmed as input or output pin.
TXD1
Output(Z)
Serial Transmit Data 1 (TXD1)—This signal transmits data from the SCI
1 transmit data register.
GPIOE3
Input/Output
Port E GPIO (3)—This pin is a General Purpose I/O (GPIO) pin that can
individually be programmed as input or output pin.
STD0
Output
ESSI Transmit Data (STD0)—This output pin transmits serial data from
the ESSI Transmitter Shift Register.
GPIOC0
Input/Output
Port C GPIO (0)—This pin is a General Purpose I/O (GPIO) pin when the
ESSI is not in use.
SRD0
Input
GPIOC1
Input/Output
Port C GPIO (1)—This pin is a General Purpose I/O (GPIO) pin when the
ESSI is not in use.
SCK0
Input/Output
ESSI Serial Clock (SCK0)—This bidirectional pin provides the serial bit
rate clock for the transmit section of the ESSI. The clock signal can be
continuous or gated and can be used by both the transmitter and receiver
in synchronous mode.
GPIOC2
Input/Output
Port C GPIO (2)—This pin is a General Purpose I/O (GPIO) pin when the
ESSI is not in use.
SC00
Input/Output
ESSI Serial Control Pin 0 (SC00)—The function of this pin is determined
by the selection of either synchronous or asynchronous mode. For
asynchronous mode, this pin will be used for the receive clock I/O. For
synchronous mode, this pin is used either for transmitter1 output or for
serial I/O flag 0.
GPIOC3
Input/Output
Port C GPIO (3)—This pin is a General Purpose I/O (GPIO) pin when the
ESSI is not in use.
74
75
92
93
94
95
ESSI Receive Data (SRD0)—This input pin receives serial data and
transfers the data to the ESSI Receive Shift Register.
56857 Technical Data, Rev. 6
16
Freescale Semiconductor
Introduction
Table 3-1 56857 Signal and Package Information for the 100-pin LQFP (Continued)
Pin No.
Signal Name
Type
Description
96
SC01
Input/Output
ESSI Serial Control Pin 1 (SC01)—The function of this pin is determined
by the selection of either synchronous or asynchronous mode. For
asynchronous mode, this pin is the receiver frame sync I/O. For
synchronous mode, this pin is used either for transmitter2 output or for
serial I/O flag 1.
GPIOC4
Input/Output
Port C GPIO (4)—This pin is a General Purpose I/O (GPIO) pin when the
ESSI is not in use.
SC02
Input/Output
ESSI Serial Control Pin 2 (SC02)—This pin is used for frame sync I/O.
SC02 is the frame sync for both the transmitter and receiver in
synchronous mode and for the transmitter only in asynchronous mode.
When configured as an output, this pin is the internally generated frame
sync signal. When configured as an input, this pin receives an external
frame sync signal for the transmitter (and the receiver in synchronous
operation).
GPIOC5
Input/Output
Port C GPIO (5)—This pin is a General Purpose I/O (GPIO) pin when the
ESSI is not in use.
STD1
Output
ESSI Transmit Data (STD1)—This output pin transmits serial data from
the ESSI Transmitter Shift Register.
GPIOD0
Input/Output
Port D GPIOD0—This pin is a General Purpose I/O (GPIO) pin when the
ESSI is not in use.
SRD1
Input
GPIOD1
Input/Output
Port D GPIO (1)—This pin is a General Purpose I/O (GPIO) pin when the
ESSI is not in use.
SCK1
Input/Output
ESSI Serial Clock (SCK1)—This bidirectional pin provides the serial bit
rate clock for the transmit section of the ESSI. The clock signal can be
continuous or gated and can be used by both the transmitter and receiver
in synchronous mode.
GPIOD2
Input/Output
Port D GPIO (2)—This pin is a General Purpose I/O (GPIO) pin when the
ESSI is not in use.
SC10
Input/Output
ESSI Serial Control Pin 0 (SC10)—The function of this pin is determined
by the selection of either synchronous or asynchronous mode. For
asynchronous mode, this pin will be used for the receive clock I/O. For
synchronous mode, this pin is used either for transmitter1 output or for
serial I/O flag 0.
GPIOD3
Input/Output
Port D GPIO (3)—This pin is a General Purpose I/O (GPIO) pin when the
ESSI is not in use.
97
66
67
68
69
ESSI Receive Data (SRD1)—This input pin receives serial data and
transfers the data to the ESSI Receive Shift Register.
56857 Technical Data, Rev. 6
Freescale Semiconductor
17
Table 3-1 56857 Signal and Package Information for the 100-pin LQFP (Continued)
Pin No.
Signal Name
Type
Description
70
SC11
Input/Output
ESSI Serial Control Pin 1 (SC11)—The function of this pin is determined
by the selection of either synchronous or asynchronous mode. For
asynchronous mode, this pin is the receiver frame sync I/O. For
synchronous mode, this pin is used either for transmitter2 output or for
serial I/O flag 1.
GPIOD4
Input/Output
Port D GPIO (4)—This pin is a General Purpose I/O (GPIO) pin when the
ESSI is not in use.
SC12
Input/Output
ESSI Serial Control Pin 2 (SC12)—This pin is used for frame sync I/O.
SC02 is the frame sync for both the transmitter and receiver in
synchronous mode and for the transmitter only in asynchronous mode.
When configured as an output, this pin is the internally generated frame
sync signal. When configured as an input, this pin receives an external
frame sync signal for the transmitter (and the receiver in synchronous
operation).
GPIOD5
Input/Output
Port D GPIO (5)—This pin is a General Purpose I/O (GPIO) pin when the
ESSI is not in use.
MISO
Input/Output
SPI Master In/Slave Out (MISO)—This serial data pin is an input to a
master device and an output from a slave device. The MISO line of a
slave device is placed in the high-impedance state if the slave device is
not selected. The driver on this pin can be configured as an open-drain
driver by the SPI’s Wired-OR mode (WOM) bit when this pin is configured
for SPI operation.
GPIOF0
Input/Output
Port F GPIO (0)—This pin is a General Purpose I/O (GPIO) pin that can
individually be programmed as input or output pin.
MOSI
Input/
Output (Z)
SPI Master Out/Slave In (MOSI)—This serial data pin is an output from a
master device and an input to a slave device. The master device places
data on the MOSI line a half-cycle before the clock edge that the slave
device uses to latch the data. The driver on this pin can be configured as
an open-drain driver by the SPI’s WOM bit when this pin is configured for
SPI operation.
GPIOF1
Input/Output
Port F GPIO (1)—This pin is a General Purpose I/O (GPIO) pin that can
be individually programmed as input or output pin.
71
1
2
56857 Technical Data, Rev. 6
18
Freescale Semiconductor
Introduction
Table 3-1 56857 Signal and Package Information for the 100-pin LQFP (Continued)
Pin No.
Signal Name
Type
Description
3
SCK
Input/Output
SPI Serial Clock (SCK)—This bidirectional pin provides a serial bit rate
clock for the SPI. This gated clock signal is an input to a slave device and
is generated as an output by a master device. Slave devices ignore the
SCK signal unless the SS pin is active low. In both master and slave SPI
devices, data is shifted on one edge of the SCK signal and is sampled on
the opposite edge where data is stable. The driver on this pin can be
configured as an open-drain driver by the SPI’s WOM bit when this pin is
configured for SPI operation. When using Wired-OR mode, the user must
provide an external pull-up device.
GPIOF2
Input/Output
Port F GPIO (2)—This pin is a General Purpose I/O (GPIO) pin that can
individually be programmed as input or output pin.
SS
Input
SPI Slave Select (SS)—This input pin selects a slave device before a
master device can exchange data with the slave device. SS must be low
before data transactions and must stay low for the duration of the
transaction. The SS line of the master must be held high.
GPIOF3
Input/Output
Port F GPIO (3)—This pin is a General Purpose I/O (GPIO) pin that can
individually be programmed as input or output pin.
20
XTAL
Input/Output
Crystal Oscillator Output (XTAL)—This output connects the internal
crystal oscillator output to an external crystal. If an external clock source
other than a crystal oscillator is used, XTAL must be used as the input.
21
EXTAL
Input
External Crystal Oscillator Input (EXTAL)—This input should be
connected to an external crystal. If an external clock source other than a
crystal oscillator is used, EXTAL must be tied off. See Section 4.5.2
26
CLKO
Output
Clock Output (CLKO)—This pin outputs a buffered clock signal. When
enabled, this signal is the system clock divided by four.
44
TCK
Input
Test Clock Input (TCK)—This input pin provides a gated clock to
synchronize the test logic and to shift serial data to the JTAG/Enhanced
OnCE port. The pin is connected internally to a pull-down resistor.
42
TDI
Input
Test Data Input (TDI)—This input pin provides a serial input data stream
to the JTAG/Enhanced OnCE port. It is sampled on the rising edge of
TCK and has an on-chip pull-up resistor.
41
TDO
Output(Z)
43
TMS
Input
4
Test Data Output (TDO)—This tri-statable output pin provides a serial
output data stream from the JTAG/Enhanced OnCE port. It is driven in
the Shift-IR and Shift-DR controller states, and changes on the falling
edge of TCK.
Test Mode Select Input (TMS)—This input pin is used to sequence the
JTAG TAP controller’s state machine. It is sampled on the rising edge of
TCK and has an on-chip pull-up resistor.
Note:
Always tie the TMS pin to VDD through a 2.2K resistor.
56857 Technical Data, Rev. 6
Freescale Semiconductor
19
Table 3-1 56857 Signal and Package Information for the 100-pin LQFP (Continued)
Pin No.
Signal Name
Type
Description
40
TRST
Input
Test Reset (TRST)—As an input, a low signal on this pin provides a reset
signal to the JTAG TAP controller. To ensure complete hardware reset,
TRST should be asserted whenever RESET is asserted. The only
exception occurs in a debugging environment, since the Enhanced
OnCE/JTAG module is under the control of the debugger. In this case it is
not necessary to assert TRST when asserting RESET. Outside of a
debugging environment RESET should be permanently asserted by
grounding the signal, thus disabling the Enhanced OnCE/JTAG module
on the device.
Note: For normal operation, connect TRST directly to VSS. If the design is to
be used in a debugging environment, TRST may be tied to VSS through a 1K
resistor.
39
DE
Input/Output
Debug Event (DE)—This is an open-drain, bidirectional, active low
signal. As an input, it is a means of entering debug mode of operation
from an external command controller. As an output, it is a means of
acknowledging that the chip has entered debug mode.
This pin is connected internally to a weak pull-up resistor.
56857 Technical Data, Rev. 6
20
Freescale Semiconductor
General Characteristics
Part 4 Specifications
4.1 General Characteristics
The 56857 is fabricated in high-density CMOS with 5-volt tolerant TTL-compatible digital inputs. The
term “5-volt tolerant” refers to the capability of an I/O pin, built on a 3.3V compatible process
technology, to withstand a voltage up to 5.5V without damaging the device. Many systems have a
mixture of devices designed for 3.3V and 5V power supplies. In such systems, a bus may carry both 3.3V
and 5V- compatible I/O voltage levels (a standard 3.3V I/O is designed to receive a maximum voltage of
3.3V ± 10% during normal operation without causing damage). This 5V tolerant capability therefore
offers the power savings of 3.3V I/O levels while being able to receive 5V levels without being damaged.
Absolute maximum ratings given in Table 4-1 are stress ratings only, and functional operation at the
maximum is not guaranteed. Stress beyond these ratings may affect device reliability or cause permanent
damage to the device.
The 56857 DC/AC electrical specifications are preliminary and are from design simulations. These
specifications may not be fully tested or guaranteed at this early stage of the product life cycle. Finalized
specifications will be published after complete characterization and device qualifications have been
completed.
CAUTION
This device contains protective circuitry to guard
against damage due to high static voltage or
electrical fields. However, normal precautions are
advised to avoid application of any voltages higher
than maximum rated voltages to this high-impedance
circuit. Reliability of operation is enhanced if unused
inputs are tied to an appropriate voltage level.
56857 Technical Data, Rev. 6
Freescale Semiconductor
21
Table 4-1 Absolute Maximum Ratings
Characteristic
Supply voltage, core
Supply voltage, IO
Supply voltage, analog
Digital input voltages
Analog input voltages (XTAL, EXTAL)
Current drain per pin excluding VDD, GND
Junction temperature
Storage temperature range
Symbol
Min
Max
Unit
VDD1
VSS – 0.3
VSS + 2.0
V
VDDIO2
VSSIO + 4.0
VDDA + 4.0
V
VDDIO2
VSSIO – 0.3
VSSA – 0.3
VIN
VINA
VSSIO – 0.3
VSSA – 0.3
VSSIO + 5.5
VDDA + 0.3
V
I
—
8
mA
TJ
-40
120
°C
TSTG
-55
150
°C
1. VDD must not exceed VDDIO
2. VDDIO and VDDA must not differ by more that 0.5V
Table 4-2 Recommended Operating Conditions
Characteristic
Symbol
Min
Max
Unit
VDD
1.62
1.98
V
Supply voltage for I/O Power
VDDIO
3.0
3.6
V
Supply voltage for Analog Power
VDDA
3.0
3.6
V
Ambient operating temperature
TA
-40
85
°C
PLL clock frequency1
fpll
—
240
MHz
Operating Frequency2
fop
—
120
MHz
Frequency of peripheral bus
fipb
—
60
MHz
Frequency of external clock
fclk
—
240
MHz
Frequency of oscillator
fosc
2
4
MHz
Frequency of clock via XTAL
fxtal
—
240
MHz
Frequency of clock via EXTAL
fextal
2
4
MHz
Supply voltage for Logic Power
1. Assumes clock source is direct clock to EXTAL or crystal oscillator running 2-4MHz. PLL must be enabled, locked, and
selected. The actual frequency depends on the source clock frequency and programming of the CGM module.
2. Master clock is derived from on of the following four sources:
fclk = fxtal when the source clock is the direct clock to EXTAL
fclk = fpll when PLL is selected
fclk = fosc when the source clock is the crystal oscillator and PLL is not selected
fclk = fextal when the source clock is the direct clock to EXTAL and PLL is not selected
56857 Technical Data, Rev. 6
22
Freescale Semiconductor
DC Electrical Characteristics
Table 4-3 Thermal Characteristics1
100-pin LQFP
Characteristic
Symbol
Value
Unit
Thermal resistance junction-to-ambient
(estimated)
θJA
41.2
°C/W
I/O pin power dissipation
PI/O
User Determined
W
Power dissipation
PD
PD = (IDD × VDD) + PI/O
W
PDMAX
(TJ – TA) / RθJA 2
W
Maximum allowed PD
1. See Section 6.1 for more detail.
2. TJ = Junction Temperature
TA = Ambient Temperature
4.2 DC Electrical Characteristics
Table 4-4 DC Electrical Characteristics
Operating Conditions: VSS = VSSIO = VSSA = 0 V, VDD = 1.62-1.98V, VDDIO = VDDA = 3.0–3.6V, TA = –40° to +120°C, CL ≤ 50pF, fop = 120MHz
Characteristic
Symbol
Min
Typ
Max
Unit
Input high voltage (XTAL/EXTAL)
VIHC
VDDA – 0.8
VDDA
VDDA + 0.3
V
Input low voltage (XTAL/EXTAL)
VILC
-0.3
—
0.5
V
Input high voltage
VIH
2.0
—
5.5
V
Input low voltage
VIL
-0.3
—
0.8
V
Input current low (pullups disabled)
IIL
-1
—
1
μA
Input current high (pullups disabled)
IIH
-1
—
1
μA
Output tri-state current low
IOZL
-10
—
10
μA
Output tri-state current high
IOZH
-10
—
10
μA
Output High Voltage
VOH
VDDIO – 0.7
—
—
V
Output Low Voltage
VOL
—
—
0.4
V
Output High Current
IOH
8
—
16
mA
Output Low Current
IOL
8
—
16
mA
Input capacitance
CIN
—
8
—
pF
Output capacitance
COUT
—
12
—
pF
VDD supply current (Core logic, memories, peripherals)
IDD4
—
—
—
70
0.05
5
110
10
14
mA
mA
mA
1
Run
Deep Stop2
Light Stop3
56857 Technical Data, Rev. 6
Freescale Semiconductor
23
Table 4-4 DC Electrical Characteristics (Continued)
Operating Conditions: VSS = VSSIO = VSSA = 0 V, VDD = 1.62-1.98V, VDDIO = VDDA = 3.0–3.6V, TA = –40° to +120°C, CL ≤ 50pF, fop = 120MHz
Characteristic
Symbol
Min
Typ
Max
Unit
—
40
0
50
1.5
mA
mA
—
60
120
μA
VEI
—
2.5
2.85
V
Low Voltage Interrupt Recovery Hysteresis
VEIH
—
50
—
mV
Power on Reset7
POR
—
1.5
2.0
V
VDDIO supply current (I/O circuity)
IDDIO
Run5
Deep Stop2
VDDA supply current (analog circuity)
Deep
IDDA
Stop2
Low Voltage Interrupt
6
Note:
Run (operating) IDD measured using external square wave clock source (fosc = 4MHz) into XTAL. All inputs 0.2V from rail;
no DC loads; outputs unloaded. All ports configured as inputs; measured with all modules enabled. PLL set to 240MHz out.
1.
Running Core, performing 50% NOP and 50% FIR. Clock at 120 MHz.
2.
Deep Stop Mode - Operation frequency = 4 MHz, PLL set to 4 MHz, crystal oscillator and time of day module operating.
3.
Light Stop Mode - Operation frequency = 120 MHz, PLL set to 240 MHz, crystal oscillator and time of day module operating.
4.
IDD includes current for core logic, internal memories, and all internal peripheral logic circuitry.
5.
Running core and performing external memory access. Clock at 120 MHz.
6.
When VDD drops below VEI max value, an interrupt is generated.
7. Power-on reset occurs whenever the digital supply drops below 1.8V. While power is ramping up, this signal remains active
for as long as the internal 2.5V is below 1.8V no matter how long the ramp up rate is. The internally regulated voltage is typically
100 mV less than VDD during ramp up until 2.5V is reached, at which time it self-regulates.
150
EMI Mode5
MAC Mode1
120
IDD (mA)
90
60
30
0
20
40
60
80
100
120
Figure 4-1 Maximum Run IDDTOTAL vs. Frequency (see Notes 1. and 5. in Table 4-4)
56857 Technical Data, Rev. 6
24
Freescale Semiconductor
Supply Voltage Sequencing and Separation Cautions
4.3 Supply Voltage Sequencing and Separation Cautions
DC Power Supply Voltage
Figure 4-2 shows two situations to avoid in sequencing the VDD and VDDIO, VDDA supplies.
3.3V
VDDIO, VDDA
2
1.8V
Supplies Stable
VDD
1
0
Time
Note: 1. VDD rising before VDDIO, VDDA
2. VDDIO, VDDA rising much faster than VDD
Figure 4-2 Supply Voltage Sequencing and Separation Cautions
VDD should not be allowed to rise early (1). This is usually avoided by running the regulator for the VDD
supply (1.8V) from the voltage generated by the 3.3V VDDIO supply, see Figure 4-3. This keeps VDD from
rising faster than VDDIO.
VDD should not rise so late that a large voltage difference is allowed between the two supplies (2).
Typically this situation is avoided by using external discrete diodes in series between supplies, as shown
in Figure 4-3. The series diodes forward bias when the difference between VDDIO and VDD reaches
approximately 2.1, causing VDD to rise as VDDIO ramps up. When the VDD regulator begins proper
operation, the difference between supplies will typically be 0.8V and conduction through the diode chain
reduces to essentially leakage current. During supply sequencing, the following general relationship
should be adhered to:
VDDIO > VDD > (VDDIO - 2.1V)
In practice, VDDA is typically connected directly to VDDIO with some filtering.
Supply
VDDIO, VDDA
3.3V
Regulator
1.8V
Regulator
VDD
Figure 4-3 Example Circuit to Control Supply Sequencing
56857 Technical Data, Rev. 6
Freescale Semiconductor
25
4.4 AC Electrical Characteristics
Timing waveforms in Section 4.4 are tested with a VIL maximum of 0.8V and a VIH minimum of 2.0V for
all pins except XTAL, which is tested using the input levels in Section 4.2. In Figure 4-4 the levels of VIH
and VIL for an input signal are shown.
Low
VIH
Input Signal
High
90%
50%
10%
Midpoint1
VIL
Fall Time
Rise Time
Note: The midpoint is VIL + (VIH – VIL)/2.
Figure 4-4 Input Signal Measurement References
Figure 4-5 shows the definitions of the following signal states:
•
•
•
Active state, when a bus or signal is driven, and enters a low impedance state
Tri-stated, when a bus or signal is placed in a high impedance state
Data Valid state, when a signal level has reached VOL or VOH
•
Data Invalid state, when a signal level is in transition between VOL and VOH
Data2 Valid
Data1 Valid
Data1
Data3 Valid
Data2
Data3
Data
Tri-stated
Data Invalid State
Data Active
Data Active
Figure 4-5 Signal States
56857 Technical Data, Rev. 6
26
Freescale Semiconductor
External Clock Operation
4.5 External Clock Operation
The 56857 system clock can be derived from a crystal or an external system clock signal. To generate a
reference frequency using the internal oscillator, a reference crystal must be connected between the
EXTAL and XTAL pins.
4.5.1
Crystal Oscillator
The internal oscillator is designed to interface with a parallel-resonant crystal resonator in the frequency
range specified for the external crystal in Table 4-6. In Figure 4-6 a typical crystal oscillator circuit is
shown. Follow the crystal supplier’s recommendations when selecting a crystal, because crystal
parameters determine the component values required to provide maximum stability and reliable start-up.
The crystal and associated components should be mounted as close as possible to the EXTAL and XTAL
pins to minimize output distortion and start-up stabilization time.
Crystal Frequency = 2–4MHz (optimized for 4MHz)
EXTAL XTAL
Rz
Sample External Crystal Parameters:
Rz = 10MΩ
TOD_SEL bit in CGM must be set to 0
Figure 4-6 Crystal Oscillator
4.5.2
High Speed External Clock Source (> 4MHz)
The recommended method of connecting an external clock is given in Figure 4-7. The external clock
source is connected to XTAL and the EXTAL pin is held at ground, VDDA, or VDDA/2. The TOD_SEL bit
in CGM must be set to 0.
56857
XTAL
EXTAL
GND,VDDA,
External
Clock
or VDDA/2
(up to 240MHz)
Figure 4-7 Connecting a High Speed External Clock Signal using XTAL
4.5.3
Low Speed External Clock Source (2-4MHz)
The recommended method of connecting an external clock is given in Figure 4-8. The external clock
source is connected to XTAL and the EXTAL pin is held at VDDA/2. The TOD_SEL bit in CGM must be
set to 0.
56857 Technical Data, Rev. 6
Freescale Semiconductor
27
56857
XTAL
EXTAL
External
Clock
(2-4MHz)
VDDA/2
Figure 4-8 Connecting a Low Speed External Clock Signal using XTAL
Table 4-5 External Clock Operation Timing Requirements4
Operating Conditions: VSS = VSSIO = VSSA = 0 V, VDD = 1.62-1.98V, VDDIO = VDDA = 3.0–3.6V, TA = –40° to +120°C, CL ≤ 50pF, fop = 120MHz
Characteristic
Symbol
Min
Typ
Max
Unit
Frequency of operation (external clock driver)1
fosc
0
—
240
MHz
Clock Pulse Width4
tPW
6.25
—
—
ns
External clock input rise time2, 4
trise
—
—
TBD
ns
External clock input fall time3, 4
tfall
—
—
TBD
ns
1.
See Figure 4-7 for details on using the recommended connection of an external clock driver.
2.
External clock input rise time is measured from 10% to 90%.
3.
External clock input fall time is measured from 90% to 10%.
4.
Parameters listed are guaranteed by design.
VIH
External
Clock
90%
50%
10%
tPW
tPW
90%
50%
10%
tfall
trise
VIL
Note: The midpoint is VIL + (VIH – VIL)/2.
Figure 4-9 External Clock Timing
56857 Technical Data, Rev. 6
28
Freescale Semiconductor
Reset, Stop, Wait, Mode Select, and Interrupt Timing
Table 4-6 PLL Timing
Operating Conditions: VSS = VSSIO = VSSA = 0 V, VDD = 1.62-1.98V, VDDIO = VDDA = 3.0–3.6V, TA = –40° to +120°C, CL ≤ 50pF, fop = 120MHz
Characteristic
Symbol
Min
Typ
Max
Unit
External reference crystal frequency for the PLL1
fosc
2
4
4
MHz
PLL output frequency
fclk
40
—
240
MHz
PLL stabilization time 2
tplls
—
1
10
ms
1. An externally supplied reference clock should be as free as possible from any phase jitter for the PLL to work correctly.
The PLL is optimized for 4MHz input crystal.
2. This is the minimum time required after the PLL setup is changed to ensure reliable operation.
4.6 Reset, Stop, Wait, Mode Select, and Interrupt Timing
Table 4-7 Reset, Stop, Wait, Mode Select, and Interrupt Timing1, 2
Operating Conditions: VSS = VSSIO = VSSA = 0 V, VDD = 1.62-1.98V, VDDIO = VDDA = 3.0–3.6V, TA = –40° to +120°C, CL ≤ 50pF, fop = 120MHz
Symbol
Typ Min
Typ
Max
Unit
See Figure
Minimum RESET Assertion Duration3
tRA
30
—
ns
4-10
Edge-sensitive Interrupt Request Width
tIRW
1T + 3
—
ns
4-11
IRQA, IRQB Assertion to General Purpose Output Valid,
caused by first instruction execution in the interrupt
service routine
tIG
18T
—
ns
4-12
IRQA Width Assertion to Recover from Stop State
tIW
2T
—
ns
4-13
Delay from IRQA Assertion to Fetch of first instruction
(exiting Stop)4
Fast5
Normal6, 7
tIF
Characteristic
RSTO pulse width7
normal operation
internal reset mode
4-13
—
—
13T
25ET
ns
ns
128ET
8ET
—
—
—
—
tRSTO
4-14
1. In the formulas, T = clock cycle. For fop = 120MHz operation and fipb = 60MHz, T = 8.33ns.
2. Parameters listed are guaranteed by design.
3. At reset, the PLL is disabled and bypassed. The part is then put into Run mode and tclk assumes the period of the source clock,
txtal, textal or tosc.
4. This interrupt instruction fetch is visible on the pins only in Mode 3.
5. Fast stop mode:
Fast stop recovery applies when external clocking is in use (direct clocking to XTAL) or when fast stop mode recovery is requested (OMR bit 6 is set to 1). In both cases the PLL and the master clock are unaffected by stop mode entry. Recovery takes one less
cycle and tclk will continue with the same value it had before stop mode was entered.
6. Normal stop mode:
As a power saving feature, normal stop mode disables and bypasses the PLL. Stop mode will then shut down the master clock,
recovery will take an extra cycle (to restart the clock), and tclk will resume at the input clock source rate.
7. ET = External Clock period; for an external crystal frequency of 4MHz, ET=250ns.
56857 Technical Data, Rev. 6
Freescale Semiconductor
29
RESET
tRA
Figure 4-10 Asynchronous Reset Timing
IRQA
IRQB
tIRW
Figure 4-11 External Interrupt Timing (Negative-Edge-Sensitive)
General
Purpose
I/O Pin
tIG
IRQA,
IRQB
b) General Purpose I/O
Figure 4-12 External Level-Sensitive Interrupt Timing
tIW
IRQA
Figure 4-13 Recovery from Stop State Using Asynchronous Interrupt Timing
RESET
tRSTO
Figure 4-14 Reset Output Timing
56857 Technical Data, Rev. 6
30
Freescale Semiconductor
Host Interface Port
4.7 Host Interface Port
Table 4-8 Host Interface Port Timing1
Operating Conditions: VSS = VSSIO = VSSA = 0 V, VDD = 1.62-1.98V, VDDIO = VDDA = 3.0–3.6V, TA = –40° to +120°C, CL ≤ 50pF, fop = 120MHz
Characteristic
Symbol
Min
Max
Unit
See Figure
Access time
TACKDV
—
13
ns
4-19
Disable time
TACKDZ
3
—
ns
4-19
Time to disassert
TACKREQH
3.5
9
ns
4-19
4-22
Lead time
TREQACKL
0
—
ns
4-19
4-22
Access time
TRADV
—
13
Disable time
TRADX
5
—
Disable time
TRADZ
3
—
Setup time
TDACKS
3
Hold time
TACKDH
Setup time
ns
4-20
4-21
ns
4-20
4-21
ns
4-20
4-21
—
ns
4-22
1
—
ns
4-22
TADSS
3
—
ns
4-23
4-24
Hold time
TDSAH
1
—
ns
4-23
4-24
Pulse width
TWDS
5
—
ns
4-23
4-24
TACKREQL
4T + 5
5
5T + 9
13
ns
ns
4-19
4-22
Time to re-assert
1. After second write in 16-bit mode
2. After first write in 16-bit mode
or after write in 8-bit mode
1. The formulas: T = clock cycle. f ipb = 60MHz, T = 16.7ns.
56857 Technical Data, Rev. 6
Freescale Semiconductor
31
HACK
TACKDZ
TACKDV
HD
TREQACKL
TACKREQH
TACKREQL
HREQ
Figure 4-15 Controller-to-Host DMA Read Model
HA
TRADX
HCS
HDS
HRW
TRADV
TRADZ
HD
Figure 4-16 Single Strobe Read Mode
HA
TRADX
HCS
HWR
HRD
TRADZ
HD
TRADV
Figure 4-17 Dual Strobe Read Mode
56857 Technical Data, Rev. 6
32
Freescale Semiconductor
Host Interface Port
HACK
TDACKS
TACKDH
HD
TREQACKL
TACKREQH
TACKREQL
HREQ
Figure 4-18 Host-to-Controller DMA Write Mode
HA
TDSAH
HCS
TWDS
HDS
TDSAH
HRW
TADSS
TADSS
TDSAH
HD
Figure 4-19 Single Strobe Write Mode
HA
HCS
TWDS
HWR
TDSAH
TADSS
HRD
TADSS
HD
Figure 4-20 Dual Strobe Write Mode
56857 Technical Data, Rev. 6
Freescale Semiconductor
33
4.8 Serial Peripheral Interface (SPI) Timing
Table 4-9 SPI Timing 1
Operating Conditions: VSS = VSSIO = VSSA = 0 V, VDD = 1.62-1.98V, VDDIO = VDDA = 3.0–3.6V, TA = –40° to +120°C, CL ≤ 50pF, fop = 120MHz
Characteristic
Symbol
Cycle time
Master
Slave
tC
Enable lead time
Master
Slave
tELD
Enable lag time
Master
Slave
tELG
Clock (SCLK) high time
Master
Slave
tCH
Clock (SCLK) low time
Master
Slave
tCL
Data set-up time required for inputs
Master
Slave
tDS
Data hold time required for inputs
Master
Slave
tDH
Access time (time to data active from high-impedance state)
Slave
tA
Disable time (hold time to high-impedance state)
Slave
tD
Data valid for outputs
Master
Slave (after enable edge)
tDV
Data invalid
Master
Slave
tDI
Rise time
Master
Slave
tR
Fall time
Master
Slave
tF
See
Figure
Min
Max
Unit
25
25
—
—
ns
ns
—
12.5
—
—
ns
ns
—
12.5
—
—
ns
ns
9
12.5
—
—
12
12.5
—
—
ns
ns
10
2
—
—
ns
ns
0
2
—
—
ns
ns
5
15
ns
ns
4-24
2
9
ns
ns
4-24
—
—
2
14
ns
ns
0
0
—
—
ns
ns
—
—
11.5
10.0
ns
ns
—
—
9.7
9.0
ns
ns
ns
ns
4-21, 4-22,
4-23, 4-24
4-24
4-24
4-21, 4-22,
4-23, 4-24
4-24
4-21, 4-22,
4-23, 4-24
4-21, 4-22,
4-23, 4-24
4-21, 4-22,
4-23, 4-24
4-21, 4-22,
4-23, 4-24
4-21, 4-22,
4-23, 4-24
4-21, 4-22,
4-23, 4-24
1. Parameters listed are guaranteed by design.
56857 Technical Data, Rev. 6
34
Freescale Semiconductor
Serial Peripheral Interface (SPI) Timing
SS
SS is held High on master
(Input)
tC
tR
tF
tCL
SCLK (CPOL = 0)
(Output)
tCH
tF
tR
tCL
SCLK (CPOL = 1)
(Output)
tDH
tDS
tCH
MISO
(Input)
tCH
MSB in
Bits 14–1
tDI(ref)
tDV
tDI
MOSI
(Output)
LSB in
Master MSB out
Bits 14–1
Master LSB out
tR
tF
Figure 4-21 SPI Master Timing (CPHA = 0)
SS
(Input)
SS is held High on master
tC
tF
SCLK (CPOL = 0)
(Output)
tCH
tF
tCL
SCLK (CPOL = 1)
(Output)
tCH
MISO
(Input)
MSB in
tDS
tR
tDH
Bits 14–1
tDI
tDV(ref)
MOSI
(Output)
tR
tCL
Master MSB out
LSB in
tDV
Bits 14– 1
tF
Master LSB out
tR
Figure 4-22 SPI Master Timing (CPHA = 1)
56857 Technical Data, Rev. 6
Freescale Semiconductor
35
SS
(Input)
tC
tF
tR
tCL
SCLK (CPOL = 0)
(Input)
tELG
tCH
tELD
tCL
SCLK (CPOL = 1)
(Input)
tA
tCH
MISO
(Output)
Slave MSB out
tDS
tDH
MOSI
(Input)
MSB in
tF
tR
tD
Bits 14–1
Slave LSB out
tDV
tDI
Bits 14–1
tDI
LSB in
Figure 4-23 SPI Slave Timing (CPHA = 0)
SS
(Input)
tF
tC
tR
tCL
SCLK (CPOL = 0)
(Input)
tCH
tELG
tELD
SCLK (CPOL = 1)
(Input)
tCL
tDV
tA
MISO
(Output)
tF
tCH
Slave MSB out
tR
Bits 14–1
tDV
tDS
tD
Slave LSB out
tDI
tDH
MOSI
(Input)
MSB in
Bits 14–1
LSB in
Figure 4-24 SPI Slave Timing (CPHA = 1)
56857 Technical Data, Rev. 6
36
Freescale Semiconductor
Quad Timer Timing
4.9 Quad Timer Timing
Table 4-10 Quad Timer Timing1, 2
Operating Conditions: VSS = VSSIO = VSSA = 0 V, VDD = 1.62-1.98V, VDDIO = VDDA = 3.0–3.6V, TA = –40° to +120°C, CL ≤ 50pF, fop = 120MHz
Characteristic
Symbol
Min
Max
Unit
PIN
2T + 3
—
ns
Timer input high/low period
PINHL
1T + 3
—
ns
Timer output period
POUT
2T - 3
—
ns
POUTHL
1T - 3
—
ns
Timer input period
Timer output high/low period
1. In the formulas listed, T = clock cycle. For fop = 120MHz operation and fipb = 60MHz, T = 8.33ns.
2. Parameters listed are guaranteed by design.
Timer Inputs
PIN
PINHL
PINHL
POUT
POUTHL
POUTHL
Timer Outputs
Figure 4-25 Timer Timing
4.10 Enhanced Synchronous Serial Interface (ESSI) Timing
Table 4-11 ESSI Master Mode1 Switching Characteristics
Operating Conditions: VSS = VSSIO = VSSA = 0 V, VDD = 1.62-1.98V, VDDIO = VDDA = 3.0–3.6V, TA = –40° to +120°C, CL ≤ 50pF, fop = 120MHz
Parameter
Symbol
Min
Typ
fs
—
SCK period3
tSCKW
SCK high time
SCK low time
SCK frequency
Output clock rise/fall time
Max
Units
—
152
MHz
66.7
—
—
ns
tSCKH
33.44
—
—
ns
tSCKL
33.44
—
—
ns
—
—
4
—
ns
56857 Technical Data, Rev. 6
Freescale Semiconductor
37
Table 4-11 ESSI Master Mode1 Switching Characteristics (Continued)
Operating Conditions: VSS = VSSIO = VSSA = 0 V, VDD = 1.62-1.98V, VDDIO = VDDA = 3.0–3.6V, TA = –40° to +120°C, CL ≤ 50pF, fop = 120MHz
Parameter
Symbol
Min
Typ
Max
Units
Delay from SCK high to SC2 (bl) high - Master5
tTFSBHM
-1.0
—
1.0
ns
Delay from SCK high to SC2 (wl) high - Master5
tTFSWHM
-1.0
—
1.0
ns
Delay from SC0 high to SC1 (bl) high - Master5
tRFSBHM
-1.0
—
1.0
ns
Delay from SC0 high to SC1 (wl) high - Master5
tRFSWHM
-1.0
—
1.0
ns
Delay from SCK high to SC2 (bl) low - Master5
tTFSBLM
-1.0
—
1.0
ns
Delay from SCK high to SC2 (wl) low - Master5
tTFSWLM
-1.0
—
1.0
ns
Delay from SC0 high to SC1 (bl) low - Master5
tRFSBLM
-1.0
—
1.0
ns
Delay from SC0 high to SC1 (wl) low - Master5
tRFSWLM
-1.0
—
1.0
ns
SCK high to STD enable from high impedance - Master
tTXEM
-0.1
—
2
ns
SCK high to STD valid - Master
tTXVM
-0.1
—
2
ns
SCK high to STD not valid - Master
tTXNVM
-0.1
—
—
ns
SCK high to STD high impedance - Master
tTXHIM
-4
—
0
ns
SRD Setup time before SC0 low - Master
tSM
4
—
—
ns
SRD Hold time after SC0 low - Master
tHM
4
—
—
ns
Synchronous Operation (in addition to standard internal clock parameters)
SRD Setup time before SCK low - Master
tTSM
4
—
—
ns
SRD Hold time after SCK low - Master
tTHM
4
—
—
ns
1. Master mode is internally generated clocks and frame syncs
2. Max clock frequency is IP_clk/4 = 60MHz / 4 = 15MHz for an 120MHz part.
3. All the timings for the ESSI are given for a non-inverted serial clock polarity (TSCKP=0 in SCR2 and RSCKP=0 in SCSR)
and a non-inverted frame sync (TFSI=0 in SCR2 and RFSI=0 in SCSR). If the polarity of the clock and/or the frame sync
have been inverted, all the timings remain valid by inverting the clock signal SCK/SC0 and/or the frame sync SC2/SC1 in
the tables and in the figures.
4. 50 percent duty cycle
5. bl = bit length; wl = word length
56857 Technical Data, Rev. 6
38
Freescale Semiconductor
Enhanced Synchronous Serial Interface (ESSI) Timing
tSCKH
tSCKW
tSCKL
SCK output
tTFSBHM
tTFSBLM
SC2 (bl) output
tTFSWHM
tTFSWLM
SC2 (wl) output
tTXVM
tTXEM
tTXNVM
tTXHIM
First Bit
STD
Last Bit
SC0 output
tRFSBHM
tRFBLM
SC1 (bl) output
tRFSWHM
tRFSWLM
SC1 (wl) output
tSM
tHM
tTSM
tTHM
SRD
Figure 4-26 Master Mode Timing Diagram
Table 4-12 ESSI Slave Mode1 Switching Characteristics
Operating Conditions: VSS = VSSIO = VSSA = 0 V, VDD = 1.62-1.98V, VDDIO = VDDA = 3.0–3.6V, TA = –40° to +120°C, CL ≤ 50pF, fop = 120MHz
Parameter
Symbol
Min
Typ
Max
Units
fs
—
—
152
MHz
SCK period3
tSCKW
66.7
—
—
ns
SCK high time
tSCKH
33.44
—
—
ns
SCK low time
tSCKL
33.44
—
—
ns
—
—
4
—
ns
Delay from SCK high to SC2 (bl) high - Slave5
tTFSBHS
-1
—
29
ns
Delay from SCK high to SC2 (wl) high - Slave5
tTFSWHS
-1
—
29
ns
SCK frequency
Output clock rise/fall time
56857 Technical Data, Rev. 6
Freescale Semiconductor
39
Table 4-12 ESSI Slave Mode1 Switching Characteristics (Continued)
Operating Conditions: VSS = VSSIO = VSSA = 0 V, VDD = 1.62-1.98V, VDDIO = VDDA = 3.0–3.6V, TA = –40° to +120°C, CL ≤ 50pF, fop = 120MHz
Parameter
Symbol
Min
Typ
Max
Units
Delay from SC0 high to SC1 (bl) high - Slave5
tRFSBHS
-1
—
29
ns
Delay from SC0 high to SC1 (wl) high - Slave5
tRFSWHS
-1
—
29
ns
Delay from SCK high to SC2 (bl) low - Slave5
tTFSBLS
-29
—
29
ns
Delay from SCK high to SC2 (wl) low - Slave5
tTFSWLS
-29
—
29
ns
Delay from SC0 high to SC1 (bl) low - Slave5
tRFSBLS
-29
—
29
ns
Delay from SC0 high to SC1 (wl) low - Slave5
tRFSWLS
-29
—
29
ns
SCK high to STD enable from high impedance - Slave
tTXES
—
—
15
ns
SCK high to STD valid - Slave
tTXVS
4
—
15
ns
SC2 high to STD enable from high impedance (first bit) - Slave
tFTXES
4
—
15
ns
SC2 high to STD valid (first bit) - Slave
tFTXVS
4
—
15
ns
SCK high to STD not valid - Slave
tTXNVS
4
—
15
ns
SCK high to STD high impedance - Slave
tTXHIS
4
—
15
ns
SRD Setup time before SC0 low - Slave
tSS
4
—
—
ns
SRD Hold time after SC0 low - Slave
tHS
4
—
—
ns
Synchronous Operation (in addition to standard external clock parameters)
SRD Setup time before SCK low - Slave
tTSS
4
—
—
ns
SRD Hold time after SCK low - Slave
tTHS
4
—
—
ns
1. Slave mode is externally generated clocks and frame syncs
2. Max clock frequency is IP_clk/4 = 60MHz / 4 = 15MHz for a 120MHz part.
3. All the timings for the ESSI are given for a non-inverted serial clock polarity (TSCKP=0 in SCR2 and RSCKP=0 in SCSR)
and a non-inverted frame sync (TFSI=0 in SCR2 and RFSI=0 in SCSR). If the polarity of the clock and/or the frame sync
have been inverted, all the timings remain valid by inverting the clock signal SCK/SC0 and/or the frame sync SC2/SC1 in
the tables and in the figures.
4. 50 percent duty cycle
5. bl = bit length; wl = word length
56857 Technical Data, Rev. 6
40
Freescale Semiconductor
Serial Communication Interface (SCI) Timing
tSCKW
tSCKH
tSCKL
SCK input
tTFSBLS
tTFSBHS
SC2 (bl) input
tTFSWHS
tTFSWLS
SC2 (wl) input
tFTXVS
tFTXES
tTXNVS
tTXVS
tTXES
tTXHIS
First Bit
STD
SC0 input
Last Bit
tRFBLS
tRFSBHS
SC1 (bl) input
tRFSWHS
tRFSWLS
SC1 (wl) input
tSS
tTSS
tHS
tTHS
SRD
Figure 4-27 Slave Mode Clock Timing
4.11 Serial Communication Interface (SCI) Timing
Table 4-13 SCI Timing4
Operating Conditions: VSS = VSSIO = VSSA = 0 V, VDD = 1.62-1.98V, VDDIO = VDDA = 3.0–3.6V, TA = –40° to +120°C, CL ≤ 50pF, fop = 120MHz
Characteristic
Symbol
Min
Max
Unit
BR
—
(fMAX)/(32)
Mbps
RXD2 Pulse Width
RXDPW
0.965/BR
1.04/BR
ns
TXD3 Pulse Width
TXDPW
0.965/BR
1.04/BR
ns
Baud Rate1
1. fMAX is the frequency of operation of the system clock in MHz.
2. The RXD pin in SCI0 is named RXD0 and the RXD pin in SCI1 is named RXD1.
3. The TXD pin in SCI0 is named TXD0 and the TXD pin in SCI1 is named TXD1.
4. Parameters listed are guaranteed by design.
56857 Technical Data, Rev. 6
Freescale Semiconductor
41
RXD
SCI receive
data pin
(Input)
RXDPW
Figure 4-28 RXD Pulse Width
TXD
SCI receive
data pin
(Input)
TXDPW
Figure 4-29 TXD Pulse Width
4.12 JTAG Timing
Table 4-14 JTAG Timing1, 3
Operating Conditions: VSS = VSSIO = VSSA = 0 V, VDD = 1.62-1.98V, VDDIO = VDDA = 3.0–3.6V, TA = –40° to +120°C, CL ≤ 50pF, fop = 120MHz
Characteristic
Symbol
Min
Max
Unit
TCK frequency of operation2
fOP
DC
30
MHz
TCK cycle time
tCY
33.3
—
ns
TCK clock pulse width
tPW
16.6
—
ns
TMS, TDI data setup time
tDS
3
—
ns
TMS, TDI data hold time
tDH
3
—
ns
TCK low to TDO data valid
tDV
—
12
ns
TCK low to TDO tri-state
tTS
—
10
ns
tTRST
35
—
ns
tDE
4T
—
ns
TRST assertion time
DE assertion time
1. Timing is both wait state and frequency dependent. For the values listed, T = clock cycle. For 120MHz
operation, T = 8.33ns.
2.
TCK frequency of operation must be less than 1/4 the processor rate.
3.
Parameters listed are guaranteed by design.
56857 Technical Data, Rev. 6
42
Freescale Semiconductor
JTAG Timing
tCY
tPW
tPW
VIH
VM
TCK
(Input)
VM
VIL
VM = VIL + (VIH – VIL)/2
Figure 4-30 Test Clock Input Timing Diagram
TCK
(Input)
tDS
TDI
TMS
(Input)
tDH
Input Data Valid
tDV
TDO
(Output)
Output Data Valid
tTS
TDO
(Output)
tDV
TDO
(Output)
Output Data Valid
Figure 4-31 Test Access Port Timing Diagram
TRST
(Input)
tTRST
Figure 4-32 TRST Timing Diagram
DE
tDE
Figure 4-33 Enhanced OnCE—Debug Event
56857 Technical Data, Rev. 6
Freescale Semiconductor
43
4.13 GPIO Timing
Table 4-15 GPIO Timing1, 2
Operating Conditions: VSS = VSSIO = VSSA = 0 V, VDD = 1.62-1.98V, VDDIO = VDDA = 3.0–3.6V, TA = –40° to +120°C, CL ≤ 50pF, fop = 120MHz
Characteristic
Symbol
Min
Max
Unit
PIN
2T + 3
—
ns
GPIO input high/low period
PINHL
1T + 3
—
ns
GPIO output period
POUT
2T - 3
—
ns
POUTHL
1T - 3
—
ns
GPIO input period
GPIO output high/low period
1. In the formulas listed, T = clock cycle. For fop = 120MHz operation and fipb = 60MHz, T = 8.33ns
2. Parameters listed are guaranteed by design.
GPIO Inputs
PIN
PINHL
PINHL
POUT
POUTHL
POUTHL
GPIO Outputs
Figure 4-34 GPIO Timing
56857 Technical Data, Rev. 6
44
Freescale Semiconductor
Package and Pin-Out Information 56857
Part 5 Packaging
5.1 Package and Pin-Out Information 56857
PIN 1
ORIENTATION
MARK
PIN 51
PIN 26
CLKO
RSTO
RESET
HD3
HD4
HD5
HD6
HD7
VDDIO
VSSIO
VDD
VSS
VSS
IRQA
IRQB
VDDA
VSSA
VSSA
XTAL
EXTAL
HD0
HD1
HD2
VDD
PIN 76
TXD1
RXD1
VSSIO
VDDIO
SC12
SC11
SC10
SCK1
SRD1
STD1
HRWB
HA2
HA1
HA0
VSS
VDD
VDD
CS3
CS2
CS1
CS0
VSSIO
VDDIO
TXDO
RXD0
DE
TRST
TDO
TDI
TMS
TCK
VDDIO
VSSIO
VDDIO
VDDIO
VSSIO
VDD
MISO
MOSI
SCK
SS
VDDIO
VDDIO
VSSIO
VDD
VSS
MODA
MODB
MODC
VDDIO
VSSIO
HACK
HREQ
HCS
HDS
VSSIO
TIO0
VDDIO
TIO1
TIO2
TIO3
ESD
VSSIO
ESD
VDDIO
SC02
SC01
SC00
SCK0
SRD0
STD0
VSSIO
VDDIO
ESD
VSS
VDD
This section contains package and pin-out information for the 100-pin LQFP configuration of the 56857.
Figure 5-1 Top View, 56857 100-pin LQFP Package
56857 Technical Data, Rev. 6
Freescale Semiconductor
45
Table 5-1 56857 Pin Identification By Pin Number
Pin No.
Signal Name
Pin No.
Signal Name
Pin No.
Signal Name
Pin No.
Signal Name
1
MISO
26
CLKO
51
RXD0
76
VDD
2
MOSI
27
RSTO
52
TXD0
77
TIO3
3
SCK
28
RESET
53
VDDIO
78
TIO2
4
SS
29
HD3
54
VSSIO
79
TIO1
5
VDDIO
30
HD4
55
CS0
80
VDDIO
6
VDDIO
31
HD5
56
CS1
81
TIO0
7
VSSIO
32
HD6
57
CS2
82
VSSIO
8
VDD
33
HD7
58
CS3
83
HDS
9
VSS
34
VDDIO
59
VDD
84
HCS
10
MODA
35
VSSIO
60
VDD
85
HREQ
11
MODB
36
VDD
61
VSS
86
HACK
12
MODC
37
VSS
62
HA0
87
VDD
13
VDDIO
38
VSS
63
HA1
88
VSS
14
VSSIO
39
DE
64
HA2
89
VSSIO
15
IRQA
40
TRST
65
HRWB
90
VDDIO
16
IRQB
41
TDO
66
STD1
91
VSSIO
17
VDDA
42
TDI
67
SRD1
92
STD0
18
VSSA
43
TMS
68
SCK1
93
SRD0
19
VSSA
44
TCK
69
SC10
94
SCK0
20
XTAL
45
VDDIO
70
SC11
95
SC00
21
EXTAL
46
VSSIO
71
SC12
96
SC01
22
HD0
47
VDDIO
72
VDDIO
97
SC02
23
HD1
48
VDDIO
73
VSSIO
98
VDDIO
24
HD2
49
VSSIO
74
RXD1
99
VSSIO
25
VDD
50
VDD
75
TXD1
100
VSSIO
56857 Technical Data, Rev. 6
46
Freescale Semiconductor
Package and Pin-Out Information 56857
S
0.15 (0.006)S
AC T-U
Z
S
S
-T-
AC Z
B
-Z-
0.15
0.15 (0.006)S
(0.006)S
V
AC Z
S
S
T-U
T-U
S
S
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DATUM PLANE -AB- IS LOCATED AT BOTTOM
OF LEAD AND IS COINCIDENT WITH THE
LEAD WHERE THE LEAD EXITS THE PLASTIC
BODY AT THE BOTTOM OF THE PARTING
LINE.
4. DATUMS -T-, -U-, AND -Z- TO BE DETERMINED
AT DATUM PLANE -AB-.
5. DIMENSIONS S AND V TO BE DETERMINED
AT SEATING PLANE -AC-.
6. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION. ALLOWABLE
PROTRUSION IS 0.250 (0.010) PER SIDE.
DIMENSIONS A AND B DO INCLUDE MOLD
MISMATCH AND ARE DETERMINED AT
DATUM PLANE -AB-.
7. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. DAMBAR PROTRUSION SHALL
NOT CAUSE THE D DIMENSION TO EXCEED
0.350 (0.014). DAMBAR CAN NOT BE LOCATED
ON THE LOWER RADIUS OR THE FOOT.
MINIMUM SPACE BETWEEN PROTRUSION
AND AN ADJACENT LEAD IS 0.070 (0.003).
8. MINIMUM SOLDER PLATE THICKNESS
SHALL BE 0.0076 (0.003).
9. EXACT SHAPE OF EACH CORNER MAY VARY
FROM DEPICTION.
-UA
9
0.15
(0.006)S
AB T-U
S
AE
Z
MILLIMETERS INCHES
DIM MIN MAX MIN MAX
A 13.950 14.050 0.549 0.553
B 13.950 14.050 0.549 0.553
C
1.400 1.600 0.055 0.063
D
0.170 0.270 0.007 0.011
E
1.350 1.450 0.053 0.057
F
0.170 0.230 0.007 0.009
G
0.500 BSC
0.020 BSC
H 0.050 0.150 0.002 0.006
J
0.090 0.200 0.004 0.008
K 0.500 0.700 0.020 0.028
M
12° REF
12° REF
N
0.090 0.160 0.004 0.006
Q
1°
5°
1°
5°
R
0.150 0.250 0.006 0.010
S 15.950 16.050 0.628 0.632
V 15.950 16.050 0.628 0.632
W
0.200 REF
0.008 REF
X
1.000 REF
0.039 REF
S
AD
-AB-AC96X
G
SEATING
PLANE
(24X PER SIDE)
AE
0.100 (0.004) AC
M°
C
R
0.25 (0.010)
E
GAUGE PLANE
D
F
J
N
H
W
Q°
K
X
0.20 (0.008)M AC T-U
S
Z
S
SECTION AE-AE
DETAIL AD
Figure 5-2 100-pin LQPF Mechanical Information
Please see www.freescale.com for the most current case outline.
56857 Technical Data, Rev. 6
Freescale Semiconductor
47
Part 6 Design Considerations
6.1 Thermal Design Considerations
An estimation of the chip junction temperature, TJ, in °C can be obtained from the equation:
Equation 1:
TJ = TA + (PD x RθJA)
Where:
TA = ambient temperature °C
RθJA = package junction-to-ambient thermal resistance °C/W
PD = power dissipation in package
Historically, thermal resistance has been expressed as the sum of a junction-to-case thermal resistance and
a case-to-ambient thermal resistance:
Equation 2:
RθJA = RθJC + RθCA
Where:
RθJA = package junction-to-ambient thermal resistance °C/W
RθJC = package junction-to-case thermal resistance °C/W
RθCA = package case-to-ambient thermal resistance °C/W
RθJC is device-related and cannot be influenced by the user. The user controls the thermal environment to
change the case-to-ambient thermal resistance, RθCA. For example, the user can change the air flow around
the device, add a heat sink, change the mounting arrangement on the Printed Circuit Board (PCB), or
otherwise change the thermal dissipation capability of the area surrounding the device on the PCB. This
model is most useful for ceramic packages with heat sinks; some 90% of the heat flow is dissipated through
the case to the heat sink and out to the ambient environment. For ceramic packages, in situations where
the heat flow is split between a path to the case and an alternate path through the PCB, analysis of the
device thermal performance may need the additional modeling capability of a system level thermal
simulation tool.
The thermal performance of plastic packages is more dependent on the temperature of the PCB to which
the package is mounted. Again, if the estimations obtained from RθJA do not satisfactorily answer whether
the thermal performance is adequate, a system level model may be appropriate.
A complicating factor is the existence of three common definitions for determining the junction-to-case
thermal resistance in plastic packages:
•
•
•
Measure the thermal resistance from the junction to the outside surface of the package (case) closest to the
chip mounting area when that surface has a proper heat sink. This is done to minimize temperature variation
across the surface.
Measure the thermal resistance from the junction to where the leads are attached to the case. This definition
is approximately equal to a junction to board thermal resistance.
Use the value obtained by the equation (TJ – TT)/PD where TT is the temperature of the package case
determined by a thermocouple.
56857 Technical Data, Rev. 6
48
Freescale Semiconductor
Electrical Design Considerations
As noted above, the junction-to-case thermal resistances quoted in this data sheet are determined using the
first definition. From a practical standpoint, that value is also suitable for determining the junction
temperature from a case thermocouple reading in forced convection environments. In natural convection,
using the junction-to-case thermal resistance to estimate junction temperature from a thermocouple
reading on the case of the package will estimate a junction temperature slightly hotter than actual. Hence,
the new thermal metric, Thermal Characterization Parameter, or ΨJT, has been defined to be (TJ – TT)/PD.
This value gives a better estimate of the junction temperature in natural convection when using the surface
temperature of the package. Remember that surface temperature readings of packages are subject to
significant errors caused by inadequate attachment of the sensor to the surface and to errors caused by heat
loss to the sensor. The recommended technique is to attach a 40-gauge thermocouple wire and bead to the
top center of the package with thermally conductive epoxy.
6.2 Electrical Design Considerations
CAUTION
This device contains protective circuitry to guard against
damage due to high static voltage or electrical fields.
However, normal precautions are advised to avoid
application of any voltages higher than maximum rated
voltages to this high-impedance circuit. Reliability of
operation is enhanced if unused inputs are tied to an
appropriate voltage level.
Use the following list of considerations to assure correct operation:
•
Provide a low-impedance path from the board power supply to each VDD pin on the controller, and from the
board ground to each VSS (GND) pin.
•
The minimum bypass requirement is to place six 0.01–0.1 μF capacitors positioned as close as possible to
the package supply pins. The recommended bypass configuration is to place one bypass capacitor on each
of the ten VDD/VSS pairs, including VDDA/VSSA.
•
Ensure that capacitor leads and associated printed circuit traces that connect to the chip VDD and VSS (GND)
pins are less than 0.5 inch per capacitor lead.
Use at least a four-layer Printed Circuit Board (PCB) with two inner layers for VDD and GND.
•
•
•
Bypass the VDD and GND layers of the PCB with approximately 100 μF, preferably with a high-grade
capacitor such as a tantalum capacitor.
Because the device’s output signals have fast rise and fall times, PCB trace lengths should be minimal.
Consider all device loads as well as parasitic capacitance due to PCB traces when calculating capacitance.
This is especially critical in systems with higher capacitive loads that could create higher transient currents
in the VDD and GND circuits.
•
All inputs must be terminated (i.e., not allowed to float) using CMOS levels.
•
56857 Technical Data, Rev. 6
Freescale Semiconductor
49
•
Take special care to minimize noise levels on the VDDA and VSSA pins.
•
•
When using Wired-OR mode on the SPI or the IRQx pins, the user must provide an external pull-up device.
Designs that utilize the TRST pin for JTAG port or Enhance OnCE module functionality (such as
development or debugging systems) should allow a means to assert TRST whenever RESET is asserted, as
well as a means to assert TRST independently of RESET. Designs that do not require debugging
functionality, such as consumer products, should tie these pins together.
The internal POR (Power on Reset) will reset the part at power on with reset asserted or pulled high but
requires that TRST be asserted at power on.
•
56857 Technical Data, Rev. 6
50
Freescale Semiconductor
Electrical Design Considerations
Part 7 Ordering Information
Table 7-1 lists the pertinent information needed to place an order. Consult a Freescale Semiconductor
sales office or authorized distributor to determine availability and to order parts.
Table 7-1 56857 Ordering Information
Part
Supply
Voltage
DSP56857
1.8V, 3.3V
DSP56857
1.8V, 3.3V
Pin
Count
Frequency
(MHz)
Order Number
Low-Profile Quad Flat Pack (LQFP)
100
120
DSP56857BU120
Low-Profile Quad Flat Pack (LQFP)
100
120
DSP56857BUE *
Package Type
*This package is RoHS compliant.
56857 Technical Data, Rev. 6
Freescale Semiconductor
51
56857 Technical Data, Rev. 6
52
Freescale Semiconductor
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This product incorporates SuperFlash® technology licensed from SST.
© Freescale Semiconductor, Inc. 2005. All rights reserved.
DSP56857
Rev. 6
01/2007