ETC2 AN221D04-DEVLP Dynamically reconfigurable fpaa with enhanced i/o Datasheet

AN221E04 Datasheet
Dynamically Reconfigurable FPAA
With Enhanced I/O
www.anadigm.com
DS030100-U006a
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Disclaimer
Anadigm reserves the right to make any changes without further notice to any products herein. Anadigm makes no
warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does
Anadigm assume any liability arising out of the application or use of any product or circuit, and specifically disclaims
any and all liability, including with out limitation consequential or incidental damages. "Typical" parameters can and
do vary in different applications. All operating parameters, including "Typicals" must be validated for each customer
application by customer's technical experts. Anadigm does not in this document convey any license under its patent
rights nor the rights of others. Anadigm software and associated products cannot be used except strictly in
accordance with an Anadigm software license. The terms of the appropriate Anadigm software license shall prevail
over the above terms to the extent of any inconsistency.
© Anadigm® Ltd. 2003
© Anadigm®, Inc. 2003
All Rights Reserved.
DS030100-U006a
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AN221E04 Datasheet – Dynamically Reconfigurable FPAA With Enhanced I/O
PRODUCT AND ARCHITECTURE OVERVIEW
The AN221E04 device consists of a 2x2 matrix of fully
Configurable Analog Blocks (CABs), surrounded by a fabric of
programmable interconnect resources. Configuration data is
stored in an on-chip SRAM configuration memory. Compared
with the first-generation FPAAs, the Anadigmvortex architecture
provides a significantly improved signal-to-noise ratio as well as
higher bandwidth. These devices also accommodate nonlinear
functions such as sensor response linearization and arbitrary
waveform synthesis.
The AN221E04 device features an advanced input/output
structure that allows the FPAA to be programmed with up to six
outputs – or triple the number provided by the ANx20E04
devices. The AN221E04 devices have four configurable I/O cells
and two dedicated output cells. For I/O-intensive applications, this
means a single FPAA can now be used to process multiple
channels of analog signals where two or more such devices were
previously needed.
In addition, the AN221E04 devices allow designers to implement
an integrated 8-bit analog-to-digital converter on the FPAA,
eliminating the potential need for an external converter. Using this
new device, designers can route the digital output of the A/D
converter off-chip using one of the dedicated output cells.
PRODUCT FEATURES
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Dynamic reconfiguration
Four configurable I/O cells, two dedicated output cells
8-bit SAR analog–to–digital converter
Fully differential architecture
Fully differential I/O buffering with options for single ended
to differential conversion
Low input offset through chopper stabilized amplifiers
256 Byte Look-Up Table (LUT) for linearization and
arbitrary signal generation
4:1 Input multiplexer
Typical Signal Bandwidth: DC-2MHz (Bandwidth is CAM
dependent)
Signal to Noise Ratio:
o
Broadband 80dB
o
Narrowband (audio) 100dB
Total Harmonic Distortion (THD): 80dB
DC offset <100µV
Package: 44-pin QFP (10x10x2mm)
o
Lead pitch 0.8mm
Supply voltage: 5V
Figure 1: Architectural overview of the AN221E04 device
With dynamic reconfigurability, the functionality of the
AN221E04 can be reconfigured in-system by the designer or
on-the-fly by a microprocessor. A single AN221E04 can thus
be programmed to implement multiple analog functions
and/or to adapt on-the-fly to maintain precision operation
despite system degradation and aging.
APPLICATIONS
•
•
•
•
•
•
•
•
•
•
Real-time software control of analog system peripherals
Intelligent sensors
Adaptive filtering and control
Adaptive DSP front-end
Adaptive industrial control and automation
Self-calibrating systems
Compensation for aging of system components
Dynamic recalibration of remote systems
Ultra-low frequency signal conditioning
Custom analog signal processing
ORDERING CODES
AN221E04-QFPSP
AN221E04-QFPTY
AN221E04-QFPTR
AN221D04-EVAL
AN221D04-DEVLP
Dynamically reconfigurable FPAA
Sample Pack
Dynamically reconfigurable FPAA
Tray (96 pcs)
Dynamically reconfigurable FPAA
Tape & Reel (1000 pcs)
AN221E04 Evaluation Kit
AN221E04 Development Kit
[For more detailed information on the features of the AN221E04 device,
please refer to the AN121E04/AN221E04 User Manual]
DS030100-U006a
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AN221E04 Datasheet – Dynamically Reconfigurable FPAA With Enhanced I/O
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
Parameter
DC Power Supplies
Symbol
Min
Typ
Max
Unit
AVDD(2)
BVDD
DVDD
-0.5
-
5.5 V
V
0.5
V
xVDD to xVDD Offset
Package Power Dissipation
Analog and Digital Input Voltage
Ambient Operating Temperature
Storage Temperature
a
-0.5
Pmax 25°C
Pmax 85°C
Vinmax
Top
Tstg
-
-
Vss-0.5
-40
-65
-
1.8
0.73
Vdd+0.5
85
150
W
Comment
AVSS, BVSS, DVSS and SVSS all
held to 0.0 V a
Ideally all supplies should be at the
same voltage
Still air, No heatsink, 4 layer board,
44 pins. θja = 55°C/W
V
°C
°C
Absolute Maximum DC Power Supply Rating - The failure mode is non-catastrophic for Vdd of up to 7 volts, but will cause reduced
operating life time. The additional stress caused by higher local electric fields within the CMOS circuitry may induce metal migration,
oxide leakage and other time/quality related issues.
Recommended Operating Conditions
Parameter
Symbol
Min
Typ
Max
Unit
AVDD(2)
BVDD
DVDD
4.75
5.00
5.25
V
Analog Input Voltage.
Vina
VMR-1.9
Digital Input Voltage
Junction Temp
Vind
Tj
DC Power Supplies
b
0
-40
Comment
AVSS, BVSS, DVSS and SVSS all
held to 0 V
-
VMR+1.9
V
VMR is 2.0 volts above AVSS
-
DVDD
125
V
°C
Assume a package θja = 55°C/W b
In order to calculate the junction temperature you must first empirically determine the current draw (total Idd) for the design. Once the
current consumption established then the following formula can be used; Tj = Ta + Idd x Vdd x 55 °C/W, where Ta is the ambient
temperature. The worst case θja of 55 °C/W assumes no air flow and no additional heatsink of any type.
General Digital I/O Characteristics (Vdd = 5v +/- 10%, -40 to 85 deg.C)
Parameter
Input Voltage Low
Input Voltage High
Output Voltage Low
Output Voltage High
Input Leakage Current
Input Leakage Current
Max. Capacitive Load
Min. Resistive Load
DCLK Frequency
ACLK Frequency
Clock Duty Cycle
Symbol
Min
Typ
Max
Unit
Vih
Vil
Vol
Voh
Iil
0
70
0
80
-
-
30
100
20
100
±1.0
µA
Iil
-
±12.0
-
µA
Cmax
-
-
10
pF
Rmin
10
-
-
Kohm
Fmax
-
-
40
MHz
Fmax
-
-
40
MHz
-
45
-
55
%
Comment
% of DVDD
% of DVDD
% of DVDD
% of DVDD
All pins except DCLK
DCLK if a crystal is connected and
the on-chip oscillator is used
The maximum load for a digital
output is 10 pF // 10 Kohm
The maximum load for a digital
output is 10 pF // 10 Kohm
For MODE = 1, Max DCLK is
16 MHz
Divide down to <8 MHz prior to use
as a CAB clock
All clocks
DS030100-U006a
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AN221E04 Datasheet – Dynamically Reconfigurable FPAA With Enhanced I/O
Detailed Digital I/O Interface Characteristics: Vdd = 5.0volts
LCCb
Parameter
Symbol
Min
Typ
Max
Unit
Comment
Output Voltage Low
Output Voltage High
Max. Capacitive Load
Min. Resistive Load
Current Sink
Current Source
Vol
Voh
Cmax
Rmin
Isnkmax
Isrcmax
Vss
4.5
50
-
-
150
Vdd
20
15
4
mV
V
pF
Kohm
mA
mA
Load 20pF//50Kohm to Vss
Load 20pF//50Kohm to Vss
Maximum load 20 pF // 50 Kohm
Maximum load 20 pF // 50 Kohm
LCCb pin shorted to Vdd
LCCb pin shorted to Vss
Symbol
Min
Typ
Max
Unit
Comment
Vil
Vih
0
70
30
100
%
%
Vol
Vss
-
85
mV
Voh
4.5
-
Vdd
V
Vol
Vss
-
200
mV
Voh
4.5
-
Vdd
V
Cmax
Rmin
Isnkmax
Isrcmax
50
-
-
50
2.5
200
pF
Kohm
mA
µA
Rpullupext
5
7.5
10
Kohm
Symbol
Min
Typ
Max
Unit
Comment
Vil
Vih
Vol
Voh
Cmax
Rmin
Isnkmax
Isrcmax
Rpullupext
0
70
Vss
4.9
50
10
%
%
mV
V
pF
Kohm
mA
µA
Kohm
% of DVDD
% of DVDD
10
30
100
50
Vdd
50
10
0
10
CFGFLG, ACTIVATE
Parameter
Input Voltage Low
Input Voltage High
Output Voltage Low
Output Voltage High
Output Voltage Low
Output Voltage High
Max. Capacitive Load
Min. Resistive Load
Current Sink
Current Source
External Resistive Pullup
% of DVDD
% of DVDD
Pin load =
Internal pullup + 20pF//50K to Vss
Pin load =
Internal pullup + 20pF//50K to Vss
Pin Load =
External 5K ohm pullup +
20pF//50K to Vss
Pin Load =
External 5Kohm pullup +
20pF//50K to Vss
Maximum load 50 pF // 50 Kohm
Maximum load 50 pF // 50 Kohm
Pin shorted to Vdd
Pin shorted to Vss
Use only if internal pullup is
deselected
ERRb
Parameter
Input Voltage Low
Input Voltage High
Output Voltage Low
Output Voltage High
Max. Capacitive Load
Min. Resistive Load
Current Sink
Current Source
External Resistive Pullup
Maximum load 50 pF // 50 Kohm
Maximum load 50 pF // 50 Kohm
DCLK,Mode,DIN,EXECUTE,PORb,CS1b,CS2b
Parameter
Input Voltage Low
Input Voltage High
Symbol
Min
Typ
Max
Unit
Comment
Vil
Vih
0
70
-
30
100
%
%
% of DVDD
% of DVDD
DS030100-U006a
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AN221E04 Datasheet – Dynamically Reconfigurable FPAA With Enhanced I/O
OUTCLK/SPIMEM,DOUTCLK
Parameter
Symbol
Min
Typ
Max
Unit
Comment
Output Voltage Low
Output Voltage High
Max. Capacitive Load
Min. Resistive Load
Current Sink
Current Source
Vol
Voh
Cmax
Rmin
Isnkmax
Isrcmax
0
80
10
-
-
20
100
50
17
4
%
%
pF
Kohm
mA
mA
% of DVDD
% of DVDD
Maximum load 50 pF // 50 Kohm
Maximum load 50 pF // 50 Kohm
Parameter
Symbol
Min
Typ
Max
Unit
Comment
Input Voltage Low
Input Voltage High
Output Voltage Low
Output Voltage High
Max. Capacitive Load
Min. Resistive Load
Current Sink
Current Source
Vil
Vih
Vol
Voh
Cmax
Rmin
Isnkmax
Isrcmax
0
70
0
80
10
-
-
30
100
20
100
50
15
4
%
%
%
%
pF
Kohm
mA
mA
% of DVDD
% of DVDD
% of DVDD
% of DVDD
Maximum load 50 pF // 50 Kohm
Maximum load 50 pF // 50 Kohm
ACLK/SPIP
DS030100-U006a
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AN221E04 Datasheet – Dynamically Reconfigurable FPAA With Enhanced I/O
Analog Inputs General
Parameter
High Precision Input Range c
Standard precision Input Range d
High Precision
Differential Input c
Standard Precision
Differential Input d
Common Mode
Input Range
Input Offset
Input Frequency
c.
d.
Symbol
Min
Typ
Max
Unit
Vina
Vina
0.5
0.1
-
3.5
3.9
V
V
Vdiffina
0
-
+/-3.0
V
Vdiffina
0
-
+/-3.8
V
Vcm
1.8
2.0
2.2
V
Vos
-
5
15
mV
Fain
0
<2
8
MHz
Comment
VMR +/- 1.5v
VMR +/- 1.9v
Common mode voltage = 2 V
Common mode voltage = 2 V
Non-chopper stabilized input
Max value is clock, CAM and input
stage dependant. Input frequency
is limited to approx <2MHz due to
CAM signal processing which is
based on sampled data
architectures.
High precision operating range provides optimal linearity and dynamic range.
Standard precision operating range provides maximum dynamic range and reduced linearity.
Input Differential Amplifier ON and filter OFF
Parameter
Input Range
Gain Setting
Gain Accuracy
Gain Drift (Temperature, Supply
Voltage zand Time)
Equivalent Input Offset Voltage
Symbol
Vina
Vdiffina
Ginamp
Dist
Min
Typ
Max
Unit
16
-
1.0
128
2.5
%
-
-
1.0
%
Vos
-
3
12
mV
Voffsettc
-
1
10
µV/°C
Fain
Fain
0
0
<2
2
8
MHz
MHz
PSRR
65
-
-
dB
CMRR
-
67
-
dB
Large Signal Harmonic Distortion
Dist
-
-65
-
dB
Input Resistance
Input Capacitance
Input Referred Noise Figure
Rin
Cin
10
-
5.0
Mohm
pF
NF
-
0.1
-
µV/sqrtHz
SINAD
-
75
-
dB
SFDR
-
73
-
dB
Offset Voltage Temperature
Coefficient
Input Frequency c
Input Frequency d
Power Supply Rejection Ratio
Common Mode Rejection Ratio
Signal-to Noise Ratio and
Distortion
Spurious Free Dynamic Range
c.
d.
Comment
Usable input range will be reduced
by the effective gain setting
See analog input above
Non-chopper stabilized input
When the input amplifier and filter
are used in combination Vos
contribution comes only from the
input amplifier
from -40°C to 125°C
d.c. Amp Gain =16
a.c. See graphs page 18
0.4v p-p Differential input at 660Hz
Gain setting = 16
Input cell Gain = 16
Applies to audio frequency range
(400Hz to 30KHz).
See graphical data on page 18
Input signal = 285 mV p-p diff,
audio frequency range
See graphical data on page 18
Input signal = 100 mV p-p diff
See graphical data on page 18
High precision operating range provides optimal linearity and dynamic range.
Standard precision operating range provides maximum dynamic range and reduced linearity.
DS030100-U006a
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AN221E04 Datasheet – Dynamically Reconfigurable FPAA With Enhanced I/O
Input Differential Chopper Amplifier on and filter OFF
Parameter
Input Range
Gain Setting
Gain Accuracy
Gain Drift, (Temperature, Supply
Voltage and Time)
Chopper Frequency Clock Range
Symbol
Vina
Vdiffina
Ginamp
Min
Typ
Max
Unit
Comment
Usable input range will be reduced
by the effective gain setting
See analog input above
16
-
1.0
128
2.5
%
-
-
1.0
%
Fch
Fc/260100
-
>250
KHz
Vos
-
<100
200
µV
Voffsettc
-
0.5
2.0
µV/°C
Fc = master clock frequency
Set Fch as slow as possible
Fch > 250KHz will result in some
signal attenuation
Chopper stabilized amplifier
The maximum value of 200µV is
guaranteed by production test
This is a tester limitation
Equivalent Input Offset Voltage
Offset Voltage Temperature
Coefficient
Power Supply Rejection Ratio
Common Mode Rejection Ratio
Large Signal Harmonic Distortion
PSRR
65
-
-
dB
CMRR
-
102
-
dB
Dist
-
-40
-
dB
Fain
0
Fch/20
Fch/2
KHz
Rin
Cin
10
-
5.0
Mohm
pF
from -40°C to 125°C
d.c.
a.c. See graphs on page 18
0.4v p-p Differential input at
660Hz
Gain setting = 16
Fch=Chopper clock frequency
The chopper frequency and
input frequency should be
chosen such that subsequent
low pass filtering can remove the
chopper stage frequency
elements
Input to filter or chopper
Input Frequency
Input Resistance
Input Capacitance
Input Referred Noise Figure
Signal-to Noise Ratio and
Distortion
NF
-
0.09
-
µV/sqrtHz
SINAD
-
75
-
dB
SFDR
-
74
-
dB
Spurious Free Dynamic Range
Input cell Gain = 16
Applies to Audio frequency
range Chopper clock Fch =
250KHz
See graphical data on page 18
Input signal = 285 mV p-p
differential,
Audio frequency range
See graphical data on page 18
Input signal =100 mV p-p
differential
See graphical data on page 18
Input Differential Amplifier OFF and filter ON
Parameter
Symbol
Min
Input Range
Vina
Vdiffina
See analog input above
Equivalent Input Offset
Offset Voltage Temperature
Coefficient
Typ
Max
Unit
Vos
-
8
32
mV
Voffsettc
-
0.05 I
1.0 II
mV/°C
Fain
-
-
-
MHz
Input Frequency
Comment
Non-chopper stabilized input,
Filter corner frequency =470KHz
from -40°C to 125°C
I. measured at filter corner=470Khz
II. maximum at Filter corner=76KHz
Input filter frequency will define the
maximum frequency
Input filter is recommended to be
>30x higher than the max input
frequency, for 80dB distortion
performance
DS030100-U006a
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AN221E04 Datasheet – Dynamically Reconfigurable FPAA With Enhanced I/O
Common Mode Rejection Ration
Power Supply Rejection Ratio
CMRR
-
60
-
dB
PSRR
68
-
-
dB
Large Signal Harmonic Distortion
Dist
-
-82
-
dB
Ffiltcorner
76
-
470
KHz
Rin
Cin
10
-
-
5.0
Mohm
pF
NF
-
0.17
-
µV/sqrtHz
SINAD
-
84
-
dB
SFDR
-
90
-
dB
Input Low Pass Filter (Anti-Alias)
Corner Frequency Settings
Input Resistance
Input Capacitance
Input Referred Noise Figure
Signal-To Noise Ratio and
Distortion
Spurious Free Dynamic Range
d.c.
a.c. See graphical data on page 19
4v p-p Differential input at 660Hz
Filter corner frequency 470KHz
Input to filter or chopper
Input cell filter corner Fc = 470KHz
Applies to Audio frequency range
See graphical data on page 18
Input signal = 1400 mV p-p diff,
Audio frequency range
See graphical data on page 18
Input signal =1400 mV p-p differential
See graphical data on page 18
Input Differential Voltage mode, Amplifier OFF, Filter OFF and Unity Gain stage ON
Parameter
Input Range
Equivalent Input Offset
Offset Voltage Temperature
Coefficient
Input Frequency
Power Supply Rejection Ratio
Common Mode Rejection Ratio
Large Signal Harmonic Distortion
Large Signal Harmonic Distortion
Input Resistance
Input Capacitance
Input Referred Noise Figure
Signal-To Noise Ratio and
Distortion
Spurious Free Dynamic Range
Symbol
Vina
Vdiffina
Vos
Min
Typ
Max
See analog input above
Unit
Comment
V
-
5
15
mV
Voffsettc
-
20
50
µV/°C
Fain
-
-
1.0
MHz
PSRR
60
-
-
dB
CMRR
Dist
Dist
Rin
Cin
-
60
-80
-80
126
2.0
5.0
dB
dB
dB
Kohm
pF
NF
-
0.16
-
µV/sqrtHz
SINAD
-
84
-
dB
SFDR
-
90
-
dB
Non-chopper stabilized input
from -40°C to 125°C
Gain Bandwidth limited by input
impedance
d.c.
a.c. See graphs on page 18
4v p-p Differential input at 660Hz
3v p-p single ended signal at 660Hz
Input to unity gain stage
Applies to Audio frequency range
See graphical data on page 18
Input signal = 1400 mV p-p diff,
Audio frequency range
See graphical data on page 18
Input signal =1400 mV p-p differential
See graphical data on page 18
Input Differential Voltage mode, Amplifier OFF, Filter OFF and Unity Gain stage OFF
Parameter
Input Range
Equivalent Input Offset
Offset Voltage Temperature
Coefficient
Input Frequency
Power Supply Rejection Ratio
Large Signal Harmonic Distortion
Input Resistance
Symbol
Vina
Vdiffina
Vos
Min
Typ
Max
See analog input above
Unit
Comment
V
N/A
N/A
N/A
mV
Voffsettc
N/A
N/A
N/A
µV/°C
Fain
PSRR
Dist
N/A
-
N/A
-85
8
N/A
-
MHz
dB
dB
Rin
-
-
-
Mohm
Cin
-
-
-
pF
Input Capacitance
See CAM Op Amp
See CAM Op Amp.
from -40°C to 125°C
Dependant upon CAM
See CAM Op Amp
See CAM Op Amp
Input to CAM directly (Input cell
bypass mode). This variable is
influenced by CAB capacitor size,
CAB clock frequency and CAB
architecture
Input to CAM directly (Input cell
bypass mode)
This variable is influenced by CAB
capacitor size, CAB clock frequency
and CAB architecture
DS030100-U006a
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AN221E04 Datasheet – Dynamically Reconfigurable FPAA With Enhanced I/O
Analog Outputs
(See “Output Cell” section in the AN120E04/AN220E04 user manual for more details)
Parameter
High Precision Output Range c
Standard Precision Output
Range d
High Precision
Differential Output c
Standard precision
Differential Output d
Common Mode
Voltage
c
Symbol
Min
Typ
Max
Unit
Vouta
0.5
-
3.5
V
Vouta
0.1
-
3.9
V
Vdiffouta
-
-
+/-3.0
V
Vdiffouta
-
-
+/-3.8
V
Vcm
1.9
2.0
2.1
V
Comment
VMR +/- 1.5v
VMR +/- 1.9v
Common mode voltage = 2 V
Common mode voltage = 2 V
. High precision operating range provides optimal linearity and dynamic range.
. Standard precision operating range provides maximum dynamic range and reduced linearity.
d
Output Voltage mode and filter ON, corner frequency 470KHz
Parameter
Input Range
Equivalent Input Offset
Offset Voltage Temperature
Coefficient
Symbol
Vina
Vdiffina
Vos
Min
Typ
Max
See analog input above
-
Voffsettc
Unit
5
15
mV
0.05 I
1.0 II
mV/°C
Output Frequency
Power Supply Rejection Ratio
Large Signal Harmonic Distortion
Input Low Pass Filter (Anti-Alias)
Corner Frequency Settings
Output Load c e
Output Load c e
Output Load d e
Output Load d e
Common Mode Rejection Ratio
Faout
-
-
-
MHz
PSRR
60
-
-
dB
Dist
-
-82
-
dB
Ffiltcorner
76
-
470
KHz
Rload
Cload
0.1
-
-
50
Mohm
pF
Rload
1
10
-
Kohm
Cload
-
-
100
pF
CMRR
-
56
-
dB
NF
-
0.22
-
µV/sqrtHz
SINAD
-
82
-
dB
SFDR
-
90
-
dB
Input Referred Noise Figure
Signal-To Noise Ratio and
Distortion
Spurious Free Dynamic Range
Comment
V
from -40°C to 125°C
I
measured at filter corner: 470Khz
II
maximum at filter corner: 76KHz
Output filter frequency will define
the maximum frequency
Input filter is recommended to be
>30x higher then the max input
frequency, for good distortion
performance
d.c.
a.c. See graphical data on page 19
4v p-p Differential input at 660Hz
Filter corner frequency 470KHz
Additional loading causes internal
voltage drops across output stage
and series resistances
The output stage has a small
signal output impedance of approx
10ohm
Output filter corner fc = 470KHz
Applies to Audio frequency range
See graphical data on page 18
Input signal = 1400 mV p-p diff,
Audio frequency range
See graphical data on page 18
Input signal =1400 mV p-p diff
See graphical data on page 18
c
. High precision operating range provides optimal linearity and dynamic range.
. Standard precision operating range provides maximum dynamic range and reduced linearity.
e
. The maximum load for an analog output is 50 pF // 100 Kohms. This load maybe with respect to analog ground VMR or AVSS.
d
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AN221E04 Datasheet – Dynamically Reconfigurable FPAA With Enhanced I/O
Output Voltage mode and filter off (bypass mode)
Parameter
Symbol
Input Range
Equivalent Input Offset
Offset Voltage Temperature
Coefficient
Output Frequency c e
Output Frequency d f
Power Supply Rejection Ratio
Large Signal Harmonic Distortion
Output Load
Output Load
Min
Typ
Max
Unit
Comment
V
Vina
Vdiffina
Vos
N/A
N/A
N/A
mV
See CAM Op Amp
Voffsettc
N/A
N/A
N/A
mV/°C
See CAM Op Amp
Faout
-
-
4
MHz
See analog input above
Faout
-
-
8
MHz
PSRR
Dist
Rload
Cload
N/A
N/A
N/A
N/A
-85
N/A
N/A
N/A
N/A
N/A
dB
dB
Mohm
pF
The realizable output frequency is
limited to approx <2MHz due to
CAM signal processing which is
based on sampled data
architectures.
See CAM Op Amp
See CAM Op Amp
See CAM Op Amp
c
. High precision operating range provides optimal linearity and dynamic range.
. Standard precision operating range provides maximum dynamic range and reduced linearity.
. The maximum load for an analog output is 50 pF // 100 Kohms. This load maybe with respect to analog ground VMR or AVSS.
f
. The maximum load for an analog output is 100 pF // 100 Kohms. This load must be differential and with respect to analog ground(VMR).
d
e
VMR (voltage Mid Rail) and VREF (Reference Voltage) Ratings
Parameter
VMR Output Voltage
VREF+ Output Voltage
VREF- Output Voltage
Output Voltage Deviation
VREF+, VMR, VREFVoltage Temperature
Coefficient
VREF+, VMR, VREFPower Supply Rejection Ratio,
VMR
Power Supply Rejection Ratio
Vref+ and VrefStart Up Time
Min
Typ
Max
Unit
Vvmr
Vref+
Vref-
1.925
3.4
0.45
2.01
3.51
0.505
2.075
3.6
0.55
V
V
V
Vrefout
-
0.5
1
%
Vreftc
-
-
-
-
PSSR
60
-
-
dB
PSSR
75
-
-
dB
Tstart
-
-
1
ms
V+ref vs temperature
2.010
3.500
3.495
-50
0
50
Tchip (C)
100
150
At 25°C, Vdd=5.00 volts
At 25°C, Vdd=5.00 volts
At 25°C, Vdd=5.00 volts
Over process and supply voltage
corners
See typical graphical data below
-40°C to 125°C f
Assuming recommended
capacitors
Vref- vs temperature
0.505
2.000
1.995
3.490
Comment
0.510
2.005
Volts
Volts
3.505
VMR vs temperature
Volts
3.510
Symbol
0.500
0.495
1.990
0.490
-50
0
50
Tchip (C)
100
150
-50
0
50
100
150
Tchip (C)
DS030100-U006a
- 11 -
AN221E04 Datasheet – Dynamically Reconfigurable FPAA With Enhanced I/O
CAB (Configurable Analog Block) Differential Operational Amplifier
Parameter
Symbol
Min
Typ
Max
Unit
Vinouta
0.5
-
3.5
V
Vinouta
0.1
-
3.9
V
Vdiffioa
-
-
+/-3.0
V
Vdiffioa
-
-
+/-3.8
V
Vcm
0
2.0
4
V
Vcm
1.9
2.0
2.1
V
Voffset
0.1
5
15
mV
Voffsettc
-
1
10
µV/°C
PSSR
-
80
-
dB
CMRR
-
77
-
dB
CMRR
-
60
-
dB
Differential Slew Rate, Internal
Slew
-
50
-
V/µsec
Differential Slew Rate, External
Slew
-
10
-
V/µsec
Unity Gain Bandwidth,
Full Power Mode.
UGB
-
50
-
MHz
Rin
10
-
-
Mohm
Output Impedance, Internal
Rout
-
-
-
Ohms
Output Impedance, External
Rout
-
-
-
Ohms
Output Load, External c e
Output Load, External c e
Output Load, External d e f
Rload
Cload
0.1
-
-
50
Mohm
pF
High Precision Input/Output
Range c
Standard Precision Input/Output
Range d
High Precision.
Differential Input/Output c
Standard Precision
Differential Input/Output d
Common Mode Input Voltage
Range d
Common Mode Output Voltage
Range
Equivalent Input Voltage Offset.
Offset Voltage Temperature
Coefficient
Power Supply Rejection Ratio
Common Mode Rejection Ratio
Common Mode Rejection Ratio
Input Impedance, Internal
Output Load, External d e f
Noise Figure g
Rload
1
10
-
Kohm
Cload
-
-
50
pF
Noise
-
0.13
-
µV/sqrtHz
Comment
VMR +/- 1.5v
VMR +/-1.9v
Common mode voltage = 2 V
Common mode voltage = 2 V
Some CAMs (Configurable
Analog Modules) can inherently
compensate
from -40°C to 125°C some
CAMs (Configurable Analog
Modules) can inherently
compensate
Variation between CAMs is
expected because of variations
in architecture
Example 1 GainInv CAM
CAM clock = 1MHz
CAM parameter settings
Gain = 1
Example 2 Filterbiquad
Setting = Low pass filter
CAM clock = 1MHz
CAM parameter settings
Gain = 1,
Corner frequency = 50KHz
Quality Factor = 0.707
Applicable when the OpAmp
load is internal to the FPAA
Applicable when the OpAmp
driving signal out of the FPAA
package
Applicable when sourcing and
loading the OpAmp with a load
internal to the FPAA
The OpAmp output is designed
to drive all internal nodes, these
are dominantly capacitive loads
Output to an FPAA output pin
(ouput cell bypass mode). This
variable is influenced by CAB
capacitor size, CAB clock
frequency and CAB architecture
Additional loading causes
internal voltage drops across
output stage and series
resistances
The output stage has a small
signal output impedance of
approx 10ohm
Example1 GainInv CAM
CAM clock = 1MHz
Gain = 1
DS030100-U006a
- 12 -
AN221E04 Datasheet – Dynamically Reconfigurable FPAA With Enhanced I/O
Signal-To Noise Ratio and
Distortion g
SINAD
-
80
-
dB
SFDR
-
92
-
dB
Spurious Free Dynamic Range g
Input signal=1400 mV p-p
differential
Audio frequency range
Example. GainInv CAM
CAM clock = 1MHz
Gain = 1
Input signal=1400 mV p-p
differential,
Audio frequency range
Example. GainInv CAM
CAM clock = 1MHz
Gain = 1
c
.
.
.
f
.
High precision operating range provides optimal linearity and dynamic range.
Standard precision operating range provides maximum dynamic range and reduced linearity.
The maximum load for an analog output is 50 pF || 100 Kohms. This load may be with respect to analog ground VMR or AVSS.
Using the FPAA with CAB Op Amp’s driving directly off-chip, requires care, full characterization of the performance of each application
circuit by the circuit designer is necessary.
g
. This specification parameter can only be characterized when a circuit topology is configured onto the CAB differential amplifier architecture.
The figure provided here is an representative on the performance of one specific CAM, as specified in the comments.
d
e
Open Loop Gain (dB)
Idealized CAB Op Am p, Open Loop Gain [dB]
90
80
70
60
50
40
30
20
10
0
-10
-20
The idealized open loop gain plot is provided for
information only. This information is associated with the
FPAA in full power mode of operation. The FPAA
operation amplifier open loop gain cannot be observed
nor used when associated with external connections to
the device. Internal reprogrammable routing impedances
and switched capacitor circuit architecture using this
operational amplifier limit the effective usable bandwidth
of a circuit realized in the FPAA to less than 2MHz.
0.1
10
1000
100000
Frequency (KHz)
DS030100-U006a
- 13 -
AN221E04 Datasheet – Dynamically Reconfigurable FPAA With Enhanced I/O
CAB (Configurable Analog Block) Differential Comparator
Parameter
Input Range, Internal
Input Range, External
Differential Input, Internal
Differential Input, External
Common Mode Output Voltage
Range, Internal c
Common Mode Input Voltage
Range, External c
Common Mode Input Voltage,
External d
Differential Output
Single Pin Output (Ox1P)
Input Voltage Offset
Offset Voltage Temperature
Coefficient
Setup Time, Internal
Setup Time, External
Delay Time
Symbol
Min
Typ
Max
Unit
Vina
Vina
Vdiffina
Vdiffina
0.1
0.0
+/- 0.0
-
3.9
Vdd
+/-3.8
+/- Vdd
V
V
V
V
Vcm
1.9
2.0
2.1
V
Vcm
0
2.0
4
V
Vcm
0
-
5
V
Voutdiff
Vout
Voffcomp
0
-
2
+/-5
5
10
V
V
mV
Voffsettc
-
1
10
µV/°C
Tsetint
Tsetext
-
-
125
500
nsec
nsec
Tdelay
½Td+25
-
1½Td+25
nsec
Rload
10
-
-
Kohm
Cload
-
-
50
pF
CompVref
0
-
+/-4.0
V
Hysta1
Hysta2
Hysta3
Hysta4
Hystb
-
Voffcomp
20
40
80
25
-
mV
mV
mV
mV
%
Hysttc1
-
5
-
µV/°C
Hysteresis setting = zero
Hysttc2
-
50
-
µV/°C
Hysteresis setting = 10mV
Hysttc3
-
100
-
µV/°C
Hysteresis setting = 20mV
Hysttc4
-
200
-
µV/°C
Hysteresis setting = 40mV
Output Load
Output Load
Differential Variable Reference
Voltage Settings
Differential Hysteresis
Differential Hysteresis
Differential Hysteresis
Differential Hysteresis
Hysteresis Setting Accuracy
Hysteresis Temperature
Coefficient
Hysteresis Temperature
Coefficient
Hysteresis Temperature
Coefficient
Hysteresis Temperature
Coefficient
c
Comment
Common mode voltage = 2 V
The comparator will function
correctly
Zero hysterisis
from -40°C to 125°C,
Zero Hysterisis
Td = 1/Fc
Fc = master clock frequency
Applies if comparator drive off
chip with output cell in bypass
mode
Applies if comparator drive off
chip with output cell in bypass
mode
Hysteresis setting = zero
Hysteresis setting = 10mV
Hysteresis setting = 20mV
Hysteresis setting = 40mV
. High precision operating range provides optimal linearity and dynamic range.
. Standard precision operating range provides maximum dynamic range and reduced linearity.
d
DS030100-U006a
- 14 -
AN221E04 Datasheet – Dynamically Reconfigurable FPAA With Enhanced I/O
ESD Characteristics
Pin Type
Human
Body
Model
Machine
Model
Charged
Device
Model
Digital Inputs
Digital Outputs
Digital Bidirectional
Digital Open Drain
Analog Inputs
Analog Outputs
Reference Voltages
4000V
4000V
4000V
4000V
2000V
1500V
1500V
250V
250V
250V
250V
200V
100V
100V
4kV
4kV
4kV
4kV
4kV
4kV
4kV
The AN221E04 is an ESD (electrostatic discharge)
sensitive device. Electrostatic charges as high as 4000V
readily accumulate on the human body and test equipment
and can discharge without detection. Although the
AN221E04 device features proprietary ESD protection
circuitry, permanent damage may occur on devices
subjected to high-energy electrostatic discharges.
Therefore, proper ESD precautions are recommended to
avoid performance degradation or loss of functionality.
Power Consumption – Low Power Mode
Symbol
Min
Typ
Max
Unit
Idd
Idd
Idd
Idd
-
-
-
30
47
55
68
-10
mA
mA
mA
mA
Idd
0.2
25
42
50
60
63
66
-2
Minimum Power 1a
Nominal 25% Power1b
Nominal 50% Power 1c
Nominal 75% Power1d
Maximum Power1e
Temperature Coefficient
mA
Comment
Vdd=5.00 volts, Tj=25°C
Vdd=5.00 volts, Tj=25°C
Vdd=5.00 volts, Tj=25°C
Vdd=5.00 volts, Tj=25°C
Vdd=4.75 volts, Tj=85°C
Vdd=5.00 volts, Tj=25°C
Vdd=5.25 volts, Tj= -40°C
µA/°C
1a. External clock, all analog function disabled, memory active.
1b FPAA active elements – Two core op-amps (low power mode), one comparator, one input
(bypass mode), one output filter and differential to single-ended converter (low power
mode).
1c. FPAA active elements – Four core op-amps (low power mode), two comparators (one
using SAR), two inputs (bypass mode), two output filters and two differential to singleended converters (low power mode).
1d FPAA active elements – Six core op-amps (low power mode), three comparators (two using
SAR), three inputs (bypass mode, two output filters and two differential to single-ended
converters (low power mode).
1e FPAA active elements – Eight core op-amps (low power mode), four comparators (two
using SAR), four inputs (bypass mode), two output filters and two differential to singleended converters (low power mode).
Power consumption low power mode
(temp 25 degree C)
70
60
50
Idd (mA)
Parameter
40
30
20
Vdd=4.75V
Vdd=5.0V
Vdd=5.25V
10
0
25%
50%
75%
100%
Resource Utilization
Power Consumption – Full Power Mode
Full Power Mode Minimum Power 2a
Full Power Mode Nominal 25% Power2b
Full Power Mode Nominal 50% Power2c
Full Power Mode Nominal 75% Power2d
Full Power Mode Maximum Power2e
Symbol
Min
Typ
Max
Idd
Idd
Idd
Idd
-
1.5
80
150
170
90
160
190
Unit
mA
mA
mA
mA
Vdd=5.00 volts, Tj=25°C
Vdd=5.00 volts, Tj=25°C
Vdd=5.00 volts, Tj=25°C
Vdd=5.00 volts, Tj=25°C
Idd
-
200
210
220
230
-
mA
Vdd=4.75 volts, Tj=85°C
Vdd=5.00 volts, Tj=25°C
Vdd=5.25 volts, Tj= -40°C
2a. AN220E04 Crystal Oscillator, all analog functions disabled, memory active.
2b. FPAA active elements – Two core op-amps, one comparator, one input filter and chopper
amplifier, one output filter and differential to single-ended converter.
2c. FPAA active elements – Four core op-amps, two comparators (one using SAR), two Input
filters and two chopper amplifiers, two output filters and two differential to single-ended
converters.
2d FPAA active elements – Six core op-amps, three comparators (two using SAR), three input
filters and three chopper amplifiers, two output filters and two differential to single-ended
converters.
2e FPAA active elements – Eight core op-amps, four comparators (two using SAR), four input
filters and two chopper amplifiers, two output filters and two differential to single-ended
converters.
Comment
Power consumption full power mode
(temp 25 degree C)
250
200
Idd (mA)
Parameter
150
100
Vdd=4.75V
Vdd=5.0V
Vdd=5.25V
50
0
25%
50%
75%
100%
Resource Utilization
DS030100-U006a
- 15 -
AN221E04 Datasheet – Dynamically Reconfigurable FPAA With Enhanced I/O
PINOUT
Pin
Numb
er
Pin
Name
Pin
Type
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
I4PA
I4NA
O1P
O1N
AVSS
AVDD
O2P
O2N
I1P
I1N
I2P
I2N
SHIELD
AVDD2
VREFMC
VREFPC
VMRC
BVDD
BVSS
CFGFLGb
Analog IN+
Analog INAnalog OUT+
Analog OUTAnalog Vss
Analog Vdd
Analog OUT
Analog OUT
Analog IN+
Analog INAnalog IN+
Analog INAnalog Vdd
Analog Vdd
Vref
Vref
Vref
Analog Vdd
Analog Vss
Digital IN
Digital OUT
21
CS2b
Digital IN
22
CS1b
23
24
25
DCLK
SVSS
MODE
Digital IN
(during config)
Digital IN
(after config)_
Digital IN
Digital Vss
Digital IN
26
ACLK / SPIP
27
28
29
30
31
OUTCLK /
SPIMEM
DVDD
DVSS
DIN
LCCb
32
ERRb
Digital IN
(monitored OUT)
Digital OUT
33
ACTIVATE
Digital IN
34
35
DOUTCLK /
TEST
PORb
Digital OUT
Digital IN
Digital IN
36
EXECUTE
Digital IN
37
38
39
I3P
I3N
I4PD
Analog IN+
Analog INAnalog IN+
40
41
I4ND
I4PC
Analog INAnalog IN+
42
I4NC
Analog IN-
43
I4PB
Analog IN+
44
I4NB
Analog IN-
Digital IN
Digital OUT
Digital OUT
Digital OUT
Digital Vdd
Digital Vss
Digital IN
Digital OUT
Comments
Low noise Vdd bias for capacitor array n-wells
Analog power
Attach filter capacitor for VREFAttach filter capacitor for VREF+
Attach filter capacitor for VMR (Voltage Main Reference)
Analog power for bandgap Vref Generators
Analog ground for bandgap Vref Generators
In multi-device systems...
0, Ignore incoming data (unless currently addressed)
1, Pay attention to incoming data (watching for address)
0, Device is being configured
Z, Device is not being configured (if internal pullup is selected)
0, Chip is selected
1, Chip is not selected
0, Allow configuration to proceed
1, Hold off configuration
Passes read-back data through to LCC_B pin
Digital ground - substrate tie
0, Synchronous serial interface
1, SPI EPROM Interface
MODE = 0, analog clock < 40 MHz
MODE = 1, SPI EPROM or serial EPROM clock
During power-up, sources SPI EPROM initialization command string
After power-up, sources any of the four internal analog clocks
Serial configuration data input
1, Local configuration is needed. Once configuration is completed, it is a registered version of
CS1b or if the device is addressed for read, it serves as serial data out port
0, Initiate reset
1, No action
0, Error condition
Z, No error condition (external pullup required)
0, Hold off completion of configuration
Rising Edge, Allow completion of configuration
O.D. Output 0, device has not yet completed primary configuration
Z, Device has completed primary configuration (if internal pullup is selected)
A buffered version of DCLK.
(Factory reserved test input. Float if unused)
0, Chip held in reset state
Rising edge, re-initiates power on reset sequence
To initiate a POR reset cycle, the minimum pulse width required on the PORb pin is 25ns.
0, No action
1, Transfer shadow RAM into configuration RAM
Analog multiplexer input signals.
The multiplexer can accept 4 differential inputs or 8 single ended inputs
DS030100-U006a
- 16 -
AN221E04 Datasheet – Dynamically Reconfigurable FPAA With Enhanced I/O
MECHANICAL AND HANDLING
The AN221E04 comes in the industry standard 44 lead QFP package.
Dry pack handling is recommended. The package is qualified to MSL3 (JEDEC Standard, J-STD-020A, Level 3). Once the device is
removed from dry pack, 30°C at 60% humidity for not longer than 168 hours is the maximum recommended exposure prior to solder
reflow. If out of dry pack for longer than this recommended period of time, then the recommended bake out procedure prior to solder
reflow is 24 hours at 125°C.
DS030100-U006a
- 17 -
AN221E04 Datasheet – Dynamically Reconfigurable FPAA With Enhanced I/O
Distortion, SINAD and SNR Measurements
The following plots give an indication of the Distortion, SINAD and SNR for some representative CAMs.
INPUT CELL UGB SNR, DSTN, SINAD
INPUT CELL LOW PASS FILTER SNR, DSTN,
SINAD
120
100
80
60
SNR[ dB]
SINAD[ dB]
[dB]
[dB]
120
100
80
60
40
20
0
DISTN[ dB]
-20
-40
-60
40
20
SNR[ dB]
0
SINAD[ dB]
-20
DISTN[ dB]
-40
-60
-80
-100
-80
0.7
1.4
2.8
5.6
7.0
-100
0.7
INPUT [Vp-p]
1.4
2.8
INPUT [Vp-p]
5.6
7.0
100.00
80.00
60.00
INPUT CELL AMPLIFIER SNR,DSTN,SINAD
Measured with Inputcell Gain G = 16
Same results for Input Amplifier and
Chopper Amplifier stage, If the signal
from the chopper Amplifier is correctly
filtered before measurement.
[dB]
40.00
20.00
0.00
SNR[ dB]
-20.00
SINAD[ dB]
-40.00
DISTN[ dB]
-60.00
-80.00
-100.00
0.08
0.14
0.21
0.28
0.35
0.42
0.49
INPUT [Vp-p]
[dB]
Output Cell SNR, DSTN, SINAD
120
100
80
60
40
20
0
-20
-40
-60
-80
-100
SNR[dB]
SINAD[dB]
DISTN[dB]
0.7
1.4
2.8
3.5
5.6
7.0
INPUT [Vp-p]
100
80
GAININV CAM SNR, DSTN, SINAD
This graph shows the typical performance
of an FPAA CAB when configured with a
CAM in this example GainInv CAM
Input signal=1400 mV p-p differential,
CAM clock = 1MHz CAM parameter settings Gain = 1
60
40
SNR[ dB]
[dB]
20
0
SINAD[ dB]
- 20
DISTN[ dB]
- 40
- 60
- 80
- 100
- 120
0.7
1.4
2.8
3.5
5.6
7.0
INPUT [Vp-p]
DS030100-U006a
- 18 -
AN221E04 Datasheet – Dynamically Reconfigurable FPAA With Enhanced I/O
Power Supply Rejection Ratio (PSRR) Measurements
The following plots give an indication of the PSRR for some representative CAMs.
AVDD to Power Supply (PS): 5v +/- 0.25v sinusoidal waveform (100 kHz to 1 MHz)
INPUT AMP PSRR [dB]
INPUT LPF PSRR [dB]
80.00
80.00
70.00
70.00
60.00
60.00
50.00
50.00
40.00
40.00
30.00
30.00
20.00
20.00
DC
100
1KHz
10KHz
100KHz
1M Hz
DC
VMR, Vref+, Vref-
100.00
15
50
100
1KHz
10KHz 100KHz 1M Hz
PSRR [dB]
90.00
PSRR_VMR [ dB]
80.00
PSRR_VREFP [ dB]
70.00
PSRR_VREFP [ dB]
60.00
50.00
40.00
30.00
20.00
DC
100
1KHz
10KHz
100KHz
1M Hz
OUTPUT Voltage Mode + LPF PSRR [dB]
80.00
70.00
60.00
50.00
40.00
30.00
20.00
DC
100
1KHz
10KHz
100KHz
GAININV_1MHz PSRR [dB]
1M Hz
GAININV_4MHz PSRR [dB]
100
100
90
90
80
80
70
70
60
60
50
50
40
40
30
30
20
20
DC
50
100
1KHz
10KHz
100KHz
1M Hz
100
1KHz
10KHz
100KHz
1M Hz
DS030100-U006a
- 19 -
AN221E04 Datasheet – Dynamically Reconfigurable FPAA With Enhanced I/O
The following is provided for information only, as and when additional characterization data is collected ‘noise measurements’
will be added formally to the datasheet.
Noise And Distortion Observations
The following plots give an indication of the noise characteristics of Anadigm®’s AN221E04 FPAA device.
These were done using a simple set-up and in many cases reflect the noise limit of the setup. Actual device noise margins are
expected to be better.
Signal and Noise for the Input Cell (input signal - 50mVp-p differential to the FPAA at 10 kHz)
Signal to Noise: -92 dB, at 376KHz, 3Hz BW
Input gain stage set at X16
Input anti-aliasing filter set off
Input chopper amplifier set off
Signal and Noise for the Output Cell (with a differential input 4V p-p, 660Hz)
Signal to Noise: -106 dB, at 345KHz, 3Hz BW
Voltage output mode (including filter) ON
Output smoothing filter set at fC = 470 kHz
DS030100-U006a
- 20 -
AN221E04 Datasheet – Dynamically Reconfigurable FPAA With Enhanced I/O
Measured THD for input and output cells (with a differential input 4V p-p, 660Hz)
Settings
Distortion in dB
Input cell with anti-aliasing filter set at fC = 470 kHz
Output cell with differential to single ended converter and output smoothing filter set at fC = 470 kHz
81.6
82
Signal and Noise for a representative CAM – Gaininv CAM (input signal of 700mV p-p differential at 10 kHz)
Signal to Noise: 108 dB, at 528 kHz, 3Hz BW
THD for a representative CAM –
Gaininv CAM (with a differential
input 4V p-p, 660Hz)
CAM Clock
Frequency
250 KHz
1 MHz
2 MHz
4 MHz
Distortion
(dB)
80.00
72.83
69.22
73.48
As above, zoom to lower frequency
DS030100-U006a
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