ON MC100EP142FAR2 3.3 v / 5 v ecl 9-bit shift register Datasheet

MC10EP142, MC100EP142
3.3 V / 5 VECL 9−Bit Shift
Register
The MC10EP/100EP142 is a 9−bit shift register, designed with
byte-parity applications in mind. The MC10/100EP142 is capable of
performing serial/parallel data into serial/parallel out and shifting in
only one direction. The nine inputs D0 − D8 accept parallel input data,
while S−IN accepts serial input data. The QT0:87 outputs do not need
to be terminated for the shift operation to function. To minimize
power, any Q output not used should be left unterminated.
The SEL (Select) input pin is used to switch between the two modes
of operation − SHIFT and LOAD. The shift direction is from Bit 0 to
Bit 8. Input data is accepted by the registers a set−up time before the
positive going edge of CLK0 or CLK1; shifting is also accomplished
on the positive clock edge. A HIGH on the Master Reset pin (MR)
asynchronously resets all the registers to zero, overriding CLK0 and
CLK1 inputs.
The 100 Series contains temperature compensation.
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MARKING
DIAGRAM*
LQFP−32
FA SUFFIX
CASE 873A
MCxxx
EP142
AWLYYWWG
32
1
Features
•
•
•
•
•
•
•
•
•
1
Shift Frequency >2.8 GHz (Typical)
9-Bit for Byte−Parity Applications
Asynchronous Master Reset
Dual Clocks
PECL Mode Operating Range: VCC = 3.0 V to 5.5 V
with VEE = 0 V
NECL Mode Operating Range: VCC = 0 V
with VEE = −3.0 V to −5.5 V
Open Input Default State
Safety Clamp on Inputs
Pb−Free Packages are Available
1
32
QFN32
MN SUFFIX
CASE 488AM
MCxxx
EP142
AWLYYWWG
G
xxx
= 10 or 100
A
= Assembly Location
WL, L = Wafer Lot
YY, Y
= Year
WW, W = Work Week
G or G = Pb−Free Package
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 11 of this data sheet.
© Semiconductor Components Industries, LLC, 2006
November, 2006 − Rev. 16
1
Publication Order Number:
MC10EP142/D
24
23
22
21
20
19
18
17
D7
D8
Q8
Q7
Q7
Q6
Q5
VCC
VCC
Q5
Q6
Q7
Q7
Q8
D8
D7
MC10EP142, MC100EP142
24
23
22
21
20
19
18
17
D6
25
16
VEE
D5
26
15
Q4
D4
27
14
Q3
VCC
VEE
28
13
VCC
12
Q2
D3
29
12
Q2
D2
30
11
Q1
D2
30
11
Q1
D1
31
10
Q0
D1
31
10
Q0
VCC
32
9
MR
VCC
32
9
MR
D4
27
14
Q3
VEE
28
13
D3
29
MC10EP142
MC100EP142
8
SEL
7
CLK1
6
CLK1
5
CLK0
4
CLK0
S−IN
3
S−IN
2
D0
1
Figure 1. Pinout: LQFP−32 (Top View)
Exposed Pad (EP)
1
2
3
4
5
6
7
8
SEL
Q4
CLK1
15
CLK1
26
CLK0
D5
CLK0
VEE
S−IN
16
S−IN
25
D0
D6
Figure 2. Pinout: QFN−32 (Top View)
Table 1. PIN DESCRIPTION
Pin
Name
I/O
Default State
Description
1,23,24,25,26,
27,29,30,31
D[0:8]
ECL Input
Low
Single−Ended Parallel Data Inputs [0:8]. Internal 75 kW to VEE.
2
S−IN
ECL Input
Low
Noninverted Differential Serial Input. Internal 75 kW to VEE.
3
S−IN
ECL Input
High
Inverted Differential Serial Input. Internal 75 kW to VEE and 36.5 kW to
VCC.
4
CLK0
ECL Input
Low
Noninverted Differential CLK0 Input. Internal 75 kW to VEE.
5
CLK0
ECL Input
High
Inverted Differential CLK0B Input. Internal 75 kW to VEE and 36.5 kW
to VCC.
6
CLK1
ECL Input
Low
Noninverted Differential CLK1 Input. Internal 75 kW to VEE.
7
CLK1
ECL Input
High
Inverted Differential CLK1B Input. Internal 75 kW to VEE and 36.5 kW
to VCC.
8
SEL
ECL Input
Low
Single−Ended Select Logic Input. Internal 75 kW to VEE.
9
MR
ECL Input
Low
Single−Ended Master Reset Logic Input. Internal 75 kW to VEE.
10,11,12,14,1
5,18,19,22
Q0,Q1,Q2,Q3,
Q4,Q5,Q6,Q8
ECL Output
−
Single−Ended parallel Data outputs [0,1,2,3,4,5,6,8]. Typically
Terminated with 50 W to VTT = VCC − 2 V.
13,17,32
VCC
−
−
Positive supply Voltage. All VCC Pins must be Externally Connected to
Power Supply to Guarantee Proper Operation.
16,28
VEE
−
−
Negative supply Voltage. All VEE Pins must be Externally connected
to Power Supply to Guarantee Proper Operation.
20
Q7
ECL Output
−
Noninverted Differential parallel/Serial Data Output 7. Typically
Terminated with 50 W to VTT = VCC − 2 V.
21
Q7
ECL Output
−
Inverted Differential parallel/Serial Data Output 7. Typically
Terminated with 50 W to VTT = VCC − 2 V.
1. All VCC and VEE pins must be externally connected to Power Supply to guarantee proper operation.
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2
MC10EP142, MC100EP142
Table 2. TRUTH TABLE
Function
(Note 2)
SEL
S−IN
MR
CLK0
CLK1
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
Q9
Load
L
X
L
Z
Z
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
Shift
H
L
L
Z
Z
L
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
H
H
L
Z
Z
H
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
X
X
H
Z
Z
L
L
L
L
L
L
L
L
L
L
Reset
2. All Load and Shift functions are accomplished on the positive edge of CLK0 or CLK1.
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3
MC10EP142, MC100EP142
S-IN
R2
S-IN
D0
R1
1
R1
R1
D1
D
Q
Q0
1
0
D
Q
Q1
1
0
D
Q
Q2
1
0
D
Q
Q3
1
0
D
Q
Q4
1
0
D
Q
Q5
D
Q
Q6
D
Q
Q7
Q
Q7
Q
Q8
0
R1
D2
R1
D3
R1
D4
R1
D5
R1
1
D6
D7
D8
CLK1
1
0
R1
SEL
CLK0
R2
R1
CLK1
1
0
R1
MR
CLK0
0
R1
D
R1
VCC
R1
VEE
R1
R2
R1
Figure 3. Logic Diagram
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4
MC10EP142, MC100EP142
Table 3. ATTRIBUTES
Characteristics
Value
Internal Input Pulldown Resistor
(R1)
75 kW
Internal Input Pullup Resistor
(R2)
37.5 kW
Human Body Model
Machine Model
Charged Device Model
> 2 kV
> 100 V
> 2 kV
LQFP
QFN
Level 2
Level 1
ESD Protection
Moisture Sensitivity (Note 3)
Flammability Rating
Oxygen Index: 28 to 34
UL−94 V−0 @ 0.125 in
Transistor Count
405 Devices
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
3. For additional information, refer to Application Note AND8003/D.
Table 4. MAXIMUM RATINGS
Symbol
Parameter
Condition 1
Condition 2
Rating
Unit
VCC
Positive Power Supply
VEE = 0 V
8
V
VEE
Negative Power Supply
VCC = 0 V
−8
V
VI
PECL Mode Input Voltage
NECL Mode Input Voltage
VEE = 0 V
VCC = 0 V
6
−6
V
Iout
Output Current
Continuous
Surge
50
100
mA
TA
Operating Temperature Range
−40 to +85
°C
Tstg
Storage Temperature Range
−65 to +150
°C
qJA
Thermal Resistance (Junction−to−Ambient)
0 lfpm
500 lfpm
LQFP−32
LQFP−32
80
55
°C/W
qJC
Thermal Resistance (Junction−to−Case)
Standard Board
LQFP−32
12 to 17
°C/W
qJA
Thermal Resistance (Junction−to−Ambient)
0 lfpm
500 lfpm
QFN−32
QFN−32
31
27
°C/W
qJC
Thermal Resistance (Junction−to−Case)
2S2P
QFN−32
12
°C/W
Tsol
Wave Solder
v3 sec @ 248°C
v3 sec @ 260°C
265
265
°C
Pb
Pb−Free
VI v VCC
VI w VEE
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
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5
MC10EP142, MC100EP142
Table 5. 10EP DC CHARACTERISTICS, PECL VCC = 3.3 V, VEE = 0 V (Note 4)
−40°C
Symbol
Characteristic
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
IEE
Negative Power Supply Current
105
125
145
105
125
145
105
125
145
mA
VOH
Output HIGH Voltage (Note 5)
2165
2290
2415
2230
2355
2480
2290
2415
2540
mV
VOL
Output LOW Voltage (Note 5)
1365
1490
1615
1430
1555
1680
1490
1615
1740
mV
VIH
Input HIGH Voltage (Single−Ended)
2090
2415
2155
2480
2215
2540
mV
VIL
Input LOW Voltage (Single−Ended)
1365
1690
1460
1755
1490
1815
mV
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential Configuration)
(Note 6)
2.0
3.3
2.0
3.3
2.0
3.3
V
IIH
Input HIGH Current (@ VIH)
150
mA
IIL
Input LOW Current (@ VIL)
CLK0, CLK1, D, S−IN
CLK0, CLK1, S−IN
150
0.5
−150
150
0.5
−150
mA
0.5
−150
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
4. Input and output parameters vary 1:1 with VCC. VEE can vary +0.3 V to −2.2 V.
5. All loading with 50 W to VCC − 2.0 V.
6. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
Table 6. 10EP DC CHARACTERISTICS, PECL VCC = 5.0 V, VEE = 0 V (Note 7)
−40°C
Symbol
25°C
85°C
Characteristic
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
IEE
Negative Power Supply Current (Note 8)
105
125
145
105
125
145
105
125
145
mA
VOH
Output HIGH Voltage (Note 9)
3865
3990
4115
3930
4055
4180
3990
4115
4240
mV
VOL
Output LOW Voltage (Note 9)
3065
3190
3315
3130
3255
3380
3190
3315
3440
mV
VIH
Input HIGH Voltage (Single−Ended)
3790
4115
3855
4180
3915
4240
mV
VIL
Input LOW Voltage (Single−Ended)
3065
3390
3130
3455
3190
3515
mV
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential Configuration)
(Note 10)
2.0
5.0
2.0
5.0
2.0
5.0
V
IIH
Input HIGH Current (@ VIH)
150
mA
IIL
Input LOW Current (@ VIL)
CLK0, CLK1, D, S−IN
CLK0, CLK1, S−IN
150
0.5
−150
150
0.5
−150
0.5
−150
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
7. Input and output parameters vary 1:1 with VCC. VEE can vary +2.0 V to −0.5 V.
8. Required 500 lfpm air flow when using +5 V power supply. For (VCC − VEE) >3.3 V, 5 W to 10 W in line with VEE required for maximum thermal
protection at elevated temperatures. Recommend VCC − VEE operation at 3.3 V.
9. All loading with 50 W to VCC − 2.0 V.
10. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
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6
MC10EP142, MC100EP142
Table 7. 10EP DC CHARACTERISTICS, NECL VCC = 0 V, VEE = −5.5 V to −3.0 V (Note 11)
−40°C
Symbol
Characteristic
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
IEE
Negative Power Supply Current
(Note 12)
105
125
145
105
125
145
105
125
145
mA
VOH
Output HIGH Voltage (Note 13)
−1135
−1010
−885
−1070
−945
−820
−1010
−885
−760
mV
VOL
Output LOW Voltage (Note 13)
−1935
−1810
−1685
−1870
−1745
−1620
−1810
−1685
−1560
mV
VIH
Input HIGH Voltage (Single−Ended)
−1210
−885
−1145
−820
−1085
−760
mV
VIL
Input LOW Voltage (Single−Ended)
−1935
−1610
−1870
−1545
−1810
−1485
mV
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential Configuration)
(Note 14)
0.0
V
IIH
Input HIGH Current (@ VIH)
150
mA
IIL
Input LOW Current (@ VIL)
CLK0, CLK1, D, S−IN
CLK0, CLK1, S−IN
VEE+2.0
0.0
VEE+2.0
150
0.5
−150
0.0
VEE+2.0
150
0.5
−150
mA
0.5
−150
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
11. Input and output parameters vary 1:1 with VCC.
12. Required 500 lfpm air flow when using −5 V power supply. For (VCC − VEE) >3.3 V, 5 W to 10 W in line with VEE required for maximum thermal
protection at elevated temperatures. Recommend VCC−VEE operation at 3.3 V.
13. All loading with 50 W to VCC − 2.0 V.
14. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
Table 8. 100EP DC CHARACTERISTICS, PECL VCC = 3.3 V, VEE = 0 V (Note 15)
−40°C
Symbol
Characteristic
Min
Typ
25°C
Max
Min
Typ
85°C
Max
Min
Typ
Max
Unit
IEE
Negative Power Supply Current
105
125
145
105
130
150
105
130
150
mA
VOH
Output HIGH Voltage (Note 16)
2155
2280
2405
2155
2280
2405
2155
2280
2405
mV
VOL
Output LOW Voltage (Note 16)
1355
1480
1605
1355
1480
1605
1355
1480
1605
mV
VIH
Input HIGH Voltage (Single−Ended)
2075
2420
2075
2420
2075
2420
mV
VIL
Input LOW Voltage (Single−Ended)
1355
1675
1355
1675
1355
1675
mV
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential Configuration)
(Note 17)
2.0
3.3
2.0
3.3
2.0
3.3
V
IIH
Input HIGH Current (@ VIH)
150
mA
IIL
Input LOW Current (@ VIL)
CLK0, CLK1, D, S−IN
CLK0, CLK1, S−IN
150
0.5
−150
150
0.5
−150
0.5
−150
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
15. Input and output parameters vary 1:1 with VCC. VEE can vary +0.3 V to −2.2 V.
16. All loading with 50 W to VCC − 2.0 V.
17. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
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7
MC10EP142, MC100EP142
Table 9. 100EP DC CHARACTERISTICS, PECL VCC = 5.0 V, VEE = 0 V (Note 18)
−40°C
Symbol
Characteristic
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
IEE
Negative Power Supply Current
(Note 19)
105
125
145
105
130
150
105
130
150
mA
VOH
Output HIGH Voltage (Note 20)
3855
3980
4105
3855
3980
4105
3855
3980
4105
mV
VOL
Output LOW Voltage (Note 20)
3055
3180
3305
3055
3180
3305
3055
3180
3305
mV
VIH
Input HIGH Voltage (Single−Ended)
3775
4120
3775
4120
3775
4120
mV
VIL
Input LOW Voltage (Single−Ended)
3055
3375
3055
3375
3055
3375
mV
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential Configuration)
(Note 21)
2.0
5.0
2.0
5.0
2.0
5.0
V
IIH
Input HIGH Current (@ VIH)
150
mA
IIL
Input LOW Current (@ VIL)
CLK0, CLK1, D, S−IN
CLK0, CLK1, S−IN
150
150
0.5
−150
0.5
−150
mA
0.5
−150
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
18. Input and output parameters vary 1:1 with VCC. VEE can vary +2.0 V to −0.5 V.
19. Required 500 lfpm air flow when using +5 V power supply. For (VCC − VEE) >3.3 V, 5 W to 10 W in line with VEE required for maximum thermal
protection at elevated temperatures. Recommend VCC−VEE operation at 3.3 V.
20. All loading with 50 W to VCC − 2.0 V.
21. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
Table 10. 100EP DC CHARACTERISTICS, NECL VCC = 0 V, VEE = −5.5 V to −3.0 V (Note 22)
−40°C
Symbol
Characteristic
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
IEE
Negative Power Supply Current
(Note 23)
105
125
145
105
130
150
105
130
150
mA
VOH
Output HIGH Voltage (Note 24)
−1145
−1020
−895
−1145
−1020
−895
−1145
−1020
−895
mV
VOL
Output LOW Voltage (Note 24)
−1945
−1820
−1695
−1945
−1820
−1695
−1945
−1820
−1695
mV
VIH
Input HIGH Voltage (Single−Ended)
−1225
−880
−1225
−880
−1225
−880
mV
VIL
Input LOW Voltage (Single−Ended)
−1945
−1625
−1945
−1625
−1945
−1625
mV
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential Configuration)
(Note 25)
0.0
V
IIH
Input HIGH Current (@ VIH)
150
mA
IIL
Input LOW Current (@ VIL)
CLK0, CLK1, D, S−IN
CLK0, CLK1, S−IN
VEE+2.0
0.0
VEE+2.0
150
0.5
−150
0.0
VEE+2.0
150
0.5
−150
0.5
−150
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
22. Input and output parameters vary 1:1 with VCC.
23. Required 500 lfpm air flow when using −5 V power supply. For (VCC − VEE) >3.3 V, 5 W to 10 W in line with VEE required for maximum thermal
protection at elevated temperatures. Recommend VCC−VEE operation at 3.3 V.
24. All loading with 50 W to VCC − 2.0 V.
25. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
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8
MC10EP142, MC100EP142
Table 11. AC CHARACTERISTICS VCC = 3.0 V to 5.5 V; VEE = 0.0 V or VCC = 0.0 V; VEE = −3.0 V to −5.5 V (Note 26)
−40°C
Symbol
Characteristic
fSHIFT
Maximum Shift Frequency
tPLH,
tPHL
Propagation Delay to Output
ts
Setup Time
th
Min
Typ
25°C
Max
Min
Typ
85°C
Max
Min
Typ
Max
2.8
CLKx
MR
500
500
625
625
D
SEL
50
100
D
SEL
100
50
750
750
550
550
675
675
−50
50
50
100
50
−50
100
50
Unit
GHz
800
800
575
575
700
700
−50
50
50
100
−50
50
50
−50
100
50
50
−50
825
825
ps
ps
Hold Time
ps
tRR
Reset Recovery Time
800
ps
tpw
Minimum Pulse Width
200
ps
tSKEW
Within-Device Skew (Note 27)
Duty Cycle Skew (Note 28)
tJITTER
Random Clock Jitter (Figure 4)
Vinpp
Input Voltage Swing/Sensitivity
(Differential Configuration)
tr,
tf
Rise/Fall Times @ 50 MHz
(20 - 80%)
Q, Q
50
5.0
100
20
50
5.0
100
20
50
5.0
100
20
ps
1
2
1
2
1
2
ps
150
800
1200
150
800
1200
150
800
1200
mV
110
180
250
125
190
275
150
215
300
ps
900
9
800
8
700
7
600
6
500
5
400
4
300
3
200
2
100
1
ÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉ
0
0
1000
2000
3000
4000
5000
INPUT FREQUENCY (MHz)
Figure 4. Output Voltage Amplitude / RMS Jitter vs.
Input Frequency at Ambient Temperature (Typical)
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9
6000
JITTER OUT ps (RMS)
Output Voltage Amplitude (mV)
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
26. Measured using a 750 mV source, 50% duty cycle clock source. All loading with 50 W to VCC − 2.0 V.
27. Within-device skew is defined as identical transitions on similar paths through a device.
28. Skew is measured between outputs under identical transitions. Duty cycle skew is defined only for differential operation when the delays
are measured from the cross point of the inputs to the cross point of the outputs.
ÉÉ
ÉÉ
ÉÉ
MC10EP142, MC100EP142
CLK
VINPP = VIH(CLK) − VIL(CLK)
CLK
Q
VOUTPP = VOH(Q) − VOL(Q)
Q
tPHL
tPLH
Figure 5. AC Reference Measurement
Q
Zo = 50 W
D
Receiver
Device
Driver
Device
Q
D
Zo = 50 W
50 W
50 W
VTT
VTT = VCC − 2.0 V
Figure 6. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020/D − Termination of ECL Logic Devices.)
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10
MC10EP142, MC100EP142
ORDERING INFORMATION
Package
Shipping †
MC10EP142FA
LQFP−32
250 Units / Tray
MC10EP142FAG
LQFP−32
(Pb−Free)
250 Units / Tray
MC10EP142FAR2
LQFP−32
2000 / Tape & Reel
MC10EP142FAR2G
LQFP−32
(Pb−Free)
2000 / Tape & Reel
MC10EP142MNG
QFN−32
(Pb−Free)
74 Units / Rail
MC10EP142MNR4G
QFN−32
(Pb−Free)
1000 / Tape & Reel
MC100EP142FA
LQFP−32
250 Units / Tray
MC100EP142FAG
LQFP−32
(Pb−Free)
250 Units / Tray
MC100EP142FAR2
LQFP−32
2000 / Tape & Reel
MC100EP142FAR2G
LQFP−32
(Pb−Free)
2000 / Tape & Reel
MC100EP142MNG
QFN−32
(Pb−Free)
74 Units / Rail
MC100EP142MNR4G
QFN−32
(Pb−Free)
1000 / Tape & Reel
Device
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
Resource Reference of Application Notes
AN1405/D
− ECL Clock Distribution Techniques
AN1406/D
− Designing with PECL (ECL at +5.0 V)
AN1503/D
− ECLinPSt I/O SPiCE Modeling Kit
AN1504/D
− Metastability and the ECLinPS Family
AN1568/D
− Interfacing Between LVDS and ECL
AN1672/D
− The ECL Translator Guide
AND8001/D
− Odd Number Counters Design
AND8002/D
− Marking and Date Codes
AND8020/D
− Termination of ECL Logic Devices
AND8066/D
− Interfacing with ECLinPS
AND8090/D
− AC Characteristics of ECL Devices
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11
MC10EP142, MC100EP142
PACKAGE DIMENSIONS
32
A1
A
−T−, −U−, −Z−
32 LEAD LQFP
CASE 873A−02
ISSUE C
4X
25
0.20 (0.008) AB T−U Z
1
AE
−U−
−T−
B
P
V
17
8
BASE
METAL
DETAIL Y
V1
AC T−U Z
AE
DETAIL Y
ÉÉ
ÉÉ
ÉÉ
9
−Z−
S1
4X
0.20 (0.008) AC T−U Z
F
S
8X M_
D
DETAIL AD
G
−AB−
SECTION AE−AE
C E
−AC−
H
W
K
X
DETAIL AD
NOTES:
1. DIMENSIONING AND TOLERANCING
PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION:
MILLIMETER.
3. DATUM PLANE −AB− IS LOCATED AT
BOTTOM OF LEAD AND IS COINCIDENT
WITH THE LEAD WHERE THE LEAD
EXITS THE PLASTIC BODY AT THE
BOTTOM OF THE PARTING LINE.
4. DATUMS −T−, −U−, AND −Z− TO BE
DETERMINED AT DATUM PLANE −AB−.
5. DIMENSIONS S AND V TO BE
DETERMINED AT SEATING PLANE −AC−.
6. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION. ALLOWABLE
PROTRUSION IS 0.250 (0.010) PER SIDE.
DIMENSIONS A AND B DO INCLUDE
MOLD MISMATCH AND ARE
DETERMINED AT DATUM PLANE −AB−.
7. DIMENSION D DOES NOT INCLUDE
DAMBAR PROTRUSION. DAMBAR
PROTRUSION SHALL NOT CAUSE THE
D DIMENSION TO EXCEED 0.520 (0.020).
8. MINIMUM SOLDER PLATE THICKNESS
SHALL BE 0.0076 (0.0003).
9. EXACT SHAPE OF EACH CORNER MAY
VARY FROM DEPICTION.
DIM
A
A1
B
B1
C
D
E
F
G
H
J
K
M
N
P
Q
R
S
S1
V
V1
W
X
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12
MILLIMETERS
MIN
MAX
7.000 BSC
3.500 BSC
7.000 BSC
3.500 BSC
1.400
1.600
0.300
0.450
1.350
1.450
0.300
0.400
0.800 BSC
0.050
0.150
0.090
0.200
0.450
0.750
12_ REF
0.090
0.160
0.400 BSC
1_
5_
0.150
0.250
9.000 BSC
4.500 BSC
9.000 BSC
4.500 BSC
0.200 REF
1.000 REF
INCHES
MIN
MAX
0.276 BSC
0.138 BSC
0.276 BSC
0.138 BSC
0.055
0.063
0.012
0.018
0.053
0.057
0.012
0.016
0.031 BSC
0.002
0.006
0.004
0.008
0.018
0.030
12_ REF
0.004
0.006
0.016 BSC
1_
5_
0.006
0.010
0.354 BSC
0.177 BSC
0.354 BSC
0.177 BSC
0.008 REF
0.039 REF
Q_
0.250 (0.010)
0.10 (0.004) AC
GAUGE PLANE
SEATING
PLANE
J
R
M
N
9
0.20 (0.008)
B1
MC10EP142, MC100EP142
PACKAGE DIMENSIONS
QFN32 5*5*1 0.5 P
CASE 488AM−01
ISSUE O
A
B
D
ÉÉ
PIN ONE
LOCATION
2X
0.15 C
2X
NOTES:
1. DIMENSIONS AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.25 AND 0.30 MM TERMINAL
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
E
DIM
A
A1
A3
b
D
D2
E
E2
e
K
L
TOP VIEW
0.15 C
(A3)
0.10 C
A
32 X
0.08 C
C
L
32 X
9
D2
SEATING
PLANE
A1
SIDE VIEW
MILLIMETERS
MIN
NOM MAX
0.800 0.900 1.000
0.000 0.025 0.050
0.200 REF
0.180 0.250 0.300
5.00 BSC
2.950 3.100 3.250
5.00 BSC
2.950 3.100 3.250
0.500 BSC
0.200
−−−
−−−
0.300 0.400 0.500
EXPOSED PAD
16
SOLDERING FOOTPRINT*
K
32 X
17
5.30
8
3.20
E2
32 X
1
0.63
24
32
25
b
0.10 C A B
32 X
e
3.20
5.30
0.05 C
BOTTOM VIEW
32 X
0.28
28 X
0.50 PITCH
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ECLinPS is a trademark of Semiconductor Components Industries, LLC (SCILLC)
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA
Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada
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Email: [email protected]
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Europe, Middle East and Africa Technical Support:
Phone: 421 33 790 2910
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Phone: 81−3−5773−3850
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13
ON Semiconductor Website: www.onsemi.com
Order Literature: http://www.onsemi.com/orderlit
For additional information, please contact your local
Sales Representative
MC10EP142/D