HIGH-SPEED 16K x 16 DUAL-PORT STATIC RAM IDT7026S/L Integrated Device Technology, Inc. FEATURES: • True Dual-Ported memory cells which allow simultaneous access of the same memory location • High-speed access — Military: 25/35/55ns (max.) — Commercial: 20/25/35/55ns (max.) • Low-power operation — IDT7026S Active: 750mW (typ.) Standby: 5mW (typ.) — IDT7026L Active: 750mW (typ.) Standby: 1mW (typ.) • Separate upper-byte and lower-byte control for multiplexed bus compatibility • IDT7026 easily expands data bus width to 32 bits or more using the Master/Slave select when cascading more than one device • M/S = H for BUSY output flag on Master, M/S = L for BUSY input on Slave • On-chip port arbitration logic • Full on-chip hardware support of semaphore signaling between ports • Fully asynchronous operation from either port • TTL-compatible, single 5V (±10%) power supply • Available in 84-pin PGA and 84-pin PLCC • Industrial temperature range (–40°C to +85°C) is available, tested to military electrical specifications FUNCTIONAL BLOCK DIAGRAM R/ WL R/ WR LBL CEL OEL LBR CE R OE R UBR UBL I/O8L-I/O 15L I/O Control I/O8R-I/O 15R I/O Control I/O0L-I/O 7L BUSY I/O0R-I/O 7R (1,2) L A13L A0L (1,2) BUSY R Address Decoder MEMORY ARRAY 14 CEL SEML Address Decoder A13R A0R 14 ARBITRATION SEMAPHORE LOGIC CER M/ S SEM R 2939 drw 01 NOTES: 1. (MASTER): BUSY is output; (SLAVE): BUSY is input. 2. BUSY outputs are non-tri-stated push-pull. The IDT logo is a registered trademark of Integrated Device Technology, Inc. MILITARY AND COMMERCIAL TEMPERATURE RANGES ©1996 Integrated Device Technology, Inc. For latest information contact IDT’s web site at www.idt.com or fax-on-demand at 408-492-8391. 6.17 OCTOBER 1996 DSC 2939/3 1 IDT7026S/L HIGH-SPEED 16K x 16 DUAL-PORT STATIC RAM MILITARY AND COMMERCIAL TEMPERATURE RANGES DESCRIPTION: The IDT7026 is a high-speed 16K x 16 Dual-Port Static RAM. The IDT7026 is designed to be used as a stand-alone Dual-Port RAM or as a combination MASTER/SLAVE DualPort RAM for 32-bit-or-more word systems. Using the IDT MASTER/SLAVE Dual-Port RAM approach in 32-bit or wider memory system applications results in full-speed, error-free operation without the need for additional discrete logic. This device provides two independent ports with separate control, address, and I/O pins that permit independent, asynchronous access for reads or writes to any location in memory. An automatic power down feature controlled by CE permits the on-chip circuitry of each port to enter a very low standby power mode. Fabricated using IDT’s CMOS high-performance technology, these devices typically operate on only 750mW of power. The IDT7026 is packaged in a ceramic 84-pin PGA, and a 84-pin PLCC. Military grade product is manufactured in compliance with the latest revision of MIL-STD-883, Class B, making it ideally suited to military temperature applications demanding the highest level of performance and reliability. A9L A11L A10L A13L A12L UBL LBL CEL W R/ L SEML OEL VCC I/O1L I/O0L GND I/O3L I/O2L I/O4L I/O5L INDEX I/O6L I/O7L PIN CONFIGURATIONS (1,2) 12 11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75 74 I/O9L 13 73 I/O10L 14 72 I/O11L 15 71 I/O12L 16 70 I/O13L 17 69 GND 18 68 I/O14L 19 I/O15L 20 VCC 21 I/O8L GND 22 I/O0R 23 67 A8L A7L A6L A5L A4L A3L A2L A1L IDT7026 J84-1 66 A0L 65 BUSYL 84-PIN PLCC TOP VIEW(3) 64 GND 63 M/S 55 I/O8R 54 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 UBR LBR SEMR W I/O9R A8R 56 31 A9R 30 I/O7R A10R 57 I/O6R A11R 29 A13R A12R 58 I/O5R CER 59 28 R/ R GND 27 I/O4R OER I/O3R A0R A1R A2R A3R A4R A5R A6R A7R I/O15R 60 GND 26 I/O14R VCC I/O12R I/O13R 61 I/O11R BUSYR 25 I/O2R I/O10R 24 62 I/O1R 2939 drw 02 NOTES: 1. All Vcc pins must be connected to the power supply. 2. All GND pins must be connected to the ground supply. 3. This text does not indicate orientation of the actual part-marking. 6.17 2 IDT7026S/L HIGH-SPEED 16K x 16 DUAL-PORT STATIC RAM MILITARY AND COMMERCIAL TEMPERATURE RANGES PIN CONFIGURATIONS (CONT'D) (1,2) 63 11 61 I/O7L 66 10 64 I/O10L 67 09 53 GND 47 CEL 52 45 A12L A10L 77 I/O1R 33 VCC BUSYL IDT7026 G84-3 32 84-PIN PGA TOP VIEW(3) GND GND 28 VCC 7 A 5 I/O10R 4 I/O11R B 11 GND 2 3 A0L 36 M/S A2L 30 A0R BUSYR 27 A2R A3R I/O7R I/O8R A1L 29 A1R 83 I/O9R A3L 34 26 1 A5L 37 31 I/O4R I/O6R 39 35 80 I/O5R A6L A7L 78 I/O2R I/O3R 40 A4L 74 GND A8L A9L 41 WL R/ VCC 42 A11L 43 44 A13L 73 I/O14L I/O0R 84 01 50 UBL 46 LBL 38 70 82 02 49 I/O1L 48 SEML I/O12L I/O15L 81 03 56 I/O3L 51 OEL 57 71 79 04 I/O6L 54 I/O0L 68 76 05 59 62 I/O9L I/O13L 75 06 55 I/O2L 65 72 07 58 I/O4L I/O8L I/O11L 69 08 60 I/O5L 8 I/O15R 6 9 I/O14R C GND 10 I/O13R I/O12R 12 R/ WR 15 OER D E 25 23 SEMR 14 17 UBR 13 LBR CER F G A4R A6R 22 20 A12R 16 A9R 18 A13R H 24 A7R 19 A11R J A5R 21 A10R A8R K L 2939 drw 03 Index NOTES: 1. All VCC pins must be connected to power supply. 2. All GND pins must be connected to ground supply. 3. This text does not indicate orientation of the actual part-marking. RECOMMENDED OPERATING TEMPERATURE AND SUPPLY VOLTAGE PIN NAMES Left Port Right Port Names CEL R/WL OEL CER R/WR OER A0L – A13L A0R – A13R Address I/O0L – I/O15L I/O0R – I/O15R Data Input/Output SEML UBL LBL BUSYL SEMR UBR LBR BUSYR M/S Grade Chip Enable Read/Write Enable Military Output Enable Commercial Ambient Temperature GND VCC –55°C to +125°C 0V 5.0V ± 10% 0°C to +70°C 0V 5.0V ± 10% 2939 tbl 02 Semaphore Enable Upper Byte Select Lower Byte Select Busy Flag Master or Slave Select VCC Power GND Ground 2939 tbl 01 6.17 3 IDT7026S/L HIGH-SPEED 16K x 16 DUAL-PORT STATIC RAM MILITARY AND COMMERCIAL TEMPERATURE RANGES TRUTH TABLE I – NON-CONTENTION READ/WRITE CONTROL Inputs(1) CE R/W OE H X X X X X Outputs UB LB SEM I/O8-15 I/O0-7 X X H High-Z High-Z Deselected: Power-Down H H H High-Z High-Z Both Bytes Deselected Mode L L X L H H DATAIN High-Z Write to Upper Byte Only L L X H L H High-Z DATAIN Write to Lower Byte Only L L X L L H DATAIN DATAIN Write to Both Bytes High-Z Read Upper Byte Only L H L L H H DATAOUT L H L H L H High-Z L H L L L H X X H X X X DATAOUT Read Lower Byte Only DATAOUT DATAOUT Read Both Bytes High-Z High-Z Outputs Disabled NOTE: 1. A0L — A13L ≠ A0R — A13R. 2939 tbl 03 TRUTH TABLE II – SEMAPHORE READ/WRITE CONTROL(1) Inputs Outputs CE R/W OE H H L X X L DATAOUT DATAOUT Read Data in Semaphore Flag X H L H H L DATAOUT DATAOUT Read Data in Semaphore Flag X X X L DATAIN DATAIN H X UB LB SEM I/O0-7 I/O8-15 Mode Write I/O0 into Semaphore Flag X H H L DATAIN DATAIN L X X L X L — — Not Allowed Write I/O0 into Semaphore Flag L X X X L L — — Not Allowed NOTE: 1. There are eight semaphore flags written to via I/O0 and read from all I/O's (I/O0-I/O15). These eight semaphores are addressed by A0 - A2. ABSOLUTE MAXIMUM RATINGS(1) Symbol VTERM TA (2) Rating Commercial Military Unit Terminal Voltage –0.5 to +7.0 with Respect to GND –0.5 to +7.0 V Operating Temperature –55 to +125 °C 0 to +70 TBIAS Temperature Under Bias –55 to +125 –65 to +135 °C TSTG Storage Temperature –55 to +125 –65 to +150 °C IOUT DC Output Current 50 50 mA 2939 tbl 04 RECOMMENDED DC OPERATING CONDTIONS Symbol Parameter Min. Typ. Max. Unit VCC Supply Voltage 4.5 5.0 5.5 V GND Supply Voltage 0 0 0 V VIH Input High Voltage 2.2 — VIL Input Low Voltage –0.5(1) — (2) 6.0 0.8 NOTES: 1. VIL > -1.5V for pulse width less than 10ns. 2. VTERM must not exceed Vcc + 0.5V. NOTES: 2939 tbl 05 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. VTERM must not exceed Vcc + 0.5V for more than 25% of the cycle time or 10ns maximum, and is limited to < 20mA for the period of VTERM > Vcc + 0.5V. V V 2939 tbl 06 CAPACITANCE(1) (TA = +25°C, f = 1.0MHz) Symbol Parameter Conditions(2) Max. Unit CIN Input Capacitance VIN = 3dv 9 pF COUT Output Capacitance VOUT = 3dv 10 pF NOTES: 2939 tbl 07 1. This parameter is determined by device characterization but is not production tested. 2. 3dV represents the interpolated capacitance when the input and output signals switch from 0V to 3V or from 3V to 0V. 6.17 4 IDT7026S/L HIGH-SPEED 16K x 16 DUAL-PORT STATIC RAM MILITARY AND COMMERCIAL TEMPERATURE RANGES DC ELECTRICAL CHARACTERISTICS OVER THE OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE (VCC = 5.0V ± 10%) IDT7026S Symbol Parameter (1) IDT7026L Test Conditions Min. Max. Min. Max. Unit VCC = 5.5V, VIN = 0V to VCC — 10 — 5 µA CE = VIH, VOUT = 0V to VCC — 10 — 5 µA |ILI| Input Leakage Current |ILO| Output Leakage Current VOL Output Low Voltage IOL = 4mA — 0.4 — 0.4 V VOH Output High Voltage IOH = –4mA 2.4 — 2.4 — V NOTE: 1. At Vcc = 2.0V, input leakages are undefined. 2939 tbl 08 DC ELECTRICAL CHARACTERISTICS OVER THE OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(1) (VCC = 5.0V ± 10%) Symbol ICC ISB1 ISB2 Parameter Dynamic Operating Current CE = VIL, Outputs Open SEM = VIH (Both Ports Active) f = fMAX(3) Standby Current (Both Ports — TTL CER = CEL = VIH SEMR = SEML = VIH Level Inputs) f = fMAX(3) Standby Current (One Port — TTL Level Inputs) ISB3 Full Standby Current (Both Ports — All CMOS Level Inputs) ISB4 Test Condition Full Standby Current (One Port — All CMOS Level Inputs) 7026X20 7026X25 Com'l. Only Typ.(2) Max. Typ.(2) Max. Unit Version CE"A" = VIL and CE"B" = VIH(5) MIL. S L — — — — 170 170 345 305 COM’L. S L 180 180 315 275 170 170 305 265 MIL. S L — — — — 25 25 100 80 COM’L. S L 30 30 85 60 25 25 85 60 MIL. S L — — — — 105 105 230 200 COM’L. S L 115 115 210 180 105 105 200 170 MIL. S L — — — — 1.0 0.2 30 10 COM’L. S L 1.0 0.2 15 5 1.0 0.2 15 5 MIL. S L — — — — 100 100 200 175 COM’L. S 110 185 100 170 L 110 160 100 145 Active Port Outputs Open, f = fMAX(3) SEMR = SEML = VIH Both Ports CEL and CER > VCC - 0.2V VIN > VCC - 0.2V or VIN < 0.2V, f = 0(4) SEMR = SEML > VCC - 0.2V CE"A" < 0.2V and CE"B" > VCC - 0.2V(5) SEMR = SEML > VCC - 0.2V VIN > VCC - 0.2V or VIN < 0.2V Active Port Outputs Open, f = fMAX(3) mA mA mA mA mA NOTES: 2939 tbl 09 1. "X" in part numbers indicates power rating (S or L). 2. VCC = 5V, TA = +25°C, and are not production tested. ICCDC = 120mA (Typ.) 3. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1 / tRC, and using “AC Test Conditions” of input levels of GND to 3V. 4. f = 0 means no address or control lines change. 5. Port "A" may be either left or right port. Port "B" is the opposite from port "A". 6.17 5 IDT7026S/L HIGH-SPEED 16K x 16 DUAL-PORT STATIC RAM MILITARY AND COMMERCIAL TEMPERATURE RANGES DC ELECTRICAL CHARACTERISTICS OVER THE OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(1)(Con't.) (VCC = 5.0V ± 10%) 7026X35 Symbol ICC ISB1 ISB2 Parameter Typ.(2) Max. Typ.(2) Max. Unit Version CE = VIL, Outputs Open SEM = VIH MIL. S L 160 160 335 295 150 150 310 270 (Both Ports Active) f = fMAX(3) COM’L. S L 160 160 295 255 150 150 270 230 Standby Current (Both Ports — TTL CEL = CER = VIH SEMR = SEML = VIH MIL. S L 20 20 100 80 13 13 100 80 Level Inputs) f = fMAX(3) COM’L. S L 20 20 85 60 13 13 85 60 CE"A"=VIL and CE"B"=VIH(5) MIL. S L 95 95 215 185 85 85 195 165 COM’L. S L 95 95 185 155 85 85 165 135 MIL. S L 1.0 0.2 30 10 1.0 0.2 30 10 COM’L. S L 1.0 0.2 15 5 1.0 0.2 15 5 MIL. S L 90 90 190 165 80 80 175 150 mA COM’L. S L 90 90 160 135 80 80 135 110 mA Standby Current (One Port — TTL Full Standby Current (Both Ports — All CMOS Level Inputs) ISB4 7026X55 Dynamic Operating Current Level Inputs) ISB3 Test Condition Full Standby Current (One Port — All CMOS Level Inputs) Active Port Outputs Open, f = fMAX(3) SEMR = SEML = VIH Both Ports CEL and CER > VCC - 0.2V VIN > VCC - 0.2V or VIN < 0.2V, f = 0(4) SEMR = SEML >VCC - 0.2V CE"A" < 0.2V and CE"B" > VCC - 0.2V(5) SEMR = SEML >VCC - 0.2V VIN > VCC - 0.2V or VIN < 0.2V Active Port Outputs Open, f = fMAX(3) NOTES: 1. "X" in part numbers indicates power rating (S or L). 2. VCC = 5V, TA = +25°C, and are not production tested. ICCDC = 120mA (Typ.) 3. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/ tRC, and using “AC Test Conditions” of input levels of GND to 3V. 4. f = 0 means no address or control lines change. 5. Port "A" may be either left or right port. Port "B" is the opposite from port "A". 6.17 mA mA mA mA 2939 tbl 10 6 IDT7026S/L HIGH-SPEED 16K x 16 DUAL-PORT STATIC RAM MILITARY AND COMMERCIAL TEMPERATURE RANGES AC TEST CONDITIONS 5V Input Pulse Levels 5V GND to 3.0V Input Rise/Fall Times 893Ω 5ns Max. Input Timing Reference Levels 1.5V Output Reference Levels 1.5V Output Load 893Ω DATAOUT BUSY INT DATAOUT 347Ω 30pF 347Ω 5pF Figures 1 and 2 2939 tbl 11 2939 drw 04 2939 drw 05 Figure 1. AC Output Load Figure 2. Output Test Load (for tLZ, tHZ, tWZ, tOW) * Including scope and jig. AC ELECTRICAL CHARACTERISTICS OVER THE OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(4) Symbol IDT7026X20 Com'l. Only Min. Max. Parameter IDT7026X25 Min. Max. Unit READ CYCLE tRC Read Cycle Time tAA Address Access Time 20 — 25 — ns — 20 — 25 ns tACE Chip Enable Access Time (3) — 20 — 25 ns tABE Byte Enable Access Time(3) — 20 — 25 ns tAOE Output Enable Access Time — 12 — 13 ns tOH Output Hold from Address Change 3 — 3 — ns tLZ Output Low-Z Time(1, 2) 3 — 3 — ns tHZ Output High-Z Time(1, 2) — 12 — 15 ns (2) tPU Chip Enable to Power Up Time 0 — 0 — ns tPD Chip Disable to Power Down Time(2) — 20 — 25 ns tSOP Semaphore Flag Update Pulse (OE or SEM) 10 — 12 — ns tSAA Semaphore Address Access Time — 20 — 25 ns Symbol Parameter IDT7026X35 IDT7026X55 Min. Max. Min. Max. Unit READ CYCLE tRC Read Cycle Time 35 — 55 — ns tAA Address Access Time — 35 — 55 ns — 55 ns (3) — 35 tABE (3) Byte Enable Access Time — 35 — 55 ns tAOE Output Enable Access Time — 20 — 30 ns tOH Output Hold from Address Change 3 — 3 — ns tLZ Output Low-Z Time(1, 2) 3 — 3 — ns tHZ Output High-Z Time(1, 2) — 15 — 25 ns tACE Chip Enable Access Time (2) tPU Chip Enable to Power Up Time 0 — 0 — ns tPD Chip Disable to Power Down Time(2) — 35 — 50 ns tSOP Semaphore Flag Update Pulse (OE or SEM) 15 — 15 — ns tSAA Semaphore Address Access Time — 35 — 55 ns NOTES: 1. Transition is measured ±200mV from Low or High-impedance voltage with Output Test Load (Figure 2). 2. This parameter is guaranteed by device characterization, but is not production tested. 3. To access RAM, CE = VIL and SEM = VIH. To access semaphore, CE = VIH and SEM = VIL. 4. "X" in part numbers indicates power rating (S or L). 6.17 2939 tbl 12 7 IDT7026S/L HIGH-SPEED 16K x 16 DUAL-PORT STATIC RAM MILITARY AND COMMERCIAL TEMPERATURE RANGES WAVEFORM OF READ CYCLES(5) tRC ADDR tAA (4) (4) tACE CE tAOE OE (4) tABE (4) , LB UB W R/ tOH tLZ (1) DATAOUT VALID DATA (4) tHZ (2) BUSYOUT tBDD (3, 4) 2939 drw 06 NOTES: 1. Timing depends on which signal is asserted last, OE, CE, LB, or UB. 2. Timing depends on which signal is de-asserted first CE, OE, LB, or UB. 3. tBDD delay is required only in cases where the opposite port is completing a write operation to the same address location. For simultaneous read operations BUSY has no relation to valid output data. 4. Start of valid data depends on which timing becomes effective last tAOE, tACE, tAA or tBDD. 5. SEM = VIH. TIMING OF POWER-UP POWER-DOWN CE ICC tPU tPD 50% 50% ISB 2939 drw 07 6.17 8 IDT7026S/L HIGH-SPEED 16K x 16 DUAL-PORT STATIC RAM MILITARY AND COMMERCIAL TEMPERATURE RANGES AC ELECTRICAL CHARACTERISTICS OVER THE OPERATING TEMPERATURE AND SUPPLY VOLTAGE (5) Symbol IDT7026X20 Com'l. Only Min. Max. Parameter IDT7026X25 Min. Max. Unit WRITE CYCLE 20 — 25 — ns tEW (3) Chip Enable to End-of-Write 15 — 20 — ns tAW Address Valid to End-of-Write 15 — 20 — ns — 0 — ns tWC Write Cycle Time (3) tAS Address Set-up Time 0 tWP Write Pulse Width 15 — 20 — ns tWR Write Recovery Time 0 — 0 — ns tDW Data Valid to End-of-Write 15 — 15 — ns (1, 2) tHZ Output High-Z Time — 12 — 15 ns tDH Data Hold Time(4) 0 — 0 — ns tWZ Write Enable to Output in High-Z(1, 2) — 12 — 15 ns tOW Output Active from End-of-Write(1, 2, 4) 0 — 0 — ns 5 — 5 — ns 5 — 5 — ns tSWRD tSPS SEM Flag Write to Read Time SEM Flag Contention Window Symbol Parameter IDT7026X35 IDT7026X55 Min. Min. Max. Max. Unit WRITE CYCLE tWC Write Cycle Time 35 — 55 — ns tEW Chip Enable to End-of-Write(3) 30 — 45 — ns tAW Address Valid to End-of-Write 30 — 45 — ns tAS Address Set-up Time(3) 0 — 0 — ns tWP Write Pulse Width 25 — 40 — ns tWR Write Recovery Time 0 — 0 — ns tDW Data Valid to End-of-Write 15 — 30 — ns — 15 — 25 ns tHZ (1, 2) Output High-Z Time (4) tDH Data Hold Time 0 — 0 — ns tWZ Write Enable to Output in High-Z(1, 2) — 15 — 25 ns tOW tSWRD tSPS (1, 2, 4) Output Active from End-of-Write SEM Flag Write to Read Time SEM Flag Contention Window 0 — 0 — ns 5 — 5 — ns 5 — 5 — ns NOTES: 2939 tbl 13 1. Transition is measured ±200mV from Low or High-impedance voltage with Output Test Load (Figure 2). 2. This parameter is guaranteed by device characterization, but is not production tested. 3. To access RAM, CE = VIL and SEM = VIH. To access semaphore, CE = VIH and SEM = VIL. Either condition must be valid for the entire tEW time. 4. The specification for tDH must be met by the device supplying write data to the RAM under all operating conditions. Although tDH and tOW values will vary over voltage and temperature, the actual tDH will always be smaller than the actual tOW. 5. "X" in part numbers indicates power rating (S or L). 6.17 9 IDT7026S/L HIGH-SPEED 16K x 16 DUAL-PORT STATIC RAM MILITARY AND COMMERCIAL TEMPERATURE RANGES TIMING WAVEFORM OF WRITE CYCLE NO. 1, R/W CONTROLLED TIMING(1,5,8) tWC ADDRESS tHZ (7) OE tAW CE or SEM UB or LB (9) (9) (3) tWP(2) tAS (6) tWR W R/ tWZ (7) DATAOUT tOW (4) (4) tDW tDH DATAIN 2939 drw 08 TIMING WAVEFORM OF WRITE CYCLE NO. 2, CE, UB, LB CONTROLLED TIMING(1,5) tWC ADDRESS tAW CE or SEM (9) (6) tAS tWR(3) tEW (2) UB or LB (9) R/ W tDW tDH DATAIN 2939 drw 09 NOTES: 1. R/W or CE or UB and LB must be HIGH during all address transitions. 2. A write occurs during the overlap (tEW or tWP) of a LOW CE and a LOW R/W for memory array writing cycle. 3. tWR is measured from the earlier of CE or R/W (or SEM or R/W) going HIGH to the end of write cycle. 4. During this period, the I/O pins are in the output state and input signals must not be applied. 5. If the CE or SEM LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the High-impedance state. 6. Timing depends on which enable signal is asserted last, CE or R/W. 7. This parameter is guaranteed by device characterization, but is not production tested. Transition is measured + 200mV from steady state with the Output Test Load (Figure 2). 8. If OE is LOW during R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off and data to be placed on the bus for the required tDW. If OE is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified tWP. 9. To access RAM, CE = VIL and SEM = VIH. To access semaphore, CE = VIH and SEM = VIL. tEW must be met for either condition. 6.17 10 IDT7026S/L HIGH-SPEED 16K x 16 DUAL-PORT STATIC RAM MILITARY AND COMMERCIAL TEMPERATURE RANGES TIMING WAVEFORM OF SEMAPHORE READ AFTER WRITE TIMING, EITHER SIDE(1) tOH tSAA A0-A2 VALID ADDRESS tWR tAW tEW SEM VALID ADDRESS tACE tSOP tDW DATAIN VALID I/O0 tAS W tWP DATAOUT VALID(2) tDH R/ tSWRD tAOE OE Write Cycle Read Cycle 2939 drw 10 NOTES: 1. CE = VIH or UB and LB = VIH for the duration of the above timing (both write and read cycle). 2. "DATAOUT VALID" represents all I/O's (I/O0-I/O15) equal to the semaphore value. TIMING WAVEFORM OF SEMAPHORE WRITE CONTENTION(1,3,4) A0"A"-A2"A" (2) SIDE “A” MATCH W"A" R/ SEM"A" tSPS A0"B"-A2"B" (2) SIDE “B” MATCH W"B" R/ SEM"B" 2939 drw 11 NOTES: 1. DOR = DOL = VIL, CER = CEL = VIH, or both UB & LB = VIH. 2. All timing is the same for left and right ports. Port “A” may be either left or right port. Port “B” is the opposite from port “A”. 3. This parameter is measured from R/W"A" or SEM"A" going HIGH to R/W"B" or SEM"B" going HIGH. 4. If tSPS is not satisfied, there is no guarantee which side will be granted the semaphore flag. 6.17 11 IDT7026S/L HIGH-SPEED 16K x 16 DUAL-PORT STATIC RAM MILITARY AND COMMERCIAL TEMPERATURE RANGES AC ELECTRICAL CHARACTERISTICS OVER THE OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(6) Symbol IDT7026X20 Com'l. Only Min. Max. Parameter IDT7026X25 Min. Max. Unit BUSY TIMING (M/S = VIH) tBDC BUSY Access Time from Address Match BUSY Disable Time from Address Not Matched BUSY Access Time from Chip Enable Low BUSY Disable Time from Chip Enable High tAPS Arbitration Priority Set-up Time(2) tBAA tBDA tBAC BUSY Disable to Valid Data(3) Write Hold After BUSY(5) tWH BUSY TIMING (M/S = VIL) BUSY Input to Write(4) tWB Write Hold After BUSY(5) tWH tBDD — 20 — 20 ns — 20 — 20 ns — 20 — 20 ns — 17 — 17 ns 5 — 5 — ns — 30 — 30 ns 15 — 17 — ns 0 — 0 — ns 15 — 17 — ns PORT-TO-PORT DELAY TIMING tWDD Write Pulse to Data Delay(1) — 45 — 50 ns tDDD Write Data Valid to Read Data Delay(1) — 30 — 35 ns Symbol Parameter IDT7026X35 IDT7026X55 Min. Max. Min. Max. Unit — 20 — 45 ns BUSY TIMING (M/S = VIH) tBAA tBDA tBAC tBDC tAPS tBDD tWH BUSY Access Time from Address Match BUSY Disable Time from Address Not Matched BUSY Access Time from Chip Enable Low BUSY Disable Time from Chip Enable High (2) Arbitration Priority Set-up Time BUSY Disable to Valid Data(3) Write Hold After BUSY(5) — 20 — 40 ns — 20 — 40 ns — 20 — 35 ns 5 — 5 — ns — 35 — 40 ns 25 — 25 — ns BUSY TIMING (M/S = VIL) tWB tWH BUSY Input to Write(4) Write Hold After BUSY(5) 0 — 0 — ns 25 — 25 — ns PORT-TO-PORT DELAY TIMING tWDD Write Pulse to Data Delay(1) — 60 — 80 ns tDDD Write Data Valid to Read Data Delay(1) — 45 — 65 ns NOTES: 1. Port-to-port delay through RAM cells from writing port to reading port, refer to "Timing Waveform of Write with Port-to-Port Read and 2. To ensure that the earlier of the two ports wins. 3. tBDD is a calculated parameter and is the greater of 0, tWDD – tWP (actual), or tDDD – tDW (actual). 4. To ensure that the write cycle is inhibited on port "B" during contention on port "A". 5. To ensure that a write cycle is completed on port "B" after contention on port "A". 6. "X" in part numbers indicates power rating (S or L). 6.17 BUSY 2939 tbl 15 (M/S = VIH)". 12 IDT7026S/L HIGH-SPEED 16K x 16 DUAL-PORT STATIC RAM MILITARY AND COMMERCIAL TEMPERATURE RANGES TIMING WAVEFORM OF WRITE WITH PORT-TO-PORT READ AND BUSY (M/S = VIH)(2,4,5) tWC MATCH ADDR"A" tWP W"A" R/ tDW tDH VALID DATAIN "A" tAPS (1) MATCH ADDR"B" tBAA tBDA tBDD BUSY"B" tWDD DATAOUT "B" VALID tDDD (3) NOTES: 1. To ensure that the earlier of the two ports wins. tAPS is ignored for M/S = VIL (slave). 2. CEL = CER = VIL. 3. OE = VIL for the reading port. 4. If M/S = VIL (slave), BUSY is an input. Then for this example BUSY"A" = VIH and BUSY"B" input is shown above. 5. All timing is the same for left and right ports. Port "A" may be either the left or right port. Port "B" is the port opposite from port "A". 2939 drw 12 TIMING WAVEFORM OF WRITE WITH BUSY (M/S = VIL) tWP W R/ "A" tWB(3) BUSY"B" tWH (1) W R/ "B" (2) 2939 drw 13 NOTES: 1. tWH must be met for both BUSY input (SLAVE) and output (MASTER). 2. BUSY is asserted on port "B" blocking R/W"B", until BUSY"B" goes High. 6.17 13 IDT7026S/L HIGH-SPEED 16K x 16 DUAL-PORT STATIC RAM MILITARY AND COMMERCIAL TEMPERATURE RANGES WAVEFORM OF BUSY ARBITRATION CONTROLLED BY CE TIMING (M/S = VIH)(1) ADDR"A" and "B" ADDRESSES MATCH CE"A" tAPS(2) CE"B" tBAC tBDC BUSY"B" 2939 drw 15 WAVEFORM OF BUSY ARBITRATION CYCLE CONTROLLED BY ADDRESS MATCH TIMING (M/S = VIH)(1) ADDRESS "N" ADDR"A" tAPS (2) MATCHING ADDRESS "N" ADDR"B" tBAA tBDA BUSY"B" 2939 drw 15 NOTES: 1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from “A”. 2. If tAPS is not satisfied, the busy signal will be asserted on one side or another but there is no guarantee on which side busy will be asserted. TRUTH TABLE III — EXAMPLE OF SEMAPHORE PROCUREMENT SEQUENCE(1,2) Functions No Action D0 - D15 Left 1 D0 - D15 Right 1 Status Semaphore free Left Port Writes "0" to Semaphore 0 1 Left port has semaphore token Right Port Writes "0" to Semaphore 0 1 No change. Right side has no write access to semaphore Left Port Writes "1" to Semaphore 1 0 Right port obtains semaphore token Left Port Writes "0" to Semaphore 1 0 No change. Left port has no write access to semaphore Right Port Writes "1" to Semaphore 0 1 Left port obtains semaphore token Left Port Writes "1" to Semaphore 1 1 Semaphore free Right Port Writes "0" to Semaphore 1 0 Right port has semaphore token Right Port Writes "1" to Semaphore 1 1 Semaphore free Left Port Writes "0" to Semaphore 0 1 Left port has semaphore token Left Port Writes "1" to Semaphore 1 1 Semaphore free NOTES: 1. This table denotes a sequence of events for only one of the eight semaphores on the IDT7026. 2. There are eight semaphore flags written to via I/O0 and read from all I/O's (I/O0-I/O15). These eight semaphores are addressed by A0 - A2. 6.17 2683 tbl 16 14 IDT7026S/L HIGH-SPEED 16K x 16 DUAL-PORT STATIC RAM MILITARY AND COMMERCIAL TEMPERATURE RANGES WIDTH EXPANSION WITH BUSY LOGIC MASTER/SLAVE ARRAYS Inputs Outputs CEL CER A0L-A13L A0R-A13R X X NO MATCH H H Normal H X MATCH H H Normal X H MATCH H H Normal L L MATCH (2) (2) Write Inhibit(3) BUSYL(1) BUSYR(1) Function NOTES: 2683 tbl 17 1. Pins BUSYL and BUSYR are both outputs when the part is configured as a master. Both are inputs when configured as a slave. BUSYX outputs on the IDT7026 are push pull, not open drain outputs. On slaves the BUSYX input internally inhibits writes. 2. LOW if the inputs to the opposite port were stable prior to the address and enable inputs of this port. HIGH if the inputs to the opposite port became stable after the address and enable inputs of this port. If tAPS is not met, either BUSYL or BUSYR = LOW will result. BUSYL and BUSYR outputs cannot be LOW simultaneously. 3. Writes to the left port are internally ignored when BUSYL outputs are driving LOW regardless of actual logic level on the pin. Writes to the right port are internally ignored when BUSYR outputs are driving LOW regardless of actual logic level on the pin. When expanding an IDT7026 RAM array in width while using busy logic, one master part is used to decide which side of the RAM array will receive a busy indication, and to output that indication. Any number of slaves to be addressed in the same address range as the master, use the busy signal as a write inhibit signal. Thus on the IDT7026 RAM the busy pin is an output if the part is used as a master (M/S pin = H), and the busy pin is an input if the part used as a slave (M/S pin = L) as shown in Figure 3. MASTER Dual Port RAM BUSYL MASTER Dual Port RAM BUSYL BUSYL CE BUSYR CE BUSYR SLAVE Dual Port RAM BUSYL SLAVE Dual Port RAM BUSYL CE BUSYR DECODER TRUTH TABLE IV — ADDRESS BUSY ARBITRATION CE BUSYR BUSYR 2939 drw 16 FUNCTIONAL DESCRIPTION The IDT7026 provides two ports with separate control, address and I/O pins that permit independent access for reads or writes to any location in memory. The IDT7026 has an automatic power down feature controlled by CE. The CE controls on-chip power down circuitry that permits the respective port to go into a standby mode when not selected (CE HIGH). When a port is enabled, access to the entire memory array is permitted. BUSY LOGIC Busy Logic provides a hardware indication that both ports of the RAM have accessed the same location at the same time. It also allows one of the two accesses to proceed and signals the other side that the RAM is “Busy”. The busy pin can then be used to stall the access until the operation on the other side is completed. If a write operation has been attempted from the side that receives a busy indication, the write signal is gated internally to prevent the write from proceeding. The use of busy logic is not required or desirable for all applications. In some cases it may be useful to logically OR the busy outputs together and use any busy indication as an interrupt source to flag the event of an illegal or illogical operation. If the write inhibit function of busy logic is not desirable, the busy logic can be disabled by placing the part in slave mode with the M/S pin. Once in slave mode the BUSY pin operates solely as a write inhibit input pin. Normal operation can be programmed by tying the BUSY pins HIGH. If desired, unintended write operations can be prevented to a port by tying the busy pin for that port LOW. The busy outputs on the IDT 7026 RAM in master mode, are push-pull type outputs and do not require pull up resistors to operate. If these RAMs are being expanded in depth, then the busy indication for the resulting array requires the use of an external AND gate. Figure 3. Busy and chip enable routing for both width and depth expansion with IDT7026 RAMs. If two or more master parts were used when expanding in width, a split decision could result with one master indicating busy on one side of the array and another master indicating busy on one other side of the array. This would inhibit the write operations from one port for part of a word and inhibit the write operations from the other port for the other part of the word. The busy arbitration, on a master, is based on the chip enable and address signals only. It ignores whether an access is a read or write. In a master/slave array, both address and chip enable must be valid long enough for a busy flag to be output from the master before the actual write pulse can be initiated with either the R/W signal or the byte enables. Failure to observe this timing can result in a glitched internal write inhibit signal and corrupted data in the slave. SEMAPHORES The IDT7026 is an extremely fast Dual-Port 16K x 16 CMOS Static RAM with an additional 8 address locations dedicated to binary semaphore flags. These flags allow either processor on the left or right side of the Dual-Port RAM to claim a privilege over the other processor for functions defined by the system designer’s software. As an example, the semaphore can be used by one processor to inhibit the other from accessing a portion of the Dual-Port RAM or any other shared resource. The Dual-Port RAM features a fast access time, and both ports are completely independent of each other. This means that the activity on the left port in no way slows the access time of the right port. Both ports are identical in function to standard 6.17 15 IDT7026S/L HIGH-SPEED 16K x 16 DUAL-PORT STATIC RAM MILITARY AND COMMERCIAL TEMPERATURE RANGES CMOS Static RAM and can be read from, or written to, at the same time with the only possible conflict arising from the simultaneous writing of, or a simultaneous READ/WRITE of, a non-semaphore location. Semaphores are protected against such ambiguous situations and may be used by the system program to avoid any conflicts in the non-semaphore portion of the Dual-Port RAM. These devices have an automatic power-down feature controlled by CE, the Dual-Port RAM enable, and SEM, the semaphore enable. The CE and SEM pins control on-chip power down circuitry that permits the respective port to go into standby mode when not selected. This is the condition which is shown in Truth Table where CE and SEM are both HIGH. Systems which can best use the IDT7026 contain multiple processors or controllers and are typically very high-speed systems which are software controlled or software intensive. These systems can benefit from a performance increase offered by the IDT7026's hardware semaphores, which provide a lockout mechanism without requiring complex programming. Software handshaking between processors offers the maximum in system flexibility by permitting shared resources to be allocated in varying configurations. The IDT7026 does not use its semaphore flags to control any resources through hardware, thus allowing the system designer total flexibility in system architecture. An advantage of using semaphores rather than the more common methods of hardware arbitration is that wait states are never incurred in either processor. This can prove to be a major advantage in very high-speed systems. HOW THE SEMAPHORE FLAGS WORK The semaphore logic is a set of eight latches which are independent of the Dual-Port RAM. These latches can be used to pass a flag, or token, from one port to the other to indicate that a shared resource is in use. The semaphores provide a hardware assist for a use assignment method called “Token Passing Allocation.” In this method, the state of a semaphore latch is used as a token indicating that shared resource is in use. If the left processor wants to use this resource, it requests the token by setting the latch. This processor then verifies its success in setting the latch by reading it. If it was successful, it proceeds to assume control over the shared resource. If it was not successful in setting the latch, it determines that the right side processor has set the latch first, has the token and is using the shared resource. The left processor can then either repeatedly request that semaphore’s status or remove its request for that semaphore to perform another task and occasionally attempt again to gain control of the token via the set and test sequence. Once the right side has relinquished the token, the left side should succeed in gaining control. The semaphore flags are active LOW. A token is requested by writing a zero into a semaphore latch and is released when the same side writes a one to that latch. The eight semaphore flags reside within the IDT7026 in a separate memory space from the Dual-Port RAM. This address space is accessed by placing a low input on the SEM pin (which acts as a chip select for the semaphore flags) and using the other control pins (Address, OE, and R/W) as they would be used in accessing a standard Static RAM. Each of the flags has a unique address which can be accessed by either side through address pins A0 – A2. When accessing the semaphores, none of the other address pins has any effect. When writing to a semaphore, only data pin D0 is used. If a low level is written into an unused semaphore location, that flag will be set to a zero on that side and a one on the other side (see Table III). That semaphore can now only be modified by the side showing the zero. When a one is written into the same location from the same side, the flag will be set to a one for both sides (unless a semaphore request from the other side is pending) and then can be written to by both sides. The fact that the side which is able to write a zero into a semaphore subsequently locks out writes from the other side is what makes semaphore flags useful in interprocessor communications. (A thorough discussing on the use of this feature follows shortly.) A zero written into the same location from the other side will be stored in the semaphore request latch for that side until the semaphore is freed by the first side. When a semaphore flag is read, its value is spread into all data bits so that a flag that is a one reads as a one in all data bits and a flag containing a zero reads as all zeros. The read value is latched into one side’s output register when that side's semaphore select (SEM) and output enable (OE) signals go active. This serves to disallow the semaphore from changing state in the middle of a read cycle due to a write cycle from the other side. Because of this latch, a repeated read of a semaphore in a test loop must cause either signal (SEM or OE) to go inactive or the output will never change. A sequence WRITE/READ must be used by the semaphore in order to guarantee that no system level contention will occur. A processor requests access to shared resources by attempting to write a zero into a semaphore location. If the semaphore is already in use, the semaphore request latch will contain a zero, yet the semaphore flag will appear as one, a fact which the processor will verify by the subsequent read (see Table III). As an example, assume a processor writes a zero to the left port at a free semaphore location. On a subsequent read, the processor will verify that it has written successfully to that location and will assume control over the resource in question. Meanwhile, if a processor on the right side attempts to write a zero to the same semaphore flag it will fail, as will be verified by the fact that a one will be read from that semaphore on the right side during subsequent read. Had a sequence of READ/WRITE been used instead, system contention problems could have occurred during the gap between the read and write cycles. It is important to note that a failed semaphore request must be followed by either repeated reads or by writing a one into the same location. The reason for this is easily understood by looking at the simple logic diagram of the semaphore flag in Figure 4. Two semaphore request latches feed into a semaphore flag. Whichever latch is first to present a zero to the semaphore flag will force its side of the semaphore flag LOW and the other side HIGH. This condition will continue until a 6.17 16 IDT7026S/L HIGH-SPEED 16K x 16 DUAL-PORT STATIC RAM MILITARY AND COMMERCIAL TEMPERATURE RANGES L PORT R PORT SEMAPHORE REQUEST FLIP FLOP D0 D Q SEMAPHORE REQUEST FLIP FLOP Q D WRITE SEMAPHORE READ D0 WRITE SEMAPHORE READ Figure 4. IDT7026 Semaphore Logic 2939 drw 17 one is written to the same semaphore request latch. Should the other side’s semaphore request latch have been written to a zero in the meantime, the semaphore flag will flip over to the other side as soon as a one is written into the first side’s request latch. The second side’s flag will now stay LOW until its semaphore request latch is written to a one. From this it is easy to understand that, if a semaphore is requested and the processor which requested it no longer needs the resource, the entire system can hang up until a one is written into that semaphore request latch. The critical case of semaphore timing is when both sides request a single token by attempting to write a zero into it at the same time. The semaphore logic is specially designed to resolve this problem. If simultaneous requests are made, the logic guarantees that only one side receives the token. If one side is earlier than the other in making the request, the first side to make the request will receive the token. If both requests arrive at the same time, the assignment will be arbitrarily made to one port or the other. One caution that should be noted when using semaphores is that semaphores alone do not guarantee that access to a resource is secure. As with any powerful programming technique, if semaphores are misused or misinterpreted, a software error can easily happen. Initialization of the semaphores is not automatic and must be handled via the initialization program at power-up. Since any semaphore request flag which contains a zero must be reset to a one, all semaphores on both sides should have a one written into them at initialization from both sides to assure that they will be free when needed. USING SEMAPHORES—SOME EXAMPLES Perhaps the simplest application of semaphores is their application as resource markers for the IDT7026’s Dual-Port RAM. Say the 16K x 16 RAM was to be divided into two 8K x 16 blocks which were to be dedicated at any one time to servicing either the left or right port. Semaphore 0 could be used to indicate the side which would control the lower section of memory, and Semaphore 1 could be defined as the indicator for the upper section of memory. To take a resource, in this example the lower 8K of Dual-Port RAM, the processor on the left port could write and then read a zero in to Semaphore 0. If this task were successfully completed (a zero was read back rather than a one), the left processor would assume control of the lower 8K. Meanwhile the right processor was attempting to gain control of the resource after the left processor, it would read back a one in response to the zero it had attempted to write into Semaphore 0. At this point, the software could choose to try and gain control of the second 8K section by writing, then reading a zero into Semaphore 1. If it succeeded in gaining control, it would lock out the left side. Once the left side was finished with its task, it would write a one to Semaphore 0 and may then try to gain access to Semaphore 1. If Semaphore 1 was still occupied by the right side, the left side could undo its semaphore request and perform other tasks until it was able to write, then read a zero into Semaphore 1. If the right processor performs a similar task with Semaphore 0, this protocol would allow the two processors to swap 8K blocks of Dual-Port RAM with each other. The blocks do not have to be any particular size and can even be variable, depending upon the complexity of the software using the semaphore flags. All eight semaphores could be used to divide the Dual-Port RAM or other shared resources into eight parts. Semaphores can even be assigned different meanings on different sides rather than being given a common meaning as was shown in the example above. Semaphores are a useful form of arbitration in systems like disk interfaces where the CPU must be locked out of a section of memory during a transfer and the I/O device cannot tolerate any wait states. With the use of semaphores, once the two devices has determined which memory area was “off-limits” to the CPU, both the CPU and the I/O devices could access their assigned portions of memory continuously without any wait states. Semaphores are also useful in applications where no memory “WAIT” state is available on one or both sides. Once a semaphore handshake has been performed, both processors can access their assigned RAM segments at full speed. Another application is in the area of complex data structures. In this case, block arbitration is very important. For this application one processor may be responsible for building and updating a data structure. The other processor then reads and interprets that data structure. If the interpreting processor reads an incomplete data structure, a major error condition may exist. Therefore, some sort of arbitration must be used between the two different processors. The building processor arbitrates for the block, locks it and then is able to go in and update the data structure. When the update is completed, the data structure block is released. This allows the interpreting processor to come back and read the complete data structure, thereby guaranteeing a consistent data structure. 6.17 17 IDT7026S/L HIGH-SPEED 16K x 16 DUAL-PORT STATIC RAM MILITARY AND COMMERCIAL TEMPERATURE RANGES ORDERING INFORMATION IDT XXXXX Device Type A 999 A A Power Speed Package Process/ Temperature Range Blank Commercial (0°C to +70°C) B Military (–55°C to +125°C) Compliant to MIL-STD-883, Class B G J 84-pin PGA (G84-3) 84-pin PLCC (J84-1) 20 25 35 55 Commercial Only S L Standard Power Low Power 7026 256K (16K x 16) Dual-Port RAM Speed in nanoseconds 2939 drw 18 6.17 18